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| author | Thomas Gleixner <tglx@linutronix.de> | 2013-04-24 20:33:46 +0200 |
|---|---|---|
| committer | Thomas Gleixner <tglx@linutronix.de> | 2013-04-24 20:33:54 +0200 |
| commit | 6402c7dc2a19c19bd8cdc7d80878b850da418942 (patch) | |
| tree | cda2ea2df40442e2aa016119f3548cc504127ea8 /arch/arm/mm/cache-v4.S | |
| parent | 77c675ba18836802f6b73d2d773481d06ebc0f04 (diff) | |
| parent | 60d509fa6a9c4653a86ad830e4c4b30360b23f0e (diff) | |
Merge branch 'linus' into timers/core
Reason: Get upstream fixes before adding conflicting code.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'arch/arm/mm/cache-v4.S')
| -rw-r--r-- | arch/arm/mm/cache-v4.S | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mm/cache-v4.S b/arch/arm/mm/cache-v4.S index 43e5d77be67..a7ba68f59f0 100644 --- a/arch/arm/mm/cache-v4.S +++ b/arch/arm/mm/cache-v4.S @@ -58,7 +58,7 @@ ENTRY(v4_flush_kern_cache_all) ENTRY(v4_flush_user_cache_range) #ifdef CONFIG_CPU_CP15 mov ip, #0 - mcreq p15, 0, ip, c7, c7, 0 @ flush ID cache + mcr p15, 0, ip, c7, c7, 0 @ flush ID cache mov pc, lr #else /* FALLTHROUGH */ |