diff options
| author | Arnd Bergmann <arnd@arndb.de> | 2012-03-19 20:46:32 +0000 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2012-03-20 09:41:43 +0000 |
| commit | b2f1df8d2fc14bf7e6d9d967043d4b60c2efd8dc (patch) | |
| tree | 065282434bde6ef9b4357c042705c5fcef3782ea /arch/arm/mm/cache-v7.S | |
| parent | c0206e228e34d8b414fcc63db45b831843adea06 (diff) | |
| parent | 5cd9eb2736a572a9ef2689829f47ffd4262adc00 (diff) | |
Merge branch 'renesas/timer' into next/timer
Conflicts:
arch/arm/mach-shmobile/timer.c
This resolves a nonobvious merge conflict between renesas
timer changes in the global timer changes with those
from the renesas soc branch and last minute bug fixes that
went into v3.3.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/mm/cache-v7.S')
| -rw-r--r-- | arch/arm/mm/cache-v7.S | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S index 7a24d39661f..a655d3da386 100644 --- a/arch/arm/mm/cache-v7.S +++ b/arch/arm/mm/cache-v7.S @@ -55,7 +55,7 @@ loop1: cmp r1, #2 @ see what cache we have at this level blt skip @ skip if no cache, or just i-cache #ifdef CONFIG_PREEMPT - save_and_disable_irqs r9 @ make cssr&csidr read atomic + save_and_disable_irqs_notrace r9 @ make cssr&csidr read atomic #endif mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr isb @ isb to sych the new cssr&csidr |