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| author | Arnd Bergmann <arnd@arndb.de> | 2012-02-28 12:33:41 +0000 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2012-02-28 12:33:46 +0000 |
| commit | abf45ce84c4e36bd64aef20d7df9a79bd5e4b799 (patch) | |
| tree | f118e135bdd60b680703d1b38c7fdc7b9d7c503d /arch/arm/mm/cache-v7.S | |
| parent | 082f53c2f573c75a8f1610c587a43b6817e20f90 (diff) | |
| parent | b1f91a9ce335eb4e0fef17c10f39a438ac3fce9b (diff) | |
Merge branch 'imx/defconfig' of git://git.linaro.org/people/shawnguo/linux-2.6 into next/soc
* 'imx/defconfig' of git://git.linaro.org/people/shawnguo/linux-2.6: (2 commits)
ARM: defconfig: imx_v6_v7: build in REGULATOR_FIXED_VOLTAGE
ARM: imx: update imx_v6_v7_defconfig
(upadte to v3.3-rc5)
Diffstat (limited to 'arch/arm/mm/cache-v7.S')
| -rw-r--r-- | arch/arm/mm/cache-v7.S | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S index 07c4bc8ea0a..a655d3da386 100644 --- a/arch/arm/mm/cache-v7.S +++ b/arch/arm/mm/cache-v7.S @@ -54,9 +54,15 @@ loop1: and r1, r1, #7 @ mask of the bits for current cache only cmp r1, #2 @ see what cache we have at this level blt skip @ skip if no cache, or just i-cache +#ifdef CONFIG_PREEMPT + save_and_disable_irqs_notrace r9 @ make cssr&csidr read atomic +#endif mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr isb @ isb to sych the new cssr&csidr mrc p15, 1, r1, c0, c0, 0 @ read the new csidr +#ifdef CONFIG_PREEMPT + restore_irqs_notrace r9 +#endif and r2, r1, #7 @ extract the length of the cache lines add r2, r2, #4 @ add 4 (line length offset) ldr r4, =0x3ff |