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| author | Takashi Iwai <tiwai@suse.de> | 2012-03-18 18:22:37 +0100 |
|---|---|---|
| committer | Takashi Iwai <tiwai@suse.de> | 2012-03-18 18:22:37 +0100 |
| commit | cb3f2adc03ab055b19c677a6283523861fafebdd (patch) | |
| tree | 59cfb6800f0635a4aec16c8e0da619f27e51ee79 /arch/arm/mm/cache-v7.S | |
| parent | 44c76a960a62fcc46cbcaa0a22a34e666a729329 (diff) | |
| parent | 828006de1bddf83b6ecf03ec459c15f7c7c22db7 (diff) | |
Merge branch 'topic/asoc' into for-linus
Diffstat (limited to 'arch/arm/mm/cache-v7.S')
| -rw-r--r-- | arch/arm/mm/cache-v7.S | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S index 07c4bc8ea0a..7a24d39661f 100644 --- a/arch/arm/mm/cache-v7.S +++ b/arch/arm/mm/cache-v7.S @@ -54,9 +54,15 @@ loop1: and r1, r1, #7 @ mask of the bits for current cache only cmp r1, #2 @ see what cache we have at this level blt skip @ skip if no cache, or just i-cache +#ifdef CONFIG_PREEMPT + save_and_disable_irqs r9 @ make cssr&csidr read atomic +#endif mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr isb @ isb to sych the new cssr&csidr mrc p15, 1, r1, c0, c0, 0 @ read the new csidr +#ifdef CONFIG_PREEMPT + restore_irqs_notrace r9 +#endif and r2, r1, #7 @ extract the length of the cache lines add r2, r2, #4 @ add 4 (line length offset) ldr r4, =0x3ff |