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| author | Tejun Heo <tj@kernel.org> | 2010-02-02 14:38:15 +0900 |
|---|---|---|
| committer | Tejun Heo <tj@kernel.org> | 2010-02-02 14:38:15 +0900 |
| commit | ab386128f20c44c458a90039ab1bdc265ac474c9 (patch) | |
| tree | 2ad188744922b1bb951fd10ff50dc04c83acce22 /arch/arm/mm/cache-xsc3l2.c | |
| parent | dbfc196a3cc1a2514ad0737a82f764de23bd65e6 (diff) | |
| parent | ab658321f32770b903a4426e2a6fae0392757755 (diff) | |
Merge branch 'master' into percpu
Diffstat (limited to 'arch/arm/mm/cache-xsc3l2.c')
| -rw-r--r-- | arch/arm/mm/cache-xsc3l2.c | 11 |
1 files changed, 5 insertions, 6 deletions
diff --git a/arch/arm/mm/cache-xsc3l2.c b/arch/arm/mm/cache-xsc3l2.c index 5d180cb0bd9..c3154928bcc 100644 --- a/arch/arm/mm/cache-xsc3l2.c +++ b/arch/arm/mm/cache-xsc3l2.c @@ -221,15 +221,14 @@ static int __init xsc3_l2_init(void) if (!cpu_is_xsc3() || !xsc3_l2_present()) return 0; - if (!(get_cr() & CR_L2)) { + if (get_cr() & CR_L2) { pr_info("XScale3 L2 cache enabled.\n"); - adjust_cr(CR_L2, CR_L2); xsc3_l2_inv_all(); - } - outer_cache.inv_range = xsc3_l2_inv_range; - outer_cache.clean_range = xsc3_l2_clean_range; - outer_cache.flush_range = xsc3_l2_flush_range; + outer_cache.inv_range = xsc3_l2_inv_range; + outer_cache.clean_range = xsc3_l2_clean_range; + outer_cache.flush_range = xsc3_l2_flush_range; + } return 0; } |