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| author | Dmitry Torokhov <dmitry.torokhov@gmail.com> | 2010-01-21 23:55:25 -0800 |
|---|---|---|
| committer | Dmitry Torokhov <dmitry.torokhov@gmail.com> | 2010-01-21 23:55:25 -0800 |
| commit | 7755726fe90a8b253659756e6de68c1a55aa427f (patch) | |
| tree | a3523fa77e07854db3b8089e3066a55ea997060c /arch/arm/mm/proc-arm925.S | |
| parent | 3bf127637e22ddf95e67e10a23c339cee3d52429 (diff) | |
| parent | 92dcffb916d309aa01778bf8963a6932e4014d07 (diff) | |
Merge commit 'v2.6.33-rc5' into next
Diffstat (limited to 'arch/arm/mm/proc-arm925.S')
| -rw-r--r-- | arch/arm/mm/proc-arm925.S | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/arch/arm/mm/proc-arm925.S b/arch/arm/mm/proc-arm925.S index cb53435a85a..8deb5bde58e 100644 --- a/arch/arm/mm/proc-arm925.S +++ b/arch/arm/mm/proc-arm925.S @@ -251,15 +251,16 @@ ENTRY(arm925_coherent_user_range) mov pc, lr /* - * flush_kern_dcache_page(void *page) + * flush_kern_dcache_area(void *addr, size_t size) * * Ensure no D cache aliasing occurs, either with itself or * the I cache * - * - addr - page aligned address + * - addr - kernel address + * - size - region size */ -ENTRY(arm925_flush_kern_dcache_page) - add r1, r0, #PAGE_SZ +ENTRY(arm925_flush_kern_dcache_area) + add r1, r0, r1 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry add r0, r0, #CACHE_DLINESIZE cmp r0, r1 @@ -346,7 +347,7 @@ ENTRY(arm925_cache_fns) .long arm925_flush_user_cache_range .long arm925_coherent_kern_range .long arm925_coherent_user_range - .long arm925_flush_kern_dcache_page + .long arm925_flush_kern_dcache_area .long arm925_dma_inv_range .long arm925_dma_clean_range .long arm925_dma_flush_range |