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authorTakashi Iwai <tiwai@suse.de>2010-08-18 15:17:30 +0200
committerTakashi Iwai <tiwai@suse.de>2010-08-18 15:17:30 +0200
commit6ab561c8aab2e4af535f09adbc6253f958536848 (patch)
tree37846adb4ea106485720d113e252d71d615c23ed /arch/arm/mm/proc-sa110.S
parent4f4e8f69895c8696a4bcc751817d4b186023ac44 (diff)
parentcbaa9f60d5d5c3af10f94e0d49789d5b82341a4a (diff)
Merge branch 'topic/isa' into topic/misc
Diffstat (limited to 'arch/arm/mm/proc-sa110.S')
-rw-r--r--arch/arm/mm/proc-sa110.S8
1 files changed, 2 insertions, 6 deletions
diff --git a/arch/arm/mm/proc-sa110.S b/arch/arm/mm/proc-sa110.S
index 7b706b38990..a201eb04b5e 100644
--- a/arch/arm/mm/proc-sa110.S
+++ b/arch/arm/mm/proc-sa110.S
@@ -44,17 +44,13 @@ ENTRY(cpu_sa110_proc_init)
* cpu_sa110_proc_fin()
*/
ENTRY(cpu_sa110_proc_fin)
- stmfd sp!, {lr}
- mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
- msr cpsr_c, ip
- bl v4wb_flush_kern_cache_all @ clean caches
-1: mov r0, #0
+ mov r0, #0
mcr p15, 0, r0, c15, c2, 2 @ Disable clock switching
mrc p15, 0, r0, c1, c0, 0 @ ctrl register
bic r0, r0, #0x1000 @ ...i............
bic r0, r0, #0x000e @ ............wca.
mcr p15, 0, r0, c1, c0, 0 @ disable caches
- ldmfd sp!, {pc}
+ mov pc, lr
/*
* cpu_sa110_reset(loc)