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author | Ingo Molnar <mingo@elte.hu> | 2011-09-26 12:53:42 +0200 |
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committer | Ingo Molnar <mingo@elte.hu> | 2011-09-26 12:54:28 +0200 |
commit | ed3982cf3748b657ffb79d9d1c2e4a562661db2d (patch) | |
tree | 6e3654f460e23aa1b1512896aa3f03886a69be1b /arch/arm/mm/proc-sa1100.S | |
parent | cba9bd22a5f8f857534b9a7f3fb3cafa0ac5fb75 (diff) | |
parent | d93dc5c4478c1fd5de85a3e8aece9aad7bbae044 (diff) |
Merge commit 'v3.1-rc7' into perf/core
Merge reason: Pick up the latest upstream fixes.
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/arm/mm/proc-sa1100.S')
-rw-r--r-- | arch/arm/mm/proc-sa1100.S | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/arm/mm/proc-sa1100.S b/arch/arm/mm/proc-sa1100.S index 07219c2ae11..69e7f2ef738 100644 --- a/arch/arm/mm/proc-sa1100.S +++ b/arch/arm/mm/proc-sa1100.S @@ -182,11 +182,11 @@ ENDPROC(cpu_sa1100_do_suspend) ENTRY(cpu_sa1100_do_resume) ldmia r0, {r4 - r7} @ load cp regs - mov r1, #0 - mcr p15, 0, r1, c8, c7, 0 @ flush I+D TLBs - mcr p15, 0, r1, c7, c7, 0 @ flush I&D cache - mcr p15, 0, r1, c9, c0, 0 @ invalidate RB - mcr p15, 0, r1, c9, c0, 5 @ allow user space to use RB + mov ip, #0 + mcr p15, 0, ip, c8, c7, 0 @ flush I+D TLBs + mcr p15, 0, ip, c7, c7, 0 @ flush I&D cache + mcr p15, 0, ip, c9, c0, 0 @ invalidate RB + mcr p15, 0, ip, c9, c0, 5 @ allow user space to use RB mcr p15, 0, r4, c3, c0, 0 @ domain ID mcr p15, 0, r5, c2, c0, 0 @ translation table base addr |