diff options
| author | Chao Xie <chao.xie@marvell.com> | 2012-05-07 11:23:59 +0800 |
|---|---|---|
| committer | Haojian Zhuang <haojian.zhuang@gmail.com> | 2012-05-07 11:43:48 +0800 |
| commit | 89326f76b7ae602eb6a2d3e4cc028190fc8d480f (patch) | |
| tree | 29d55ffa2b9c46f22962e6a7ff08e3b04e9b0dbe /arch/arm/mm | |
| parent | 3f5d081957cee794fe2937bb7edafa7ac949044d (diff) | |
ARM: cache: tauros2: add disable and resume callback
For the SOC chips using tauros2 cache, will need disable
and resume tauros2 cache for SOC suspend/resume.
Signed-off-by: Chao Xie <chao.xie@marvell.com>
Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Diffstat (limited to 'arch/arm/mm')
| -rw-r--r-- | arch/arm/mm/cache-tauros2.c | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/arch/arm/mm/cache-tauros2.c b/arch/arm/mm/cache-tauros2.c index 1fbca05fe90..23a7643e9a8 100644 --- a/arch/arm/mm/cache-tauros2.c +++ b/arch/arm/mm/cache-tauros2.c @@ -108,6 +108,26 @@ static void tauros2_flush_range(unsigned long start, unsigned long end) dsb(); } + +static void tauros2_disable(void) +{ + __asm__ __volatile__ ( + "mcr p15, 1, %0, c7, c11, 0 @L2 Cache Clean All\n\t" + "mrc p15, 0, %0, c1, c0, 0\n\t" + "bic %0, %0, #(1 << 26)\n\t" + "mcr p15, 0, %0, c1, c0, 0 @Disable L2 Cache\n\t" + : : "r" (0x0)); +} + +static void tauros2_resume(void) +{ + __asm__ __volatile__ ( + "mcr p15, 1, %0, c7, c7, 0 @L2 Cache Invalidate All\n\t" + "mrc p15, 0, %0, c1, c0, 0\n\t" + "orr %0, %0, #(1 << 26)\n\t" + "mcr p15, 0, %0, c1, c0, 0 @Enable L2 Cache\n\t" + : : "r" (0x0)); +} #endif static inline u32 __init read_extra_features(void) @@ -194,6 +214,8 @@ void __init tauros2_init(void) outer_cache.inv_range = tauros2_inv_range; outer_cache.clean_range = tauros2_clean_range; outer_cache.flush_range = tauros2_flush_range; + outer_cache.disable = tauros2_disable; + outer_cache.resume = tauros2_resume; } #endif @@ -219,6 +241,8 @@ void __init tauros2_init(void) outer_cache.inv_range = tauros2_inv_range; outer_cache.clean_range = tauros2_clean_range; outer_cache.flush_range = tauros2_flush_range; + outer_cache.disable = tauros2_disable; + outer_cache.resume = tauros2_resume; } #endif |