diff options
| author | Ingo Molnar <mingo@elte.hu> | 2010-05-03 09:17:01 +0200 |
|---|---|---|
| committer | Ingo Molnar <mingo@elte.hu> | 2010-05-03 09:17:01 +0200 |
| commit | 53ba4f2fa73225113a488584df0d85d3cba52943 (patch) | |
| tree | d85b984d9818abc3ccc0237eb53b710d9e96c39e /arch/arm/plat-mxc/include/mach/irqs.h | |
| parent | bd6d29c25bb1a24a4c160ec5de43e0004e01f72b (diff) | |
| parent | 66f41d4c5c8a5deed66fdcc84509376c9a0bf9d8 (diff) | |
Merge commit 'v2.6.34-rc6' into core/locking
Diffstat (limited to 'arch/arm/plat-mxc/include/mach/irqs.h')
| -rw-r--r-- | arch/arm/plat-mxc/include/mach/irqs.h | 20 |
1 files changed, 14 insertions, 6 deletions
diff --git a/arch/arm/plat-mxc/include/mach/irqs.h b/arch/arm/plat-mxc/include/mach/irqs.h index 0cb347645db..86781f7b0c0 100644 --- a/arch/arm/plat-mxc/include/mach/irqs.h +++ b/arch/arm/plat-mxc/include/mach/irqs.h @@ -12,22 +12,29 @@ #define __ASM_ARCH_MXC_IRQS_H__ /* - * So far all i.MX SoCs have 64 internal interrupts + * SoCs with TZIC interrupt controller have 128 IRQs, those with AVIC have 64 */ +#ifdef CONFIG_MXC_TZIC +#define MXC_INTERNAL_IRQS 128 +#else #define MXC_INTERNAL_IRQS 64 +#endif #define MXC_GPIO_IRQ_START MXC_INTERNAL_IRQS -#if defined CONFIG_ARCH_MX1 -#define MXC_GPIO_IRQS (32 * 4) -#elif defined CONFIG_ARCH_MX2 +/* these are ordered by size to support multi-SoC kernels */ +#if defined CONFIG_ARCH_MX2 #define MXC_GPIO_IRQS (32 * 6) -#elif defined CONFIG_ARCH_MX3 -#define MXC_GPIO_IRQS (32 * 3) +#elif defined CONFIG_ARCH_MX1 +#define MXC_GPIO_IRQS (32 * 4) #elif defined CONFIG_ARCH_MX25 #define MXC_GPIO_IRQS (32 * 4) +#elif defined CONFIG_ARCH_MX5 +#define MXC_GPIO_IRQS (32 * 4) #elif defined CONFIG_ARCH_MXC91231 #define MXC_GPIO_IRQS (32 * 4) +#elif defined CONFIG_ARCH_MX3 +#define MXC_GPIO_IRQS (32 * 3) #endif /* @@ -51,6 +58,7 @@ #else #define MX3_IPU_IRQS 0 #endif +/* REVISIT: Add IPU irqs on IMX51 */ #define NR_IRQS (MXC_IPU_IRQ_START + MX3_IPU_IRQS) |