diff options
| author | Peter Horton <phorton@bitbox.co.uk> | 2010-12-03 17:07:28 +0000 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2010-12-14 09:54:35 +0100 |
| commit | f25972233fbe4b60dc4b514def4caf40aa1bb85a (patch) | |
| tree | 1c1927bde94052d72f240acffd545439b75395d9 /arch/arm/plat-mxc/include/mach/mx51.h | |
| parent | 2c1f4672f0711e7f23ae49cbb7541088126fe576 (diff) | |
mx51: add SSI3
Add SSI3 to MX51
Signed-off-by: Peter Horton <phorton@bitbox.co.uk>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/plat-mxc/include/mach/mx51.h')
| -rw-r--r-- | arch/arm/plat-mxc/include/mach/mx51.h | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/arch/arm/plat-mxc/include/mach/mx51.h b/arch/arm/plat-mxc/include/mach/mx51.h index 882f1f4e7f2..fa3a2a5d3e3 100644 --- a/arch/arm/plat-mxc/include/mach/mx51.h +++ b/arch/arm/plat-mxc/include/mach/mx51.h @@ -109,7 +109,7 @@ #define MX51_MIPI_HSC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xdc000) #define MX51_ATA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe0000) #define MX51_SIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe4000) -#define MX51_SSI3BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe8000) +#define MX51_SSI3_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe8000) #define MX51_FEC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xec000) #define MX51_TVE_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xf0000) #define MX51_VPU_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xf4000) @@ -223,9 +223,9 @@ #define MX51_DMA_REQ_EMI_WR 32 #define MX51_DMA_REQ_CTI2_1 33 #define MX51_DMA_REQ_EPIT2 34 -#define MX51_DMA_REQ_SSI3_RX2 35 +#define MX51_DMA_REQ_SSI3_RX1 35 #define MX51_DMA_REQ_IPU 36 -#define MX51_DMA_REQ_SSI3_TX2 37 +#define MX51_DMA_REQ_SSI3_TX1 37 #define MX51_DMA_REQ_CSPI_RX 38 #define MX51_DMA_REQ_CSPI_TX 39 #define MX51_DMA_REQ_SDHC3 40 @@ -234,8 +234,8 @@ #define MX51_DMA_REQ_UART3_RX 43 #define MX51_DMA_REQ_UART3_TX 44 #define MX51_DMA_REQ_SPDIF 45 -#define MX51_DMA_REQ_SSI3_RX1 46 -#define MX51_DMA_REQ_SSI3_TX1 47 +#define MX51_DMA_REQ_SSI3_RX0 46 +#define MX51_DMA_REQ_SSI3_TX0 47 /* * Interrupt numbers @@ -337,7 +337,7 @@ #define MX51_MXC_INT_FIRI 93 #define MX51_MXC_INT_PWM2 94 #define MX51_MXC_INT_SLIM_EXP 95 -#define MX51_MXC_INT_SSI3 96 +#define MX51_INT_SSI3 96 #define MX51_MXC_INT_EMI_BOOT 97 #define MX51_MXC_INT_CTI1_TG3 98 #define MX51_MXC_INT_SMC_RX 99 |