diff options
author | Arnd Bergmann <arnd@arndb.de> | 2012-01-09 16:01:00 +0000 |
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committer | Arnd Bergmann <arnd@arndb.de> | 2012-01-09 16:01:00 +0000 |
commit | a07613a54d700a974f3a4a657da78ef5d097315d (patch) | |
tree | e4bc91713e02fa6d8f08b07de53ea8f905593dfa /arch/arm/plat-mxc/time.c | |
parent | 65db039bf7402f0a5b19cbf6dcff55ebea433b8b (diff) | |
parent | 928a11ba36f999436915ea2b1eadf54301f93059 (diff) |
Merge branch 'samsung/dt' into samsung/cleanup
Conflicts:
arch/arm/mach-s3c64xx/Makefile
arch/arm/mach-s5pc100/Makefile
arch/arm/mach-s5pv210/Makefile
Pull in previously resolved conflicts:
The Makefiles were reorganized in the "rmk/restart" series and modified
in the "samsung/cleanup series". This also pulls in the other conflict
resolutions from the restart series against the samsung/dt series.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/plat-mxc/time.c')
-rw-r--r-- | arch/arm/plat-mxc/time.c | 15 |
1 files changed, 3 insertions, 12 deletions
diff --git a/arch/arm/plat-mxc/time.c b/arch/arm/plat-mxc/time.c index 4b0fe285e83..1c96cdb4c35 100644 --- a/arch/arm/plat-mxc/time.c +++ b/arch/arm/plat-mxc/time.c @@ -108,18 +108,9 @@ static void gpt_irq_acknowledge(void) static void __iomem *sched_clock_reg; -static DEFINE_CLOCK_DATA(cd); -unsigned long long notrace sched_clock(void) +static u32 notrace mxc_read_sched_clock(void) { - cycle_t cyc = sched_clock_reg ? __raw_readl(sched_clock_reg) : 0; - - return cyc_to_sched_clock(&cd, cyc, (u32)~0); -} - -static void notrace mxc_update_sched_clock(void) -{ - cycle_t cyc = sched_clock_reg ? __raw_readl(sched_clock_reg) : 0; - update_sched_clock(&cd, cyc, (u32)~0); + return sched_clock_reg ? __raw_readl(sched_clock_reg) : 0; } static int __init mxc_clocksource_init(struct clk *timer_clk) @@ -129,7 +120,7 @@ static int __init mxc_clocksource_init(struct clk *timer_clk) sched_clock_reg = reg; - init_sched_clock(&cd, mxc_update_sched_clock, 32, c); + setup_sched_clock(mxc_read_sched_clock, 32, c); return clocksource_mmio_init(reg, "mxc_timer1", c, 200, 32, clocksource_mmio_readl_up); } |