diff options
| author | Shawn Guo <shawn.guo@linaro.org> | 2012-09-13 19:48:07 +0800 |
|---|---|---|
| committer | Shawn Guo <shawn.guo@linaro.org> | 2012-10-15 10:02:19 +0800 |
| commit | 3995eb82050a81e11217a0b88b2a5eddd53eb4d6 (patch) | |
| tree | b1c04b25317c9dade08d911e8077c8745df8a954 /arch/arm/plat-mxc | |
| parent | e0557c0d1a3a9c38af6777d308f98da12c94e137 (diff) | |
ARM: imx: merge plat-mxc into mach-imx
It's really unnecessary to have plat-mxc, and let's merge it into
mach-imx. It's pretty much just a bunch of file renaming and
Kconfig/Makefile merge.
To make the change less invasive, we keep using Kconfig symbol
CONFIG_ARCH_MXC for mach-imx sub-architecture.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/plat-mxc')
41 files changed, 0 insertions, 5655 deletions
diff --git a/arch/arm/plat-mxc/3ds_debugboard.c b/arch/arm/plat-mxc/3ds_debugboard.c deleted file mode 100644 index 5c10ad05df7..00000000000 --- a/arch/arm/plat-mxc/3ds_debugboard.c +++ /dev/null @@ -1,213 +0,0 @@ -/* - * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright (C) 2010 Jason Wang <jason77.wang@gmail.com> - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include <linux/interrupt.h> -#include <linux/irq.h> -#include <linux/irqdomain.h> -#include <linux/io.h> -#include <linux/platform_device.h> -#include <linux/gpio.h> -#include <linux/module.h> -#include <linux/smsc911x.h> -#include <linux/regulator/machine.h> -#include <linux/regulator/fixed.h> - -#include <mach/hardware.h> - -/* LAN9217 ethernet base address */ -#define LAN9217_BASE_ADDR(n) (n + 0x0) -/* External UART */ -#define UARTA_BASE_ADDR(n) (n + 0x8000) -#define UARTB_BASE_ADDR(n) (n + 0x10000) - -#define BOARD_IO_ADDR(n) (n + 0x20000) -/* LED switchs */ -#define LED_SWITCH_REG 0x00 -/* buttons */ -#define SWITCH_BUTTONS_REG 0x08 -/* status, interrupt */ -#define INTR_STATUS_REG 0x10 -#define INTR_MASK_REG 0x38 -#define INTR_RESET_REG 0x20 -/* magic word for debug CPLD */ -#define MAGIC_NUMBER1_REG 0x40 -#define MAGIC_NUMBER2_REG 0x48 -/* CPLD code version */ -#define CPLD_CODE_VER_REG 0x50 -/* magic word for debug CPLD */ -#define MAGIC_NUMBER3_REG 0x58 -/* module reset register*/ -#define MODULE_RESET_REG 0x60 -/* CPU ID and Personality ID */ -#define MCU_BOARD_ID_REG 0x68 - -#define MXC_MAX_EXP_IO_LINES 16 - -/* interrupts like external uart , external ethernet etc*/ -#define EXPIO_INT_ENET 0 -#define EXPIO_INT_XUART_A 1 -#define EXPIO_INT_XUART_B 2 -#define EXPIO_INT_BUTTON_A 3 -#define EXPIO_INT_BUTTON_B 4 - -static void __iomem *brd_io; -static struct irq_domain *domain; - -static struct resource smsc911x_resources[] = { - { - .flags = IORESOURCE_MEM, - } , { - .flags = IORESOURCE_IRQ, - }, -}; - -static struct smsc911x_platform_config smsc911x_config = { - .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, - .flags = SMSC911X_USE_32BIT | SMSC911X_FORCE_INTERNAL_PHY, -}; - -static struct platform_device smsc_lan9217_device = { - .name = "smsc911x", - .id = -1, - .dev = { - .platform_data = &smsc911x_config, - }, - .num_resources = ARRAY_SIZE(smsc911x_resources), - .resource = smsc911x_resources, -}; - -static void mxc_expio_irq_handler(u32 irq, struct irq_desc *desc) -{ - u32 imr_val; - u32 int_valid; - u32 expio_irq; - - /* irq = gpio irq number */ - desc->irq_data.chip->irq_mask(&desc->irq_data); - - imr_val = __raw_readw(brd_io + INTR_MASK_REG); - int_valid = __raw_readw(brd_io + INTR_STATUS_REG) & ~imr_val; - - expio_irq = 0; - for (; int_valid != 0; int_valid >>= 1, expio_irq++) { - if ((int_valid & 1) == 0) - continue; - generic_handle_irq(irq_find_mapping(domain, expio_irq)); - } - - desc->irq_data.chip->irq_ack(&desc->irq_data); - desc->irq_data.chip->irq_unmask(&desc->irq_data); -} - -/* - * Disable an expio pin's interrupt by setting the bit in the imr. - * Irq is an expio virtual irq number - */ -static void expio_mask_irq(struct irq_data *d) -{ - u16 reg; - u32 expio = d->hwirq; - - reg = __raw_readw(brd_io + INTR_MASK_REG); - reg |= (1 << expio); - __raw_writew(reg, brd_io + INTR_MASK_REG); -} - -static void expio_ack_irq(struct irq_data *d) -{ - u32 expio = d->hwirq; - - __raw_writew(1 << expio, brd_io + INTR_RESET_REG); - __raw_writew(0, brd_io + INTR_RESET_REG); - expio_mask_irq(d); -} - -static void expio_unmask_irq(struct irq_data *d) -{ - u16 reg; - u32 expio = d->hwirq; - - reg = __raw_readw(brd_io + INTR_MASK_REG); - reg &= ~(1 << expio); - __raw_writew(reg, brd_io + INTR_MASK_REG); -} - -static struct irq_chip expio_irq_chip = { - .irq_ack = expio_ack_irq, - .irq_mask = expio_mask_irq, - .irq_unmask = expio_unmask_irq, -}; - -static struct regulator_consumer_supply dummy_supplies[] = { - REGULATOR_SUPPLY("vdd33a", "smsc911x"), - REGULATOR_SUPPLY("vddvario", "smsc911x"), -}; - -int __init mxc_expio_init(u32 base, u32 intr_gpio) -{ - u32 p_irq = gpio_to_irq(intr_gpio); - int irq_base; - int i; - - brd_io = ioremap(BOARD_IO_ADDR(base), SZ_4K); - if (brd_io == NULL) - return -ENOMEM; - - if ((__raw_readw(brd_io + MAGIC_NUMBER1_REG) != 0xAAAA) || - (__raw_readw(brd_io + MAGIC_NUMBER2_REG) != 0x5555) || - (__raw_readw(brd_io + MAGIC_NUMBER3_REG) != 0xCAFE)) { - pr_info("3-Stack Debug board not detected\n"); - iounmap(brd_io); - brd_io = NULL; - return -ENODEV; - } - - pr_info("3-Stack Debug board detected, rev = 0x%04X\n", - readw(brd_io + CPLD_CODE_VER_REG)); - - /* - * Configure INT line as GPIO input - */ - gpio_request(intr_gpio, "expio_pirq"); - gpio_direction_input(intr_gpio); - - /* disable the interrupt and clear the status */ - __raw_writew(0, brd_io + INTR_MASK_REG); - __raw_writew(0xFFFF, brd_io + INTR_RESET_REG); - __raw_writew(0, brd_io + INTR_RESET_REG); - __raw_writew(0x1F, brd_io + INTR_MASK_REG); - - irq_base = irq_alloc_descs(-1, 0, MXC_MAX_EXP_IO_LINES, numa_node_id()); - WARN_ON(irq_base < 0); - - domain = irq_domain_add_legacy(NULL, MXC_MAX_EXP_IO_LINES, irq_base, 0, - &irq_domain_simple_ops, NULL); - WARN_ON(!domain); - - for (i = irq_base; i < irq_base + MXC_MAX_EXP_IO_LINES; i++) { - irq_set_chip_and_handler(i, &expio_irq_chip, handle_level_irq); - set_irq_flags(i, IRQF_VALID); - } - irq_set_irq_type(p_irq, IRQF_TRIGGER_LOW); - irq_set_chained_handler(p_irq, mxc_expio_irq_handler); - - /* Register Lan device on the debugboard */ - regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies)); - - smsc911x_resources[0].start = LAN9217_BASE_ADDR(base); - smsc911x_resources[0].end = LAN9217_BASE_ADDR(base) + 0x100 - 1; - smsc911x_resources[1].start = irq_find_mapping(domain, EXPIO_INT_ENET); - smsc911x_resources[1].end = irq_find_mapping(domain, EXPIO_INT_ENET); - platform_device_register(&smsc_lan9217_device); - - return 0; -} diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig deleted file mode 100644 index 559c9d84627..00000000000 --- a/arch/arm/plat-mxc/Kconfig +++ /dev/null @@ -1,81 +0,0 @@ -if ARCH_MXC - -menu "Freescale MXC Implementations" - -choice - prompt "Freescale CPU family:" - default ARCH_IMX_V6_V7 - -config ARCH_IMX_V4_V5 - bool "i.MX1, i.MX21, i.MX25, i.MX27" - select ARM_PATCH_PHYS_VIRT - select AUTO_ZRELADDR if !ZBOOT_ROM - help - This enables support for systems based on the Freescale i.MX ARMv4 - and ARMv5 SoCs - -config ARCH_IMX_V6_V7 - bool "i.MX3, i.MX5, i.MX6" - select ARM_PATCH_PHYS_VIRT - select AUTO_ZRELADDR if !ZBOOT_ROM - select MIGHT_HAVE_CACHE_L2X0 - help - This enables support for systems based on the Freescale i.MX3, i.MX5 - and i.MX6 family. - -endchoice - -source "arch/arm/mach-imx/Kconfig" - -endmenu - -config MXC_IRQ_PRIOR - bool "Use IRQ priority" - help - Select this if you want to use prioritized IRQ handling. - This feature prevents higher priority ISR to be interrupted - by lower priority IRQ even IRQF_DISABLED flag is not set. - This may be useful in embedded applications, where are strong - requirements for timing. - Say N here, unless you have a specialized requirement. - -config MXC_TZIC - bool - -config MXC_AVIC - bool - -config MXC_DEBUG_BOARD - bool "Enable MXC debug board(for 3-stack)" - help - The debug board is an integral part of the MXC 3-stack(PDK) - platforms, it can be attached or removed from the peripheral - board. On debug board, several debug devices(ethernet, UART, - buttons, LEDs and JTAG) are implemented. Between the MCU and - these devices, a CPLD is added as a bridge which performs - data/address de-multiplexing and decode, signal level shift, - interrupt control and various board functions. - -config HAVE_EPIT - bool - -config MXC_USE_EPIT - bool "Use EPIT instead of GPT" - depends on HAVE_EPIT - help - Use EPIT as the system timer on systems that have it. Normally you - don't have a reason to do so as the EPIT has the same features and - uses the same clocks as the GPT. Anyway, on some systems the GPT - may be in use for other purposes. - -config MXC_ULPI - bool - -config ARCH_HAS_RNGA - bool - -config IRAM_ALLOC - bool - select GENERIC_ALLOCATOR - -endif diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile deleted file mode 100644 index e33d2d139ba..00000000000 --- a/arch/arm/plat-mxc/Makefile +++ /dev/null @@ -1,20 +0,0 @@ -# -# Makefile for the linux kernel. -# - -# Common support -obj-y := time.o cpu.o system.o irq-common.o - -obj-$(CONFIG_MXC_TZIC) += tzic.o -obj-$(CONFIG_MXC_AVIC) += avic.o - -obj-$(CONFIG_IRAM_ALLOC) += iram_alloc.o -obj-$(CONFIG_MXC_ULPI) += ulpi.o -obj-$(CONFIG_MXC_USE_EPIT) += epit.o -obj-$(CONFIG_MXC_DEBUG_BOARD) += 3ds_debugboard.o -obj-$(CONFIG_CPU_FREQ_IMX) += cpufreq.o -obj-$(CONFIG_CPU_IDLE) += cpuidle.o -ifdef CONFIG_SND_IMX_SOC -obj-y += ssi-fiq.o -obj-y += ssi-fiq-ksym.o -endif diff --git a/arch/arm/plat-mxc/avic.c b/arch/arm/plat-mxc/avic.c deleted file mode 100644 index cbd55c36def..00000000000 --- a/arch/arm/plat-mxc/avic.c +++ /dev/null @@ -1,225 +0,0 @@ -/* - * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Juergen Beisert, kernel@pengutronix.de - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#include <linux/module.h> -#include <linux/irq.h> -#include <linux/irqdomain.h> -#include <linux/io.h> -#include <linux/of.h> -#include <mach/common.h> -#include <asm/mach/irq.h> -#include <asm/exception.h> -#include <mach/hardware.h> -#include <mach/irqs.h> - -#include "irq-common.h" - -#define AVIC_INTCNTL 0x00 /* int control reg */ -#define AVIC_NIMASK 0x04 /* int mask reg */ -#define AVIC_INTENNUM 0x08 /* int enable number reg */ -#define AVIC_INTDISNUM 0x0C /* int disable number reg */ -#define AVIC_INTENABLEH 0x10 /* int enable reg high */ -#define AVIC_INTENABLEL 0x14 /* int enable reg low */ -#define AVIC_INTTYPEH 0x18 /* int type reg high */ -#define AVIC_INTTYPEL 0x1C /* int type reg low */ -#define AVIC_NIPRIORITY(x) (0x20 + 4 * (7 - (x))) /* int priority */ -#define AVIC_NIVECSR 0x40 /* norm int vector/status */ -#define AVIC_FIVECSR 0x44 /* fast int vector/status */ -#define AVIC_INTSRCH 0x48 /* int source reg high */ -#define AVIC_INTSRCL 0x4C /* int source reg low */ -#define AVIC_INTFRCH 0x50 /* int force reg high */ -#define AVIC_INTFRCL 0x54 /* int force reg low */ -#define AVIC_NIPNDH 0x58 /* norm int pending high */ -#define AVIC_NIPNDL 0x5C /* norm int pending low */ -#define AVIC_FIPNDH 0x60 /* fast int pending high */ -#define AVIC_FIPNDL 0x64 /* fast int pending low */ - -#define AVIC_NUM_IRQS 64 - -void __iomem *avic_base; -static struct irq_domain *domain; - -static u32 avic_saved_mask_reg[2]; - -#ifdef CONFIG_MXC_IRQ_PRIOR -static int avic_irq_set_priority(unsigned char irq, unsigned char prio) -{ - struct irq_data *d = irq_get_irq_data(irq); - unsigned int temp; - unsigned int mask = 0x0F << irq % 8 * 4; - - irq = d->hwirq; - - if (irq >= AVIC_NUM_IRQS) - return -EINVAL; - - temp = __raw_readl(avic_base + AVIC_NIPRIORITY(irq / 8)); - temp &= ~mask; - temp |= prio & mask; - - __raw_writel(temp, avic_base + AVIC_NIPRIORITY(irq / 8)); - - return 0; -} -#endif - -#ifdef CONFIG_FIQ -static int avic_set_irq_fiq(unsigned int irq, unsigned int type) -{ - struct irq_data *d = irq_get_irq_data(irq); - unsigned int irqt; - - irq = d->hwirq; - - if (irq >= AVIC_NUM_IRQS) - return -EINVAL; - - if (irq < AVIC_NUM_IRQS / 2) { - irqt = __raw_readl(avic_base + AVIC_INTTYPEL) & ~(1 << irq); - __raw_writel(irqt | (!!type << irq), avic_base + AVIC_INTTYPEL); - } else { - irq -= AVIC_NUM_IRQS / 2; - irqt = __raw_readl(avic_base + AVIC_INTTYPEH) & ~(1 << irq); - __raw_writel(irqt | (!!type << irq), avic_base + AVIC_INTTYPEH); - } - - return 0; -} -#endif /* CONFIG_FIQ */ - - -static struct mxc_extra_irq avic_extra_irq = { -#ifdef CONFIG_MXC_IRQ_PRIOR - .set_priority = avic_irq_set_priority, -#endif -#ifdef CONFIG_FIQ - .set_irq_fiq = avic_set_irq_fiq, -#endif -}; - -#ifdef CONFIG_PM -static void avic_irq_suspend(struct irq_data *d) -{ - struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); - struct irq_chip_type *ct = gc->chip_types; - int idx = d->hwirq >> 5; - - avic_saved_mask_reg[idx] = __raw_readl(avic_base + ct->regs.mask); - __raw_writel(gc->wake_active, avic_base + ct->regs.mask); -} - -static void avic_irq_resume(struct irq_data *d) -{ - struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); - struct irq_chip_type *ct = gc->chip_types; - int idx = d->hwirq >> 5; - - __raw_writel(avic_saved_mask_reg[idx], avic_base + ct->regs.mask); -} - -#else -#define avic_irq_suspend NULL -#define avic_irq_resume NULL -#endif - -static __init void avic_init_gc(int idx, unsigned int irq_start) -{ - struct irq_chip_generic *gc; - struct irq_chip_type *ct; - - gc = irq_alloc_generic_chip("mxc-avic", 1, irq_start, avic_base, - handle_level_irq); - gc->private = &avic_extra_irq; - gc->wake_enabled = IRQ_MSK(32); - - ct = gc->chip_types; - ct->chip.irq_mask = irq_gc_mask_clr_bit; - ct->chip.irq_unmask = irq_gc_mask_set_bit; - ct->chip.irq_ack = irq_gc_mask_clr_bit; - ct->chip.irq_set_wake = irq_gc_set_wake; - ct->chip.irq_suspend = avic_irq_suspend; - ct->chip.irq_resume = avic_irq_resume; - ct->regs.mask = !idx ? AVIC_INTENABLEL : AVIC_INTENABLEH; - ct->regs.ack = ct->regs.mask; - - irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0); -} - -asmlinkage void __exception_irq_entry avic_handle_irq(struct pt_regs *regs) -{ - u32 nivector; - - do { - nivector = __raw_readl(avic_base + AVIC_NIVECSR) >> 16; - if (nivector == 0xffff) - break; - - handle_IRQ(irq_find_mapping(domain, nivector), regs); - } while (1); -} - -/* - * This function initializes the AVIC hardware and disables all the - * interrupts. It registers the interrupt enable and disable functions - * to the kernel for each interrupt source. - */ -void __init mxc_init_irq(void __iomem *irqbase) -{ - struct device_node *np; - int irq_base; - int i; - - avic_base = irqbase; - - /* put the AVIC into the reset value with - * all interrupts disabled - */ - __raw_writel(0, avic_base + AVIC_INTCNTL); - __raw_writel(0x1f, avic_base + AVIC_NIMASK); - - /* disable all interrupts */ - __raw_writel(0, avic_base + AVIC_INTENABLEH); - __raw_writel(0, avic_base + AVIC_INTENABLEL); - - /* all IRQ no FIQ */ - __raw_writel(0, avic_base + AVIC_INTTYPEH); - __raw_writel(0, avic_base + AVIC_INTTYPEL); - - irq_base = irq_alloc_descs(-1, 0, AVIC_NUM_IRQS, numa_node_id()); - WARN_ON(irq_base < 0); - - np = of_find_compatible_node(NULL, NULL, "fsl,avic"); - domain = irq_domain_add_legacy(np, AVIC_NUM_IRQS, irq_base, 0, - &irq_domain_simple_ops, NULL); - WARN_ON(!domain); - - for (i = 0; i < AVIC_NUM_IRQS / 32; i++, irq_base += 32) - avic_init_gc(i, irq_base); - - /* Set default priority value (0) for all IRQ's */ - for (i = 0; i < 8; i++) - __raw_writel(0, avic_base + AVIC_NIPRIORITY(i)); - -#ifdef CONFIG_FIQ - /* Initialize FIQ */ - init_FIQ(FIQ_START); -#endif - - printk(KERN_INFO "MXC IRQ initialized\n"); -} diff --git a/arch/arm/plat-mxc/cpu.c b/arch/arm/plat-mxc/cpu.c deleted file mode 100644 index 220dd6f9312..00000000000 --- a/arch/arm/plat-mxc/cpu.c +++ /dev/null @@ -1,44 +0,0 @@ - -#include <linux/module.h> -#include <linux/io.h> -#include <mach/hardware.h> - -unsigned int __mxc_cpu_type; -EXPORT_SYMBOL(__mxc_cpu_type); - -void mxc_set_cpu_type(unsigned int type) -{ - __mxc_cpu_type = type; -} - -void imx_print_silicon_rev(const char *cpu, int srev) -{ - if (srev == IMX_CHIP_REVISION_UNKNOWN) - pr_info("CPU identified as %s, unknown revision\n", cpu); - else - pr_info("CPU identified as %s, silicon rev %d.%d\n", - cpu, (srev >> 4) & 0xf, srev & 0xf); -} - -void __init imx_set_aips(void __iomem *base) -{ - unsigned int reg; -/* - * Set all MPROTx to be non-bufferable, trusted for R/W, - * not forced to user-mode. - */ - __raw_writel(0x77777777, base + 0x0); - __raw_writel(0x77777777, base + 0x4); - -/* - * Set all OPACRx to be non-bufferable, to not require - * supervisor privilege level for access, allow for - * write access and untrusted master access. - */ - __raw_writel(0x0, base + 0x40); - __raw_writel(0x0, base + 0x44); - __raw_writel(0x0, base + 0x48); - __raw_writel(0x0, base + 0x4C); - reg = __raw_readl(base + 0x50) & 0x00FFFFFF; - __raw_writel(reg, base + 0x50); -} diff --git a/arch/arm/plat-mxc/cpufreq.c b/arch/arm/plat-mxc/cpufreq.c deleted file mode 100644 index b5b6f808313..00000000000 --- a/arch/arm/plat-mxc/cpufreq.c +++ /dev/null @@ -1,205 +0,0 @@ -/* - * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/* - * A driver for the Freescale Semiconductor i.MXC CPUfreq module. - * The CPUFREQ driver is for controlling CPU frequency. It allows you to change - * the CPU clock speed on the fly. - */ - -#include <linux/module.h> -#include <linux/cpufreq.h> -#include <linux/clk.h> -#include <linux/err.h> -#include <linux/slab.h> -#include <mach/hardware.h> - -#define CLK32_FREQ 32768 -#define NANOSECOND (1000 * 1000 * 1000) - -struct cpu_op *(*get_cpu_op)(int *op); - -static int cpu_freq_khz_min; -static int cpu_freq_khz_max; - -static struct clk *cpu_clk; -static struct cpufreq_frequency_table *imx_freq_table; - -static int cpu_op_nr; -static struct cpu_op *cpu_op_tbl; - -static int set_cpu_freq(int freq) -{ - int ret = 0; - int org_cpu_rate; - - org_cpu_rate = clk_get_rate(cpu_clk); - if (org_cpu_rate == freq) - return ret; - - ret = clk_set_rate(cpu_clk, freq); - if (ret != 0) { - printk(KERN_DEBUG "cannot set CPU clock rate\n"); - return ret; - } - - return ret; -} - -static int mxc_verify_speed(struct cpufreq_policy *policy) -{ - if (policy->cpu != 0) - return -EINVAL; - - return cpufreq_frequency_table_verify(policy, imx_freq_table); -} - -static unsigned int mxc_get_speed(unsigned int cpu) -{ - if (cpu) - return 0; - - return clk_get_rate(cpu_clk) / 1000; -} - -static int mxc_set_target(struct cpufreq_policy *policy, - unsigned int target_freq, unsigned int relation) -{ - struct cpufreq_freqs freqs; - int freq_Hz; - int ret = 0; - unsigned int index; - - cpufreq_frequency_table_target(policy, imx_freq_table, - target_freq, relation, &index); - freq_Hz = imx_freq_table[index].frequency * 1000; - - freqs.old = clk_get_rate(cpu_clk) / 1000; - freqs.new = freq_Hz / 1000; - freqs.cpu = 0; - freqs.flags = 0; - cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); - - ret = set_cpu_freq(freq_Hz); - - cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); - - return ret; -} - -static int mxc_cpufreq_init(struct cpufreq_policy *policy) -{ - int ret; - int i; - - printk(KERN_INFO "i.MXC CPU frequency driver\n"); - - if (policy->cpu != 0) - return -EINVAL; - - if (!get_cpu_op) - return -EINVAL; - - cpu_clk = clk_get(NULL, "cpu_clk"); - if (IS_ERR(cpu_clk)) { - printk(KERN_ERR "%s: failed to get cpu clock\n", __func__); - return PTR_ERR(cpu_clk); - } - - cpu_op_tbl = get_cpu_op(&cpu_op_nr); - - cpu_freq_khz_min = cpu_op_tbl[0].cpu_rate / 1000; - cpu_freq_khz_max = cpu_op_tbl[0].cpu_rate / 1000; - - imx_freq_table = kmalloc( - sizeof(struct cpufreq_frequency_table) * (cpu_op_nr + 1), - GFP_KERNEL); - if (!imx_freq_table) { - ret = -ENOMEM; - goto err1; - } - - for (i = 0; i < cpu_op_nr; i++) { - imx_freq_table[i].index = i; - imx_freq_table[i].frequency = cpu_op_tbl[i].cpu_rate / 1000; - - if ((cpu_op_tbl[i].cpu_rate / 1000) < cpu_freq_khz_min) - cpu_freq_khz_min = cpu_op_tbl[i].cpu_rate / 1000; - - if ((cpu_op_tbl[i].cpu_rate / 1000) > cpu_freq_khz_max) - cpu_freq_khz_max = cpu_op_tbl[i].cpu_rate / 1000; - } - - imx_freq_table[i].index = i; - imx_freq_table[i].frequency = CPUFREQ_TABLE_END; - - policy->cur = clk_get_rate(cpu_clk) / 1000; - policy->min = policy->cpuinfo.min_freq = cpu_freq_khz_min; - policy->max = policy->cpuinfo.max_freq = cpu_freq_khz_max; - - /* Manual states, that PLL stabilizes in two CLK32 periods */ - policy->cpuinfo.transition_latency = 2 * NANOSECOND / CLK32_FREQ; - - ret = cpufreq_frequency_table_cpuinfo(policy, imx_freq_table); - - if (ret < 0) { - printk(KERN_ERR "%s: failed to register i.MXC CPUfreq with error code %d\n", - __func__, ret); - goto err; - } - - cpufreq_frequency_table_get_attr(imx_freq_table, policy->cpu); - return 0; -err: - kfree(imx_freq_table); -err1: - clk_put(cpu_clk); - return ret; -} - -static int mxc_cpufreq_exit(struct cpufreq_policy *policy) -{ - cpufreq_frequency_table_put_attr(policy->cpu); - - set_cpu_freq(cpu_freq_khz_max * 1000); - clk_put(cpu_clk); - kfree(imx_freq_table); - return 0; -} - -static struct cpufreq_driver mxc_driver = { - .flags = CPUFREQ_STICKY, - .verify = mxc_verify_speed, - .target = mxc_set_target, - .get = mxc_get_speed, - .init = mxc_cpufreq_init, - .exit = mxc_cpufreq_exit, - .name = "imx", -}; - -static int __devinit mxc_cpufreq_driver_init(void) -{ - return cpufreq_register_driver(&mxc_driver); -} - -static void mxc_cpufreq_driver_exit(void) -{ - cpufreq_unregister_driver(&mxc_driver); -} - -module_init(mxc_cpufreq_driver_init); -module_exit(mxc_cpufreq_driver_exit); - -MODULE_AUTHOR("Freescale Semiconductor Inc. Yong Shen <yong.shen@linaro.org>"); -MODULE_DESCRIPTION("CPUfreq driver for i.MX"); -MODULE_LICENSE("GPL"); diff --git a/arch/arm/plat-mxc/cpuidle.c b/arch/arm/plat-mxc/cpuidle.c deleted file mode 100644 index d4cb511a44a..00000000000 --- a/arch/arm/plat-mxc/cpuidle.c +++ /dev/null @@ -1,80 +0,0 @@ -/* - * Copyright 2012 Freescale Semiconductor, Inc. - * Copyright 2012 Linaro Ltd. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include <linux/cpuidle.h> -#include <linux/err.h> -#include <linux/hrtimer.h> -#include <linux/io.h> -#include <linux/kernel.h> -#include <linux/slab.h> - -static struct cpuidle_device __percpu * imx_cpuidle_devices; - -static void __init imx_cpuidle_devices_uninit(void) -{ - int cpu_id; - struct cpuidle_device *dev; - - for_each_possible_cpu(cpu_id) { - dev = per_cpu_ptr(imx_cpuidle_devices, cpu_id); - cpuidle_unregister_device(dev); - } - - free_percpu(imx_cpuidle_devices); -} - -int __init imx_cpuidle_init(struct cpuidle_driver *drv) -{ - struct cpuidle_device *dev; - int cpu_id, ret; - - if (drv->state_count > CPUIDLE_STATE_MAX) { - pr_err("%s: state_count exceeds maximum\n", __func__); - return -EINVAL; - } - - ret = cpuidle_register_driver(drv); - if (ret) { - pr_err("%s: Failed to register cpuidle driver with error: %d\n", - __func__, ret); - return ret; - } - - imx_cpuidle_devices = alloc_percpu(struct cpuidle_device); - if (imx_cpuidle_devices == NULL) { - ret = -ENOMEM; - goto unregister_drv; - } - - /* initialize state data for each cpuidle_device */ - for_each_possible_cpu(cpu_id) { - dev = per_cpu_ptr(imx_cpuidle_devices, cpu_id); - dev->cpu = cpu_id; - dev->state_count = drv->state_count; - - ret = cpuidle_register_device(dev); - if (ret) { - pr_err("%s: Failed to register cpu %u, error: %d\n", - __func__, cpu_id, ret); - goto uninit; - } - } - - return 0; - -uninit: - imx_cpuidle_devices_uninit(); - -unregister_drv: - cpuidle_unregister_driver(drv); - return ret; -} diff --git a/arch/arm/plat-mxc/epit.c b/arch/arm/plat-mxc/epit.c deleted file mode 100644 index 88726f4dbbf..00000000000 --- a/arch/arm/plat-mxc/epit.c +++ /dev/null @@ -1,234 +0,0 @@ -/* - * linux/arch/arm/plat-mxc/epit.c - * - * Copyright (C) 2010 Sascha Hauer <s.hauer@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#define EPITCR 0x00 -#define EPITSR 0x04 -#define EPITLR 0x08 -#define EPITCMPR 0x0c -#define EPITCNR 0x10 - -#define EPITCR_EN (1 << 0) -#define EPITCR_ENMOD (1 << 1) -#define EPITCR_OCIEN (1 << 2) -#define EPITCR_RLD (1 << 3) -#define EPITCR_PRESC(x) (((x) & 0xfff) << 4) -#define EPITCR_SWR (1 << 16) -#define EPITCR_IOVW (1 << 17) -#define EPITCR_DBGEN (1 << 18) -#define EPITCR_WAITEN (1 << 19) -#define EPITCR_RES (1 << 20) -#define EPITCR_STOPEN (1 << 21) -#define EPITCR_OM_DISCON (0 << 22) -#define EPITCR_OM_TOGGLE (1 << 22) -#define EPITCR_OM_CLEAR (2 << 22) -#define EPITCR_OM_SET (3 << 22) -#define EPITCR_CLKSRC_OFF (0 << 24) -#define EPITCR_CLKSRC_PERIPHERAL (1 << 24) -#define EPITCR_CLKSRC_REF_HIGH (1 << 24) -#define EPITCR_CLKSRC_REF_LOW (3 << 24) - -#define EPITSR_OCIF (1 << 0) - -#include <linux/interrupt.h> -#include <linux/irq.h> -#include <linux/clockchips.h> -#include <linux/clk.h> -#include <linux/err.h> - -#include <mach/hardware.h> -#include <asm/mach/time.h> -#include <mach/common.h> - -static struct clock_event_device clockevent_epit; -static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED; - -static void __iomem *timer_base; - -static inline void epit_irq_disable(void) -{ - u32 val; - - val = __raw_readl(timer_base + EPITCR); - val &= ~EPITCR_OCIEN; - __raw_writel(val, timer_base + EPITCR); -} - -static inline void epit_irq_enable(void) -{ - u32 val; - - val = __raw_readl(timer_base + EPITCR); - val |= EPITCR_OCIEN; - __raw_writel(val, timer_base + EPITCR); -} - -static void epit_irq_acknowledge(void) -{ - __raw_writel(EPITSR_OCIF, timer_base + EPITSR); -} - -static int __init epit_clocksource_init(struct clk *timer_clk) -{ - unsigned int c = clk_get_rate(timer_clk); - - return clocksource_mmio_init(timer_base + EPITCNR, "epit", c, 200, 32, - clocksource_mmio_readl_down); -} - -/* clock event */ - -static int epit_set_next_event(unsigned long evt, - struct clock_event_device *unused) -{ - unsigned long tcmp; - - tcmp = __raw_readl(timer_base + EPITCNR); - - __raw_writel(tcmp - evt, timer_base + EPITCMPR); - - return 0; -} - -static void epit_set_mode(enum clock_event_mode mode, - struct clock_event_device *evt) -{ - unsigned long flags; - - /* - * The timer interrupt generation is disabled at least - * for enough time to call epit_set_next_event() - */ - local_irq_save(flags); - - /* Disable interrupt in GPT module */ - epit_irq_disable(); - - if (mode != clockevent_mode) { - /* Set event time into far-far future */ - - /* Clear pending interrupt */ - epit_irq_acknowledge(); - } - - /* Remember timer mode */ - clockevent_mode = mode; - local_irq_restore(flags); - - switch (mode) { - case CLOCK_EVT_MODE_PERIODIC: - printk(KERN_ERR "epit_set_mode: Periodic mode is not " - "supported for i.MX EPIT\n"); - break; - case CLOCK_EVT_MODE_ONESHOT: - /* - * Do not put overhead of interrupt enable/disable into - * epit_set_next_event(), the core has about 4 minutes - * to call epit_set_next_event() or shutdown clock after - * mode switching - */ - local_irq_save(flags); - epit_irq_enable(); - local_irq_restore(flags); - break; - case CLOCK_EVT_MODE_SHUTDOWN: - case CLOCK_EVT_MODE_UNUSED: - case CLOCK_EVT_MODE_RESUME: - /* Left event sources disabled, no more interrupts appear */ - break; - } -} - -/* - * IRQ handler for the timer - */ -static irqreturn_t epit_timer_interrupt(int irq, void *dev_id) -{ - struct clock_event_device *evt = &clockevent_epit; - - epit_irq_acknowledge(); - - evt->event_handler(evt); - - return IRQ_HANDLED; -} - -static struct irqaction epit_timer_irq = { - .name = "i.MX EPIT Timer Tick", - .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, - .handler = epit_timer_interrupt, -}; - -static struct clock_event_device clockevent_epit = { - .name = "epit", - .features = CLOCK_EVT_FEAT_ONESHOT, - .shift = 32, - .set_mode = epit_set_mode, - .set_next_event = epit_set_next_event, - .rating = 200, -}; - -static int __init epit_clockevent_init(struct clk *timer_clk) -{ - unsigned int c = clk_get_rate(timer_clk); - - clockevent_epit.mult = div_sc(c, NSEC_PER_SEC, - clockevent_epit.shift); - clockevent_epit.max_delta_ns = - clockevent_delta2ns(0xfffffffe, &clockevent_epit); - clockevent_epit.min_delta_ns = - clockevent_delta2ns(0x800, &clockevent_epit); - - clockevent_epit.cpumask = cpumask_of(0); - - clockevents_register_device(&clockevent_epit); - - return 0; -} - -void __init epit_timer_init(void __iomem *base, int irq) -{ - struct clk *timer_clk; - - timer_clk = clk_get_sys("imx-epit.0", NULL); - if (IS_ERR(timer_clk)) { - pr_err("i.MX epit: unable to get clk\n"); - return; - } - - clk_prepare_enable(timer_clk); - - timer_base = base; - - /* - * Initialise to a known state (all timers off, and timing reset) - */ - __raw_writel(0x0, timer_base + EPITCR); - - __raw_writel(0xffffffff, timer_base + EPITLR); - __raw_writel(EPITCR_EN | EPITCR_CLKSRC_REF_HIGH | EPITCR_WAITEN, - timer_base + EPITCR); - - /* init and register the timer to the framework */ - epit_clocksource_init(timer_clk); - epit_clockevent_init(timer_clk); - - /* Make irqs happen */ - setup_irq(irq, &epit_timer_irq); -} diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h deleted file mode 100644 index ead901814c0..00000000000 --- a/arch/arm/plat-mxc/include/mach/common.h +++ /dev/null @@ -1,162 +0,0 @@ -/* - * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. - */ - -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ASM_ARCH_MXC_COMMON_H__ -#define __ASM_ARCH_MXC_COMMON_H__ - -struct platform_device; -struct clk; -enum mxc_cpu_pwr_mode; - -extern void mx1_map_io(void); -extern void mx21_map_io(void); -extern void mx25_map_io(void); -extern void mx27_map_io(void); -extern void mx31_map_io(void); -extern void mx35_map_io(void); -extern void mx50_map_io(void); -extern void mx51_map_io(void); -extern void mx53_map_io(void); -extern void imx1_init_early(void); -extern void imx21_init_early(void); -extern void imx25_init_early(void); -extern void imx27_init_early(void); -extern void imx31_init_early(void); -extern void imx35_init_early(void); -extern void imx50_init_early(void); -extern void imx51_init_early(void); -extern void imx53_init_early(void); -extern void mxc_init_irq(void __iomem *); -extern void tzic_init_irq(void __iomem *); -extern void mx1_init_irq(void); -extern void mx21_init_irq(void); -extern void mx25_init_irq(void); -extern void mx27_init_irq(void); -extern void mx31_init_irq(void); -extern void mx35_init_irq(void); -extern void mx50_init_irq(void); -extern void mx51_init_irq(void); -extern void mx53_init_irq(void); -extern void imx1_soc_init(void); -extern void imx21_soc_init(void); -extern void imx25_soc_init(void); -extern void imx27_soc_init(void); -extern void imx31_soc_init(void); -extern void imx35_soc_init(void); -extern void imx50_soc_init(void); -extern void imx51_soc_init(void); -extern void imx51_init_late(void); -extern void imx53_init_late(void); -extern void epit_timer_init(void __iomem *base, int irq); -extern void mxc_timer_init(void __iomem *, int); -extern int mx1_clocks_init(unsigned long fref); -extern int mx21_clocks_init(unsigned long lref, unsigned long fref); -extern int mx25_clocks_init(void); -extern int mx27_clocks_init(unsigned long fref); -extern int mx31_clocks_init(unsigned long fref); -extern int mx35_clocks_init(void); -extern int mx51_clocks_init(unsigned long ckil, unsigned long osc, - unsigned long ckih1, unsigned long ckih2); -extern int mx53_clocks_init(unsigned long ckil, unsigned long osc, - unsigned long ckih1, unsigned long ckih2); -extern int mx27_clocks_init_dt(void); -extern int mx31_clocks_init_dt(void); -extern int mx51_clocks_init_dt(void); -extern int mx53_clocks_init_dt(void); -extern int mx6q_clocks_init(void); -extern struct platform_device *mxc_register_gpio(char *name, int id, - resource_size_t iobase, resource_size_t iosize, int irq, int irq_high); -extern void mxc_set_cpu_type(unsigned int type); -extern void mxc_restart(char, const char *); -extern void mxc_arch_reset_init(void __iomem *); -extern int mx53_revision(void); -extern int mx53_display_revision(void); -extern void imx_set_aips(void __iomem *); - -enum mxc_cpu_pwr_mode { - WAIT_CLOCKED, /* wfi only */ - WAIT_UNCLOCKED, /* WAIT */ - WAIT_UNCLOCKED_POWER_OFF, /* WAIT + SRPG */ - STOP_POWER_ON, /* just STOP */ - STOP_POWER_OFF, /* STOP + SRPG */ -}; - -enum mx3_cpu_pwr_mode { - MX3_RUN, - MX3_WAIT, - MX3_DOZE, - MX3_SLEEP, -}; - -extern void mx3_cpu_lp_set(enum mx3_cpu_pwr_mode mode); -extern void imx_print_silicon_rev(const char *cpu, int srev); - -void avic_handle_irq(struct pt_regs *); -void tzic_handle_irq(struct pt_regs *); - -#define imx1_handle_irq avic_handle_irq -#define imx21_handle_irq avic_handle_irq -#define imx25_handle_irq avic_handle_irq -#define imx27_handle_irq avic_handle_irq -#define imx31_handle_irq avic_handle_irq -#define imx35_handle_irq avic_handle_irq -#define imx50_handle_irq tzic_handle_irq -#define imx51_handle_irq tzic_handle_irq -#define imx53_handle_irq tzic_handle_irq -#define imx6q_handle_irq gic_handle_irq - -extern void imx_enable_cpu(int cpu, bool enable); -extern void imx_set_cpu_jump(int cpu, void *jump_addr); -#ifdef CONFIG_DEBUG_LL -extern void imx_lluart_map_io(void); -#else -static inline void imx_lluart_map_io(void) {} -#endif -extern void v7_cpu_resume(void); -extern u32 *pl310_get_save_ptr(void); -#ifdef CONFIG_SMP -extern void v7_secondary_startup(void); -extern void imx_scu_map_io(void); -extern void imx_smp_prepare(void); -#else -static inline void imx_scu_map_io(void) {} -static inline void imx_smp_prepare(void) {} -#endif -extern void imx_enable_cpu(int cpu, bool enable); -extern void imx_set_cpu_jump(int cpu, void *jump_addr); -extern void imx_src_init(void); -extern void imx_src_prepare_restart(void); -extern void imx_gpc_init(void); -extern void imx_gpc_pre_suspend(void); -extern void imx_gpc_post_resume(void); -extern int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode); -extern void imx6q_clock_map_io(void); - -extern void imx_cpu_die(unsigned int cpu); - -#ifdef CONFIG_PM -extern void imx6q_pm_init(void); -extern void imx51_pm_init(void); -extern void imx53_pm_init(void); -#else -static inline void imx6q_pm_init(void) {} -static inline void imx51_pm_init(void) {} -static inline void imx53_pm_init(void) {} -#endif - -#ifdef CONFIG_NEON -extern int mx51_neon_fixup(void); -#else -static inline int mx51_neon_fixup(void) { return 0; } -#endif - -extern struct smp_operations imx_smp_ops; - -#endif diff --git a/arch/arm/plat-mxc/include/mach/cpuidle.h b/arch/arm/plat-mxc/include/mach/cpuidle.h deleted file mode 100644 index bc932d1af37..00000000000 --- a/arch/arm/plat-mxc/include/mach/cpuidle.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Copyright 2012 Freescale Semiconductor, Inc. - * Copyright 2012 Linaro Ltd. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include <linux/cpuidle.h> - -#ifdef CONFIG_CPU_IDLE -extern int imx_cpuidle_init(struct cpuidle_driver *drv); -#else -static inline int imx_cpuidle_init(struct cpuidle_driver *drv) -{ - return -ENODEV; -} -#endif diff --git a/arch/arm/plat-mxc/include/mach/debug-macro.S b/arch/arm/plat-mxc/include/mach/debug-macro.S deleted file mode 100644 index 761e45f9456..00000000000 --- a/arch/arm/plat-mxc/include/mach/debug-macro.S +++ /dev/null @@ -1,51 +0,0 @@ -/* arch/arm/mach-imx/include/mach/debug-macro.S - * - * Debugging macro include header - * - * Copyright (C) 1994-1999 Russell King - * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ -#include <mach/hardware.h> - -#ifdef CONFIG_DEBUG_IMX1_UART -#define UART_PADDR MX1_UART1_BASE_ADDR -#elif defined (CONFIG_DEBUG_IMX25_UART) -#define UART_PADDR MX25_UART1_BASE_ADDR -#elif defined (CONFIG_DEBUG_IMX21_IMX27_UART) -#define UART_PADDR MX2x_UART1_BASE_ADDR -#elif defined (CONFIG_DEBUG_IMX31_IMX35_UART) -#define UART_PADDR MX3x_UART1_BASE_ADDR -#elif defined (CONFIG_DEBUG_IMX51_UART) -#define UART_PADDR MX51_UART1_BASE_ADDR -#elif defined (CONFIG_DEBUG_IMX50_IMX53_UART) -#define UART_PADDR MX53_UART1_BASE_ADDR -#elif defined (CONFIG_DEBUG_IMX6Q_UART2) -#define UART_PADDR MX6Q_UART2_BASE_ADDR -#elif defined (CONFIG_DEBUG_IMX6Q_UART4) -#define UART_PADDR MX6Q_UART4_BASE_ADDR -#endif - -#define UART_VADDR IMX_IO_ADDRESS(UART_PADDR) - - .macro addruart, rp, rv, tmp - ldr \rp, =UART_PADDR @ physical - ldr \rv, =UART_VADDR @ virtual - .endm - - .macro senduart,rd,rx - str \rd, [\rx, #0x40] @ TXDATA - .endm - - .macro waituart,rd,rx - .endm - - .macro busyuart,rd,rx -1002: ldr \rd, [\rx, #0x98] @ SR2 - tst \rd, #1 << 3 @ TXDC - beq 1002b @ wait until transmit done - .endm diff --git a/arch/arm/plat-mxc/include/mach/hardware.h b/arch/arm/plat-mxc/include/mach/hardware.h deleted file mode 100644 index ebf10654bb4..00000000000 --- a/arch/arm/plat-mxc/include/mach/hardware.h +++ /dev/null @@ -1,134 +0,0 @@ -/* - * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Juergen Beisert, kernel@pengutronix.de - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#ifndef __ASM_ARCH_MXC_HARDWARE_H__ -#define __ASM_ARCH_MXC_HARDWARE_H__ - -#include <asm/sizes.h> - -#define addr_in_module(addr, mod) \ - ((unsigned long)(addr) - mod ## _BASE_ADDR < mod ## _SIZE) - -#define IMX_IO_P2V_MODULE(addr, module) \ - (((addr) - module ## _BASE_ADDR) < module ## _SIZE ? \ - (addr) - (module ## _BASE_ADDR) + (module ## _BASE_ADDR_VIRT) : 0) - -/* - * This is rather complicated for humans and ugly to verify, but for a machine - * it's OK. Still more as it is usually only applied to constants. The upsides - * on using this approach are: - * - * - same mapping on all i.MX machines - * - works for assembler, too - * - no need to nurture #defines for virtual addresses - * - * The downside it, it's hard to verify (but I have a script for that). - * - * Obviously this needs to be injective for each SoC. In general it maps the - * whole address space to [0xf4000000, 0xf5ffffff]. So [0xf6000000,0xfeffffff] - * is free for per-machine use (e.g. KZM_ARM11_01 uses 64MiB there). - * - * It applies the following mappings for the different SoCs: - * - * mx1: - * IO 0x00200000+0x100000 -> 0xf4000000+0x100000 - * mx21: - * AIPI 0x10000000+0x100000 -> 0xf4400000+0x100000 - * SAHB1 0x80000000+0x100000 -> 0xf5000000+0x100000 - * X_MEMC 0xdf000000+0x004000 -> 0xf5f00000+0x004000 - * mx25: - * AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000 - * AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000 - * AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000 - * mx27: - * AIPI 0x10000000+0x100000 -> 0xf4400000+0x100000 - * SAHB1 0x80000000+0x100000 -> 0xf5000000+0x100000 - * X_MEMC 0xd8000000+0x100000 -> 0xf5c00000+0x100000 - * mx31: - * AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000 - * AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000 - * AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000 - * X_MEMC 0xb8000000+0x010000 -> 0xf5c00000+0x010000 - * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000 - * mx35: - * AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000 - * AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000 - * AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000 - * X_MEMC 0xb8000000+0x010000 -> 0xf5c00000+0x010000 - * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000 - * mx50: - * TZIC 0x0fffc000+0x004000 -> 0xf4bfc000+0x004000 - * AIPS1 0x53f00000+0x100000 -> 0xf5700000+0x100000 - * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000 - * AIPS2 0x63f00000+0x100000 -> 0xf5300000+0x100000 - * mx51: - * TZIC 0x0fffc000+0x004000 -> 0xf4bfc000+0x004000 - * IRAM 0x1ffe0000+0x020000 -> 0xf4fe0000+0x020000 - * DEBUG 0x60000000+0x100000 -> 0xf5000000+0x100000 - * SPBA0 0x70000000+0x100000 -> 0xf5400000+0x100000 - * AIPS1 0x73f00000+0x100000 -> 0xf5700000+0x100000 - * AIPS2 0x83f00000+0x100000 -> 0xf5300000+0x100000 - * mx53: - * TZIC 0x0fffc000+0x004000 -> 0xf4bfc000+0x004000 - * DEBUG 0x40000000+0x100000 -> 0xf5000000+0x100000 - * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000 - * AIPS1 0x53f00000+0x100000 -> 0xf5700000+0x100000 - * AIPS2 0x63f00000+0x100000 -> 0xf5300000+0x100000 - * mx6q: - * SCU 0x00a00000+0x004000 -> 0xf4000000+0x004000 - * CCM 0x020c4000+0x004000 -> 0xf42c4000+0x004000 - * ANATOP 0x020c8000+0x004000 -> 0xf42c8000+0x004000 - * UART4 0x021f0000+0x004000 -> 0xf42f0000+0x004000 - */ -#define IMX_IO_P2V(x) ( \ - (((x) & 0x80000000) >> 7) | \ - (0xf4000000 + \ - (((x) & 0x50000000) >> 6) + \ - (((x) & 0x0b000000) >> 4) + \ - (((x) & 0x000fffff)))) - -#define IMX_IO_ADDRESS(x) IOMEM(IMX_IO_P2V(x)) - -#include <mach/mxc.h> - -#include <mach/mx6q.h> -#include <mach/mx50.h> -#include <mach/mx51.h> -#include <mach/mx53.h> -#include <mach/mx3x.h> -#include <mach/mx31.h> -#include <mach/mx35.h> -#include <mach/mx2x.h> -#include <mach/mx21.h> -#include <mach/mx27.h> -#include <mach/mx1.h> -#include <mach/mx25.h> - -#define imx_map_entry(soc, name, _type) { \ - .virtual = soc ## _IO_P2V(soc ## _ ## name ## _BASE_ADDR), \ - .pfn = __phys_to_pfn(soc ## _ ## name ## _BASE_ADDR), \ - .length = soc ## _ ## name ## _SIZE, \ - .type = _type, \ -} - -/* There's a off-by-one betweem the gpio bank number and the gpiochip */ -/* range e.g. GPIO_1_5 is gpio 5 under linux */ -#define IMX_GPIO_NR(bank, nr) (((bank) - 1) * 32 + (nr)) - -#endif /* __ASM_ARCH_MXC_HARDWARE_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/iim.h b/arch/arm/plat-mxc/include/mach/iim.h deleted file mode 100644 index 315bffadafd..00000000000 --- a/arch/arm/plat-mxc/include/mach/iim.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Juergen Beisert, kernel@pengutronix.de - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#ifndef __ASM_ARCH_MXC_IIM_H__ -#define __ASM_ARCH_MXC_IIM_H__ - -/* Register offsets */ -#define MXC_IIMSTAT 0x0000 -#define MXC_IIMSTATM 0x0004 -#define MXC_IIMERR 0x0008 -#define MXC_IIMEMASK 0x000C -#define MXC_IIMFCTL 0x0010 -#define MXC_IIMUA 0x0014 -#define MXC_IIMLA 0x0018 -#define MXC_IIMSDAT 0x001C -#define MXC_IIMPREV 0x0020 -#define MXC_IIMSREV 0x0024 -#define MXC_IIMPRG_P 0x0028 -#define MXC_IIMSCS0 0x002C -#define MXC_IIMSCS1 0x0030 -#define MXC_IIMSCS2 0x0034 -#define MXC_IIMSCS3 0x0038 -#define MXC_IIMFBAC0 0x0800 -#define MXC_IIMJAC 0x0804 -#define MXC_IIMHWV1 0x0808 -#define MXC_IIMHWV2 0x080C -#define MXC_IIMHAB0 0x0810 -#define MXC_IIMHAB1 0x0814 -/* Definitions for i.MX27 TO2 */ -#define MXC_IIMMAC 0x0814 -#define MXC_IIMPREV_FUSE 0x0818 -#define MXC_IIMSREV_FUSE 0x081C -#define MXC_IIMSJC_CHALL_0 0x0820 -#define MXC_IIMSJC_CHALL_7 0x083C -#define MXC_IIMFB0UC17 0x0840 -#define MXC_IIMFB0UC255 0x0BFC -#define MXC_IIMFBAC1 0x0C00 -/* Definitions for i.MX27 TO2 */ -#define MXC_IIMSUID 0x0C04 -#define MXC_IIMKEY0 0x0C04 -#define MXC_IIMKEY20 0x0C54 -#define MXC_IIMSJC_RESP_0 0x0C58 -#define MXC_IIMSJC_RESP_7 0x0C74 -#define MXC_IIMFB1UC30 0x0C78 -#define MXC_IIMFB1UC255 0x0FFC - -/* Bit definitions */ - -#define MXC_IIMHWV1_WLOCK (0x1 << 7) -#define MXC_IIMHWV1_MCU_ENDIAN (0x1 << 6) -#define MXC_IIMHWV1_DSP_ENDIAN (0x1 << 5) -#define MXC_IIMHWV1_BOOT_INT (0x1 << 4) -#define MXC_IIMHWV1_SCC_DISABLE (0x1 << 3) -#define MXC_IIMHWV1_HANTRO_DISABLE (0x1 << 2) -#define MXC_IIMHWV1_MEMSTICK_DIS (0x1 << 1) - -#define MXC_IIMHWV2_WLOCK (0x1 << 7) -#define MXC_IIMHWV2_BP_SDMA (0x1 << 6) -#define MXC_IIMHWV2_SCM_DCM (0x1 << 5) - -#endif /* __ASM_ARCH_MXC_IIM_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/ipu.h b/arch/arm/plat-mxc/include/mach/ipu.h deleted file mode 100644 index 539e559d18b..00000000000 --- a/arch/arm/plat-mxc/include/mach/ipu.h +++ /dev/null @@ -1,177 +0,0 @@ -/* - * Copyright (C) 2008 - * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de> - * - * Copyright (C) 2005-2007 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef _IPU_H_ -#define _IPU_H_ - -#include <linux/types.h> -#include <linux/dmaengine.h> - -/* IPU DMA Controller channel definitions. */ -enum ipu_channel { - IDMAC_IC_0 = 0, /* IC (encoding task) to memory */ - IDMAC_IC_1 = 1, /* IC (viewfinder task) to memory */ - IDMAC_ADC_0 = 1, - IDMAC_IC_2 = 2, - IDMAC_ADC_1 = 2, - IDMAC_IC_3 = 3, - IDMAC_IC_4 = 4, - IDMAC_IC_5 = 5, - IDMAC_IC_6 = 6, - IDMAC_IC_7 = 7, /* IC (sensor data) to memory */ - IDMAC_IC_8 = 8, - IDMAC_IC_9 = 9, - IDMAC_IC_10 = 10, - IDMAC_IC_11 = 11, - IDMAC_IC_12 = 12, - IDMAC_IC_13 = 13, - IDMAC_SDC_0 = 14, /* Background synchronous display data */ - IDMAC_SDC_1 = 15, /* Foreground data (overlay) */ - IDMAC_SDC_2 = 16, - IDMAC_SDC_3 = 17, - IDMAC_ADC_2 = 18, - IDMAC_ADC_3 = 19, - IDMAC_ADC_4 = 20, - IDMAC_ADC_5 = 21, - IDMAC_ADC_6 = 22, - IDMAC_ADC_7 = 23, - IDMAC_PF_0 = 24, - IDMAC_PF_1 = 25, - IDMAC_PF_2 = 26, - IDMAC_PF_3 = 27, - IDMAC_PF_4 = 28, - IDMAC_PF_5 = 29, - IDMAC_PF_6 = 30, - IDMAC_PF_7 = 31, -}; - -/* Order significant! */ -enum ipu_channel_status { - IPU_CHANNEL_FREE, - IPU_CHANNEL_INITIALIZED, - IPU_CHANNEL_READY, - IPU_CHANNEL_ENABLED, -}; - -#define IPU_CHANNELS_NUM 32 - -enum pixel_fmt { - /* 1 byte */ - IPU_PIX_FMT_GENERIC, - IPU_PIX_FMT_RGB332, - IPU_PIX_FMT_YUV420P, - IPU_PIX_FMT_YUV422P, - IPU_PIX_FMT_YUV420P2, - IPU_PIX_FMT_YVU422P, - /* 2 bytes */ - IPU_PIX_FMT_RGB565, - IPU_PIX_FMT_RGB666, - IPU_PIX_FMT_BGR666, - IPU_PIX_FMT_YUYV, - IPU_PIX_FMT_UYVY, - /* 3 bytes */ - IPU_PIX_FMT_RGB24, - IPU_PIX_FMT_BGR24, - /* 4 bytes */ - IPU_PIX_FMT_GENERIC_32, - IPU_PIX_FMT_RGB32, - IPU_PIX_FMT_BGR32, - IPU_PIX_FMT_ABGR32, - IPU_PIX_FMT_BGRA32, - IPU_PIX_FMT_RGBA32, -}; - -enum ipu_color_space { - IPU_COLORSPACE_RGB, - IPU_COLORSPACE_YCBCR, - IPU_COLORSPACE_YUV -}; - -/* - * Enumeration of IPU rotation modes - */ -enum ipu_rotate_mode { - /* Note the enum values correspond to BAM value */ - IPU_ROTATE_NONE = 0, - IPU_ROTATE_VERT_FLIP = 1, - IPU_ROTATE_HORIZ_FLIP = 2, - IPU_ROTATE_180 = 3, - IPU_ROTATE_90_RIGHT = 4, - IPU_ROTATE_90_RIGHT_VFLIP = 5, - IPU_ROTATE_90_RIGHT_HFLIP = 6, - IPU_ROTATE_90_LEFT = 7, -}; - -/* - * Enumeration of DI ports for ADC. - */ -enum display_port { - DISP0, - DISP1, - DISP2, - DISP3 -}; - -struct idmac_video_param { - unsigned short in_width; - unsigned short in_height; - uint32_t in_pixel_fmt; - unsigned short out_width; - unsigned short out_height; - uint32_t out_pixel_fmt; - unsigned short out_stride; - bool graphics_combine_en; - bool global_alpha_en; - bool key_color_en; - enum display_port disp; - unsigned short out_left; - unsigned short out_top; -}; - -/* - * Union of initialization parameters for a logical channel. So far only video - * parameters are used. - */ -union ipu_channel_param { - struct idmac_video_param video; -}; - -struct idmac_tx_desc { - struct dma_async_tx_descriptor txd; - struct scatterlist *sg; /* scatterlist for this */ - unsigned int sg_len; /* tx-descriptor. */ - struct list_head list; -}; - -struct idmac_channel { - struct dma_chan dma_chan; - dma_cookie_t completed; /* last completed cookie */ - union ipu_channel_param params; - enum ipu_channel link; /* input channel, linked to the output */ - enum ipu_channel_status status; - void *client; /* Only one client per channel */ - unsigned int n_tx_desc; - struct idmac_tx_desc *desc; /* allocated tx-descriptors */ - struct scatterlist *sg[2]; /* scatterlist elements in buffer-0 and -1 */ - struct list_head free_list; /* free tx-descriptors */ - struct list_head queue; /* queued tx-descriptors */ - spinlock_t lock; /* protects sg[0,1], queue */ - struct mutex chan_mutex; /* protects status, cookie, free_list */ - bool sec_chan_en; - int active_buffer; - unsigned int eof_irq; - char eof_name[16]; /* EOF IRQ name for request_irq() */ -}; - -#define to_tx_desc(tx) container_of(tx, struct idmac_tx_desc, txd) -#define to_idmac_chan(c) container_of(c, struct idmac_channel, dma_chan) - -#endif diff --git a/arch/arm/plat-mxc/include/mach/iram.h b/arch/arm/plat-mxc/include/mach/iram.h deleted file mode 100644 index 022690c3370..00000000000 --- a/arch/arm/plat-mxc/include/mach/iram.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ -#include <linux/errno.h> - -#ifdef CONFIG_IRAM_ALLOC - -int __init iram_init(unsigned long base, unsigned long size); -void __iomem *iram_alloc(unsigned int size, unsigned long *dma_addr); -void iram_free(unsigned long dma_addr, unsigned int size); - -#else - -static inline int __init iram_init(unsigned long base, unsigned long size) -{ - return -ENOMEM; -} - -static inline void __iomem *iram_alloc(unsigned int size, unsigned long *dma_addr) -{ - return NULL; -} - -static inline void iram_free(unsigned long base, unsigned long size) {} - -#endif diff --git a/arch/arm/plat-mxc/include/mach/irqs.h b/arch/arm/plat-mxc/include/mach/irqs.h deleted file mode 100644 index d73f5e8ea9c..00000000000 --- a/arch/arm/plat-mxc/include/mach/irqs.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. - */ - -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ASM_ARCH_MXC_IRQS_H__ -#define __ASM_ARCH_MXC_IRQS_H__ - -extern int imx_irq_set_priority(unsigned char irq, unsigned char prio); - -/* all normal IRQs can be FIQs */ -#define FIQ_START 0 -/* switch between IRQ and FIQ */ -extern int mxc_set_irq_fiq(unsigned int irq, unsigned int type); - -#endif /* __ASM_ARCH_MXC_IRQS_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx1.h b/arch/arm/plat-mxc/include/mach/mx1.h deleted file mode 100644 index 45bd31cc34d..00000000000 --- a/arch/arm/plat-mxc/include/mach/mx1.h +++ /dev/null @@ -1,172 +0,0 @@ -/* - * Copyright (C) 1997,1998 Russell King - * Copyright (C) 1999 ARM Limited - * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright (c) 2008 Paulius Zaleckas <paulius.zaleckas@teltonika.lt> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __MACH_MX1_H__ -#define __MACH_MX1_H__ - -/* - * Memory map - */ -#define MX1_IO_BASE_ADDR 0x00200000 -#define MX1_IO_SIZE SZ_1M - -#define MX1_CS0_PHYS 0x10000000 -#define MX1_CS0_SIZE 0x02000000 - -#define MX1_CS1_PHYS 0x12000000 -#define MX1_CS1_SIZE 0x01000000 - -#define MX1_CS2_PHYS 0x13000000 -#define MX1_CS2_SIZE 0x01000000 - -#define MX1_CS3_PHYS 0x14000000 -#define MX1_CS3_SIZE 0x01000000 - -#define MX1_CS4_PHYS 0x15000000 -#define MX1_CS4_SIZE 0x01000000 - -#define MX1_CS5_PHYS 0x16000000 -#define MX1_CS5_SIZE 0x01000000 - -/* - * Register BASEs, based on OFFSETs - */ -#define MX1_AIPI1_BASE_ADDR (0x00000 + MX1_IO_BASE_ADDR) -#define MX1_WDT_BASE_ADDR (0x01000 + MX1_IO_BASE_ADDR) -#define MX1_TIM1_BASE_ADDR (0x02000 + MX1_IO_BASE_ADDR) -#define MX1_TIM2_BASE_ADDR (0x03000 + MX1_IO_BASE_ADDR) -#define MX1_RTC_BASE_ADDR (0x04000 + MX1_IO_BASE_ADDR) -#define MX1_LCDC_BASE_ADDR (0x05000 + MX1_IO_BASE_ADDR) -#define MX1_UART1_BASE_ADDR (0x06000 + MX1_IO_BASE_ADDR) -#define MX1_UART2_BASE_ADDR (0x07000 + MX1_IO_BASE_ADDR) -#define MX1_PWM_BASE_ADDR (0x08000 + MX1_IO_BASE_ADDR) -#define MX1_DMA_BASE_ADDR (0x09000 + MX1_IO_BASE_ADDR) -#define MX1_AIPI2_BASE_ADDR (0x10000 + MX1_IO_BASE_ADDR) -#define MX1_SIM_BASE_ADDR (0x11000 + MX1_IO_BASE_ADDR) -#define MX1_USBD_BASE_ADDR (0x12000 + MX1_IO_BASE_ADDR) -#define MX1_CSPI1_BASE_ADDR (0x13000 + MX1_IO_BASE_ADDR) -#define MX1_MMC_BASE_ADDR (0x14000 + MX1_IO_BASE_ADDR) -#define MX1_ASP_BASE_ADDR (0x15000 + MX1_IO_BASE_ADDR) -#define MX1_BTA_BASE_ADDR (0x16000 + MX1_IO_BASE_ADDR) -#define MX1_I2C_BASE_ADDR (0x17000 + MX1_IO_BASE_ADDR) -#define MX1_SSI_BASE_ADDR (0x18000 + MX1_IO_BASE_ADDR) -#define MX1_CSPI2_BASE_ADDR (0x19000 + MX1_IO_BASE_ADDR) -#define MX1_MSHC_BASE_ADDR (0x1A000 + MX1_IO_BASE_ADDR) -#define MX1_CCM_BASE_ADDR (0x1B000 + MX1_IO_BASE_ADDR) -#define MX1_SCM_BASE_ADDR (0x1B804 + MX1_IO_BASE_ADDR) -#define MX1_GPIO_BASE_ADDR (0x1C000 + MX1_IO_BASE_ADDR) -#define MX1_GPIO1_BASE_ADDR (0x1C000 + MX1_IO_BASE_ADDR) -#define MX1_GPIO2_BASE_ADDR (0x1C100 + MX1_IO_BASE_ADDR) -#define MX1_GPIO3_BASE_ADDR (0x1C200 + MX1_IO_BASE_ADDR) -#define MX1_GPIO4_BASE_ADDR (0x1C300 + MX1_IO_BASE_ADDR) -#define MX1_EIM_BASE_ADDR (0x20000 + MX1_IO_BASE_ADDR) -#define MX1_SDRAMC_BASE_ADDR (0x21000 + MX1_IO_BASE_ADDR) -#define MX1_MMA_BASE_ADDR (0x22000 + MX1_IO_BASE_ADDR) -#define MX1_AVIC_BASE_ADDR (0x23000 + MX1_IO_BASE_ADDR) -#define MX1_CSI_BASE_ADDR (0x24000 + MX1_IO_BASE_ADDR) - -/* macro to get at IO space when running virtually */ -#define MX1_IO_P2V(x) IMX_IO_P2V(x) -#define MX1_IO_ADDRESS(x) IOMEM(MX1_IO_P2V(x)) - -/* fixed interrput numbers */ -#include <asm/irq.h> -#define MX1_INT_SOFTINT (NR_IRQS_LEGACY + 0) -#define MX1_INT_CSI (NR_IRQS_LEGACY + 6) -#define MX1_DSPA_MAC_INT (NR_IRQS_LEGACY + 7) -#define MX1_DSPA_INT (NR_IRQS_LEGACY + 8) -#define MX1_COMP_INT (NR_IRQS_LEGACY + 9) -#define MX1_MSHC_XINT (NR_IRQS_LEGACY + 10) -#define MX1_GPIO_INT_PORTA (NR_IRQS_LEGACY + 11) -#define MX1_GPIO_INT_PORTB (NR_IRQS_LEGACY + 12) -#define MX1_GPIO_INT_PORTC (NR_IRQS_LEGACY + 13) -#define MX1_INT_LCDC (NR_IRQS_LEGACY + 14) -#define MX1_SIM_INT (NR_IRQS_LEGACY + 15) -#define MX1_SIM_DATA_INT (NR_IRQS_LEGACY + 16) -#define MX1_RTC_INT (NR_IRQS_LEGACY + 17) -#define MX1_RTC_SAMINT (NR_IRQS_LEGACY + 18) -#define MX1_INT_UART2PFERR (NR_IRQS_LEGACY + 19) -#define MX1_INT_UART2RTS (NR_IRQS_LEGACY + 20) -#define MX1_INT_UART2DTR (NR_IRQS_LEGACY + 21) -#define MX1_INT_UART2UARTC (NR_IRQS_LEGACY + 22) -#define MX1_INT_UART2TX (NR_IRQS_LEGACY + 23) -#define MX1_INT_UART2RX (NR_IRQS_LEGACY + 24) -#define MX1_INT_UART1PFERR (NR_IRQS_LEGACY + 25) -#define MX1_INT_UART1RTS (NR_IRQS_LEGACY + 26) -#define MX1_INT_UART1DTR (NR_IRQS_LEGACY + 27) -#define MX1_INT_UART1UARTC (NR_IRQS_LEGACY + 28) -#define MX1_INT_UART1TX (NR_IRQS_LEGACY + 29) -#define MX1_INT_UART1RX (NR_IRQS_LEGACY + 30) -#define MX1_VOICE_DAC_INT (NR_IRQS_LEGACY + 31) -#define MX1_VOICE_ADC_INT (NR_IRQS_LEGACY + 32) -#define MX1_PEN_DATA_INT (NR_IRQS_LEGACY + 33) -#define MX1_PWM_INT (NR_IRQS_LEGACY + 34) -#define MX1_SDHC_INT (NR_IRQS_LEGACY + 35) -#define MX1_INT_I2C (NR_IRQS_LEGACY + 39) -#define MX1_INT_CSPI2 (NR_IRQS_LEGACY + 40) -#define MX1_INT_CSPI1 (NR_IRQS_LEGACY + 41) -#define MX1_SSI_TX_INT (NR_IRQS_LEGACY + 42) -#define MX1_SSI_TX_ERR_INT (NR_IRQS_LEGACY + 43) -#define MX1_SSI_RX_INT (NR_IRQS_LEGACY + 44) -#define MX1_SSI_RX_ERR_INT (NR_IRQS_LEGACY + 45) -#define MX1_TOUCH_INT (NR_IRQS_LEGACY + 46) -#define MX1_INT_USBD0 (NR_IRQS_LEGACY + 47) -#define MX1_INT_USBD1 (NR_IRQS_LEGACY + 48) -#define MX1_INT_USBD2 (NR_IRQS_LEGACY + 49) -#define MX1_INT_USBD3 (NR_IRQS_LEGACY + 50) -#define MX1_INT_USBD4 (NR_IRQS_LEGACY + 51) -#define MX1_INT_USBD5 (NR_IRQS_LEGACY + 52) -#define MX1_INT_USBD6 (NR_IRQS_LEGACY + 53) -#define MX1_BTSYS_INT (NR_IRQS_LEGACY + 55) -#define MX1_BTTIM_INT (NR_IRQS_LEGACY + 56) -#define MX1_BTWUI_INT (NR_IRQS_LEGACY + 57) -#define MX1_TIM2_INT (NR_IRQS_LEGACY + 58) -#define MX1_TIM1_INT (NR_IRQS_LEGACY + 59) -#define MX1_DMA_ERR (NR_IRQS_LEGACY + 60) -#define MX1_DMA_INT (NR_IRQS_LEGACY + 61) -#define MX1_GPIO_INT_PORTD (NR_IRQS_LEGACY + 62) -#define MX1_WDT_INT (NR_IRQS_LEGACY + 63) - -/* DMA */ -#define MX1_DMA_REQ_UART3_T 2 -#define MX1_DMA_REQ_UART3_R 3 -#define MX1_DMA_REQ_SSI2_T 4 -#define MX1_DMA_REQ_SSI2_R 5 -#define MX1_DMA_REQ_CSI_STAT 6 -#define MX1_DMA_REQ_CSI_R 7 -#define MX1_DMA_REQ_MSHC 8 -#define MX1_DMA_REQ_DSPA_DCT_DOUT 9 -#define MX1_DMA_REQ_DSPA_DCT_DIN 10 -#define MX1_DMA_REQ_DSPA_MAC 11 -#define MX1_DMA_REQ_EXT 12 -#define MX1_DMA_REQ_SDHC 13 -#define MX1_DMA_REQ_SPI1_R 14 -#define MX1_DMA_REQ_SPI1_T 15 -#define MX1_DMA_REQ_SSI_T 16 -#define MX1_DMA_REQ_SSI_R 17 -#define MX1_DMA_REQ_ASP_DAC 18 -#define MX1_DMA_REQ_ASP_ADC 19 -#define MX1_DMA_REQ_USP_EP(x) (20 + (x)) -#define MX1_DMA_REQ_SPI2_R 26 -#define MX1_DMA_REQ_SPI2_T 27 -#define MX1_DMA_REQ_UART2_T 28 -#define MX1_DMA_REQ_UART2_R 29 -#define MX1_DMA_REQ_UART1_T 30 -#define MX1_DMA_REQ_UART1_R 31 - -/* - * This doesn't depend on IMX_NEEDS_DEPRECATED_SYMBOLS - * to not break drivers/usb/gadget/imx_udc. Should go - * away after this driver uses the new name. - */ -#define USBD_INT0 MX1_INT_USBD0 - -#endif /* ifndef __MACH_MX1_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx21.h b/arch/arm/plat-mxc/include/mach/mx21.h deleted file mode 100644 index 468738aa997..00000000000 --- a/arch/arm/plat-mxc/include/mach/mx21.h +++ /dev/null @@ -1,189 +0,0 @@ -/* - * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Juergen Beisert, kernel@pengutronix.de - * Copyright 2009 Holger Schurig, hs4233@mail.mn-solutions.de - * - * This contains i.MX21-specific hardware definitions. For those - * hardware pieces that are common between i.MX21 and i.MX27, have a - * look at mx2x.h. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#ifndef __MACH_MX21_H__ -#define __MACH_MX21_H__ - -#define MX21_AIPI_BASE_ADDR 0x10000000 -#define MX21_AIPI_SIZE SZ_1M -#define MX21_DMA_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x01000) -#define MX21_WDOG_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x02000) -#define MX21_GPT1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x03000) -#define MX21_GPT2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x04000) -#define MX21_GPT3_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x05000) -#define MX21_PWM_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x06000) -#define MX21_RTC_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x07000) -#define MX21_KPP_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x08000) -#define MX21_OWIRE_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x09000) -#define MX21_UART1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0a000) -#define MX21_UART2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0b000) -#define MX21_UART3_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0c000) -#define MX21_UART4_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0d000) -#define MX21_CSPI1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0e000) -#define MX21_CSPI2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0f000) -#define MX21_SSI1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x10000) -#define MX21_SSI2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x11000) -#define MX21_I2C_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x12000) -#define MX21_SDHC1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x13000) -#define MX21_SDHC2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x14000) -#define MX21_GPIO_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x15000) -#define MX21_GPIO1_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x000) -#define MX21_GPIO2_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x100) -#define MX21_GPIO3_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x200) -#define MX21_GPIO4_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x300) -#define MX21_GPIO5_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x400) -#define MX21_GPIO6_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x500) -#define MX21_AUDMUX_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x16000) -#define MX21_CSPI3_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x17000) -#define MX21_LCDC_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x21000) -#define MX21_SLCDC_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x22000) -#define MX21_USBOTG_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x24000) -#define MX21_EMMA_PP_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x26000) -#define MX21_EMMA_PRP_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x26400) -#define MX21_CCM_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x27000) -#define MX21_SYSCTRL_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x27800) -#define MX21_JAM_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x3e000) -#define MX21_MAX_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x3f000) - -#define MX21_AVIC_BASE_ADDR 0x10040000 - -#define MX21_SAHB1_BASE_ADDR 0x80000000 -#define MX21_SAHB1_SIZE SZ_1M -#define MX21_CSI_BASE_ADDR (MX2x_SAHB1_BASE_ADDR + 0x0000) - -/* Memory regions and CS */ -#define MX21_SDRAM_BASE_ADDR 0xc0000000 -#define MX21_CSD1_BASE_ADDR 0xc4000000 - -#define MX21_CS0_BASE_ADDR 0xc8000000 -#define MX21_CS1_BASE_ADDR 0xcc000000 -#define MX21_CS2_BASE_ADDR 0xd0000000 -#define MX21_CS3_BASE_ADDR 0xd1000000 -#define MX21_CS4_BASE_ADDR 0xd2000000 -#define MX21_PCMCIA_MEM_BASE_ADDR 0xd4000000 -#define MX21_CS5_BASE_ADDR 0xdd000000 - -/* NAND, SDRAM, WEIM etc controllers */ -#define MX21_X_MEMC_BASE_ADDR 0xdf000000 -#define MX21_X_MEMC_SIZE SZ_256K - -#define MX21_SDRAMC_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x0000) -#define MX21_EIM_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x1000) -#define MX21_PCMCIA_CTL_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x2000) -#define MX21_NFC_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x3000) - -#define MX21_IRAM_BASE_ADDR 0xffffe800 /* internal ram */ - -#define MX21_IO_P2V(x) IMX_IO_P2V(x) -#define MX21_IO_ADDRESS(x) IOMEM(MX21_IO_P2V(x)) - -/* fixed interrupt numbers */ -#include <asm/irq.h> -#define MX21_INT_CSPI3 (NR_IRQS_LEGACY + 6) -#define MX21_INT_GPIO (NR_IRQS_LEGACY + 8) -#define MX21_INT_FIRI (NR_IRQS_LEGACY + 9) -#define MX21_INT_SDHC2 (NR_IRQS_LEGACY + 10) -#define MX21_INT_SDHC1 (NR_IRQS_LEGACY + 11) -#define MX21_INT_I2C (NR_IRQS_LEGACY + 12) -#define MX21_INT_SSI2 (NR_IRQS_LEGACY + 13) -#define MX21_INT_SSI1 (NR_IRQS_LEGACY + 14) -#define MX21_INT_CSPI2 (NR_IRQS_LEGACY + 15) -#define MX21_INT_CSPI1 (NR_IRQS_LEGACY + 16) -#define MX21_INT_UART4 (NR_IRQS_LEGACY + 17) -#define MX21_INT_UART3 (NR_IRQS_LEGACY + 18) -#define MX21_INT_UART2 (NR_IRQS_LEGACY + 19) -#define MX21_INT_UART1 (NR_IRQS_LEGACY + 20) -#define MX21_INT_KPP (NR_IRQS_LEGACY + 21) -#define MX21_INT_RTC (NR_IRQS_LEGACY + 22) -#define MX21_INT_PWM (NR_IRQS_LEGACY + 23) -#define MX21_INT_GPT3 (NR_IRQS_LEGACY + 24) -#define MX21_INT_GPT2 (NR_IRQS_LEGACY + 25) -#define MX21_INT_GPT1 (NR_IRQS_LEGACY + 26) -#define MX21_INT_WDOG (NR_IRQS_LEGACY + 27) -#define MX21_INT_PCMCIA (NR_IRQS_LEGACY + 28) -#define MX21_INT_NFC (NR_IRQS_LEGACY + 29) -#define MX21_INT_BMI (NR_IRQS_LEGACY + 30) -#define MX21_INT_CSI (NR_IRQS_LEGACY + 31) -#define MX21_INT_DMACH0 (NR_IRQS_LEGACY + 32) -#define MX21_INT_DMACH1 (NR_IRQS_LEGACY + 33) -#define MX21_INT_DMACH2 (NR_IRQS_LEGACY + 34) -#define MX21_INT_DMACH3 (NR_IRQS_LEGACY + 35) -#define MX21_INT_DMACH4 (NR_IRQS_LEGACY + 36) -#define MX21_INT_DMACH5 (NR_IRQS_LEGACY + 37) -#define MX21_INT_DMACH6 (NR_IRQS_LEGACY + 38) -#define MX21_INT_DMACH7 (NR_IRQS_LEGACY + 39) -#define MX21_INT_DMACH8 (NR_IRQS_LEGACY + 40) -#define MX21_INT_DMACH9 (NR_IRQS_LEGACY + 41) -#define MX21_INT_DMACH10 (NR_IRQS_LEGACY + 42) -#define MX21_INT_DMACH11 (NR_IRQS_LEGACY + 43) -#define MX21_INT_DMACH12 (NR_IRQS_LEGACY + 44) -#define MX21_INT_DMACH13 (NR_IRQS_LEGACY + 45) -#define MX21_INT_DMACH14 (NR_IRQS_LEGACY + 46) -#define MX21_INT_DMACH15 (NR_IRQS_LEGACY + 47) -#define MX21_INT_EMMAENC (NR_IRQS_LEGACY + 49) -#define MX21_INT_EMMADEC (NR_IRQS_LEGACY + 50) -#define MX21_INT_EMMAPRP (NR_IRQS_LEGACY + 51) -#define MX21_INT_EMMAPP (NR_IRQS_LEGACY + 52) -#define MX21_INT_USBWKUP (NR_IRQS_LEGACY + 53) -#define MX21_INT_USBDMA (NR_IRQS_LEGACY + 54) -#define MX21_INT_USBHOST (NR_IRQS_LEGACY + 55) -#define MX21_INT_USBFUNC (NR_IRQS_LEGACY + 56) -#define MX21_INT_USBMNP (NR_IRQS_LEGACY + 57) -#define MX21_INT_USBCTRL (NR_IRQS_LEGACY + 58) -#define MX21_INT_SLCDC (NR_IRQS_LEGACY + 60) -#define MX21_INT_LCDC (NR_IRQS_LEGACY + 61) - -/* fixed DMA request numbers */ -#define MX21_DMA_REQ_CSPI3_RX 1 -#define MX21_DMA_REQ_CSPI3_TX 2 -#define MX21_DMA_REQ_EXT 3 -#define MX21_DMA_REQ_FIRI_RX 4 -#define MX21_DMA_REQ_SDHC2 6 -#define MX21_DMA_REQ_SDHC1 7 -#define MX21_DMA_REQ_SSI2_RX0 8 -#define MX21_DMA_REQ_SSI2_TX0 9 -#define MX21_DMA_REQ_SSI2_RX1 10 -#define MX21_DMA_REQ_SSI2_TX1 11 -#define MX21_DMA_REQ_SSI1_RX0 12 -#define MX21_DMA_REQ_SSI1_TX0 13 -#define MX21_DMA_REQ_SSI1_RX1 14 -#define MX21_DMA_REQ_SSI1_TX1 15 -#define MX21_DMA_REQ_CSPI2_RX 16 -#define MX21_DMA_REQ_CSPI2_TX 17 -#define MX21_DMA_REQ_CSPI1_RX 18 -#define MX21_DMA_REQ_CSPI1_TX 19 -#define MX21_DMA_REQ_UART4_RX 20 -#define MX21_DMA_REQ_UART4_TX 21 -#define MX21_DMA_REQ_UART3_RX 22 -#define MX21_DMA_REQ_UART3_TX 23 -#define MX21_DMA_REQ_UART2_RX 24 -#define MX21_DMA_REQ_UART2_TX 25 -#define MX21_DMA_REQ_UART1_RX 26 -#define MX21_DMA_REQ_UART1_TX 27 -#define MX21_DMA_REQ_BMI_TX 28 -#define MX21_DMA_REQ_BMI_RX 29 -#define MX21_DMA_REQ_CSI_STAT 30 -#define MX21_DMA_REQ_CSI_RX 31 - -#endif /* ifndef __MACH_MX21_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h deleted file mode 100644 index ec466400a20..00000000000 --- a/arch/arm/plat-mxc/include/mach/mx25.h +++ /dev/null @@ -1,117 +0,0 @@ -#ifndef __MACH_MX25_H__ -#define __MACH_MX25_H__ - -#define MX25_AIPS1_BASE_ADDR 0x43f00000 -#define MX25_AIPS1_SIZE SZ_1M -#define MX25_AIPS2_BASE_ADDR 0x53f00000 -#define MX25_AIPS2_SIZE SZ_1M -#define MX25_AVIC_BASE_ADDR 0x68000000 -#define MX25_AVIC_SIZE SZ_1M - -#define MX25_I2C1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x80000) -#define MX25_I2C3_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x84000) -#define MX25_CAN1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x88000) -#define MX25_CAN2_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x8c000) -#define MX25_I2C2_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x98000) -#define MX25_CSPI1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xa4000) -#define MX25_IOMUXC_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xac000) - -#define MX25_CRM_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x80000) -#define MX25_GPT1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x90000) -#define MX25_GPIO4_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x9c000) -#define MX25_PWM2_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa0000) -#define MX25_GPIO3_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa4000) -#define MX25_PWM3_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa8000) -#define MX25_PWM4_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xc8000) -#define MX25_GPIO1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xcc000) -#define MX25_GPIO2_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xd0000) -#define MX25_WDOG_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xdc000) -#define MX25_PWM1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xe0000) - -#define MX25_UART1_BASE_ADDR 0x43f90000 -#define MX25_UART2_BASE_ADDR 0x43f94000 -#define MX25_AUDMUX_BASE_ADDR 0x43fb0000 -#define MX25_UART3_BASE_ADDR 0x5000c000 -#define MX25_UART4_BASE_ADDR 0x50008000 -#define MX25_UART5_BASE_ADDR 0x5002c000 - -#define MX25_CSPI3_BASE_ADDR 0x50004000 -#define MX25_CSPI2_BASE_ADDR 0x50010000 -#define MX25_FEC_BASE_ADDR 0x50038000 -#define MX25_SSI2_BASE_ADDR 0x50014000 -#define MX25_SSI1_BASE_ADDR 0x50034000 -#define MX25_NFC_BASE_ADDR 0xbb000000 -#define MX25_IIM_BASE_ADDR 0x53ff0000 -#define MX25_DRYICE_BASE_ADDR 0x53ffc000 -#define MX25_ESDHC1_BASE_ADDR 0x53fb4000 -#define MX25_ESDHC2_BASE_ADDR 0x53fb8000 -#define MX25_LCDC_BASE_ADDR 0x53fbc000 -#define MX25_KPP_BASE_ADDR 0x43fa8000 -#define MX25_SDMA_BASE_ADDR 0x53fd4000 -#define MX25_USB_BASE_ADDR 0x53ff4000 -#define MX25_USB_OTG_BASE_ADDR (MX25_USB_BASE_ADDR + 0x0000) -/* - * The reference manual (IMX25RM, Rev. 1, 06/2009) specifies an offset of 0x200 - * for the host controller. Early documentation drafts specified 0x400 and - * Freescale internal sources confirm only the latter value to work. - */ -#define MX25_USB_HS_BASE_ADDR (MX25_USB_BASE_ADDR + 0x0400) -#define MX25_CSI_BASE_ADDR 0x53ff8000 - -#define MX25_IO_P2V(x) IMX_IO_P2V(x) -#define MX25_IO_ADDRESS(x) IOMEM(MX25_IO_P2V(x)) - -/* - * Interrupt numbers - */ -#include <asm/irq.h> -#define MX25_INT_CSPI3 (NR_IRQS_LEGACY + 0) -#define MX25_INT_I2C1 (NR_IRQS_LEGACY + 3) -#define MX25_INT_I2C2 (NR_IRQS_LEGACY + 4) -#define MX25_INT_UART4 (NR_IRQS_LEGACY + 5) -#define MX25_INT_ESDHC2 (NR_IRQS_LEGACY + 8) -#define MX25_INT_ESDHC1 (NR_IRQS_LEGACY + 9) -#define MX25_INT_I2C3 (NR_IRQS_LEGACY + 10) -#define MX25_INT_SSI2 (NR_IRQS_LEGACY + 11) -#define MX25_INT_SSI1 (NR_IRQS_LEGACY + 12) -#define MX25_INT_CSPI2 (NR_IRQS_LEGACY + 13) -#define MX25_INT_CSPI1 (NR_IRQS_LEGACY + 14) -#define MX25_INT_GPIO3 (NR_IRQS_LEGACY + 16) -#define MX25_INT_CSI (NR_IRQS_LEGACY + 17) -#define MX25_INT_UART3 (NR_IRQS_LEGACY + 18) -#define MX25_INT_GPIO4 (NR_IRQS_LEGACY + 23) -#define MX25_INT_KPP (NR_IRQS_LEGACY + 24) -#define MX25_INT_DRYICE (NR_IRQS_LEGACY + 25) -#define MX25_INT_PWM1 (NR_IRQS_LEGACY + 26) -#define MX25_INT_UART2 (NR_IRQS_LEGACY + 32) -#define MX25_INT_NFC (NR_IRQS_LEGACY + 33) -#define MX25_INT_SDMA (NR_IRQS_LEGACY + 34) -#define MX25_INT_USB_HS (NR_IRQS_LEGACY + 35) -#define MX25_INT_PWM2 (NR_IRQS_LEGACY + 36) -#define MX25_INT_USB_OTG (NR_IRQS_LEGACY + 37) -#define MX25_INT_LCDC (NR_IRQS_LEGACY + 39) -#define MX25_INT_UART5 (NR_IRQS_LEGACY + 40) -#define MX25_INT_PWM3 (NR_IRQS_LEGACY + 41) -#define MX25_INT_PWM4 (NR_IRQS_LEGACY + 42) -#define MX25_INT_CAN1 (NR_IRQS_LEGACY + 43) -#define MX25_INT_CAN2 (NR_IRQS_LEGACY + 44) -#define MX25_INT_UART1 (NR_IRQS_LEGACY + 45) -#define MX25_INT_GPIO2 (NR_IRQS_LEGACY + 51) -#define MX25_INT_GPIO1 (NR_IRQS_LEGACY + 52) -#define MX25_INT_GPT1 (NR_IRQS_LEGACY + 54) -#define MX25_INT_FEC (NR_IRQS_LEGACY + 57) - -#define MX25_DMA_REQ_SSI2_RX1 22 -#define MX25_DMA_REQ_SSI2_TX1 23 -#define MX25_DMA_REQ_SSI2_RX0 24 -#define MX25_DMA_REQ_SSI2_TX0 25 -#define MX25_DMA_REQ_SSI1_RX1 26 -#define MX25_DMA_REQ_SSI1_TX1 27 -#define MX25_DMA_REQ_SSI1_RX0 28 -#define MX25_DMA_REQ_SSI1_TX0 29 - -#ifndef __ASSEMBLY__ -extern int mx25_revision(void); -#endif - -#endif /* ifndef __MACH_MX25_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h deleted file mode 100644 index e074616d54c..00000000000 --- a/arch/arm/plat-mxc/include/mach/mx27.h +++ /dev/null @@ -1,238 +0,0 @@ -/* - * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Juergen Beisert, kernel@pengutronix.de - * - * This contains i.MX27-specific hardware definitions. For those - * hardware pieces that are common between i.MX21 and i.MX27, have a - * look at mx2x.h. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#ifndef __MACH_MX27_H__ -#define __MACH_MX27_H__ - -#define MX27_AIPI_BASE_ADDR 0x10000000 -#define MX27_AIPI_SIZE SZ_1M -#define MX27_DMA_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x01000) -#define MX27_WDOG_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x02000) -#define MX27_GPT1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x03000) -#define MX27_GPT2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x04000) -#define MX27_GPT3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x05000) -#define MX27_PWM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x06000) -#define MX27_RTC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x07000) -#define MX27_KPP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x08000) -#define MX27_OWIRE_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x09000) -#define MX27_UART1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0a000) -#define MX27_UART2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0b000) -#define MX27_UART3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0c000) -#define MX27_UART4_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0d000) -#define MX27_CSPI1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0e000) -#define MX27_CSPI2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0f000) -#define MX27_SSI1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x10000) -#define MX27_SSI2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x11000) -#define MX27_I2C1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x12000) -#define MX27_SDHC1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x13000) -#define MX27_SDHC2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x14000) -#define MX27_GPIO_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x15000) -#define MX27_GPIO1_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x000) -#define MX27_GPIO2_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x100) -#define MX27_GPIO3_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x200) -#define MX27_GPIO4_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x300) -#define MX27_GPIO5_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x400) -#define MX27_GPIO6_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x500) -#define MX27_AUDMUX_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x16000) -#define MX27_CSPI3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x17000) -#define MX27_MSHC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x18000) -#define MX27_GPT4_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x19000) -#define MX27_GPT5_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1a000) -#define MX27_UART5_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1b000) -#define MX27_UART6_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1c000) -#define MX27_I2C2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1d000) -#define MX27_SDHC3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1e000) -#define MX27_GPT6_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1f000) -#define MX27_LCDC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x21000) -#define MX27_SLCDC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x22000) -#define MX27_VPU_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x23000) -#define MX27_USB_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x24000) -#define MX27_USB_OTG_BASE_ADDR (MX27_USB_BASE_ADDR + 0x0000) -#define MX27_USB_HS1_BASE_ADDR (MX27_USB_BASE_ADDR + 0x0200) -#define MX27_USB_HS2_BASE_ADDR (MX27_USB_BASE_ADDR + 0x0400) -#define MX27_SAHARA_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x25000) -#define MX27_EMMAPP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26000) -#define MX27_EMMAPRP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26400) -#define MX27_CCM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x27000) -#define MX27_SYSCTRL_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x27800) -#define MX27_IIM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x28000) -#define MX27_RTIC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x2a000) -#define MX27_FEC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x2b000) -#define MX27_SCC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x2c000) -#define MX27_ETB_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3b000) -#define MX27_ETB_RAM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3c000) -#define MX27_JAM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3e000) -#define MX27_MAX_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3f000) - -#define MX27_AVIC_BASE_ADDR 0x10040000 - -/* ROM patch */ -#define MX27_ROMP_BASE_ADDR 0x10041000 - -#define MX27_SAHB1_BASE_ADDR 0x80000000 -#define MX27_SAHB1_SIZE SZ_1M -#define MX27_CSI_BASE_ADDR (MX27_SAHB1_BASE_ADDR + 0x0000) -#define MX27_ATA_BASE_ADDR (MX27_SAHB1_BASE_ADDR + 0x1000) - -/* Memory regions and CS */ -#define MX27_SDRAM_BASE_ADDR 0xa0000000 -#define MX27_CSD1_BASE_ADDR 0xb0000000 - -#define MX27_CS0_BASE_ADDR 0xc0000000 -#define MX27_CS1_BASE_ADDR 0xc8000000 -#define MX27_CS2_BASE_ADDR 0xd0000000 -#define MX27_CS3_BASE_ADDR 0xd2000000 -#define MX27_CS4_BASE_ADDR 0xd4000000 -#define MX27_CS5_BASE_ADDR 0xd6000000 - -/* NAND, SDRAM, WEIM, M3IF, EMI controllers */ -#define MX27_X_MEMC_BASE_ADDR 0xd8000000 -#define MX27_X_MEMC_SIZE SZ_1M -#define MX27_NFC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR) -#define MX27_SDRAMC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x1000) -#define MX27_WEIM_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x2000) -#define MX27_M3IF_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x3000) -#define MX27_PCMCIA_CTL_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x4000) - -#define MX27_WEIM_CSCRx_BASE_ADDR(cs) (MX27_WEIM_BASE_ADDR + (cs) * 0x10) -#define MX27_WEIM_CSCRxU(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs)) -#define MX27_WEIM_CSCRxL(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs) + 0x4) -#define MX27_WEIM_CSCRxA(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs) + 0x8) - -#define MX27_PCMCIA_MEM_BASE_ADDR 0xdc000000 - -/* IRAM */ -#define MX27_IRAM_BASE_ADDR 0xffff4c00 /* internal ram */ - -#define MX27_IO_P2V(x) IMX_IO_P2V(x) -#define MX27_IO_ADDRESS(x) IOMEM(MX27_IO_P2V(x)) - -/* fixed interrupt numbers */ -#include <asm/irq.h> -#define MX27_INT_I2C2 (NR_IRQS_LEGACY + 1) -#define MX27_INT_GPT6 (NR_IRQS_LEGACY + 2) -#define MX27_INT_GPT5 (NR_IRQS_LEGACY + 3) -#define MX27_INT_GPT4 (NR_IRQS_LEGACY + 4) -#define MX27_INT_RTIC (NR_IRQS_LEGACY + 5) -#define MX27_INT_CSPI3 (NR_IRQS_LEGACY + 6) -#define MX27_INT_SDHC (NR_IRQS_LEGACY + 7) -#define MX27_INT_GPIO (NR_IRQS_LEGACY + 8) -#define MX27_INT_SDHC3 (NR_IRQS_LEGACY + 9) -#define MX27_INT_SDHC2 (NR_IRQS_LEGACY + 10) -#define MX27_INT_SDHC1 (NR_IRQS_LEGACY + 11) -#define MX27_INT_I2C1 (NR_IRQS_LEGACY + 12) -#define MX27_INT_SSI2 (NR_IRQS_LEGACY + 13) -#define MX27_INT_SSI1 (NR_IRQS_LEGACY + 14) -#define MX27_INT_CSPI2 (NR_IRQS_LEGACY + 15) -#define MX27_INT_CSPI1 (NR_IRQS_LEGACY + 16) -#define MX27_INT_UART4 (NR_IRQS_LEGACY + 17) -#define MX27_INT_UART3 (NR_IRQS_LEGACY + 18) -#define MX27_INT_UART2 (NR_IRQS_LEGACY + 19) -#define MX27_INT_UART1 (NR_IRQS_LEGACY + 20) -#define MX27_INT_KPP (NR_IRQS_LEGACY + 21) -#define MX27_INT_RTC (NR_IRQS_LEGACY + 22) -#define MX27_INT_PWM (NR_IRQS_LEGACY + 23) -#define MX27_INT_GPT3 (NR_IRQS_LEGACY + 24) -#define MX27_INT_GPT2 (NR_IRQS_LEGACY + 25) -#define MX27_INT_GPT1 (NR_IRQS_LEGACY + 26) -#define MX27_INT_WDOG (NR_IRQS_LEGACY + 27) -#define MX27_INT_PCMCIA (NR_IRQS_LEGACY + 28) -#define MX27_INT_NFC (NR_IRQS_LEGACY + 29) -#define MX27_INT_ATA (NR_IRQS_LEGACY + 30) -#define MX27_INT_CSI (NR_IRQS_LEGACY + 31) -#define MX27_INT_DMACH0 (NR_IRQS_LEGACY + 32) -#define MX27_INT_DMACH1 (NR_IRQS_LEGACY + 33) -#define MX27_INT_DMACH2 (NR_IRQS_LEGACY + 34) -#define MX27_INT_DMACH3 (NR_IRQS_LEGACY + 35) -#define MX27_INT_DMACH4 (NR_IRQS_LEGACY + 36) -#define MX27_INT_DMACH5 (NR_IRQS_LEGACY + 37) -#define MX27_INT_DMACH6 (NR_IRQS_LEGACY + 38) -#define MX27_INT_DMACH7 (NR_IRQS_LEGACY + 39) -#define MX27_INT_DMACH8 (NR_IRQS_LEGACY + 40) -#define MX27_INT_DMACH9 (NR_IRQS_LEGACY + 41) -#define MX27_INT_DMACH10 (NR_IRQS_LEGACY + 42) -#define MX27_INT_DMACH11 (NR_IRQS_LEGACY + 43) -#define MX27_INT_DMACH12 (NR_IRQS_LEGACY + 44) -#define MX27_INT_DMACH13 (NR_IRQS_LEGACY + 45) -#define MX27_INT_DMACH14 (NR_IRQS_LEGACY + 46) -#define MX27_INT_DMACH15 (NR_IRQS_LEGACY + 47) -#define MX27_INT_UART6 (NR_IRQS_LEGACY + 48) -#define MX27_INT_UART5 (NR_IRQS_LEGACY + 49) -#define MX27_INT_FEC (NR_IRQS_LEGACY + 50) -#define MX27_INT_EMMAPRP (NR_IRQS_LEGACY + 51) -#define MX27_INT_EMMAPP (NR_IRQS_LEGACY + 52) -#define MX27_INT_VPU (NR_IRQS_LEGACY + 53) -#define MX27_INT_USB_HS1 (NR_IRQS_LEGACY + 54) -#define MX27_INT_USB_HS2 (NR_IRQS_LEGACY + 55) -#define MX27_INT_USB_OTG (NR_IRQS_LEGACY + 56) -#define MX27_INT_SCC_SMN (NR_IRQS_LEGACY + 57) -#define MX27_INT_SCC_SCM (NR_IRQS_LEGACY + 58) -#define MX27_INT_SAHARA (NR_IRQS_LEGACY + 59) -#define MX27_INT_SLCDC (NR_IRQS_LEGACY + 60) -#define MX27_INT_LCDC (NR_IRQS_LEGACY + 61) -#define MX27_INT_IIM (NR_IRQS_LEGACY + 62) -#define MX27_INT_CCM (NR_IRQS_LEGACY + 63) - -/* fixed DMA request numbers */ -#define MX27_DMA_REQ_CSPI3_RX 1 -#define MX27_DMA_REQ_CSPI3_TX 2 -#define MX27_DMA_REQ_EXT 3 -#define MX27_DMA_REQ_MSHC 4 -#define MX27_DMA_REQ_SDHC2 6 -#define MX27_DMA_REQ_SDHC1 7 -#define MX27_DMA_REQ_SSI2_RX0 8 -#define MX27_DMA_REQ_SSI2_TX0 9 -#define MX27_DMA_REQ_SSI2_RX1 10 -#define MX27_DMA_REQ_SSI2_TX1 11 -#define MX27_DMA_REQ_SSI1_RX0 12 -#define MX27_DMA_REQ_SSI1_TX0 13 -#define MX27_DMA_REQ_SSI1_RX1 14 -#define MX27_DMA_REQ_SSI1_TX1 15 -#define MX27_DMA_REQ_CSPI2_RX 16 -#define MX27_DMA_REQ_CSPI2_TX 17 -#define MX27_DMA_REQ_CSPI1_RX 18 -#define MX27_DMA_REQ_CSPI1_TX 19 -#define MX27_DMA_REQ_UART4_RX 20 -#define MX27_DMA_REQ_UART4_TX 21 -#define MX27_DMA_REQ_UART3_RX 22 -#define MX27_DMA_REQ_UART3_TX 23 -#define MX27_DMA_REQ_UART2_RX 24 -#define MX27_DMA_REQ_UART2_TX 25 -#define MX27_DMA_REQ_UART1_RX 26 -#define MX27_DMA_REQ_UART1_TX 27 -#define MX27_DMA_REQ_ATA_TX 28 -#define MX27_DMA_REQ_ATA_RCV 29 -#define MX27_DMA_REQ_CSI_STAT 30 -#define MX27_DMA_REQ_CSI_RX 31 -#define MX27_DMA_REQ_UART5_TX 32 -#define MX27_DMA_REQ_UART5_RX 33 -#define MX27_DMA_REQ_UART6_TX 34 -#define MX27_DMA_REQ_UART6_RX 35 -#define MX27_DMA_REQ_SDHC3 36 -#define MX27_DMA_REQ_NFC 37 - -#ifndef __ASSEMBLY__ -extern int mx27_revision(void); -#endif - -#endif /* ifndef __MACH_MX27_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx2x.h b/arch/arm/plat-mxc/include/mach/mx2x.h deleted file mode 100644 index 11642f5b224..00000000000 --- a/arch/arm/plat-mxc/include/mach/mx2x.h +++ /dev/null @@ -1,145 +0,0 @@ -/* - * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Juergen Beisert, kernel@pengutronix.de - * - * This contains hardware definitions that are common between i.MX21 and - * i.MX27. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#ifndef __MACH_MX2x_H__ -#define __MACH_MX2x_H__ - -/* The following addresses are common between i.MX21 and i.MX27 */ - -/* Register offsets */ -#define MX2x_AIPI_BASE_ADDR 0x10000000 -#define MX2x_AIPI_SIZE SZ_1M -#define MX2x_DMA_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x01000) -#define MX2x_WDOG_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x02000) -#define MX2x_GPT1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x03000) -#define MX2x_GPT2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x04000) -#define MX2x_GPT3_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x05000) -#define MX2x_PWM_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x06000) -#define MX2x_RTC_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x07000) -#define MX2x_KPP_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x08000) -#define MX2x_OWIRE_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x09000) -#define MX2x_UART1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0a000) -#define MX2x_UART2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0b000) -#define MX2x_UART3_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0c000) -#define MX2x_UART4_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0d000) -#define MX2x_CSPI1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0e000) -#define MX2x_CSPI2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0f000) -#define MX2x_SSI1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x10000) -#define MX2x_SSI2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x11000) -#define MX2x_I2C_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x12000) -#define MX2x_SDHC1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x13000) -#define MX2x_SDHC2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x14000) -#define MX2x_GPIO_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x15000) -#define MX2x_AUDMUX_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x16000) -#define MX2x_CSPI3_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x17000) -#define MX2x_LCDC_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x21000) -#define MX2x_SLCDC_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x22000) -#define MX2x_USBOTG_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x24000) -#define MX2x_EMMA_PP_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x26000) -#define MX2x_EMMA_PRP_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x26400) -#define MX2x_CCM_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x27000) -#define MX2x_SYSCTRL_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x27800) -#define MX2x_JAM_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x3e000) -#define MX2x_MAX_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x3f000) - -#define MX2x_AVIC_BASE_ADDR 0x10040000 - -#define MX2x_SAHB1_BASE_ADDR 0x80000000 -#define MX2x_SAHB1_SIZE SZ_1M -#define MX2x_CSI_BASE_ADDR (MX2x_SAHB1_BASE_ADDR + 0x0000) - -/* fixed interrupt numbers */ -#include <asm/irq.h> -#define MX2x_INT_CSPI3 (NR_IRQS_LEGACY + 6) -#define MX2x_INT_GPIO (NR_IRQS_LEGACY + 8) -#define MX2x_INT_SDHC2 (NR_IRQS_LEGACY + 10) -#define MX2x_INT_SDHC1 (NR_IRQS_LEGACY + 11) -#define MX2x_INT_I2C (NR_IRQS_LEGACY + 12) -#define MX2x_INT_SSI2 (NR_IRQS_LEGACY + 13) -#define MX2x_INT_SSI1 (NR_IRQS_LEGACY + 14) -#define MX2x_INT_CSPI2 (NR_IRQS_LEGACY + 15) -#define MX2x_INT_CSPI1 (NR_IRQS_LEGACY + 16) -#define MX2x_INT_UART4 (NR_IRQS_LEGACY + 17) -#define MX2x_INT_UART3 (NR_IRQS_LEGACY + 18) -#define MX2x_INT_UART2 (NR_IRQS_LEGACY + 19) -#define MX2x_INT_UART1 (NR_IRQS_LEGACY + 20) -#define MX2x_INT_KPP (NR_IRQS_LEGACY + 21) -#define MX2x_INT_RTC (NR_IRQS_LEGACY + 22) -#define MX2x_INT_PWM (NR_IRQS_LEGACY + 23) -#define MX2x_INT_GPT3 (NR_IRQS_LEGACY + 24) -#define MX2x_INT_GPT2 (NR_IRQS_LEGACY + 25) -#define MX2x_INT_GPT1 (NR_IRQS_LEGACY + 26) -#define MX2x_INT_WDOG (NR_IRQS_LEGACY + 27) -#define MX2x_INT_PCMCIA (NR_IRQS_LEGACY + 28) -#define MX2x_INT_NANDFC (NR_IRQS_LEGACY + 29) -#define MX2x_INT_CSI (NR_IRQS_LEGACY + 31) -#define MX2x_INT_DMACH0 (NR_IRQS_LEGACY + 32) -#define MX2x_INT_DMACH1 (NR_IRQS_LEGACY + 33) -#define MX2x_INT_DMACH2 (NR_IRQS_LEGACY + 34) -#define MX2x_INT_DMACH3 (NR_IRQS_LEGACY + 35) -#define MX2x_INT_DMACH4 (NR_IRQS_LEGACY + 36) -#define MX2x_INT_DMACH5 (NR_IRQS_LEGACY + 37) -#define MX2x_INT_DMACH6 (NR_IRQS_LEGACY + 38) -#define MX2x_INT_DMACH7 (NR_IRQS_LEGACY + 39) -#define MX2x_INT_DMACH8 (NR_IRQS_LEGACY + 40) -#define MX2x_INT_DMACH9 (NR_IRQS_LEGACY + 41) -#define MX2x_INT_DMACH10 (NR_IRQS_LEGACY + 42) -#define MX2x_INT_DMACH11 (NR_IRQS_LEGACY + 43) -#define MX2x_INT_DMACH12 (NR_IRQS_LEGACY + 44) -#define MX2x_INT_DMACH13 (NR_IRQS_LEGACY + 45) -#define MX2x_INT_DMACH14 (NR_IRQS_LEGACY + 46) -#define MX2x_INT_DMACH15 (NR_IRQS_LEGACY + 47) -#define MX2x_INT_EMMAPRP (NR_IRQS_LEGACY + 51) -#define MX2x_INT_EMMAPP (NR_IRQS_LEGACY + 52) -#define MX2x_INT_SLCDC (NR_IRQS_LEGACY + 60) -#define MX2x_INT_LCDC (NR_IRQS_LEGACY + 61) - -/* fixed DMA request numbers */ -#define MX2x_DMA_REQ_CSPI3_RX 1 -#define MX2x_DMA_REQ_CSPI3_TX 2 -#define MX2x_DMA_REQ_EXT 3 -#define MX2x_DMA_REQ_SDHC2 6 -#define MX2x_DMA_REQ_SDHC1 7 -#define MX2x_DMA_REQ_SSI2_RX0 8 -#define MX2x_DMA_REQ_SSI2_TX0 9 -#define MX2x_DMA_REQ_SSI2_RX1 10 -#define MX2x_DMA_REQ_SSI2_TX1 11 -#define MX2x_DMA_REQ_SSI1_RX0 12 -#define MX2x_DMA_REQ_SSI1_TX0 13 -#define MX2x_DMA_REQ_SSI1_RX1 14 -#define MX2x_DMA_REQ_SSI1_TX1 15 -#define MX2x_DMA_REQ_CSPI2_RX 16 -#define MX2x_DMA_REQ_CSPI2_TX 17 -#define MX2x_DMA_REQ_CSPI1_RX 18 -#define MX2x_DMA_REQ_CSPI1_TX 19 -#define MX2x_DMA_REQ_UART4_RX 20 -#define MX2x_DMA_REQ_UART4_TX 21 -#define MX2x_DMA_REQ_UART3_RX 22 -#define MX2x_DMA_REQ_UART3_TX 23 -#define MX2x_DMA_REQ_UART2_RX 24 -#define MX2x_DMA_REQ_UART2_TX 25 -#define MX2x_DMA_REQ_UART1_RX 26 -#define MX2x_DMA_REQ_UART1_TX 27 -#define MX2x_DMA_REQ_CSI_STAT 30 -#define MX2x_DMA_REQ_CSI_RX 31 - -#endif /* ifndef __MACH_MX2x_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h deleted file mode 100644 index ee9b1f9215d..00000000000 --- a/arch/arm/plat-mxc/include/mach/mx31.h +++ /dev/null @@ -1,196 +0,0 @@ -#ifndef __MACH_MX31_H__ -#define __MACH_MX31_H__ - -/* - * IRAM - */ -#define MX31_IRAM_BASE_ADDR 0x1ffc0000 /* internal ram */ -#define MX31_IRAM_SIZE SZ_16K - -#define MX31_L2CC_BASE_ADDR 0x30000000 -#define MX31_L2CC_SIZE SZ_1M - -#define MX31_AIPS1_BASE_ADDR 0x43f00000 -#define MX31_AIPS1_SIZE SZ_1M -#define MX31_MAX_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x04000) -#define MX31_EVTMON_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x08000) -#define MX31_CLKCTL_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x0c000) -#define MX31_ETB_SLOT4_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x10000) -#define MX31_ETB_SLOT5_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x14000) -#define MX31_ECT_CTIO_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x18000) -#define MX31_I2C1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x80000) -#define MX31_I2C3_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x84000) -#define MX31_USB_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x88000) -#define MX31_USB_OTG_BASE_ADDR (MX31_USB_BASE_ADDR + 0x0000) -#define MX31_USB_HS1_BASE_ADDR (MX31_USB_BASE_ADDR + 0x0200) -#define MX31_USB_HS2_BASE_ADDR (MX31_USB_BASE_ADDR + 0x0400) -#define MX31_ATA_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x8c000) -#define MX31_UART1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x90000) -#define MX31_UART2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x94000) -#define MX31_I2C2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x98000) -#define MX31_OWIRE_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x9c000) -#define MX31_SSI1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xa0000) -#define MX31_CSPI1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xa4000) -#define MX31_KPP_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xa8000) -#define MX31_IOMUXC_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xac000) -#define MX31_UART4_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xb0000) -#define MX31_UART5_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xb4000) -#define MX31_ECT_IP1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xb8000) -#define MX31_ECT_IP2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xbc000) - -#define MX31_SPBA0_BASE_ADDR 0x50000000 -#define MX31_SPBA0_SIZE SZ_1M -#define MX31_SDHC1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x04000) -#define MX31_SDHC2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x08000) -#define MX31_UART3_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x0c000) -#define MX31_CSPI2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x10000) -#define MX31_SSI2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x14000) -#define MX31_SIM1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x18000) -#define MX31_IIM_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x1c000) -#define MX31_ATA_DMA_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x20000) -#define MX31_MSHC1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x24000) -#define MX31_SPBA_CTRL_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x3c000) - -#define MX31_AIPS2_BASE_ADDR 0x53f00000 -#define MX31_AIPS2_SIZE SZ_1M -#define MX31_CCM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x80000) -#define MX31_CSPI3_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x84000) -#define MX31_FIRI_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x8c000) -#define MX31_GPT1_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x90000) -#define MX31_EPIT1_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x94000) -#define MX31_EPIT2_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x98000) -#define MX31_GPIO3_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xa4000) -#define MX31_SCC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xac000) -#define MX31_SCM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xae000) -#define MX31_SMN_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xaf000) -#define MX31_RNGA_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xb0000) -#define MX31_IPU_CTRL_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xc0000) -#define MX31_AUDMUX_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xc4000) -#define MX31_MPEG4_ENC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xc8000) -#define MX31_GPIO1_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xcc000) -#define MX31_GPIO2_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xd0000) -#define MX31_SDMA_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xd4000) -#define MX31_RTC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xd8000) -#define MX31_WDOG_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xdc000) -#define MX31_PWM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xe0000) -#define MX31_RTIC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xec000) - -#define MX31_ROMP_BASE_ADDR 0x60000000 -#define MX31_ROMP_BASE_ADDR_VIRT IOMEM(0xfc500000) -#define MX31_ROMP_SIZE SZ_1M - -#define MX31_AVIC_BASE_ADDR 0x68000000 -#define MX31_AVIC_SIZE SZ_1M - -#define MX31_IPU_MEM_BASE_ADDR 0x70000000 -#define MX31_CSD0_BASE_ADDR 0x80000000 -#define MX31_CSD1_BASE_ADDR 0x90000000 - -#define MX31_CS0_BASE_ADDR 0xa0000000 -#define MX31_CS1_BASE_ADDR 0xa8000000 -#define MX31_CS2_BASE_ADDR 0xb0000000 -#define MX31_CS3_BASE_ADDR 0xb2000000 - -#define MX31_CS4_BASE_ADDR 0xb4000000 -#define MX31_CS4_BASE_ADDR_VIRT IOMEM(0xf6000000) -#define MX31_CS4_SIZE SZ_32M - -#define MX31_CS5_BASE_ADDR 0xb6000000 -#define MX31_CS5_BASE_ADDR_VIRT IOMEM(0xf8000000) -#define MX31_CS5_SIZE SZ_32M - -#define MX31_X_MEMC_BASE_ADDR 0xb8000000 -#define MX31_X_MEMC_SIZE SZ_64K -#define MX31_NFC_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x0000) -#define MX31_ESDCTL_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x1000) -#define MX31_WEIM_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x2000) -#define MX31_M3IF_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x3000) -#define MX31_EMI_CTL_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x4000) -#define MX31_PCMCIA_CTL_BASE_ADDR MX31_EMI_CTL_BASE_ADDR - -#define MX31_WEIM_CSCRx_BASE_ADDR(cs) (MX31_WEIM_BASE_ADDR + (cs) * 0x10) -#define MX31_WEIM_CSCRxU(cs) (MX31_WEIM_CSCRx_BASE_ADDR(cs)) -#define MX31_WEIM_CSCRxL(cs) (MX31_WEIM_CSCRx_BASE_ADDR(cs) + 0x4) -#define MX31_WEIM_CSCRxA(cs) (MX31_WEIM_CSCRx_BASE_ADDR(cs) + 0x8) - -#define MX31_PCMCIA_MEM_BASE_ADDR 0xbc000000 - -#define MX31_IO_P2V(x) IMX_IO_P2V(x) -#define MX31_IO_ADDRESS(x) IOMEM(MX31_IO_P2V(x)) - -/* - * Interrupt numbers - */ -#include <asm/irq.h> -#define MX31_INT_I2C3 (NR_IRQS_LEGACY + 3) -#define MX31_INT_I2C2 (NR_IRQS_LEGACY + 4) -#define MX31_INT_MPEG4_ENCODER (NR_IRQS_LEGACY + 5) -#define MX31_INT_RTIC (NR_IRQS_LEGACY + 6) -#define MX31_INT_FIRI (NR_IRQS_LEGACY + 7) -#define MX31_INT_SDHC2 (NR_IRQS_LEGACY + 8) -#define MX31_INT_SDHC1 (NR_IRQS_LEGACY + 9) -#define MX31_INT_I2C1 (NR_IRQS_LEGACY + 10) -#define MX31_INT_SSI2 (NR_IRQS_LEGACY + 11) -#define MX31_INT_SSI1 (NR_IRQS_LEGACY + 12) -#define MX31_INT_CSPI2 (NR_IRQS_LEGACY + 13) -#define MX31_INT_CSPI1 (NR_IRQS_LEGACY + 14) -#define MX31_INT_ATA (NR_IRQS_LEGACY + 15) -#define MX31_INT_MBX (NR_IRQS_LEGACY + 16) -#define MX31_INT_CSPI3 (NR_IRQS_LEGACY + 17) -#define MX31_INT_UART3 (NR_IRQS_LEGACY + 18) -#define MX31_INT_IIM (NR_IRQS_LEGACY + 19) -#define MX31_INT_SIM2 (NR_IRQS_LEGACY + 20) -#define MX31_INT_SIM1 (NR_IRQS_LEGACY + 21) -#define MX31_INT_RNGA (NR_IRQS_LEGACY + 22) -#define MX31_INT_EVTMON (NR_IRQS_LEGACY + 23) -#define MX31_INT_KPP (NR_IRQS_LEGACY + 24) -#define MX31_INT_RTC (NR_IRQS_LEGACY + 25) -#define MX31_INT_PWM (NR_IRQS_LEGACY + 26) -#define MX31_INT_EPIT2 (NR_IRQS_LEGACY + 27) -#define MX31_INT_EPIT1 (NR_IRQS_LEGACY + 28) -#define MX31_INT_GPT (NR_IRQS_LEGACY + 29) -#define MX31_INT_POWER_FAIL (NR_IRQS_LEGACY + 30) -#define MX31_INT_CCM_DVFS (NR_IRQS_LEGACY + 31) -#define MX31_INT_UART2 (NR_IRQS_LEGACY + 32) -#define MX31_INT_NFC (NR_IRQS_LEGACY + 33) -#define MX31_INT_SDMA (NR_IRQS_LEGACY + 34) -#define MX31_INT_USB_HS1 (NR_IRQS_LEGACY + 35) -#define MX31_INT_USB_HS2 (NR_IRQS_LEGACY + 36) -#define MX31_INT_USB_OTG (NR_IRQS_LEGACY + 37) -#define MX31_INT_MSHC1 (NR_IRQS_LEGACY + 39) -#define MX31_INT_MSHC2 (NR_IRQS_LEGACY + 40) -#define MX31_INT_IPU_ERR (NR_IRQS_LEGACY + 41) -#define MX31_INT_IPU_SYN (NR_IRQS_LEGACY + 42) -#define MX31_INT_UART1 (NR_IRQS_LEGACY + 45) -#define MX31_INT_UART4 (NR_IRQS_LEGACY + 46) -#define MX31_INT_UART5 (NR_IRQS_LEGACY + 47) -#define MX31_INT_ECT (NR_IRQS_LEGACY + 48) -#define MX31_INT_SCC_SCM (NR_IRQS_LEGACY + 49) -#define MX31_INT_SCC_SMN (NR_IRQS_LEGACY + 50) -#define MX31_INT_GPIO2 (NR_IRQS_LEGACY + 51) -#define MX31_INT_GPIO1 (NR_IRQS_LEGACY + 52) -#define MX31_INT_CCM (NR_IRQS_LEGACY + 53) -#define MX31_INT_PCMCIA (NR_IRQS_LEGACY + 54) -#define MX31_INT_WDOG (NR_IRQS_LEGACY + 55) -#define MX31_INT_GPIO3 (NR_IRQS_LEGACY + 56) -#define MX31_INT_EXT_POWER (NR_IRQS_LEGACY + 58) -#define MX31_INT_EXT_TEMPER (NR_IRQS_LEGACY + 59) -#define MX31_INT_EXT_SENSOR60 (NR_IRQS_LEGACY + 60) -#define MX31_INT_EXT_SENSOR61 (NR_IRQS_LEGACY + 61) -#define MX31_INT_EXT_WDOG (NR_IRQS_LEGACY + 62) -#define MX31_INT_EXT_TV (NR_IRQS_LEGACY + 63) - -#define MX31_DMA_REQ_SDHC1 20 -#define MX31_DMA_REQ_SDHC2 21 -#define MX31_DMA_REQ_SSI2_RX1 22 -#define MX31_DMA_REQ_SSI2_TX1 23 -#define MX31_DMA_REQ_SSI2_RX0 24 -#define MX31_DMA_REQ_SSI2_TX0 25 -#define MX31_DMA_REQ_SSI1_RX1 26 -#define MX31_DMA_REQ_SSI1_TX1 27 -#define MX31_DMA_REQ_SSI1_RX0 28 -#define MX31_DMA_REQ_SSI1_TX0 29 - -#define MX31_PROD_SIGNATURE 0x1 /* For MX31 */ - -#endif /* ifndef __MACH_MX31_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx35.h b/arch/arm/plat-mxc/include/mach/mx35.h deleted file mode 100644 index 2af5d3a699c..00000000000 --- a/arch/arm/plat-mxc/include/mach/mx35.h +++ /dev/null @@ -1,190 +0,0 @@ -#ifndef __MACH_MX35_H__ -#define __MACH_MX35_H__ - -/* - * IRAM - */ -#define MX35_IRAM_BASE_ADDR 0x10000000 /* internal ram */ -#define MX35_IRAM_SIZE SZ_128K - -#define MX35_L2CC_BASE_ADDR 0x30000000 -#define MX35_L2CC_SIZE SZ_1M - -#define MX35_AIPS1_BASE_ADDR 0x43f00000 -#define MX35_AIPS1_SIZE SZ_1M -#define MX35_MAX_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x04000) -#define MX35_EVTMON_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x08000) -#define MX35_CLKCTL_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x0c000) -#define MX35_ETB_SLOT4_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x10000) -#define MX35_ETB_SLOT5_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x14000) -#define MX35_ECT_CTIO_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x18000) -#define MX35_I2C1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x80000) -#define MX35_I2C3_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x84000) -#define MX35_UART1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x90000) -#define MX35_UART2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x94000) -#define MX35_I2C2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x98000) -#define MX35_OWIRE_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x9c000) -#define MX35_SSI1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xa0000) -#define MX35_CSPI1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xa4000) -#define MX35_KPP_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xa8000) -#define MX35_IOMUXC_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xac000) -#define MX35_ECT_IP1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xb8000) -#define MX35_ECT_IP2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xbc000) - -#define MX35_SPBA0_BASE_ADDR 0x50000000 -#define MX35_SPBA0_SIZE SZ_1M -#define MX35_UART3_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x0c000) -#define MX35_CSPI2_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x10000) -#define MX35_SSI2_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x14000) -#define MX35_ATA_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x20000) -#define MX35_MSHC1_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x24000) -#define MX35_FEC_BASE_ADDR 0x50038000 -#define MX35_SPBA_CTRL_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x3c000) - -#define MX35_AIPS2_BASE_ADDR 0x53f00000 -#define MX35_AIPS2_SIZE SZ_1M -#define MX35_CCM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x80000) -#define MX35_GPT1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x90000) -#define MX35_EPIT1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x94000) -#define MX35_EPIT2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x98000) -#define MX35_GPIO3_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xa4000) -#define MX35_SCC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xac000) -#define MX35_RNGA_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xb0000) -#define MX35_ESDHC1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xb4000) -#define MX35_ESDHC2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xb8000) -#define MX35_ESDHC3_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xbc000) -#define MX35_IPU_CTRL_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xc0000) -#define MX35_AUDMUX_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xc4000) -#define MX35_GPIO1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xcc000) -#define MX35_GPIO2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xd0000) -#define MX35_SDMA_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xd4000) -#define MX35_RTC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xd8000) -#define MX35_WDOG_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xdc000) -#define MX35_PWM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe0000) -#define MX35_CAN1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe4000) -#define MX35_CAN2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe8000) -#define MX35_RTIC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xec000) -#define MX35_IIM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xf0000) -#define MX35_USB_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xf4000) -#define MX35_USB_OTG_BASE_ADDR (MX35_USB_BASE_ADDR + 0x0000) -/* - * The Reference Manual (IMX35RM, Rev. 2, 3/2009) claims an offset of 0x200 for - * HS. When host support was implemented only a preliminary document was - * available, which told 0x400. This works fine. - */ -#define MX35_USB_HS_BASE_ADDR (MX35_USB_BASE_ADDR + 0x0400) - -#define MX35_ROMP_BASE_ADDR 0x60000000 -#define MX35_ROMP_SIZE SZ_1M - -#define MX35_AVIC_BASE_ADDR 0x68000000 -#define MX35_AVIC_SIZE SZ_1M - -/* - * Memory regions and CS - */ -#define MX35_IPU_MEM_BASE_ADDR 0x70000000 -#define MX35_CSD0_BASE_ADDR 0x80000000 -#define MX35_CSD1_BASE_ADDR 0x90000000 - -#define MX35_CS0_BASE_ADDR 0xa0000000 -#define MX35_CS1_BASE_ADDR 0xa8000000 -#define MX35_CS2_BASE_ADDR 0xb0000000 -#define MX35_CS3_BASE_ADDR 0xb2000000 - -#define MX35_CS4_BASE_ADDR 0xb4000000 -#define MX35_CS4_BASE_ADDR_VIRT 0xf6000000 -#define MX35_CS4_SIZE SZ_32M - -#define MX35_CS5_BASE_ADDR 0xb6000000 -#define MX35_CS5_BASE_ADDR_VIRT 0xf8000000 -#define MX35_CS5_SIZE SZ_32M - -/* - * NAND, SDRAM, WEIM, M3IF, EMI controllers - */ -#define MX35_X_MEMC_BASE_ADDR 0xb8000000 -#define MX35_X_MEMC_SIZE SZ_64K -#define MX35_ESDCTL_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x1000) -#define MX35_WEIM_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x2000) -#define MX35_M3IF_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x3000) -#define MX35_EMI_CTL_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x4000) -#define MX35_PCMCIA_CTL_BASE_ADDR MX35_EMI_CTL_BASE_ADDR - -#define MX35_NFC_BASE_ADDR 0xbb000000 -#define MX35_PCMCIA_MEM_BASE_ADDR 0xbc000000 - -#define MX35_IO_P2V(x) IMX_IO_P2V(x) -#define MX35_IO_ADDRESS(x) IOMEM(MX35_IO_P2V(x)) - -/* - * Interrupt numbers - */ -#include <asm/irq.h> -#define MX35_INT_OWIRE (NR_IRQS_LEGACY + 2) -#define MX35_INT_I2C3 (NR_IRQS_LEGACY + 3) -#define MX35_INT_I2C2 (NR_IRQS_LEGACY + 4) -#define MX35_INT_RTIC (NR_IRQS_LEGACY + 6) -#define MX35_INT_ESDHC1 (NR_IRQS_LEGACY + 7) -#define MX35_INT_ESDHC2 (NR_IRQS_LEGACY + 8) -#define MX35_INT_ESDHC3 (NR_IRQS_LEGACY + 9) -#define MX35_INT_I2C1 (NR_IRQS_LEGACY + 10) -#define MX35_INT_SSI1 (NR_IRQS_LEGACY + 11) -#define MX35_INT_SSI2 (NR_IRQS_LEGACY + 12) -#define MX35_INT_CSPI2 (NR_IRQS_LEGACY + 13) -#define MX35_INT_CSPI1 (NR_IRQS_LEGACY + 14) -#define MX35_INT_ATA (NR_IRQS_LEGACY + 15) -#define MX35_INT_GPU2D (NR_IRQS_LEGACY + 16) -#define MX35_INT_ASRC (NR_IRQS_LEGACY + 17) -#define MX35_INT_UART3 (NR_IRQS_LEGACY + 18) -#define MX35_INT_IIM (NR_IRQS_LEGACY + 19) -#define MX35_INT_RNGA (NR_IRQS_LEGACY + 22) -#define MX35_INT_EVTMON (NR_IRQS_LEGACY + 23) -#define MX35_INT_KPP (NR_IRQS_LEGACY + 24) -#define MX35_INT_RTC (NR_IRQS_LEGACY + 25) -#define MX35_INT_PWM (NR_IRQS_LEGACY + 26) -#define MX35_INT_EPIT2 (NR_IRQS_LEGACY + 27) -#define MX35_INT_EPIT1 (NR_IRQS_LEGACY + 28) -#define MX35_INT_GPT (NR_IRQS_LEGACY + 29) -#define MX35_INT_POWER_FAIL (NR_IRQS_LEGACY + 30) -#define MX35_INT_UART2 (NR_IRQS_LEGACY + 32) -#define MX35_INT_NFC (NR_IRQS_LEGACY + 33) -#define MX35_INT_SDMA (NR_IRQS_LEGACY + 34) -#define MX35_INT_USB_HS (NR_IRQS_LEGACY + 35) -#define MX35_INT_USB_OTG (NR_IRQS_LEGACY + 37) -#define MX35_INT_MSHC1 (NR_IRQS_LEGACY + 39) -#define MX35_INT_ESAI (NR_IRQS_LEGACY + 40) -#define MX35_INT_IPU_ERR (NR_IRQS_LEGACY + 41) -#define MX35_INT_IPU_SYN (NR_IRQS_LEGACY + 42) -#define MX35_INT_CAN1 (NR_IRQS_LEGACY + 43) -#define MX35_INT_CAN2 (NR_IRQS_LEGACY + 44) -#define MX35_INT_UART1 (NR_IRQS_LEGACY + 45) -#define MX35_INT_MLB (NR_IRQS_LEGACY + 46) -#define MX35_INT_SPDIF (NR_IRQS_LEGACY + 47) -#define MX35_INT_ECT (NR_IRQS_LEGACY + 48) -#define MX35_INT_SCC_SCM (NR_IRQS_LEGACY + 49) -#define MX35_INT_SCC_SMN (NR_IRQS_LEGACY + 50) -#define MX35_INT_GPIO2 (NR_IRQS_LEGACY + 51) -#define MX35_INT_GPIO1 (NR_IRQS_LEGACY + 52) -#define MX35_INT_WDOG (NR_IRQS_LEGACY + 55) -#define MX35_INT_GPIO3 (NR_IRQS_LEGACY + 56) -#define MX35_INT_FEC (NR_IRQS_LEGACY + 57) -#define MX35_INT_EXT_POWER (NR_IRQS_LEGACY + 58) -#define MX35_INT_EXT_TEMPER (NR_IRQS_LEGACY + 59) -#define MX35_INT_EXT_SENSOR60 (NR_IRQS_LEGACY + 60) -#define MX35_INT_EXT_SENSOR61 (NR_IRQS_LEGACY + 61) -#define MX35_INT_EXT_WDOG (NR_IRQS_LEGACY + 62) -#define MX35_INT_EXT_TV (NR_IRQS_LEGACY + 63) - -#define MX35_DMA_REQ_SSI2_RX1 22 -#define MX35_DMA_REQ_SSI2_TX1 23 -#define MX35_DMA_REQ_SSI2_RX0 24 -#define MX35_DMA_REQ_SSI2_TX0 25 -#define MX35_DMA_REQ_SSI1_RX1 26 -#define MX35_DMA_REQ_SSI1_TX1 27 -#define MX35_DMA_REQ_SSI1_RX0 28 -#define MX35_DMA_REQ_SSI1_TX0 29 - -#define MX35_PROD_SIGNATURE 0x1 /* For MX31 */ - -#endif /* ifndef __MACH_MX35_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx3x.h b/arch/arm/plat-mxc/include/mach/mx3x.h deleted file mode 100644 index 96fb4fbc8ad..00000000000 --- a/arch/arm/plat-mxc/include/mach/mx3x.h +++ /dev/null @@ -1,195 +0,0 @@ -/* - * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. - */ - -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __MACH_MX3x_H__ -#define __MACH_MX3x_H__ - -/* - * MX31 memory map: - * - * Virt Phys Size What - * --------------------------------------------------------------------------- - * FC000000 43F00000 1M AIPS 1 - * FC100000 50000000 1M SPBA - * FC200000 53F00000 1M AIPS 2 - * FC500000 60000000 128M ROMPATCH - * FC400000 68000000 128M AVIC - * 70000000 256M IPU (MAX M2) - * 80000000 256M CSD0 SDRAM/DDR - * 90000000 256M CSD1 SDRAM/DDR - * A0000000 128M CS0 Flash - * A8000000 128M CS1 Flash - * B0000000 32M CS2 - * B2000000 32M CS3 - * F4000000 B4000000 32M CS4 - * B6000000 32M CS5 - * FC320000 B8000000 64K NAND, SDRAM, WEIM, M3IF, EMI controllers - * C0000000 64M PCMCIA/CF - */ - -/* - * L2CC - */ -#define MX3x_L2CC_BASE_ADDR 0x30000000 -#define MX3x_L2CC_SIZE SZ_1M - -/* - * AIPS 1 - */ -#define MX3x_AIPS1_BASE_ADDR 0x43f00000 -#define MX3x_AIPS1_SIZE SZ_1M -#define MX3x_MAX_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x04000) -#define MX3x_EVTMON_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x08000) -#define MX3x_CLKCTL_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x0c000) -#define MX3x_ETB_SLOT4_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x10000) -#define MX3x_ETB_SLOT5_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x14000) -#define MX3x_ECT_CTIO_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x18000) -#define MX3x_I2C_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x80000) -#define MX3x_I2C3_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x84000) -#define MX3x_UART1_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x90000) -#define MX3x_UART2_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x94000) -#define MX3x_I2C2_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x98000) -#define MX3x_OWIRE_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x9c000) -#define MX3x_SSI1_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xa0000) -#define MX3x_CSPI1_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xa4000) -#define MX3x_KPP_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xa8000) -#define MX3x_IOMUXC_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xac000) -#define MX3x_ECT_IP1_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xb8000) -#define MX3x_ECT_IP2_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xbc000) - -/* - * SPBA global module enabled #0 - */ -#define MX3x_SPBA0_BASE_ADDR 0x50000000 -#define MX3x_SPBA0_SIZE SZ_1M -#define MX3x_UART3_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x0c000) -#define MX3x_CSPI2_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x10000) -#define MX3x_SSI2_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x14000) -#define MX3x_ATA_DMA_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x20000) -#define MX3x_MSHC1_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x24000) -#define MX3x_SPBA_CTRL_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x3c000) - -/* - * AIPS 2 - */ -#define MX3x_AIPS2_BASE_ADDR 0x53f00000 -#define MX3x_AIPS2_SIZE SZ_1M -#define MX3x_CCM_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x80000) -#define MX3x_GPT1_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x90000) -#define MX3x_EPIT1_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x94000) -#define MX3x_EPIT2_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x98000) -#define MX3x_GPIO3_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xa4000) -#define MX3x_SCC_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xac000) -#define MX3x_RNGA_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xb0000) -#define MX3x_IPU_CTRL_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xc0000) -#define MX3x_AUDMUX_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xc4000) -#define MX3x_GPIO1_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xcc000) -#define MX3x_GPIO2_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xd0000) -#define MX3x_SDMA_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xd4000) -#define MX3x_RTC_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xd8000) -#define MX3x_WDOG_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xdc000) -#define MX3x_PWM_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xe0000) -#define MX3x_RTIC_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xec000) - -/* - * ROMP and AVIC - */ -#define MX3x_ROMP_BASE_ADDR 0x60000000 -#define MX3x_ROMP_SIZE SZ_1M - -#define MX3x_AVIC_BASE_ADDR 0x68000000 -#define MX3x_AVIC_SIZE SZ_1M - -/* - * Memory regions and CS - */ -#define MX3x_IPU_MEM_BASE_ADDR 0x70000000 -#define MX3x_CSD0_BASE_ADDR 0x80000000 -#define MX3x_CSD1_BASE_ADDR 0x90000000 - -#define MX3x_CS0_BASE_ADDR 0xa0000000 -#define MX3x_CS1_BASE_ADDR 0xa8000000 -#define MX3x_CS2_BASE_ADDR 0xb0000000 -#define MX3x_CS3_BASE_ADDR 0xb2000000 - -#define MX3x_CS4_BASE_ADDR 0xb4000000 -#define MX3x_CS4_BASE_ADDR_VIRT 0xf6000000 -#define MX3x_CS4_SIZE SZ_32M - -#define MX3x_CS5_BASE_ADDR 0xb6000000 -#define MX3x_CS5_BASE_ADDR_VIRT 0xf8000000 -#define MX3x_CS5_SIZE SZ_32M - -/* - * NAND, SDRAM, WEIM, M3IF, EMI controllers - */ -#define MX3x_X_MEMC_BASE_ADDR 0xb8000000 -#define MX3x_X_MEMC_SIZE SZ_64K -#define MX3x_ESDCTL_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x1000) -#define MX3x_WEIM_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x2000) -#define MX3x_M3IF_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x3000) -#define MX3x_EMI_CTL_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x4000) -#define MX3x_PCMCIA_CTL_BASE_ADDR MX3x_EMI_CTL_BASE_ADDR - -#define MX3x_PCMCIA_MEM_BASE_ADDR 0xbc000000 - -/* - * Interrupt numbers - */ -#include <asm/irq.h> -#define MX3x_INT_I2C3 (NR_IRQS_LEGACY + 3) -#define MX3x_INT_I2C2 (NR_IRQS_LEGACY + 4) -#define MX3x_INT_RTIC (NR_IRQS_LEGACY + 6) -#define MX3x_INT_I2C (NR_IRQS_LEGACY + 10) -#define MX3x_INT_CSPI2 (NR_IRQS_LEGACY + 13) -#define MX3x_INT_CSPI1 (NR_IRQS_LEGACY + 14) -#define MX3x_INT_ATA (NR_IRQS_LEGACY + 15) -#define MX3x_INT_UART3 (NR_IRQS_LEGACY + 18) -#define MX3x_INT_IIM (NR_IRQS_LEGACY + 19) -#define MX3x_INT_RNGA (NR_IRQS_LEGACY + 22) -#define MX3x_INT_EVTMON (NR_IRQS_LEGACY + 23) -#define MX3x_INT_KPP (NR_IRQS_LEGACY + 24) -#define MX3x_INT_RTC (NR_IRQS_LEGACY + 25) -#define MX3x_INT_PWM (NR_IRQS_LEGACY + 26) -#define MX3x_INT_EPIT2 (NR_IRQS_LEGACY + 27) -#define MX3x_INT_EPIT1 (NR_IRQS_LEGACY + 28) -#define MX3x_INT_GPT (NR_IRQS_LEGACY + 29) -#define MX3x_INT_POWER_FAIL (NR_IRQS_LEGACY + 30) -#define MX3x_INT_UART2 (NR_IRQS_LEGACY + 32) -#define MX3x_INT_NANDFC (NR_IRQS_LEGACY + 33) -#define MX3x_INT_SDMA (NR_IRQS_LEGACY + 34) -#define MX3x_INT_MSHC1 (NR_IRQS_LEGACY + 39) -#define MX3x_INT_IPU_ERR (NR_IRQS_LEGACY + 41) -#define MX3x_INT_IPU_SYN (NR_IRQS_LEGACY + 42) -#define MX3x_INT_UART1 (NR_IRQS_LEGACY + 45) -#define MX3x_INT_ECT (NR_IRQS_LEGACY + 48) -#define MX3x_INT_SCC_SCM (NR_IRQS_LEGACY + 49) -#define MX3x_INT_SCC_SMN (NR_IRQS_LEGACY + 50) -#define MX3x_INT_GPIO2 (NR_IRQS_LEGACY + 51) -#define MX3x_INT_GPIO1 (NR_IRQS_LEGACY + 52) -#define MX3x_INT_WDOG (NR_IRQS_LEGACY + 55) -#define MX3x_INT_GPIO3 (NR_IRQS_LEGACY + 56) -#define MX3x_INT_EXT_POWER (NR_IRQS_LEGACY + 58) -#define MX3x_INT_EXT_TEMPER (NR_IRQS_LEGACY + 59) -#define MX3x_INT_EXT_SENSOR60 (NR_IRQS_LEGACY + 60) -#define MX3x_INT_EXT_SENSOR61 (NR_IRQS_LEGACY + 61) -#define MX3x_INT_EXT_WDOG (NR_IRQS_LEGACY + 62) -#define MX3x_INT_EXT_TV (NR_IRQS_LEGACY + 63) - -#define MX3x_PROD_SIGNATURE 0x1 /* For MX31 */ - -/* Mandatory defines used globally */ - -#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS) -extern int mx35_revision(void); -extern int mx31_revision(void); -#endif - -#endif /* ifndef __MACH_MX3x_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx50.h b/arch/arm/plat-mxc/include/mach/mx50.h deleted file mode 100644 index 09ac19c1570..00000000000 --- a/arch/arm/plat-mxc/include/mach/mx50.h +++ /dev/null @@ -1,290 +0,0 @@ -#ifndef __MACH_MX50_H__ -#define __MACH_MX50_H__ - -/* - * IROM - */ -#define MX50_IROM_BASE_ADDR 0x0 -#define MX50_IROM_SIZE SZ_64K - -/* TZIC */ -#define MX50_TZIC_BASE_ADDR 0x0fffc000 -#define MX50_TZIC_SIZE SZ_16K - -/* - * IRAM - */ -#define MX50_IRAM_BASE_ADDR 0xf8000000 /* internal ram */ -#define MX50_IRAM_PARTITIONS 16 -#define MX50_IRAM_SIZE (MX50_IRAM_PARTITIONS * SZ_8K) /* 128KB */ - -/* - * Databahn - */ -#define MX50_DATABAHN_BASE_ADDR 0x14000000 - -/* - * Graphics Memory of GPU - */ -#define MX50_GPU2D_BASE_ADDR 0x20000000 - -#define MX50_DEBUG_BASE_ADDR 0x40000000 -#define MX50_DEBUG_SIZE SZ_1M -#define MX50_ETB_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00001000) -#define MX50_ETM_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00002000) -#define MX50_TPIU_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00003000) -#define MX50_CTI0_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00004000) -#define MX50_CTI1_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00005000) -#define MX50_CTI2_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00006000) -#define MX50_CTI3_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00007000) -#define MX50_CORTEX_DBG_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00008000) - -#define MX50_APBHDMA_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01000000) -#define MX50_OCOTP_CTRL_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01002000) -#define MX50_DIGCTL_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01004000) -#define MX50_GPMI_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01006000) -#define MX50_BCH_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01008000) -#define MX50_ELCDIF_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x0100a000) -#define MX50_EPXP_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x0100c000) -#define MX50_DCP_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x0100e000) -#define MX50_EPDC_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01010000) -#define MX50_QOSC_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01012000) -#define MX50_PERFMON_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01014000) -#define MX50_SSP_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01016000) -#define MX50_ANATOP_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01018000) -#define MX50_NIC_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x08000000) - -/* - * SPBA global module enabled #0 - */ -#define MX50_SPBA0_BASE_ADDR 0x50000000 -#define MX50_SPBA0_SIZE SZ_1M - -#define MX50_MMC_SDHC1_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00004000) -#define MX50_MMC_SDHC2_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00008000) -#define MX50_UART3_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x0000c000) -#define MX50_CSPI1_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00010000) -#define MX50_SSI2_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00014000) -#define MX50_MMC_SDHC3_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00020000) -#define MX50_MMC_SDHC4_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00024000) - -/* - * AIPS 1 - */ -#define MX50_AIPS1_BASE_ADDR 0x53f00000 -#define MX50_AIPS1_SIZE SZ_1M - -#define MX50_OTG_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00080000) -#define MX50_GPIO1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00084000) -#define MX50_GPIO2_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00088000) -#define MX50_GPIO3_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x0008c000) -#define MX50_GPIO4_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00090000) -#define MX50_KPP_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00094000) -#define MX50_WDOG_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00098000) -#define MX50_GPT1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000a0000) -#define MX50_SRTC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000a4000) -#define MX50_IOMUXC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000a8000) -#define MX50_EPIT1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000ac000) -#define MX50_PWM1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000b4000) -#define MX50_PWM2_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000b8000) -#define MX50_UART1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000bc000) -#define MX50_UART2_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000c0000) -#define MX50_SRC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000d0000) -#define MX50_CCM_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000d4000) -#define MX50_GPC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000d8000) -#define MX50_GPIO5_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000dc000) -#define MX50_GPIO6_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000e0000) -#define MX50_I2C3_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000ec000) -#define MX50_UART4_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000f0000) - -#define MX50_MSHC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000f4000) -#define MX50_RNGB_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000f8000) - -/* - * AIPS 2 - */ -#define MX50_AIPS2_BASE_ADDR 0x63f00000 -#define MX50_AIPS2_SIZE SZ_1M - -#define MX50_PLL1_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00080000) -#define MX50_PLL2_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00084000) -#define MX50_PLL3_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00088000) -#define MX50_UART5_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00090000) -#define MX50_AHBMAX_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00094000) -#define MX50_ARM_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000a0000) -#define MX50_OWIRE_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000a4000) -#define MX50_CSPI2_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000ac000) -#define MX50_SDMA_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000b0000) -#define MX50_ROMCP_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000b8000) -#define MX50_CSPI3_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000c0000) -#define MX50_I2C2_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000c4000) -#define MX50_I2C1_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000c8000) -#define MX50_SSI1_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000cc000) -#define MX50_AUDMUX_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000d0000) -#define MX50_WEIM_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000d8000) -#define MX50_FEC_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000ec000) - -/* - * Memory regions and CS - */ -#define MX50_CSD0_BASE_ADDR 0x70000000 -#define MX50_CSD1_BASE_ADDR 0xb0000000 -#define MX50_CS0_BASE_ADDR 0xf0000000 - -#define MX50_IO_P2V(x) IMX_IO_P2V(x) -#define MX50_IO_ADDRESS(x) IOMEM(MX50_IO_P2V(x)) - -/* - * defines for SPBA modules - */ -#define MX50_SPBA_SDHC1 0x04 -#define MX50_SPBA_SDHC2 0x08 -#define MX50_SPBA_UART3 0x0c -#define MX50_SPBA_CSPI1 0x10 -#define MX50_SPBA_SSI2 0x14 -#define MX50_SPBA_SDHC3 0x20 -#define MX50_SPBA_SDHC4 0x24 -#define MX50_SPBA_SPDIF 0x28 -#define MX50_SPBA_ATA 0x30 -#define MX50_SPBA_SLIM 0x34 -#define MX50_SPBA_HSI2C 0x38 -#define MX50_SPBA_CTRL 0x3c - -/* - * DMA request assignments - */ -#define MX50_DMA_REQ_GPC 1 -#define MX50_DMA_REQ_ATA_UART4_RX 2 -#define MX50_DMA_REQ_ATA_UART4_TX 3 -#define MX50_DMA_REQ_CSPI1_RX 6 -#define MX50_DMA_REQ_CSPI1_TX 7 -#define MX50_DMA_REQ_CSPI2_RX 8 -#define MX50_DMA_REQ_CSPI2_TX 9 -#define MX50_DMA_REQ_I2C3_SDHC3 10 -#define MX50_DMA_REQ_SDHC4 11 -#define MX50_DMA_REQ_UART2_FIRI_RX 12 -#define MX50_DMA_REQ_UART2_FIRI_TX 13 -#define MX50_DMA_REQ_EXT0 14 -#define MX50_DMA_REQ_EXT1 15 -#define MX50_DMA_REQ_UART5_RX 16 -#define MX50_DMA_REQ_UART5_TX 17 -#define MX50_DMA_REQ_UART1_RX 18 -#define MX50_DMA_REQ_UART1_TX 19 -#define MX50_DMA_REQ_I2C1_SDHC1 20 -#define MX50_DMA_REQ_I2C2_SDHC2 21 -#define MX50_DMA_REQ_SSI2_RX2 22 -#define MX50_DMA_REQ_SSI2_TX2 23 -#define MX50_DMA_REQ_SSI2_RX1 24 -#define MX50_DMA_REQ_SSI2_TX1 25 -#define MX50_DMA_REQ_SSI1_RX2 26 -#define MX50_DMA_REQ_SSI1_TX2 27 -#define MX50_DMA_REQ_SSI1_RX1 28 -#define MX50_DMA_REQ_SSI1_TX1 29 -#define MX50_DMA_REQ_CSPI_RX 38 -#define MX50_DMA_REQ_CSPI_TX 39 -#define MX50_DMA_REQ_UART3_RX 42 -#define MX50_DMA_REQ_UART3_TX 43 - -/* - * Interrupt numbers - */ -#include <asm/irq.h> -#define MX50_INT_MMC_SDHC1 (NR_IRQS_LEGACY + 1) -#define MX50_INT_MMC_SDHC2 (NR_IRQS_LEGACY + 2) -#define MX50_INT_MMC_SDHC3 (NR_IRQS_LEGACY + 3) -#define MX50_INT_MMC_SDHC4 (NR_IRQS_LEGACY + 4) -#define MX50_INT_DAP (NR_IRQS_LEGACY + 5) -#define MX50_INT_SDMA (NR_IRQS_LEGACY + 6) -#define MX50_INT_IOMUX (NR_IRQS_LEGACY + 7) -#define MX50_INT_UART4 (NR_IRQS_LEGACY + 13) -#define MX50_INT_USB_H1 (NR_IRQS_LEGACY + 14) -#define MX50_INT_USB_OTG (NR_IRQS_LEGACY + 18) -#define MX50_INT_DATABAHN (NR_IRQS_LEGACY + 19) -#define MX50_INT_ELCDIF (NR_IRQS_LEGACY + 20) -#define MX50_INT_EPXP (NR_IRQS_LEGACY + 21) -#define MX50_INT_SRTC_NTZ (NR_IRQS_LEGACY + 24) -#define MX50_INT_SRTC_TZ (NR_IRQS_LEGACY + 25) -#define MX50_INT_EPDC (NR_IRQS_LEGACY + 27) -#define MX50_INT_NIC (NR_IRQS_LEGACY + 28) -#define MX50_INT_SSI1 (NR_IRQS_LEGACY + 29) -#define MX50_INT_SSI2 (NR_IRQS_LEGACY + 30) -#define MX50_INT_UART1 (NR_IRQS_LEGACY + 31) -#define MX50_INT_UART2 (NR_IRQS_LEGACY + 32) -#define MX50_INT_UART3 (NR_IRQS_LEGACY + 33) -#define MX50_INT_RESV34 (NR_IRQS_LEGACY + 34) -#define MX50_INT_RESV35 (NR_IRQS_LEGACY + 35) -#define MX50_INT_CSPI1 (NR_IRQS_LEGACY + 36) -#define MX50_INT_CSPI2 (NR_IRQS_LEGACY + 37) -#define MX50_INT_CSPI (NR_IRQS_LEGACY + 38) -#define MX50_INT_GPT (NR_IRQS_LEGACY + 39) -#define MX50_INT_EPIT1 (NR_IRQS_LEGACY + 40) -#define MX50_INT_GPIO1_INT7 (NR_IRQS_LEGACY + 42) -#define MX50_INT_GPIO1_INT6 (NR_IRQS_LEGACY + 43) -#define MX50_INT_GPIO1_INT5 (NR_IRQS_LEGACY + 44) -#define MX50_INT_GPIO1_INT4 (NR_IRQS_LEGACY + 45) -#define MX50_INT_GPIO1_INT3 (NR_IRQS_LEGACY + 46) -#define MX50_INT_GPIO1_INT2 (NR_IRQS_LEGACY + 47) -#define MX50_INT_GPIO1_INT1 (NR_IRQS_LEGACY + 48) -#define MX50_INT_GPIO1_INT0 (NR_IRQS_LEGACY + 49) -#define MX50_INT_GPIO1_LOW (NR_IRQS_LEGACY + 50) -#define MX50_INT_GPIO1_HIGH (NR_IRQS_LEGACY + 51) -#define MX50_INT_GPIO2_LOW (NR_IRQS_LEGACY + 52) -#define MX50_INT_GPIO2_HIGH (NR_IRQS_LEGACY + 53) -#define MX50_INT_GPIO3_LOW (NR_IRQS_LEGACY + 54) -#define MX50_INT_GPIO3_HIGH (NR_IRQS_LEGACY + 55) -#define MX50_INT_GPIO4_LOW (NR_IRQS_LEGACY + 56) -#define MX50_INT_GPIO4_HIGH (NR_IRQS_LEGACY + 57) -#define MX50_INT_WDOG1 (NR_IRQS_LEGACY + 58) -#define MX50_INT_KPP (NR_IRQS_LEGACY + 60) -#define MX50_INT_PWM1 (NR_IRQS_LEGACY + 61) -#define MX50_INT_I2C1 (NR_IRQS_LEGACY + 62) -#define MX50_INT_I2C2 (NR_IRQS_LEGACY + 63) -#define MX50_INT_I2C3 (NR_IRQS_LEGACY + 64) -#define MX50_INT_RESV65 (NR_IRQS_LEGACY + 65) -#define MX50_INT_DCDC (NR_IRQS_LEGACY + 66) -#define MX50_INT_THERMAL_ALARM (NR_IRQS_LEGACY + 67) -#define MX50_INT_ANA3 (NR_IRQS_LEGACY + 68) -#define MX50_INT_ANA4 (NR_IRQS_LEGACY + 69) -#define MX50_INT_CCM1 (NR_IRQS_LEGACY + 71) -#define MX50_INT_CCM2 (NR_IRQS_LEGACY + 72) -#define MX50_INT_GPC1 (NR_IRQS_LEGACY + 73) -#define MX50_INT_GPC2 (NR_IRQS_LEGACY + 74) -#define MX50_INT_SRC (NR_IRQS_LEGACY + 75) -#define MX50_INT_NM (NR_IRQS_LEGACY + 76) -#define MX50_INT_PMU (NR_IRQS_LEGACY + 77) -#define MX50_INT_CTI_IRQ (NR_IRQS_LEGACY + 78) -#define MX50_INT_CTI1_TG0 (NR_IRQS_LEGACY + 79) -#define MX50_INT_CTI1_TG1 (NR_IRQS_LEGACY + 80) -#define MX50_INT_GPU2_IRQ (NR_IRQS_LEGACY + 84) -#define MX50_INT_GPU2_BUSY (NR_IRQS_LEGACY + 85) -#define MX50_INT_UART5 (NR_IRQS_LEGACY + 86) -#define MX50_INT_FEC (NR_IRQS_LEGACY + 87) -#define MX50_INT_OWIRE (NR_IRQS_LEGACY + 88) -#define MX50_INT_CTI1_TG2 (NR_IRQS_LEGACY + 89) -#define MX50_INT_SJC (NR_IRQS_LEGACY + 90) -#define MX50_INT_DCP_CHAN1_3 (NR_IRQS_LEGACY + 91) -#define MX50_INT_DCP_CHAN0 (NR_IRQS_LEGACY + 92) -#define MX50_INT_PWM2 (NR_IRQS_LEGACY + 94) -#define MX50_INT_RNGB (NR_IRQS_LEGACY + 97) -#define MX50_INT_CTI1_TG3 (NR_IRQS_LEGACY + 98) -#define MX50_INT_RAWNAND_BCH (NR_IRQS_LEGACY + 100) -#define MX50_INT_RAWNAND_GPMI (NR_IRQS_LEGACY + 102) -#define MX50_INT_GPIO5_LOW (NR_IRQS_LEGACY + 103) -#define MX50_INT_GPIO5_HIGH (NR_IRQS_LEGACY + 104) -#define MX50_INT_GPIO6_LOW (NR_IRQS_LEGACY + 105) -#define MX50_INT_GPIO6_HIGH (NR_IRQS_LEGACY + 106) -#define MX50_INT_MSHC (NR_IRQS_LEGACY + 109) -#define MX50_INT_APBHDMA_CHAN0 (NR_IRQS_LEGACY + 110) -#define MX50_INT_APBHDMA_CHAN1 (NR_IRQS_LEGACY + 111) -#define MX50_INT_APBHDMA_CHAN2 (NR_IRQS_LEGACY + 112) -#define MX50_INT_APBHDMA_CHAN3 (NR_IRQS_LEGACY + 113) -#define MX50_INT_APBHDMA_CHAN4 (NR_IRQS_LEGACY + 114) -#define MX50_INT_APBHDMA_CHAN5 (NR_IRQS_LEGACY + 115) -#define MX50_INT_APBHDMA_CHAN6 (NR_IRQS_LEGACY + 116) -#define MX50_INT_APBHDMA_CHAN7 (NR_IRQS_LEGACY + 117) - -#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS) -extern int mx50_revision(void); -#endif - -#endif /* ifndef __MACH_MX50_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx51.h b/arch/arm/plat-mxc/include/mach/mx51.h deleted file mode 100644 index af844f76261..00000000000 --- a/arch/arm/plat-mxc/include/mach/mx51.h +++ /dev/null @@ -1,346 +0,0 @@ -#ifndef __MACH_MX51_H__ -#define __MACH_MX51_H__ - -/* - * IROM - */ -#define MX51_IROM_BASE_ADDR 0x0 -#define MX51_IROM_SIZE SZ_64K - -/* - * IRAM - */ -#define MX51_IRAM_BASE_ADDR 0x1ffe0000 /* internal ram */ -#define MX51_IRAM_PARTITIONS 16 -#define MX51_IRAM_SIZE (MX51_IRAM_PARTITIONS * SZ_8K) /* 128KB */ - -#define MX51_GPU_BASE_ADDR 0x20000000 -#define MX51_GPU_CTRL_BASE_ADDR 0x30000000 -#define MX51_IPU_CTRL_BASE_ADDR 0x40000000 - -/* - * SPBA global module enabled #0 - */ -#define MX51_SPBA0_BASE_ADDR 0x70000000 -#define MX51_SPBA0_SIZE SZ_1M - -#define MX51_ESDHC1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x04000) -#define MX51_ESDHC2_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x08000) -#define MX51_UART3_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x0c000) -#define MX51_ECSPI1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x10000) -#define MX51_SSI2_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x14000) -#define MX51_ESDHC3_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x20000) -#define MX51_ESDHC4_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x24000) -#define MX51_SPDIF_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x28000) -#define MX51_ATA_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x30000) -#define MX51_SLIM_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x34000) -#define MX51_HSI2C_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x38000) -#define MX51_SPBA_CTRL_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x3c000) - -/* - * AIPS 1 - */ -#define MX51_AIPS1_BASE_ADDR 0x73f00000 -#define MX51_AIPS1_SIZE SZ_1M - -#define MX51_USB_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x80000) -#define MX51_USB_OTG_BASE_ADDR (MX51_USB_BASE_ADDR + 0x0000) -#define MX51_USB_HS1_BASE_ADDR (MX51_USB_BASE_ADDR + 0x0200) -#define MX51_USB_HS2_BASE_ADDR (MX51_USB_BASE_ADDR + 0x0400) -#define MX51_GPIO1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x84000) -#define MX51_GPIO2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x88000) -#define MX51_GPIO3_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x8c000) -#define MX51_GPIO4_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x90000) -#define MX51_KPP_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x94000) -#define MX51_WDOG1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x98000) -#define MX51_WDOG2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x9c000) -#define MX51_GPT1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xa0000) -#define MX51_SRTC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xa4000) -#define MX51_IOMUXC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xa8000) -#define MX51_EPIT1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xac000) -#define MX51_EPIT2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xb0000) -#define MX51_PWM1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xb4000) -#define MX51_PWM2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xb8000) -#define MX51_UART1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xbc000) -#define MX51_UART2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xc0000) -#define MX51_SRC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xd0000) -#define MX51_CCM_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xd4000) -#define MX51_GPC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xd8000) - -/* - * AIPS 2 - */ -#define MX51_AIPS2_BASE_ADDR 0x83f00000 -#define MX51_AIPS2_SIZE SZ_1M - -#define MX51_PLL1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x80000) -#define MX51_PLL2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x84000) -#define MX51_PLL3_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x88000) -#define MX51_AHBMAX_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x94000) -#define MX51_IIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x98000) -#define MX51_CSU_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x9c000) -#define MX51_ARM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xa0000) -#define MX51_OWIRE_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xa4000) -#define MX51_FIRI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xa8000) -#define MX51_ECSPI2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xac000) -#define MX51_SDMA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xb0000) -#define MX51_SCC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xb4000) -#define MX51_ROMCP_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xb8000) -#define MX51_RTIC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xbc000) -#define MX51_CSPI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xc0000) -#define MX51_I2C2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xc4000) -#define MX51_I2C1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xc8000) -#define MX51_SSI1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xcc000) -#define MX51_AUDMUX_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xd0000) -#define MX51_M4IF_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xd8000) -#define MX51_ESDCTL_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xd9000) -#define MX51_WEIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xda000) -#define MX51_NFC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xdb000) -#define MX51_EMI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xdbf00) -#define MX51_MIPI_HSC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xdc000) -#define MX51_ATA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe0000) -#define MX51_SIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe4000) -#define MX51_SSI3_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe8000) -#define MX51_FEC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xec000) -#define MX51_TVE_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xf0000) -#define MX51_VPU_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xf4000) -#define MX51_SAHARA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xf8000) - -#define MX51_CSD0_BASE_ADDR 0x90000000 -#define MX51_CSD1_BASE_ADDR 0xa0000000 -#define MX51_CS0_BASE_ADDR 0xb0000000 -#define MX51_CS1_BASE_ADDR 0xb8000000 -#define MX51_CS2_BASE_ADDR 0xc0000000 -#define MX51_CS3_BASE_ADDR 0xc8000000 -#define MX51_CS4_BASE_ADDR 0xcc000000 -#define MX51_CS5_BASE_ADDR 0xce000000 - -/* - * NFC - */ -#define MX51_NFC_AXI_BASE_ADDR 0xcfff0000 /* NAND flash AXI */ -#define MX51_NFC_AXI_SIZE SZ_64K - -#define MX51_GPU2D_BASE_ADDR 0xd0000000 -#define MX51_TZIC_BASE_ADDR 0xe0000000 -#define MX51_TZIC_SIZE SZ_16K - -#define MX51_IO_P2V(x) IMX_IO_P2V(x) -#define MX51_IO_ADDRESS(x) IOMEM(MX51_IO_P2V(x)) - -/* - * defines for SPBA modules - */ -#define MX51_SPBA_SDHC1 0x04 -#define MX51_SPBA_SDHC2 0x08 -#define MX51_SPBA_UART3 0x0c -#define MX51_SPBA_CSPI1 0x10 -#define MX51_SPBA_SSI2 0x14 -#define MX51_SPBA_SDHC3 0x20 -#define MX51_SPBA_SDHC4 0x24 -#define MX51_SPBA_SPDIF 0x28 -#define MX51_SPBA_ATA 0x30 -#define MX51_SPBA_SLIM 0x34 -#define MX51_SPBA_HSI2C 0x38 -#define MX51_SPBA_CTRL 0x3c - -/* - * Defines for modules using static and dynamic DMA channels - */ -#define MX51_MXC_DMA_CHANNEL_IRAM 30 -#define MX51_MXC_DMA_CHANNEL_SPDIF_TX MXC_DMA_DYNAMIC_CHANNEL -#define MX51_MXC_DMA_CHANNEL_UART1_RX MXC_DMA_DYNAMIC_CHANNEL -#define MX51_MXC_DMA_CHANNEL_UART1_TX MXC_DMA_DYNAMIC_CHANNEL -#define MX51_MXC_DMA_CHANNEL_UART2_RX MXC_DMA_DYNAMIC_CHANNEL -#define MX51_MXC_DMA_CHANNEL_UART2_TX MXC_DMA_DYNAMIC_CHANNEL -#define MX51_MXC_DMA_CHANNEL_UART3_RX MXC_DMA_DYNAMIC_CHANNEL -#define MX51_MXC_DMA_CHANNEL_UART3_TX MXC_DMA_DYNAMIC_CHANNEL -#define MX51_MXC_DMA_CHANNEL_MMC1 MXC_DMA_DYNAMIC_CHANNEL -#define MX51_MXC_DMA_CHANNEL_MMC2 MXC_DMA_DYNAMIC_CHANNEL -#define MX51_MXC_DMA_CHANNEL_SSI1_RX MXC_DMA_DYNAMIC_CHANNEL -#define MX51_MXC_DMA_CHANNEL_SSI1_TX MXC_DMA_DYNAMIC_CHANNEL -#define MX51_MXC_DMA_CHANNEL_SSI2_RX MXC_DMA_DYNAMIC_CHANNEL -#ifdef CONFIG_SDMA_IRAM -#define MX51_MXC_DMA_CHANNEL_SSI2_TX (MX51_MXC_DMA_CHANNEL_IRAM + 1) -#else /*CONFIG_SDMA_IRAM */ -#define MX51_MXC_DMA_CHANNEL_SSI2_TX MXC_DMA_DYNAMIC_CHANNEL -#endif /*CONFIG_SDMA_IRAM */ -#define MX51_MXC_DMA_CHANNEL_CSPI1_RX MXC_DMA_DYNAMIC_CHANNEL -#define MX51_MXC_DMA_CHANNEL_CSPI1_TX MXC_DMA_DYNAMIC_CHANNEL -#define MX51_MXC_DMA_CHANNEL_CSPI2_RX MXC_DMA_DYNAMIC_CHANNEL -#define MX51_MXC_DMA_CHANNEL_CSPI2_TX MXC_DMA_DYNAMIC_CHANNEL -#define MX51_MXC_DMA_CHANNEL_CSPI3_RX MXC_DMA_DYNAMIC_CHANNEL -#define MX51_MXC_DMA_CHANNEL_CSPI3_TX MXC_DMA_DYNAMIC_CHANNEL -#define MX51_MXC_DMA_CHANNEL_ATA_RX MXC_DMA_DYNAMIC_CHANNEL -#define MX51_MXC_DMA_CHANNEL_ATA_TX MXC_DMA_DYNAMIC_CHANNEL -#define MX51_MXC_DMA_CHANNEL_MEMORY MXC_DMA_DYNAMIC_CHANNEL - -#define MX51_IS_MEM_DEVICE_NONSHARED(x) 0 - -/* - * DMA request assignments - */ -#define MX51_DMA_REQ_VPU 0 -#define MX51_DMA_REQ_GPC 1 -#define MX51_DMA_REQ_ATA_RX 2 -#define MX51_DMA_REQ_ATA_TX 3 -#define MX51_DMA_REQ_ATA_TX_END 4 -#define MX51_DMA_REQ_SLIM_B 5 -#define MX51_DMA_REQ_CSPI1_RX 6 -#define MX51_DMA_REQ_CSPI1_TX 7 -#define MX51_DMA_REQ_CSPI2_RX 8 -#define MX51_DMA_REQ_CSPI2_TX 9 -#define MX51_DMA_REQ_HS_I2C_TX 10 -#define MX51_DMA_REQ_HS_I2C_RX 11 -#define MX51_DMA_REQ_FIRI_RX 12 -#define MX51_DMA_REQ_FIRI_TX 13 -#define MX51_DMA_REQ_EXTREQ1 14 -#define MX51_DMA_REQ_GPU 15 -#define MX51_DMA_REQ_UART2_RX 16 -#define MX51_DMA_REQ_UART2_TX 17 -#define MX51_DMA_REQ_UART1_RX 18 -#define MX51_DMA_REQ_UART1_TX 19 -#define MX51_DMA_REQ_SDHC1 20 -#define MX51_DMA_REQ_SDHC2 21 -#define MX51_DMA_REQ_SSI2_RX1 22 -#define MX51_DMA_REQ_SSI2_TX1 23 -#define MX51_DMA_REQ_SSI2_RX0 24 -#define MX51_DMA_REQ_SSI2_TX0 25 -#define MX51_DMA_REQ_SSI1_RX1 26 -#define MX51_DMA_REQ_SSI1_TX1 27 -#define MX51_DMA_REQ_SSI1_RX0 28 -#define MX51_DMA_REQ_SSI1_TX0 29 -#define MX51_DMA_REQ_EMI_RD 30 -#define MX51_DMA_REQ_CTI2_0 31 -#define MX51_DMA_REQ_EMI_WR 32 -#define MX51_DMA_REQ_CTI2_1 33 -#define MX51_DMA_REQ_EPIT2 34 -#define MX51_DMA_REQ_SSI3_RX1 35 -#define MX51_DMA_REQ_IPU 36 -#define MX51_DMA_REQ_SSI3_TX1 37 -#define MX51_DMA_REQ_CSPI_RX 38 -#define MX51_DMA_REQ_CSPI_TX 39 -#define MX51_DMA_REQ_SDHC3 40 -#define MX51_DMA_REQ_SDHC4 41 -#define MX51_DMA_REQ_SLIM_B_TX 42 -#define MX51_DMA_REQ_UART3_RX 43 -#define MX51_DMA_REQ_UART3_TX 44 -#define MX51_DMA_REQ_SPDIF 45 -#define MX51_DMA_REQ_SSI3_RX0 46 -#define MX51_DMA_REQ_SSI3_TX0 47 - -/* - * Interrupt numbers - */ -#include <asm/irq.h> -#define MX51_INT_BASE (NR_IRQS_LEGACY + 0) -#define MX51_INT_RESV0 (NR_IRQS_LEGACY + 0) -#define MX51_INT_ESDHC1 (NR_IRQS_LEGACY + 1) -#define MX51_INT_ESDHC2 (NR_IRQS_LEGACY + 2) -#define MX51_INT_ESDHC3 (NR_IRQS_LEGACY + 3) -#define MX51_INT_ESDHC4 (NR_IRQS_LEGACY + 4) -#define MX51_INT_RESV5 (NR_IRQS_LEGACY + 5) -#define MX51_INT_SDMA (NR_IRQS_LEGACY + 6) -#define MX51_INT_IOMUX (NR_IRQS_LEGACY + 7) -#define MX51_INT_NFC (NR_IRQS_LEGACY + 8) -#define MX51_INT_VPU (NR_IRQS_LEGACY + 9) -#define MX51_INT_IPU_ERR (NR_IRQS_LEGACY + 10) -#define MX51_INT_IPU_SYN (NR_IRQS_LEGACY + 11) -#define MX51_INT_GPU (NR_IRQS_LEGACY + 12) -#define MX51_INT_RESV13 (NR_IRQS_LEGACY + 13) -#define MX51_INT_USB_HS1 (NR_IRQS_LEGACY + 14) -#define MX51_INT_EMI (NR_IRQS_LEGACY + 15) -#define MX51_INT_USB_HS2 (NR_IRQS_LEGACY + 16) -#define MX51_INT_USB_HS3 (NR_IRQS_LEGACY + 17) -#define MX51_INT_USB_OTG (NR_IRQS_LEGACY + 18) -#define MX51_INT_SAHARA_H0 (NR_IRQS_LEGACY + 19) -#define MX51_INT_SAHARA_H1 (NR_IRQS_LEGACY + 20) -#define MX51_INT_SCC_SMN (NR_IRQS_LEGACY + 21) -#define MX51_INT_SCC_STZ (NR_IRQS_LEGACY + 22) -#define MX51_INT_SCC_SCM (NR_IRQS_LEGACY + 23) -#define MX51_INT_SRTC_NTZ (NR_IRQS_LEGACY + 24) -#define MX51_INT_SRTC_TZ (NR_IRQS_LEGACY + 25) -#define MX51_INT_RTIC (NR_IRQS_LEGACY + 26) -#define MX51_INT_CSU (NR_IRQS_LEGACY + 27) -#define MX51_INT_SLIM_B (NR_IRQS_LEGACY + 28) -#define MX51_INT_SSI1 (NR_IRQS_LEGACY + 29) -#define MX51_INT_SSI2 (NR_IRQS_LEGACY + 30) -#define MX51_INT_UART1 (NR_IRQS_LEGACY + 31) -#define MX51_INT_UART2 (NR_IRQS_LEGACY + 32) -#define MX51_INT_UART3 (NR_IRQS_LEGACY + 33) -#define MX51_INT_RESV34 (NR_IRQS_LEGACY + 34) -#define MX51_INT_RESV35 (NR_IRQS_LEGACY + 35) -#define MX51_INT_ECSPI1 (NR_IRQS_LEGACY + 36) -#define MX51_INT_ECSPI2 (NR_IRQS_LEGACY + 37) -#define MX51_INT_CSPI (NR_IRQS_LEGACY + 38) -#define MX51_INT_GPT (NR_IRQS_LEGACY + 39) -#define MX51_INT_EPIT1 (NR_IRQS_LEGACY + 40) -#define MX51_INT_EPIT2 (NR_IRQS_LEGACY + 41) -#define MX51_INT_GPIO1_INT7 (NR_IRQS_LEGACY + 42) -#define MX51_INT_GPIO1_INT6 (NR_IRQS_LEGACY + 43) -#define MX51_INT_GPIO1_INT5 (NR_IRQS_LEGACY + 44) -#define MX51_INT_GPIO1_INT4 (NR_IRQS_LEGACY + 45) -#define MX51_INT_GPIO1_INT3 (NR_IRQS_LEGACY + 46) -#define MX51_INT_GPIO1_INT2 (NR_IRQS_LEGACY + 47) -#define MX51_INT_GPIO1_INT1 (NR_IRQS_LEGACY + 48) -#define MX51_INT_GPIO1_INT0 (NR_IRQS_LEGACY + 49) -#define MX51_INT_GPIO1_LOW (NR_IRQS_LEGACY + 50) -#define MX51_INT_GPIO1_HIGH (NR_IRQS_LEGACY + 51) -#define MX51_INT_GPIO2_LOW (NR_IRQS_LEGACY + 52) -#define MX51_INT_GPIO2_HIGH (NR_IRQS_LEGACY + 53) -#define MX51_INT_GPIO3_LOW (NR_IRQS_LEGACY + 54) -#define MX51_INT_GPIO3_HIGH (NR_IRQS_LEGACY + 55) -#define MX51_INT_GPIO4_LOW (NR_IRQS_LEGACY + 56) -#define MX51_INT_GPIO4_HIGH (NR_IRQS_LEGACY + 57) -#define MX51_INT_WDOG1 (NR_IRQS_LEGACY + 58) -#define MX51_INT_WDOG2 (NR_IRQS_LEGACY + 59) -#define MX51_INT_KPP (NR_IRQS_LEGACY + 60) -#define MX51_INT_PWM1 (NR_IRQS_LEGACY + 61) -#define MX51_INT_I2C1 (NR_IRQS_LEGACY + 62) -#define MX51_INT_I2C2 (NR_IRQS_LEGACY + 63) -#define MX51_INT_HS_I2C (NR_IRQS_LEGACY + 64) -#define MX51_INT_RESV65 (NR_IRQS_LEGACY + 65) -#define MX51_INT_RESV66 (NR_IRQS_LEGACY + 66) -#define MX51_INT_SIM_IPB (NR_IRQS_LEGACY + 67) -#define MX51_INT_SIM_DAT (NR_IRQS_LEGACY + 68) -#define MX51_INT_IIM (NR_IRQS_LEGACY + 69) -#define MX51_INT_ATA (NR_IRQS_LEGACY + 70) -#define MX51_INT_CCM1 (NR_IRQS_LEGACY + 71) -#define MX51_INT_CCM2 (NR_IRQS_LEGACY + 72) -#define MX51_INT_GPC1 (NR_IRQS_LEGACY + 73) -#define MX51_INT_GPC2 (NR_IRQS_LEGACY + 74) -#define MX51_INT_SRC (NR_IRQS_LEGACY + 75) -#define MX51_INT_NM (NR_IRQS_LEGACY + 76) -#define MX51_INT_PMU (NR_IRQS_LEGACY + 77) -#define MX51_INT_CTI_IRQ (NR_IRQS_LEGACY + 78) -#define MX51_INT_CTI1_TG0 (NR_IRQS_LEGACY + 79) -#define MX51_INT_CTI1_TG1 (NR_IRQS_LEGACY + 80) -#define MX51_INT_MCG_ERR (NR_IRQS_LEGACY + 81) -#define MX51_INT_MCG_TMR (NR_IRQS_LEGACY + 82) -#define MX51_INT_MCG_FUNC (NR_IRQS_LEGACY + 83) -#define MX51_INT_GPU2_IRQ (NR_IRQS_LEGACY + 84) -#define MX51_INT_GPU2_BUSY (NR_IRQS_LEGACY + 85) -#define MX51_INT_RESV86 (NR_IRQS_LEGACY + 86) -#define MX51_INT_FEC (NR_IRQS_LEGACY + 87) -#define MX51_INT_OWIRE (NR_IRQS_LEGACY + 88) -#define MX51_INT_CTI1_TG2 (NR_IRQS_LEGACY + 89) -#define MX51_INT_SJC (NR_IRQS_LEGACY + 90) -#define MX51_INT_SPDIF (NR_IRQS_LEGACY + 91) -#define MX51_INT_TVE (NR_IRQS_LEGACY + 92) -#define MX51_INT_FIRI (NR_IRQS_LEGACY + 93) -#define MX51_INT_PWM2 (NR_IRQS_LEGACY + 94) -#define MX51_INT_SLIM_EXP (NR_IRQS_LEGACY + 95) -#define MX51_INT_SSI3 (NR_IRQS_LEGACY + 96) -#define MX51_INT_EMI_BOOT (NR_IRQS_LEGACY + 97) -#define MX51_INT_CTI1_TG3 (NR_IRQS_LEGACY + 98) -#define MX51_INT_SMC_RX (NR_IRQS_LEGACY + 99) -#define MX51_INT_VPU_IDLE (NR_IRQS_LEGACY + 100) -#define MX51_INT_EMI_NFC (NR_IRQS_LEGACY + 101) -#define MX51_INT_GPU_IDLE (NR_IRQS_LEGACY + 102) - -#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS) -extern int mx51_revision(void); -extern void mx51_display_revision(void); -#endif - -#endif /* ifndef __MACH_MX51_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx53.h b/arch/arm/plat-mxc/include/mach/mx53.h deleted file mode 100644 index f829d1c2250..00000000000 --- a/arch/arm/plat-mxc/include/mach/mx53.h +++ /dev/null @@ -1,342 +0,0 @@ -#ifndef __MACH_MX53_H__ -#define __MACH_MX53_H__ - -/* - * IROM - */ -#define MX53_IROM_BASE_ADDR 0x0 -#define MX53_IROM_SIZE SZ_64K - -/* TZIC */ -#define MX53_TZIC_BASE_ADDR 0x0FFFC000 -#define MX53_TZIC_SIZE SZ_16K - -/* - * AHCI SATA - */ -#define MX53_SATA_BASE_ADDR 0x10000000 - -/* - * NFC - */ -#define MX53_NFC_AXI_BASE_ADDR 0xF7FF0000 /* NAND flash AXI */ -#define MX53_NFC_AXI_SIZE SZ_64K - -/* - * IRAM - */ -#define MX53_IRAM_BASE_ADDR 0xF8000000 /* internal ram */ -#define MX53_IRAM_PARTITIONS 16 -#define MX53_IRAM_SIZE (MX53_IRAM_PARTITIONS * SZ_8K) /* 128KB */ - -/* - * Graphics Memory of GPU - */ -#define MX53_IPU_CTRL_BASE_ADDR 0x18000000 -#define MX53_GPU2D_BASE_ADDR 0x20000000 -#define MX53_GPU_BASE_ADDR 0x30000000 -#define MX53_GPU_GMEM_BASE_ADDR 0xF8020000 - -#define MX53_DEBUG_BASE_ADDR 0x40000000 -#define MX53_DEBUG_SIZE SZ_1M -#define MX53_ETB_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00001000) -#define MX53_ETM_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00002000) -#define MX53_TPIU_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00003000) -#define MX53_CTI0_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00004000) -#define MX53_CTI1_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00005000) -#define MX53_CTI2_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00006000) -#define MX53_CTI3_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00007000) -#define MX53_CORTEX_DBG_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00008000) - -/* - * SPBA global module enabled #0 - */ -#define MX53_SPBA0_BASE_ADDR 0x50000000 -#define MX53_SPBA0_SIZE SZ_1M - -#define MX53_ESDHC1_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00004000) -#define MX53_ESDHC2_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00008000) -#define MX53_UART3_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x0000C000) -#define MX53_ECSPI1_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00010000) -#define MX53_SSI2_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00014000) -#define MX53_ESDHC3_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00020000) -#define MX53_ESDHC4_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00024000) -#define MX53_SPDIF_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00028000) -#define MX53_ASRC_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x0002C000) -#define MX53_ATA_DMA_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00030000) -#define MX53_SLIM_DMA_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00034000) -#define MX53_HSI2C_DMA_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00038000) -#define MX53_SPBA_CTRL_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x0003C000) - -/* - * AIPS 1 - */ -#define MX53_AIPS1_BASE_ADDR 0x53F00000 -#define MX53_AIPS1_SIZE SZ_1M - -#define MX53_OTG_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00080000) -#define MX53_GPIO1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00084000) -#define MX53_GPIO2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00088000) -#define MX53_GPIO3_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x0008C000) -#define MX53_GPIO4_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00090000) -#define MX53_KPP_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00094000) -#define MX53_WDOG1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00098000) -#define MX53_WDOG2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x0009C000) -#define MX53_GPT1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000A0000) -#define MX53_SRTC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000A4000) -#define MX53_IOMUXC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000A8000) -#define MX53_EPIT1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000AC000) -#define MX53_EPIT2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000B0000) -#define MX53_PWM1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000B4000) -#define MX53_PWM2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000B8000) -#define MX53_UART1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000BC000) -#define MX53_UART2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000C0000) -#define MX53_SRC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000D0000) -#define MX53_CCM_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000D4000) -#define MX53_GPC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000D8000) -#define MX53_GPIO5_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000DC000) -#define MX53_GPIO6_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000E0000) -#define MX53_GPIO7_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000E4000) -#define MX53_ATA_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000E8000) -#define MX53_I2C3_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000EC000) -#define MX53_UART4_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000F0000) - -/* - * AIPS 2 - */ -#define MX53_AIPS2_BASE_ADDR 0x63F00000 -#define MX53_AIPS2_SIZE SZ_1M - -#define MX53_PLL1_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00080000) -#define MX53_PLL2_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00084000) -#define MX53_PLL3_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00088000) -#define MX53_PLL4_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x0008C000) -#define MX53_UART5_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00090000) -#define MX53_AHBMAX_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00094000) -#define MX53_IIM_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00098000) -#define MX53_CSU_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x0009C000) -#define MX53_ARM_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000A0000) -#define MX53_OWIRE_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000A4000) -#define MX53_FIRI_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000A8000) -#define MX53_ECSPI2_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000AC000) -#define MX53_SDMA_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000B0000) -#define MX53_SCC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000B4000) -#define MX53_ROMCP_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000B8000) -#define MX53_RTIC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000BC000) -#define MX53_CSPI_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C0000) -#define MX53_I2C2_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C4000) -#define MX53_I2C1_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C8000) -#define MX53_SSI1_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000CC000) -#define MX53_AUDMUX_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000D0000) -#define MX53_RTC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000D4000) -#define MX53_M4IF_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000D8000) -#define MX53_ESDCTL_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000D9000) -#define MX53_WEIM_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DA000) -#define MX53_NFC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DB000) -#define MX53_EMI_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DBF00) -#define MX53_MIPI_HSC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DC000) -#define MX53_MLB_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000E4000) -#define MX53_SSI3_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000E8000) -#define MX53_FEC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000EC000) -#define MX53_TVE_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000F0000) -#define MX53_VPU_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000F4000) -#define MX53_SAHARA_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000F8000) -#define MX53_PTP_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000FC000) - -/* - * Memory regions and CS - */ -#define MX53_CSD0_BASE_ADDR 0x70000000 -#define MX53_CSD1_BASE_ADDR 0xB0000000 -#define MX53_CS0_BASE_ADDR 0xF0000000 -#define MX53_CS1_32MB_BASE_ADDR 0xF2000000 -#define MX53_CS1_64MB_BASE_ADDR 0xF4000000 -#define MX53_CS2_64MB_BASE_ADDR 0xF4000000 -#define MX53_CS2_96MB_BASE_ADDR 0xF6000000 -#define MX53_CS3_BASE_ADDR 0xF6000000 - -#define MX53_IO_P2V(x) IMX_IO_P2V(x) -#define MX53_IO_ADDRESS(x) IOMEM(MX53_IO_P2V(x)) - -/* - * defines for SPBA modules - */ -#define MX53_SPBA_SDHC1 0x04 -#define MX53_SPBA_SDHC2 0x08 -#define MX53_SPBA_UART3 0x0C -#define MX53_SPBA_CSPI1 0x10 -#define MX53_SPBA_SSI2 0x14 -#define MX53_SPBA_SDHC3 0x20 -#define MX53_SPBA_SDHC4 0x24 -#define MX53_SPBA_SPDIF 0x28 -#define MX53_SPBA_ATA 0x30 -#define MX53_SPBA_SLIM 0x34 -#define MX53_SPBA_HSI2C 0x38 -#define MX53_SPBA_CTRL 0x3C - -/* - * DMA request assignments - */ -#define MX53_DMA_REQ_SSI3_TX0 47 -#define MX53_DMA_REQ_SSI3_RX0 46 -#define MX53_DMA_REQ_SSI3_TX1 45 -#define MX53_DMA_REQ_SSI3_RX1 44 -#define MX53_DMA_REQ_UART3_TX 43 -#define MX53_DMA_REQ_UART3_RX 42 -#define MX53_DMA_REQ_ESAI_TX 41 -#define MX53_DMA_REQ_ESAI_RX 40 -#define MX53_DMA_REQ_CSPI_TX 39 -#define MX53_DMA_REQ_CSPI_RX 38 -#define MX53_DMA_REQ_ASRC_DMA6 37 -#define MX53_DMA_REQ_ASRC_DMA5 36 -#define MX53_DMA_REQ_ASRC_DMA4 35 -#define MX53_DMA_REQ_ASRC_DMA3 34 -#define MX53_DMA_REQ_ASRC_DMA2 33 -#define MX53_DMA_REQ_ASRC_DMA1 32 -#define MX53_DMA_REQ_EMI_WR 31 -#define MX53_DMA_REQ_EMI_RD 30 -#define MX53_DMA_REQ_SSI1_TX0 29 -#define MX53_DMA_REQ_SSI1_RX0 28 -#define MX53_DMA_REQ_SSI1_TX1 27 -#define MX53_DMA_REQ_SSI1_RX1 26 -#define MX53_DMA_REQ_SSI2_TX0 25 -#define MX53_DMA_REQ_SSI2_RX0 24 -#define MX53_DMA_REQ_SSI2_TX1 23 -#define MX53_DMA_REQ_SSI2_RX1 22 -#define MX53_DMA_REQ_I2C2_SDHC2 21 -#define MX53_DMA_REQ_I2C1_SDHC1 20 -#define MX53_DMA_REQ_UART1_TX 19 -#define MX53_DMA_REQ_UART1_RX 18 -#define MX53_DMA_REQ_UART5_TX 17 -#define MX53_DMA_REQ_UART5_RX 16 -#define MX53_DMA_REQ_SPDIF_TX 15 -#define MX53_DMA_REQ_SPDIF_RX 14 -#define MX53_DMA_REQ_UART2_FIRI_TX 13 -#define MX53_DMA_REQ_UART2_FIRI_RX 12 -#define MX53_DMA_REQ_SDHC4 11 -#define MX53_DMA_REQ_I2C3_SDHC3 10 -#define MX53_DMA_REQ_CSPI2_TX 9 -#define MX53_DMA_REQ_CSPI2_RX 8 -#define MX53_DMA_REQ_CSPI1_TX 7 -#define MX53_DMA_REQ_CSPI1_RX 6 -#define MX53_DMA_REQ_IPU 5 -#define MX53_DMA_REQ_ATA_TX_END 4 -#define MX53_DMA_REQ_ATA_UART4_TX 3 -#define MX53_DMA_REQ_ATA_UART4_RX 2 -#define MX53_DMA_REQ_GPC 1 -#define MX53_DMA_REQ_VPU 0 - -/* - * Interrupt numbers - */ -#include <asm/irq.h> -#define MX53_INT_RESV0 (NR_IRQS_LEGACY + 0) -#define MX53_INT_ESDHC1 (NR_IRQS_LEGACY + 1) -#define MX53_INT_ESDHC2 (NR_IRQS_LEGACY + 2) -#define MX53_INT_ESDHC3 (NR_IRQS_LEGACY + 3) -#define MX53_INT_ESDHC4 (NR_IRQS_LEGACY + 4) -#define MX53_INT_DAP (NR_IRQS_LEGACY + 5) -#define MX53_INT_SDMA (NR_IRQS_LEGACY + 6) -#define MX53_INT_IOMUX (NR_IRQS_LEGACY + 7) -#define MX53_INT_NFC (NR_IRQS_LEGACY + 8) -#define MX53_INT_VPU (NR_IRQS_LEGACY + 9) -#define MX53_INT_IPU_ERR (NR_IRQS_LEGACY + 10) -#define MX53_INT_IPU_SYN (NR_IRQS_LEGACY + 11) -#define MX53_INT_GPU (NR_IRQS_LEGACY + 12) -#define MX53_INT_UART4 (NR_IRQS_LEGACY + 13) -#define MX53_INT_USB_H1 (NR_IRQS_LEGACY + 14) -#define MX53_INT_EMI (NR_IRQS_LEGACY + 15) -#define MX53_INT_USB_H2 (NR_IRQS_LEGACY + 16) -#define MX53_INT_USB_H3 (NR_IRQS_LEGACY + 17) -#define MX53_INT_USB_OTG (NR_IRQS_LEGACY + 18) -#define MX53_INT_SAHARA_H0 (NR_IRQS_LEGACY + 19) -#define MX53_INT_SAHARA_H1 (NR_IRQS_LEGACY + 20) -#define MX53_INT_SCC_SMN (NR_IRQS_LEGACY + 21) -#define MX53_INT_SCC_STZ (NR_IRQS_LEGACY + 22) -#define MX53_INT_SCC_SCM (NR_IRQS_LEGACY + 23) -#define MX53_INT_SRTC_NTZ (NR_IRQS_LEGACY + 24) -#define MX53_INT_SRTC_TZ (NR_IRQS_LEGACY + 25) -#define MX53_INT_RTIC (NR_IRQS_LEGACY + 26) -#define MX53_INT_CSU (NR_IRQS_LEGACY + 27) -#define MX53_INT_SATA (NR_IRQS_LEGACY + 28) -#define MX53_INT_SSI1 (NR_IRQS_LEGACY + 29) -#define MX53_INT_SSI2 (NR_IRQS_LEGACY + 30) -#define MX53_INT_UART1 (NR_IRQS_LEGACY + 31) -#define MX53_INT_UART2 (NR_IRQS_LEGACY + 32) -#define MX53_INT_UART3 (NR_IRQS_LEGACY + 33) -#define MX53_INT_RTC (NR_IRQS_LEGACY + 34) -#define MX53_INT_PTP (NR_IRQS_LEGACY + 35) -#define MX53_INT_ECSPI1 (NR_IRQS_LEGACY + 36) -#define MX53_INT_ECSPI2 (NR_IRQS_LEGACY + 37) -#define MX53_INT_CSPI (NR_IRQS_LEGACY + 38) -#define MX53_INT_GPT (NR_IRQS_LEGACY + 39) -#define MX53_INT_EPIT1 (NR_IRQS_LEGACY + 40) -#define MX53_INT_EPIT2 (NR_IRQS_LEGACY + 41) -#define MX53_INT_GPIO1_INT7 (NR_IRQS_LEGACY + 42) -#define MX53_INT_GPIO1_INT6 (NR_IRQS_LEGACY + 43) -#define MX53_INT_GPIO1_INT5 (NR_IRQS_LEGACY + 44) -#define MX53_INT_GPIO1_INT4 (NR_IRQS_LEGACY + 45) -#define MX53_INT_GPIO1_INT3 (NR_IRQS_LEGACY + 46) -#define MX53_INT_GPIO1_INT2 (NR_IRQS_LEGACY + 47) -#define MX53_INT_GPIO1_INT1 (NR_IRQS_LEGACY + 48) -#define MX53_INT_GPIO1_INT0 (NR_IRQS_LEGACY + 49) -#define MX53_INT_GPIO1_LOW (NR_IRQS_LEGACY + 50) -#define MX53_INT_GPIO1_HIGH (NR_IRQS_LEGACY + 51) -#define MX53_INT_GPIO2_LOW (NR_IRQS_LEGACY + 52) -#define MX53_INT_GPIO2_HIGH (NR_IRQS_LEGACY + 53) -#define MX53_INT_GPIO3_LOW (NR_IRQS_LEGACY + 54) -#define MX53_INT_GPIO3_HIGH (NR_IRQS_LEGACY + 55) -#define MX53_INT_GPIO4_LOW (NR_IRQS_LEGACY + 56) -#define MX53_INT_GPIO4_HIGH (NR_IRQS_LEGACY + 57) -#define MX53_INT_WDOG1 (NR_IRQS_LEGACY + 58) -#define MX53_INT_WDOG2 (NR_IRQS_LEGACY + 59) -#define MX53_INT_KPP (NR_IRQS_LEGACY + 60) -#define MX53_INT_PWM1 (NR_IRQS_LEGACY + 61) -#define MX53_INT_I2C1 (NR_IRQS_LEGACY + 62) -#define MX53_INT_I2C2 (NR_IRQS_LEGACY + 63) -#define MX53_INT_I2C3 (NR_IRQS_LEGACY + 64) -#define MX53_INT_MLB (NR_IRQS_LEGACY + 65) -#define MX53_INT_ASRC (NR_IRQS_LEGACY + 66) -#define MX53_INT_SPDIF (NR_IRQS_LEGACY + 67) -#define MX53_INT_SIM_DAT (NR_IRQS_LEGACY + 68) -#define MX53_INT_IIM (NR_IRQS_LEGACY + 69) -#define MX53_INT_ATA (NR_IRQS_LEGACY + 70) -#define MX53_INT_CCM1 (NR_IRQS_LEGACY + 71) -#define MX53_INT_CCM2 (NR_IRQS_LEGACY + 72) -#define MX53_INT_GPC1 (NR_IRQS_LEGACY + 73) -#define MX53_INT_GPC2 (NR_IRQS_LEGACY + 74) -#define MX53_INT_SRC (NR_IRQS_LEGACY + 75) -#define MX53_INT_NM (NR_IRQS_LEGACY + 76) -#define MX53_INT_PMU (NR_IRQS_LEGACY + 77) -#define MX53_INT_CTI_IRQ (NR_IRQS_LEGACY + 78) -#define MX53_INT_CTI1_TG0 (NR_IRQS_LEGACY + 79) -#define MX53_INT_CTI1_TG1 (NR_IRQS_LEGACY + 80) -#define MX53_INT_ESAI (NR_IRQS_LEGACY + 81) -#define MX53_INT_CAN1 (NR_IRQS_LEGACY + 82) -#define MX53_INT_CAN2 (NR_IRQS_LEGACY + 83) -#define MX53_INT_GPU2_IRQ (NR_IRQS_LEGACY + 84) -#define MX53_INT_GPU2_BUSY (NR_IRQS_LEGACY + 85) -#define MX53_INT_UART5 (NR_IRQS_LEGACY + 86) -#define MX53_INT_FEC (NR_IRQS_LEGACY + 87) -#define MX53_INT_OWIRE (NR_IRQS_LEGACY + 88) -#define MX53_INT_CTI1_TG2 (NR_IRQS_LEGACY + 89) -#define MX53_INT_SJC (NR_IRQS_LEGACY + 90) -#define MX53_INT_TVE (NR_IRQS_LEGACY + 92) -#define MX53_INT_FIRI (NR_IRQS_LEGACY + 93) -#define MX53_INT_PWM2 (NR_IRQS_LEGACY + 94) -#define MX53_INT_SLIM_EXP (NR_IRQS_LEGACY + 95) -#define MX53_INT_SSI3 (NR_IRQS_LEGACY + 96) -#define MX53_INT_EMI_BOOT (NR_IRQS_LEGACY + 97) -#define MX53_INT_CTI1_TG3 (NR_IRQS_LEGACY + 98) -#define MX53_INT_SMC_RX (NR_IRQS_LEGACY + 99) -#define MX53_INT_VPU_IDLE (NR_IRQS_LEGACY + 100) -#define MX53_INT_EMI_NFC (NR_IRQS_LEGACY + 101) -#define MX53_INT_GPU_IDLE (NR_IRQS_LEGACY + 102) -#define MX53_INT_GPIO5_LOW (NR_IRQS_LEGACY + 103) -#define MX53_INT_GPIO5_HIGH (NR_IRQS_LEGACY + 104) -#define MX53_INT_GPIO6_LOW (NR_IRQS_LEGACY + 105) -#define MX53_INT_GPIO6_HIGH (NR_IRQS_LEGACY + 106) -#define MX53_INT_GPIO7_LOW (NR_IRQS_LEGACY + 107) -#define MX53_INT_GPIO7_HIGH (NR_IRQS_LEGACY + 108) - -#endif /* ifndef __MACH_MX53_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx6q.h b/arch/arm/plat-mxc/include/mach/mx6q.h deleted file mode 100644 index f7e7dbac8f4..00000000000 --- a/arch/arm/plat-mxc/include/mach/mx6q.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2011 Linaro Ltd. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#ifndef __MACH_MX6Q_H__ -#define __MACH_MX6Q_H__ - -#define MX6Q_IO_P2V(x) IMX_IO_P2V(x) -#define MX6Q_IO_ADDRESS(x) IOMEM(MX6Q_IO_P2V(x)) - -/* - * The following are the blocks that need to be statically mapped. - * For other blocks, the base address really should be retrieved from - * device tree. - */ -#define MX6Q_SCU_BASE_ADDR 0x00a00000 -#define MX6Q_SCU_SIZE 0x1000 -#define MX6Q_CCM_BASE_ADDR 0x020c4000 -#define MX6Q_CCM_SIZE 0x4000 -#define MX6Q_ANATOP_BASE_ADDR 0x020c8000 -#define MX6Q_ANATOP_SIZE 0x1000 -#define MX6Q_UART2_BASE_ADDR 0x021e8000 -#define MX6Q_UART2_SIZE 0x4000 -#define MX6Q_UART4_BASE_ADDR 0x021f0000 -#define MX6Q_UART4_SIZE 0x4000 - -#endif /* __MACH_MX6Q_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h deleted file mode 100644 index d78298366a9..00000000000 --- a/arch/arm/plat-mxc/include/mach/mxc.h +++ /dev/null @@ -1,179 +0,0 @@ -/* - * Copyright 2004-2007, 2010 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#ifndef __ASM_ARCH_MXC_H__ -#define __ASM_ARCH_MXC_H__ - -#include <linux/types.h> - -#ifndef __ASM_ARCH_MXC_HARDWARE_H__ -#error "Do not include directly." -#endif - -#define MXC_CPU_MX1 1 -#define MXC_CPU_MX21 21 -#define MXC_CPU_MX25 25 -#define MXC_CPU_MX27 27 -#define MXC_CPU_MX31 31 -#define MXC_CPU_MX35 35 -#define MXC_CPU_MX50 50 -#define MXC_CPU_MX51 51 -#define MXC_CPU_MX53 53 - -#define IMX_CHIP_REVISION_1_0 0x10 -#define IMX_CHIP_REVISION_1_1 0x11 -#define IMX_CHIP_REVISION_1_2 0x12 -#define IMX_CHIP_REVISION_1_3 0x13 -#define IMX_CHIP_REVISION_2_0 0x20 -#define IMX_CHIP_REVISION_2_1 0x21 -#define IMX_CHIP_REVISION_2_2 0x22 -#define IMX_CHIP_REVISION_2_3 0x23 -#define IMX_CHIP_REVISION_3_0 0x30 -#define IMX_CHIP_REVISION_3_1 0x31 -#define IMX_CHIP_REVISION_3_2 0x32 -#define IMX_CHIP_REVISION_3_3 0x33 -#define IMX_CHIP_REVISION_UNKNOWN 0xff - -#ifndef __ASSEMBLY__ -extern unsigned int __mxc_cpu_type; -#endif - -#ifdef CONFIG_SOC_IMX1 -# ifdef mxc_cpu_type -# undef mxc_cpu_type -# define mxc_cpu_type __mxc_cpu_type -# else -# define mxc_cpu_type MXC_CPU_MX1 -# endif -# define cpu_is_mx1() (mxc_cpu_type == MXC_CPU_MX1) -#else -# define cpu_is_mx1() (0) -#endif - -#ifdef CONFIG_SOC_IMX21 -# ifdef mxc_cpu_type -# undef mxc_cpu_type -# define mxc_cpu_type __mxc_cpu_type -# else -# define mxc_cpu_type MXC_CPU_MX21 -# endif -# define cpu_is_mx21() (mxc_cpu_type == MXC_CPU_MX21) -#else -# define cpu_is_mx21() (0) -#endif - -#ifdef CONFIG_SOC_IMX25 -# ifdef mxc_cpu_type -# undef mxc_cpu_type -# define mxc_cpu_type __mxc_cpu_type -# else -# define mxc_cpu_type MXC_CPU_MX25 -# endif -# define cpu_is_mx25() (mxc_cpu_type == MXC_CPU_MX25) -#else -# define cpu_is_mx25() (0) -#endif - -#ifdef CONFIG_SOC_IMX27 -# ifdef mxc_cpu_type -# undef mxc_cpu_type -# define mxc_cpu_type __mxc_cpu_type -# else -# define mxc_cpu_type MXC_CPU_MX27 -# endif -# define cpu_is_mx27() (mxc_cpu_type == MXC_CPU_MX27) -#else -# define cpu_is_mx27() (0) -#endif - -#ifdef CONFIG_SOC_IMX31 -# ifdef mxc_cpu_type -# undef mxc_cpu_type -# define mxc_cpu_type __mxc_cpu_type -# else -# define mxc_cpu_type MXC_CPU_MX31 -# endif -# define cpu_is_mx31() (mxc_cpu_type == MXC_CPU_MX31) -#else -# define cpu_is_mx31() (0) -#endif - -#ifdef CONFIG_SOC_IMX35 -# ifdef mxc_cpu_type -# undef mxc_cpu_type -# define mxc_cpu_type __mxc_cpu_type -# else -# define mxc_cpu_type MXC_CPU_MX35 -# endif -# define cpu_is_mx35() (mxc_cpu_type == MXC_CPU_MX35) -#else -# define cpu_is_mx35() (0) -#endif - -#ifdef CONFIG_SOC_IMX50 -# ifdef mxc_cpu_type -# undef mxc_cpu_type -# define mxc_cpu_type __mxc_cpu_type -# else -# define mxc_cpu_type MXC_CPU_MX50 -# endif -# define cpu_is_mx50() (mxc_cpu_type == MXC_CPU_MX50) -#else -# define cpu_is_mx50() (0) -#endif - -#ifdef CONFIG_SOC_IMX51 -# ifdef mxc_cpu_type -# undef mxc_cpu_type -# define mxc_cpu_type __mxc_cpu_type -# else -# define mxc_cpu_type MXC_CPU_MX51 -# endif -# define cpu_is_mx51() (mxc_cpu_type == MXC_CPU_MX51) -#else -# define cpu_is_mx51() (0) -#endif - -#ifdef CONFIG_SOC_IMX53 -# ifdef mxc_cpu_type -# undef mxc_cpu_type -# define mxc_cpu_type __mxc_cpu_type -# else -# define mxc_cpu_type MXC_CPU_MX53 -# endif -# define cpu_is_mx53() (mxc_cpu_type == MXC_CPU_MX53) -#else -# define cpu_is_mx53() (0) -#endif - -#ifndef __ASSEMBLY__ - -struct cpu_op { - u32 cpu_rate; -}; - -int tzic_enable_wake(void); - -extern struct cpu_op *(*get_cpu_op)(int *op); -#endif - -#define cpu_is_mx3() (cpu_is_mx31() || cpu_is_mx35()) -#define cpu_is_mx2() (cpu_is_mx21() || cpu_is_mx27()) - -#endif /* __ASM_ARCH_MXC_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/timex.h b/arch/arm/plat-mxc/include/mach/timex.h deleted file mode 100644 index 10343d1f87e..00000000000 --- a/arch/arm/plat-mxc/include/mach/timex.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Copyright (C) 1999 ARM Limited - * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __ASM_ARCH_MXC_TIMEX_H__ -#define __ASM_ARCH_MXC_TIMEX_H__ - -/* Bogus value */ -#define CLOCK_TICK_RATE 12345678 - -#endif /* __ASM_ARCH_MXC_TIMEX_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/ulpi.h b/arch/arm/plat-mxc/include/mach/ulpi.h deleted file mode 100644 index 42bdaca6d7d..00000000000 --- a/arch/arm/plat-mxc/include/mach/ulpi.h +++ /dev/null @@ -1,16 +0,0 @@ -#ifndef __MACH_ULPI_H -#define __MACH_ULPI_H - -#ifdef CONFIG_USB_ULPI -struct usb_phy *imx_otg_ulpi_create(unsigned int flags); -#else -static inline struct usb_phy *imx_otg_ulpi_create(unsigned int flags) -{ - return NULL; -} -#endif - -extern struct usb_phy_io_ops mxc_ulpi_access_ops; - -#endif /* __MACH_ULPI_H */ - diff --git a/arch/arm/plat-mxc/include/mach/uncompress.h b/arch/arm/plat-mxc/include/mach/uncompress.h deleted file mode 100644 index 477971b0093..00000000000 --- a/arch/arm/plat-mxc/include/mach/uncompress.h +++ /dev/null @@ -1,132 +0,0 @@ -/* - * arch/arm/plat-mxc/include/mach/uncompress.h - * - * Copyright (C) 1999 ARM Limited - * Copyright (C) Shane Nay (shane@minirl.com) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#ifndef __ASM_ARCH_MXC_UNCOMPRESS_H__ -#define __ASM_ARCH_MXC_UNCOMPRESS_H__ - -#define __MXC_BOOT_UNCOMPRESS - -#include <asm/mach-types.h> - -unsigned long uart_base; - -#define UART(x) (*(volatile unsigned long *)(uart_base + (x))) - -#define USR2 0x98 -#define USR2_TXFE (1<<14) -#define TXR 0x40 -#define UCR1 0x80 -#define UCR1_UARTEN 1 - -/* - * The following code assumes the serial port has already been - * initialized by the bootloader. We search for the first enabled - * port in the most probable order. If you didn't setup a port in - * your bootloader then nothing will appear (which might be desired). - * - * This does not append a newline - */ - -static void putc(int ch) -{ - if (!uart_base) - return; - if (!(UART(UCR1) & UCR1_UARTEN)) - return; - - while (!(UART(USR2) & USR2_TXFE)) - barrier(); - - UART(TXR) = ch; -} - -static inline void flush(void) -{ -} - -#define MX1_UART1_BASE_ADDR 0x00206000 -#define MX25_UART1_BASE_ADDR 0x43f90000 -#define MX2X_UART1_BASE_ADDR 0x1000a000 -#define MX3X_UART1_BASE_ADDR 0x43F90000 -#define MX3X_UART2_BASE_ADDR 0x43F94000 -#define MX3X_UART5_BASE_ADDR 0x43FB4000 -#define MX51_UART1_BASE_ADDR 0x73fbc000 -#define MX50_UART1_BASE_ADDR 0x53fbc000 -#define MX53_UART1_BASE_ADDR 0x53fbc000 - -static __inline__ void __arch_decomp_setup(unsigned long arch_id) -{ - switch (arch_id) { - case MACH_TYPE_MX1ADS: - case MACH_TYPE_SCB9328: - uart_base = MX1_UART1_BASE_ADDR; - break; - case MACH_TYPE_MX25_3DS: - uart_base = MX25_UART1_BASE_ADDR; - break; - case MACH_TYPE_IMX27LITE: - case MACH_TYPE_MX27_3DS: - case MACH_TYPE_MX27ADS: - case MACH_TYPE_PCM038: - case MACH_TYPE_MX21ADS: - case MACH_TYPE_PCA100: - case MACH_TYPE_MXT_TD60: - case MACH_TYPE_IMX27IPCAM: - uart_base = MX2X_UART1_BASE_ADDR; - break; - case MACH_TYPE_MX31LITE: - case MACH_TYPE_ARMADILLO5X0: - case MACH_TYPE_MX31MOBOARD: - case MACH_TYPE_QONG: - case MACH_TYPE_MX31_3DS: - case MACH_TYPE_PCM037: - case MACH_TYPE_MX31ADS: - case MACH_TYPE_MX35_3DS: - case MACH_TYPE_PCM043: - case MACH_TYPE_LILLY1131: - case MACH_TYPE_VPR200: - case MACH_TYPE_EUKREA_CPUIMX35SD: - uart_base = MX3X_UART1_BASE_ADDR; - break; - case MACH_TYPE_MAGX_ZN5: - uart_base = MX3X_UART2_BASE_ADDR; - break; - case MACH_TYPE_BUG: - uart_base = MX3X_UART5_BASE_ADDR; - break; - case MACH_TYPE_MX51_BABBAGE: - case MACH_TYPE_EUKREA_CPUIMX51SD: - case MACH_TYPE_MX51_3DS: - uart_base = MX51_UART1_BASE_ADDR; - break; - case MACH_TYPE_MX50_RDP: - uart_base = MX50_UART1_BASE_ADDR; - break; - case MACH_TYPE_MX53_EVK: - case MACH_TYPE_MX53_LOCO: - case MACH_TYPE_MX53_SMD: - case MACH_TYPE_MX53_ARD: - uart_base = MX53_UART1_BASE_ADDR; - break; - default: - break; - } -} - -#define arch_decomp_setup() __arch_decomp_setup(arch_id) -#define arch_decomp_wdog() - -#endif /* __ASM_ARCH_MXC_UNCOMPRESS_H__ */ diff --git a/arch/arm/plat-mxc/iram_alloc.c b/arch/arm/plat-mxc/iram_alloc.c deleted file mode 100644 index 074c3869626..00000000000 --- a/arch/arm/plat-mxc/iram_alloc.c +++ /dev/null @@ -1,73 +0,0 @@ -/* - * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#include <linux/kernel.h> -#include <linux/io.h> -#include <linux/module.h> -#include <linux/spinlock.h> -#include <linux/genalloc.h> -#include <mach/iram.h> - -static unsigned long iram_phys_base; -static void __iomem *iram_virt_base; -static struct gen_pool *iram_pool; - -static inline void __iomem *iram_phys_to_virt(unsigned long p) -{ - return iram_virt_base + (p - iram_phys_base); -} - -void __iomem *iram_alloc(unsigned int size, unsigned long *dma_addr) -{ - if (!iram_pool) - return NULL; - - *dma_addr = gen_pool_alloc(iram_pool, size); - pr_debug("iram alloc - %dB@0x%lX\n", size, *dma_addr); - if (!*dma_addr) - return NULL; - return iram_phys_to_virt(*dma_addr); -} -EXPORT_SYMBOL(iram_alloc); - -void iram_free(unsigned long addr, unsigned int size) -{ - if (!iram_pool) - return; - - gen_pool_free(iram_pool, addr, size); -} -EXPORT_SYMBOL(iram_free); - -int __init iram_init(unsigned long base, unsigned long size) -{ - iram_phys_base = base; - - iram_pool = gen_pool_create(PAGE_SHIFT, -1); - if (!iram_pool) - return -ENOMEM; - - gen_pool_add(iram_pool, base, size, -1); - iram_virt_base = ioremap(iram_phys_base, size); - if (!iram_virt_base) - return -EIO; - - pr_debug("i.MX IRAM pool: %ld KB@0x%p\n", size / 1024, iram_virt_base); - return 0; -} diff --git a/arch/arm/plat-mxc/irq-common.c b/arch/arm/plat-mxc/irq-common.c deleted file mode 100644 index b6e11458e5a..00000000000 --- a/arch/arm/plat-mxc/irq-common.c +++ /dev/null @@ -1,60 +0,0 @@ -/* - * Copyright (C) BitBox Ltd 2010 - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#include <linux/module.h> -#include <linux/irq.h> - -#include "irq-common.h" - -int imx_irq_set_priority(unsigned char irq, unsigned char prio) -{ - struct irq_chip_generic *gc; - struct mxc_extra_irq *exirq; - int ret; - - ret = -ENOSYS; - - gc = irq_get_chip_data(irq); - if (gc && gc->private) { - exirq = gc->private; - if (exirq->set_priority) - ret = exirq->set_priority(irq, prio); - } - - return ret; -} -EXPORT_SYMBOL(imx_irq_set_priority); - -int mxc_set_irq_fiq(unsigned int irq, unsigned int type) -{ - struct irq_chip_generic *gc; - struct mxc_extra_irq *exirq; - int ret; - - ret = -ENOSYS; - - gc = irq_get_chip_data(irq); - if (gc && gc->private) { - exirq = gc->private; - if (exirq->set_irq_fiq) - ret = exirq->set_irq_fiq(irq, type); - } - - return ret; -} -EXPORT_SYMBOL(mxc_set_irq_fiq); diff --git a/arch/arm/plat-mxc/irq-common.h b/arch/arm/plat-mxc/irq-common.h deleted file mode 100644 index 6ccb3a14c69..00000000000 --- a/arch/arm/plat-mxc/irq-common.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Copyright (C) BitBox Ltd 2010 - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#ifndef __PLAT_MXC_IRQ_COMMON_H__ -#define __PLAT_MXC_IRQ_COMMON_H__ - -struct mxc_extra_irq -{ - int (*set_priority)(unsigned char irq, unsigned char prio); - int (*set_irq_fiq)(unsigned int irq, unsigned int type); -}; - -#endif diff --git a/arch/arm/plat-mxc/ssi-fiq-ksym.c b/arch/arm/plat-mxc/ssi-fiq-ksym.c deleted file mode 100644 index 792090f9a03..00000000000 --- a/arch/arm/plat-mxc/ssi-fiq-ksym.c +++ /dev/null @@ -1,20 +0,0 @@ -/* - * Exported ksyms for the SSI FIQ handler - * - * Copyright (C) 2009, Sascha Hauer <s.hauer@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/module.h> - -#include <linux/platform_data/asoc-imx-ssi.h> - -EXPORT_SYMBOL(imx_ssi_fiq_tx_buffer); -EXPORT_SYMBOL(imx_ssi_fiq_rx_buffer); -EXPORT_SYMBOL(imx_ssi_fiq_start); -EXPORT_SYMBOL(imx_ssi_fiq_end); -EXPORT_SYMBOL(imx_ssi_fiq_base); - diff --git a/arch/arm/plat-mxc/ssi-fiq.S b/arch/arm/plat-mxc/ssi-fiq.S deleted file mode 100644 index a8b93c5f29b..00000000000 --- a/arch/arm/plat-mxc/ssi-fiq.S +++ /dev/null @@ -1,147 +0,0 @@ -/* - * Copyright (C) 2009 Sascha Hauer <s.hauer@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/linkage.h> -#include <asm/assembler.h> - -/* - * r8 = bit 0-15: tx offset, bit 16-31: tx buffer size - * r9 = bit 0-15: rx offset, bit 16-31: rx buffer size - */ - -#define SSI_STX0 0x00 -#define SSI_SRX0 0x08 -#define SSI_SISR 0x14 -#define SSI_SIER 0x18 -#define SSI_SACNT 0x38 - -#define SSI_SACNT_AC97EN (1 << 0) - -#define SSI_SIER_TFE0_EN (1 << 0) -#define SSI_SISR_TFE0 (1 << 0) -#define SSI_SISR_RFF0 (1 << 2) -#define SSI_SIER_RFF0_EN (1 << 2) - - .text - .global imx_ssi_fiq_start - .global imx_ssi_fiq_end - .global imx_ssi_fiq_base - .global imx_ssi_fiq_rx_buffer - .global imx_ssi_fiq_tx_buffer - -/* - * imx_ssi_fiq_start is _intentionally_ not marked as a function symbol - * using ENDPROC(). imx_ssi_fiq_start and imx_ssi_fiq_end are used to - * mark the function body so that it can be copied to the FIQ vector in - * the vectors page. imx_ssi_fiq_start should only be called as the result - * of an FIQ: calling it directly will not work. - */ -imx_ssi_fiq_start: - ldr r12, .L_imx_ssi_fiq_base - - /* TX */ - ldr r13, .L_imx_ssi_fiq_tx_buffer - - /* shall we send? */ - ldr r11, [r12, #SSI_SIER] - tst r11, #SSI_SIER_TFE0_EN - beq 1f - - /* TX FIFO empty? */ - ldr r11, [r12, #SSI_SISR] - tst r11, #SSI_SISR_TFE0 - beq 1f - - mov r10, #0x10000 - sub r10, #1 - and r10, r10, r8 /* r10: current buffer offset */ - - add r13, r13, r10 - - ldrh r11, [r13] - strh r11, [r12, #SSI_STX0] - - ldrh r11, [r13, #2] - strh r11, [r12, #SSI_STX0] - - ldrh r11, [r13, #4] - strh r11, [r12, #SSI_STX0] - - ldrh r11, [r13, #6] - strh r11, [r12, #SSI_STX0] - - add r10, #8 - lsr r11, r8, #16 /* r11: buffer size */ - cmp r10, r11 - lslgt r8, r11, #16 - addle r8, #8 -1: - /* RX */ - - /* shall we receive? */ - ldr r11, [r12, #SSI_SIER] - tst r11, #SSI_SIER_RFF0_EN - beq 1f - - /* RX FIFO full? */ - ldr r11, [r12, #SSI_SISR] - tst r11, #SSI_SISR_RFF0 - beq 1f - - ldr r13, .L_imx_ssi_fiq_rx_buffer - - mov r10, #0x10000 - sub r10, #1 - and r10, r10, r9 /* r10: current buffer offset */ - - add r13, r13, r10 - - ldr r11, [r12, #SSI_SACNT] - tst r11, #SSI_SACNT_AC97EN - - ldr r11, [r12, #SSI_SRX0] - strh r11, [r13] - - ldr r11, [r12, #SSI_SRX0] - strh r11, [r13, #2] - - /* dummy read to skip slot 12 */ - ldrne r11, [r12, #SSI_SRX0] - - ldr r11, [r12, #SSI_SRX0] - strh r11, [r13, #4] - - ldr r11, [r12, #SSI_SRX0] - strh r11, [r13, #6] - - /* dummy read to skip slot 12 */ - ldrne r11, [r12, #SSI_SRX0] - - add r10, #8 - lsr r11, r9, #16 /* r11: buffer size */ - cmp r10, r11 - lslgt r9, r11, #16 - addle r9, #8 - -1: - @ return from FIQ - subs pc, lr, #4 - - .align -.L_imx_ssi_fiq_base: -imx_ssi_fiq_base: - .word 0x0 -.L_imx_ssi_fiq_rx_buffer: -imx_ssi_fiq_rx_buffer: - .word 0x0 -.L_imx_ssi_fiq_tx_buffer: -imx_ssi_fiq_tx_buffer: - .word 0x0 -.L_imx_ssi_fiq_end: -imx_ssi_fiq_end: - diff --git a/arch/arm/plat-mxc/system.c b/arch/arm/plat-mxc/system.c deleted file mode 100644 index 3da78cfc5a9..00000000000 --- a/arch/arm/plat-mxc/system.c +++ /dev/null @@ -1,69 +0,0 @@ -/* - * Copyright (C) 1999 ARM Limited - * Copyright (C) 2000 Deep Blue Solutions Ltd - * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Juergen Beisert, kernel@pengutronix.de - * Copyright 2009 Ilya Yanok, Emcraft Systems Ltd, yanok@emcraft.com - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <linux/kernel.h> -#include <linux/clk.h> -#include <linux/io.h> -#include <linux/err.h> -#include <linux/delay.h> - -#include <mach/hardware.h> -#include <mach/common.h> -#include <asm/system_misc.h> -#include <asm/proc-fns.h> -#include <asm/mach-types.h> - -static void __iomem *wdog_base; - -/* - * Reset the system. It is called by machine_restart(). - */ -void mxc_restart(char mode, const char *cmd) -{ - unsigned int wcr_enable; - - if (cpu_is_mx1()) { - wcr_enable = (1 << 0); - } else { - struct clk *clk; - - clk = clk_get_sys("imx2-wdt.0", NULL); - if (!IS_ERR(clk)) - clk_prepare_enable(clk); - wcr_enable = (1 << 2); - } - - /* Assert SRS signal */ - __raw_writew(wcr_enable, wdog_base); - - /* wait for reset to assert... */ - mdelay(500); - - printk(KERN_ERR "Watchdog reset failed to assert reset\n"); - - /* delay to allow the serial port to show the message */ - mdelay(50); - - /* we'll take a jump through zero as a poor second */ - soft_restart(0); -} - -void mxc_arch_reset_init(void __iomem *base) -{ - wdog_base = base; -} diff --git a/arch/arm/plat-mxc/time.c b/arch/arm/plat-mxc/time.c deleted file mode 100644 index a17abcf9832..00000000000 --- a/arch/arm/plat-mxc/time.c +++ /dev/null @@ -1,325 +0,0 @@ -/* - * linux/arch/arm/plat-mxc/time.c - * - * Copyright (C) 2000-2001 Deep Blue Solutions - * Copyright (C) 2002 Shane Nay (shane@minirl.com) - * Copyright (C) 2006-2007 Pavel Pisa (ppisa@pikron.com) - * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#include <linux/interrupt.h> -#include <linux/irq.h> -#include <linux/clockchips.h> -#include <linux/clk.h> -#include <linux/err.h> - -#include <mach/hardware.h> -#include <asm/sched_clock.h> -#include <asm/mach/time.h> -#include <mach/common.h> - -/* - * There are 2 versions of the timer hardware on Freescale MXC hardware. - * Version 1: MX1/MXL, MX21, MX27. - * Version 2: MX25, MX31, MX35, MX37, MX51 - */ - -/* defines common for all i.MX */ -#define MXC_TCTL 0x00 -#define MXC_TCTL_TEN (1 << 0) /* Enable module */ -#define MXC_TPRER 0x04 - -/* MX1, MX21, MX27 */ -#define MX1_2_TCTL_CLK_PCLK1 (1 << 1) -#define MX1_2_TCTL_IRQEN (1 << 4) -#define MX1_2_TCTL_FRR (1 << 8) -#define MX1_2_TCMP 0x08 -#define MX1_2_TCN 0x10 -#define MX1_2_TSTAT 0x14 - -/* MX21, MX27 */ -#define MX2_TSTAT_CAPT (1 << 1) -#define MX2_TSTAT_COMP (1 << 0) - -/* MX31, MX35, MX25, MX5 */ -#define V2_TCTL_WAITEN (1 << 3) /* Wait enable mode */ -#define V2_TCTL_CLK_IPG (1 << 6) -#define V2_TCTL_CLK_PER (2 << 6) -#define V2_TCTL_FRR (1 << 9) -#define V2_IR 0x0c -#define V2_TSTAT 0x08 -#define V2_TSTAT_OF1 (1 << 0) -#define V2_TCN 0x24 -#define V2_TCMP 0x10 - -#define timer_is_v1() (cpu_is_mx1() || cpu_is_mx21() || cpu_is_mx27()) -#define timer_is_v2() (!timer_is_v1()) - -static struct clock_event_device clockevent_mxc; -static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED; - -static void __iomem *timer_base; - -static inline void gpt_irq_disable(void) -{ - unsigned int tmp; - - if (timer_is_v2()) - __raw_writel(0, timer_base + V2_IR); - else { - tmp = __raw_readl(timer_base + MXC_TCTL); - __raw_writel(tmp & ~MX1_2_TCTL_IRQEN, timer_base + MXC_TCTL); - } -} - -static inline void gpt_irq_enable(void) -{ - if (timer_is_v2()) - __raw_writel(1<<0, timer_base + V2_IR); - else { - __raw_writel(__raw_readl(timer_base + MXC_TCTL) | MX1_2_TCTL_IRQEN, - timer_base + MXC_TCTL); - } -} - -static void gpt_irq_acknowledge(void) -{ - if (timer_is_v1()) { - if (cpu_is_mx1()) - __raw_writel(0, timer_base + MX1_2_TSTAT); - else - __raw_writel(MX2_TSTAT_CAPT | MX2_TSTAT_COMP, - timer_base + MX1_2_TSTAT); - } else if (timer_is_v2()) - __raw_writel(V2_TSTAT_OF1, timer_base + V2_TSTAT); -} - -static void __iomem *sched_clock_reg; - -static u32 notrace mxc_read_sched_clock(void) -{ - return sched_clock_reg ? __raw_readl(sched_clock_reg) : 0; -} - -static int __init mxc_clocksource_init(struct clk *timer_clk) -{ - unsigned int c = clk_get_rate(timer_clk); - void __iomem *reg = timer_base + (timer_is_v2() ? V2_TCN : MX1_2_TCN); - - sched_clock_reg = reg; - - setup_sched_clock(mxc_read_sched_clock, 32, c); - return clocksource_mmio_init(reg, "mxc_timer1", c, 200, 32, - clocksource_mmio_readl_up); -} - -/* clock event */ - -static int mx1_2_set_next_event(unsigned long evt, - struct clock_event_device *unused) -{ - unsigned long tcmp; - - tcmp = __raw_readl(timer_base + MX1_2_TCN) + evt; - - __raw_writel(tcmp, timer_base + MX1_2_TCMP); - - return (int)(tcmp - __raw_readl(timer_base + MX1_2_TCN)) < 0 ? - -ETIME : 0; -} - -static int v2_set_next_event(unsigned long evt, - struct clock_event_device *unused) -{ - unsigned long tcmp; - - tcmp = __raw_readl(timer_base + V2_TCN) + evt; - - __raw_writel(tcmp, timer_base + V2_TCMP); - - return (int)(tcmp - __raw_readl(timer_base + V2_TCN)) < 0 ? - -ETIME : 0; -} - -#ifdef DEBUG -static const char *clock_event_mode_label[] = { - [CLOCK_EVT_MODE_PERIODIC] = "CLOCK_EVT_MODE_PERIODIC", - [CLOCK_EVT_MODE_ONESHOT] = "CLOCK_EVT_MODE_ONESHOT", - [CLOCK_EVT_MODE_SHUTDOWN] = "CLOCK_EVT_MODE_SHUTDOWN", - [CLOCK_EVT_MODE_UNUSED] = "CLOCK_EVT_MODE_UNUSED", - [CLOCK_EVT_MODE_RESUME] = "CLOCK_EVT_MODE_RESUME", -}; -#endif /* DEBUG */ - -static void mxc_set_mode(enum clock_event_mode mode, - struct clock_event_device *evt) -{ - unsigned long flags; - - /* - * The timer interrupt generation is disabled at least - * for enough time to call mxc_set_next_event() - */ - local_irq_save(flags); - - /* Disable interrupt in GPT module */ - gpt_irq_disable(); - - if (mode != clockevent_mode) { - /* Set event time into far-far future */ - if (timer_is_v2()) - __raw_writel(__raw_readl(timer_base + V2_TCN) - 3, - timer_base + V2_TCMP); - else - __raw_writel(__raw_readl(timer_base + MX1_2_TCN) - 3, - timer_base + MX1_2_TCMP); - - /* Clear pending interrupt */ - gpt_irq_acknowledge(); - } - -#ifdef DEBUG - printk(KERN_INFO "mxc_set_mode: changing mode from %s to %s\n", - clock_event_mode_label[clockevent_mode], - clock_event_mode_label[mode]); -#endif /* DEBUG */ - - /* Remember timer mode */ - clockevent_mode = mode; - local_irq_restore(flags); - - switch (mode) { - case CLOCK_EVT_MODE_PERIODIC: - printk(KERN_ERR"mxc_set_mode: Periodic mode is not " - "supported for i.MX\n"); - break; - case CLOCK_EVT_MODE_ONESHOT: - /* - * Do not put overhead of interrupt enable/disable into - * mxc_set_next_event(), the core has about 4 minutes - * to call mxc_set_next_event() or shutdown clock after - * mode switching - */ - local_irq_save(flags); - gpt_irq_enable(); - local_irq_restore(flags); - break; - case CLOCK_EVT_MODE_SHUTDOWN: - case CLOCK_EVT_MODE_UNUSED: - case CLOCK_EVT_MODE_RESUME: - /* Left event sources disabled, no more interrupts appear */ - break; - } -} - -/* - * IRQ handler for the timer - */ -static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id) -{ - struct clock_event_device *evt = &clockevent_mxc; - uint32_t tstat; - - if (timer_is_v2()) - tstat = __raw_readl(timer_base + V2_TSTAT); - else - tstat = __raw_readl(timer_base + MX1_2_TSTAT); - - gpt_irq_acknowledge(); - - evt->event_handler(evt); - - return IRQ_HANDLED; -} - -static struct irqaction mxc_timer_irq = { - .name = "i.MX Timer Tick", - .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, - .handler = mxc_timer_interrupt, -}; - -static struct clock_event_device clockevent_mxc = { - .name = "mxc_timer1", - .features = CLOCK_EVT_FEAT_ONESHOT, - .shift = 32, - .set_mode = mxc_set_mode, - .set_next_event = mx1_2_set_next_event, - .rating = 200, -}; - -static int __init mxc_clockevent_init(struct clk *timer_clk) -{ - unsigned int c = clk_get_rate(timer_clk); - - if (timer_is_v2()) - clockevent_mxc.set_next_event = v2_set_next_event; - - clockevent_mxc.mult = div_sc(c, NSEC_PER_SEC, - clockevent_mxc.shift); - clockevent_mxc.max_delta_ns = - clockevent_delta2ns(0xfffffffe, &clockevent_mxc); - clockevent_mxc.min_delta_ns = - clockevent_delta2ns(0xff, &clockevent_mxc); - - clockevent_mxc.cpumask = cpumask_of(0); - - clockevents_register_device(&clockevent_mxc); - - return 0; -} - -void __init mxc_timer_init(void __iomem *base, int irq) -{ - uint32_t tctl_val; - struct clk *timer_clk; - struct clk *timer_ipg_clk; - - timer_clk = clk_get_sys("imx-gpt.0", "per"); - if (IS_ERR(timer_clk)) { - pr_err("i.MX timer: unable to get clk\n"); - return; - } - - timer_ipg_clk = clk_get_sys("imx-gpt.0", "ipg"); - if (!IS_ERR(timer_ipg_clk)) - clk_prepare_enable(timer_ipg_clk); - - clk_prepare_enable(timer_clk); - - timer_base = base; - - /* - * Initialise to a known state (all timers off, and timing reset) - */ - - __raw_writel(0, timer_base + MXC_TCTL); - __raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */ - - if (timer_is_v2()) - tctl_val = V2_TCTL_CLK_PER | V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN; - else - tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN; - - __raw_writel(tctl_val, timer_base + MXC_TCTL); - - /* init and register the timer to the framework */ - mxc_clocksource_init(timer_clk); - mxc_clockevent_init(timer_clk); - - /* Make irqs happen */ - setup_irq(irq, &mxc_timer_irq); -} diff --git a/arch/arm/plat-mxc/tzic.c b/arch/arm/plat-mxc/tzic.c deleted file mode 100644 index 3ed1adbc09f..00000000000 --- a/arch/arm/plat-mxc/tzic.c +++ /dev/null @@ -1,224 +0,0 @@ -/* - * Copyright (C)2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include <linux/module.h> -#include <linux/moduleparam.h> -#include <linux/init.h> -#include <linux/device.h> -#include <linux/errno.h> -#include <linux/io.h> -#include <linux/irqdomain.h> -#include <linux/of.h> - -#include <asm/mach/irq.h> -#include <asm/exception.h> - -#include <mach/hardware.h> -#include <mach/common.h> -#include <mach/irqs.h> - -#include "irq-common.h" - -/* - ***************************************** - * TZIC Registers * - ***************************************** - */ - -#define TZIC_INTCNTL 0x0000 /* Control register */ -#define TZIC_INTTYPE 0x0004 /* Controller Type register */ -#define TZIC_IMPID 0x0008 /* Distributor Implementer Identification */ -#define TZIC_PRIOMASK 0x000C /* Priority Mask Reg */ -#define TZIC_SYNCCTRL 0x0010 /* Synchronizer Control register */ -#define TZIC_DSMINT 0x0014 /* DSM interrupt Holdoffregister */ -#define TZIC_INTSEC0(i) (0x0080 + ((i) << 2)) /* Interrupt Security Reg 0 */ -#define TZIC_ENSET0(i) (0x0100 + ((i) << 2)) /* Enable Set Reg 0 */ -#define TZIC_ENCLEAR0(i) (0x0180 + ((i) << 2)) /* Enable Clear Reg 0 */ -#define TZIC_SRCSET0 0x0200 /* Source Set Register 0 */ -#define TZIC_SRCCLAR0 0x0280 /* Source Clear Register 0 */ -#define TZIC_PRIORITY0 0x0400 /* Priority Register 0 */ -#define TZIC_PND0 0x0D00 /* Pending Register 0 */ -#define TZIC_HIPND(i) (0x0D80+ ((i) << 2)) /* High Priority Pending Register */ -#define TZIC_WAKEUP0(i) (0x0E00 + ((i) << 2)) /* Wakeup Config Register */ -#define TZIC_SWINT 0x0F00 /* Software Interrupt Rigger Register */ -#define TZIC_ID0 0x0FD0 /* Indentification Register 0 */ - -void __iomem *tzic_base; /* Used as irq controller base in entry-macro.S */ -static struct irq_domain *domain; - -#define TZIC_NUM_IRQS 128 - -#ifdef CONFIG_FIQ -static int tzic_set_irq_fiq(unsigned int irq, unsigned int type) -{ - unsigned int index, mask, value; - - index = irq >> 5; - if (unlikely(index >= 4)) - return -EINVAL; - mask = 1U << (irq & 0x1F); - - value = __raw_readl(tzic_base + TZIC_INTSEC0(index)) | mask; - if (type) - value &= ~mask; - __raw_writel(value, tzic_base + TZIC_INTSEC0(index)); - - return 0; -} -#else -#define tzic_set_irq_fiq NULL -#endif - -#ifdef CONFIG_PM -static void tzic_irq_suspend(struct irq_data *d) -{ - struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); - int idx = d->hwirq >> 5; - - __raw_writel(gc->wake_active, tzic_base + TZIC_WAKEUP0(idx)); -} - -static void tzic_irq_resume(struct irq_data *d) -{ - int idx = d->hwirq >> 5; - - __raw_writel(__raw_readl(tzic_base + TZIC_ENSET0(idx)), - tzic_base + TZIC_WAKEUP0(idx)); -} - -#else -#define tzic_irq_suspend NULL -#define tzic_irq_resume NULL -#endif - -static struct mxc_extra_irq tzic_extra_irq = { -#ifdef CONFIG_FIQ - .set_irq_fiq = tzic_set_irq_fiq, -#endif -}; - -static __init void tzic_init_gc(int idx, unsigned int irq_start) -{ - struct irq_chip_generic *gc; - struct irq_chip_type *ct; - - gc = irq_alloc_generic_chip("tzic", 1, irq_start, tzic_base, - handle_level_irq); - gc->private = &tzic_extra_irq; - gc->wake_enabled = IRQ_MSK(32); - - ct = gc->chip_types; - ct->chip.irq_mask = irq_gc_mask_disable_reg; - ct->chip.irq_unmask = irq_gc_unmask_enable_reg; - ct->chip.irq_set_wake = irq_gc_set_wake; - ct->chip.irq_suspend = tzic_irq_suspend; - ct->chip.irq_resume = tzic_irq_resume; - ct->regs.disable = TZIC_ENCLEAR0(idx); - ct->regs.enable = TZIC_ENSET0(idx); - - irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0); -} - -asmlinkage void __exception_irq_entry tzic_handle_irq(struct pt_regs *regs) -{ - u32 stat; - int i, irqofs, handled; - - do { - handled = 0; - - for (i = 0; i < 4; i++) { - stat = __raw_readl(tzic_base + TZIC_HIPND(i)) & - __raw_readl(tzic_base + TZIC_INTSEC0(i)); - - while (stat) { - handled = 1; - irqofs = fls(stat) - 1; - handle_IRQ(irq_find_mapping(domain, - irqofs + i * 32), regs); - stat &= ~(1 << irqofs); - } - } - } while (handled); -} - -/* - * This function initializes the TZIC hardware and disables all the - * interrupts. It registers the interrupt enable and disable functions - * to the kernel for each interrupt source. - */ -void __init tzic_init_irq(void __iomem *irqbase) -{ - struct device_node *np; - int irq_base; - int i; - - tzic_base = irqbase; - /* put the TZIC into the reset value with - * all interrupts disabled - */ - i = __raw_readl(tzic_base + TZIC_INTCNTL); - - __raw_writel(0x80010001, tzic_base + TZIC_INTCNTL); - __raw_writel(0x1f, tzic_base + TZIC_PRIOMASK); - __raw_writel(0x02, tzic_base + TZIC_SYNCCTRL); - - for (i = 0; i < 4; i++) - __raw_writel(0xFFFFFFFF, tzic_base + TZIC_INTSEC0(i)); - - /* disable all interrupts */ - for (i = 0; i < 4; i++) - __raw_writel(0xFFFFFFFF, tzic_base + TZIC_ENCLEAR0(i)); - - /* all IRQ no FIQ Warning :: No selection */ - - irq_base = irq_alloc_descs(-1, 0, TZIC_NUM_IRQS, numa_node_id()); - WARN_ON(irq_base < 0); - - np = of_find_compatible_node(NULL, NULL, "fsl,tzic"); - domain = irq_domain_add_legacy(np, TZIC_NUM_IRQS, irq_base, 0, - &irq_domain_simple_ops, NULL); - WARN_ON(!domain); - - for (i = 0; i < 4; i++, irq_base += 32) - tzic_init_gc(i, irq_base); - -#ifdef CONFIG_FIQ - /* Initialize FIQ */ - init_FIQ(FIQ_START); -#endif - - pr_info("TrustZone Interrupt Controller (TZIC) initialized\n"); -} - -/** - * tzic_enable_wake() - enable wakeup interrupt - * - * @return 0 if successful; non-zero otherwise - * - * This function provides an interrupt synchronization point that is required - * by tzic enabled platforms before entering imx specific low power modes (ie, - * those low power modes beyond the WAIT_CLOCKED basic ARM WFI only mode). - */ -int tzic_enable_wake(void) -{ - unsigned int i; - - __raw_writel(1, tzic_base + TZIC_DSMINT); - if (unlikely(__raw_readl(tzic_base + TZIC_DSMINT) == 0)) - return -EAGAIN; - - for (i = 0; i < 4; i++) - __raw_writel(__raw_readl(tzic_base + TZIC_ENSET0(i)), - tzic_base + TZIC_WAKEUP0(i)); - - return 0; -} diff --git a/arch/arm/plat-mxc/ulpi.c b/arch/arm/plat-mxc/ulpi.c deleted file mode 100644 index d2963427184..00000000000 --- a/arch/arm/plat-mxc/ulpi.c +++ /dev/null @@ -1,118 +0,0 @@ -/* - * Copyright 2008 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de> - * Copyright 2009 Daniel Mack <daniel@caiaq.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#include <linux/module.h> -#include <linux/kernel.h> -#include <linux/io.h> -#include <linux/delay.h> -#include <linux/usb/otg.h> -#include <linux/usb/ulpi.h> - -#include <mach/ulpi.h> - -/* ULPIVIEW register bits */ -#define ULPIVW_WU (1 << 31) /* Wakeup */ -#define ULPIVW_RUN (1 << 30) /* read/write run */ -#define ULPIVW_WRITE (1 << 29) /* 0 = read 1 = write */ -#define ULPIVW_SS (1 << 27) /* SyncState */ -#define ULPIVW_PORT_MASK 0x07 /* Port field */ -#define ULPIVW_PORT_SHIFT 24 -#define ULPIVW_ADDR_MASK 0xff /* data address field */ -#define ULPIVW_ADDR_SHIFT 16 -#define ULPIVW_RDATA_MASK 0xff /* read data field */ -#define ULPIVW_RDATA_SHIFT 8 -#define ULPIVW_WDATA_MASK 0xff /* write data field */ -#define ULPIVW_WDATA_SHIFT 0 - -static int ulpi_poll(void __iomem *view, u32 bit) -{ - int timeout = 10000; - - while (timeout--) { - u32 data = __raw_readl(view); - - if (!(data & bit)) - return 0; - - cpu_relax(); - }; - - printk(KERN_WARNING "timeout polling for ULPI device\n"); - - return -ETIMEDOUT; -} - -static int ulpi_read(struct usb_phy *otg, u32 reg) -{ - int ret; - void __iomem *view = otg->io_priv; - - /* make sure interface is running */ - if (!(__raw_readl(view) & ULPIVW_SS)) { - __raw_writel(ULPIVW_WU, view); - - /* wait for wakeup */ - ret = ulpi_poll(view, ULPIVW_WU); - if (ret) - return ret; - } - - /* read the register */ - __raw_writel((ULPIVW_RUN | (reg << ULPIVW_ADDR_SHIFT)), view); - - /* wait for completion */ - ret = ulpi_poll(view, ULPIVW_RUN); - if (ret) - return ret; - - return (__raw_readl(view) >> ULPIVW_RDATA_SHIFT) & ULPIVW_RDATA_MASK; -} - -static int ulpi_write(struct usb_phy *otg, u32 val, u32 reg) -{ - int ret; - void __iomem *view = otg->io_priv; - - /* make sure the interface is running */ - if (!(__raw_readl(view) & ULPIVW_SS)) { - __raw_writel(ULPIVW_WU, view); - /* wait for wakeup */ - ret = ulpi_poll(view, ULPIVW_WU); - if (ret) - return ret; - } - - __raw_writel((ULPIVW_RUN | ULPIVW_WRITE | - (reg << ULPIVW_ADDR_SHIFT) | - ((val & ULPIVW_WDATA_MASK) << ULPIVW_WDATA_SHIFT)), view); - - /* wait for completion */ - return ulpi_poll(view, ULPIVW_RUN); -} - -struct usb_phy_io_ops mxc_ulpi_access_ops = { - .read = ulpi_read, - .write = ulpi_write, -}; -EXPORT_SYMBOL_GPL(mxc_ulpi_access_ops); - -struct usb_phy *imx_otg_ulpi_create(unsigned int flags) -{ - return otg_ulpi_create(&mxc_ulpi_access_ops, flags); -} |