diff options
| author | Uwe Kleine-König <u.kleine-koenig@pengutronix.de> | 2010-06-30 12:16:24 +0200 |
|---|---|---|
| committer | Uwe Kleine-König <u.kleine-koenig@pengutronix.de> | 2010-07-26 14:27:25 +0200 |
| commit | 2dcf78c0eeae3bd07082821557014f25f02ca2e9 (patch) | |
| tree | 8ca5c4c7f35c9a9ab07fcd9732124c905e609aa1 /arch/arm/plat-mxc | |
| parent | 6b6322676add0fa2713d0ec89a28390fd4d907f5 (diff) | |
| parent | 5109a4597f7e758b8d20694392d0361a0b4c43b1 (diff) | |
Merge branch 'imx/for-2.6.36' of git://git.pengutronix.de/git/ukl/linux-2.6 into HEAD
There are some more conflicts than detected by git, namely support for
the newly added cpuimx machines needed to be converted to dynamic device
registration.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Conflicts:
arch/arm/mach-imx/Makefile
arch/arm/mach-imx/devices.c
arch/arm/mach-imx/devices.h
arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
arch/arm/mach-mx2/Kconfig
arch/arm/mach-mx25/Makefile
arch/arm/mach-mx25/devices.c
arch/arm/plat-mxc/include/mach/mx25.h
arch/arm/plat-mxc/include/mach/mxc_nand.h
Diffstat (limited to 'arch/arm/plat-mxc')
48 files changed, 315 insertions, 1798 deletions
diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig index 902ba9e42c5..20b2e79e54f 100644 --- a/arch/arm/plat-mxc/Kconfig +++ b/arch/arm/plat-mxc/Kconfig @@ -1,5 +1,7 @@ if ARCH_MXC +source "arch/arm/plat-mxc/devices/Kconfig" + menu "Freescale MXC Implementations" choice @@ -8,15 +10,12 @@ choice config ARCH_MX1 bool "MX1-based" - select CPU_ARM920T - select IMX_HAVE_IOMUX_V1 + select SOC_IMX1 help This enables support for systems based on the Freescale i.MX1 family config ARCH_MX2 bool "MX2-based" - select CPU_ARM926T - select IMX_HAVE_IOMUX_V1 help This enables support for systems based on the Freescale i.MX2 family @@ -49,8 +48,7 @@ config ARCH_MX5 endchoice -source "arch/arm/mach-mx1/Kconfig" -source "arch/arm/mach-mx2/Kconfig" +source "arch/arm/mach-imx/Kconfig" source "arch/arm/mach-mx3/Kconfig" source "arch/arm/mach-mx25/Kconfig" source "arch/arm/mach-mxc91231/Kconfig" diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile index 895bc3c5e0c..c7506a80eb3 100644 --- a/arch/arm/plat-mxc/Makefile +++ b/arch/arm/plat-mxc/Makefile @@ -8,8 +8,6 @@ obj-y := irq.o clock.o gpio.o time.o devices.o cpu.o system.o # MX51 uses the TZIC interrupt controller, older platforms use AVIC (irq.o) obj-$(CONFIG_MXC_TZIC) += tzic.o -obj-$(CONFIG_ARCH_MX1) += dma-mx1-mx2.o -obj-$(CONFIG_ARCH_MX2) += dma-mx1-mx2.o obj-$(CONFIG_IMX_HAVE_IOMUX_V1) += iomux-v1.o obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o obj-$(CONFIG_MXC_PWM) += pwm.o @@ -21,3 +19,5 @@ ifdef CONFIG_SND_IMX_SOC obj-y += ssi-fiq.o obj-y += ssi-fiq-ksym.o endif + +obj-y += devices/ diff --git a/arch/arm/plat-mxc/audmux-v1.c b/arch/arm/plat-mxc/audmux-v1.c index b62917ca3f9..1180bef7664 100644 --- a/arch/arm/plat-mxc/audmux-v1.c +++ b/arch/arm/plat-mxc/audmux-v1.c @@ -13,10 +13,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ #include <linux/module.h> diff --git a/arch/arm/plat-mxc/audmux-v2.c b/arch/arm/plat-mxc/audmux-v2.c index ab94d78a927..f9e7cdbd000 100644 --- a/arch/arm/plat-mxc/audmux-v2.c +++ b/arch/arm/plat-mxc/audmux-v2.c @@ -13,10 +13,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ #include <linux/module.h> diff --git a/arch/arm/plat-mxc/devices.c b/arch/arm/plat-mxc/devices.c index 56f2fb5cc45..735776d8495 100644 --- a/arch/arm/plat-mxc/devices.c +++ b/arch/arm/plat-mxc/devices.c @@ -18,6 +18,7 @@ #include <linux/kernel.h> #include <linux/init.h> +#include <linux/err.h> #include <linux/platform_device.h> #include <mach/common.h> @@ -35,3 +36,35 @@ int __init mxc_register_device(struct platform_device *pdev, void *data) return ret; } +struct platform_device *__init imx_add_platform_device(const char *name, int id, + const struct resource *res, unsigned int num_resources, + const void *data, size_t size_data) +{ + int ret = -ENOMEM; + struct platform_device *pdev; + + pdev = platform_device_alloc(name, id); + if (!pdev) + goto err; + + if (res) { + ret = platform_device_add_resources(pdev, res, num_resources); + if (ret) + goto err; + } + + if (data) { + ret = platform_device_add_data(pdev, data, size_data); + if (ret) + goto err; + } + + ret = platform_device_add(pdev); + if (ret) { +err: + platform_device_put(pdev); + return ERR_PTR(ret); + } + + return pdev; +} diff --git a/arch/arm/plat-mxc/devices/Kconfig b/arch/arm/plat-mxc/devices/Kconfig new file mode 100644 index 00000000000..09230f8c802 --- /dev/null +++ b/arch/arm/plat-mxc/devices/Kconfig @@ -0,0 +1,11 @@ +config IMX_HAVE_PLATFORM_IMX_I2C + bool + +config IMX_HAVE_PLATFORM_IMX_UART + bool + +config IMX_HAVE_PLATFORM_MXC_NAND + bool + +config IMX_HAVE_PLATFORM_SPI_IMX + bool diff --git a/arch/arm/plat-mxc/devices/Makefile b/arch/arm/plat-mxc/devices/Makefile new file mode 100644 index 00000000000..5ecbb244d21 --- /dev/null +++ b/arch/arm/plat-mxc/devices/Makefile @@ -0,0 +1,4 @@ +obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_I2C) += platform-imx-i2c.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UART) += platform-imx-uart.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_NAND) += platform-mxc_nand.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_SPI_IMX) += platform-spi_imx.o diff --git a/arch/arm/plat-mxc/devices/platform-imx-i2c.c b/arch/arm/plat-mxc/devices/platform-imx-i2c.c new file mode 100644 index 00000000000..d0af9f7d8ae --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imx-i2c.c @@ -0,0 +1,29 @@ +/* + * Copyright (C) 2009-2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <mach/devices-common.h> + +struct platform_device *__init imx_add_imx_i2c(int id, + resource_size_t iobase, resource_size_t iosize, int irq, + const struct imxi2c_platform_data *pdata) +{ + struct resource res[] = { + { + .start = iobase, + .end = iobase + iosize - 1, + .flags = IORESOURCE_MEM, + }, { + .start = irq, + .end = irq, + .flags = IORESOURCE_IRQ, + }, + }; + + return imx_add_platform_device("imx-i2c", id, res, ARRAY_SIZE(res), + pdata, sizeof(*pdata)); +} diff --git a/arch/arm/plat-mxc/devices/platform-imx-uart.c b/arch/arm/plat-mxc/devices/platform-imx-uart.c new file mode 100644 index 00000000000..fa3dff1433e --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imx-uart.c @@ -0,0 +1,60 @@ +/* + * Copyright (C) 2009-2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <mach/devices-common.h> + +struct platform_device *__init imx_add_imx_uart_3irq(int id, + resource_size_t iobase, resource_size_t iosize, + resource_size_t irqrx, resource_size_t irqtx, + resource_size_t irqrts, + const struct imxuart_platform_data *pdata) +{ + struct resource res[] = { + { + .start = iobase, + .end = iobase + iosize - 1, + .flags = IORESOURCE_MEM, + }, { + .start = irqrx, + .end = irqrx, + .flags = IORESOURCE_IRQ, + }, { + .start = irqtx, + .end = irqtx, + .flags = IORESOURCE_IRQ, + }, { + .start = irqrts, + .end = irqrx, + .flags = IORESOURCE_IRQ, + }, + }; + + return imx_add_platform_device("imx-uart", id, res, ARRAY_SIZE(res), + pdata, sizeof(*pdata)); +} + +struct platform_device *__init imx_add_imx_uart_1irq(int id, + resource_size_t iobase, resource_size_t iosize, + resource_size_t irq, + const struct imxuart_platform_data *pdata) +{ + struct resource res[] = { + { + .start = iobase, + .end = iobase + iosize - 1, + .flags = IORESOURCE_MEM, + }, { + .start = irq, + .end = irq, + .flags = IORESOURCE_IRQ, + }, + }; + + return imx_add_platform_device("imx-uart", id, res, ARRAY_SIZE(res), + pdata, sizeof(*pdata)); +} diff --git a/arch/arm/plat-mxc/devices/platform-mxc_nand.c b/arch/arm/plat-mxc/devices/platform-mxc_nand.c new file mode 100644 index 00000000000..1c286418d12 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-mxc_nand.c @@ -0,0 +1,44 @@ +/* + * Copyright (C) 2009-2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <asm/sizes.h> +#include <mach/devices-common.h> + +static struct platform_device *__init imx_add_mxc_nand(resource_size_t iobase, + int irq, const struct mxc_nand_platform_data *pdata, + resource_size_t iosize) +{ + static int id = 0; + + struct resource res[] = { + { + .start = iobase, + .end = iobase + iosize - 1, + .flags = IORESOURCE_MEM, + }, { + .start = irq, + .end = irq, + .flags = IORESOURCE_IRQ, + }, + }; + + return imx_add_platform_device("mxc_nand", id++, res, ARRAY_SIZE(res), + pdata, sizeof(*pdata)); +} + +struct platform_device *__init imx_add_mxc_nand_v1(resource_size_t iobase, + int irq, const struct mxc_nand_platform_data *pdata) +{ + return imx_add_mxc_nand(iobase, irq, pdata, SZ_4K); +} + +struct platform_device *__init imx_add_mxc_nand_v21(resource_size_t iobase, + int irq, const struct mxc_nand_platform_data *pdata) +{ + return imx_add_mxc_nand(iobase, irq, pdata, SZ_8K); +} diff --git a/arch/arm/plat-mxc/devices/platform-spi_imx.c b/arch/arm/plat-mxc/devices/platform-spi_imx.c new file mode 100644 index 00000000000..2831a6d3eb4 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-spi_imx.c @@ -0,0 +1,30 @@ +/* + * Copyright (C) 2009-2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <asm/sizes.h> +#include <mach/devices-common.h> + +struct platform_device *__init imx_add_spi_imx(int id, + resource_size_t iobase, resource_size_t iosize, int irq, + const struct spi_imx_master *pdata) +{ + struct resource res[] = { + { + .start = iobase, + .end = iobase + iosize - 1, + .flags = IORESOURCE_MEM, + }, { + .start = irq, + .end = irq, + .flags = IORESOURCE_IRQ, + }, + }; + + return imx_add_platform_device("spi_imx", id, res, ARRAY_SIZE(res), + pdata, sizeof(*pdata)); +} diff --git a/arch/arm/plat-mxc/dma-mx1-mx2.c b/arch/arm/plat-mxc/dma-mx1-mx2.c deleted file mode 100644 index e16014b0d13..00000000000 --- a/arch/arm/plat-mxc/dma-mx1-mx2.c +++ /dev/null @@ -1,863 +0,0 @@ -/* - * linux/arch/arm/plat-mxc/dma-mx1-mx2.c - * - * i.MX DMA registration and IRQ dispatching - * - * Copyright 2006 Pavel Pisa <pisa@cmp.felk.cvut.cz> - * Copyright 2008 Juergen Beisert, <kernel@pengutronix.de> - * Copyright 2008 Sascha Hauer, <s.hauer@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#include <linux/module.h> -#include <linux/init.h> -#include <linux/kernel.h> -#include <linux/interrupt.h> -#include <linux/errno.h> -#include <linux/clk.h> -#include <linux/scatterlist.h> -#include <linux/io.h> - -#include <asm/system.h> -#include <asm/irq.h> -#include <mach/hardware.h> -#include <mach/dma-mx1-mx2.h> - -#define DMA_DCR 0x00 /* Control Register */ -#define DMA_DISR 0x04 /* Interrupt status Register */ -#define DMA_DIMR 0x08 /* Interrupt mask Register */ -#define DMA_DBTOSR 0x0c /* Burst timeout status Register */ -#define DMA_DRTOSR 0x10 /* Request timeout Register */ -#define DMA_DSESR 0x14 /* Transfer Error Status Register */ -#define DMA_DBOSR 0x18 /* Buffer overflow status Register */ -#define DMA_DBTOCR 0x1c /* Burst timeout control Register */ -#define DMA_WSRA 0x40 /* W-Size Register A */ -#define DMA_XSRA 0x44 /* X-Size Register A */ -#define DMA_YSRA 0x48 /* Y-Size Register A */ -#define DMA_WSRB 0x4c /* W-Size Register B */ -#define DMA_XSRB 0x50 /* X-Size Register B */ -#define DMA_YSRB 0x54 /* Y-Size Register B */ -#define DMA_SAR(x) (0x80 + ((x) << 6)) /* Source Address Registers */ -#define DMA_DAR(x) (0x84 + ((x) << 6)) /* Destination Address Registers */ -#define DMA_CNTR(x) (0x88 + ((x) << 6)) /* Count Registers */ -#define DMA_CCR(x) (0x8c + ((x) << 6)) /* Control Registers */ -#define DMA_RSSR(x) (0x90 + ((x) << 6)) /* Request source select Registers */ -#define DMA_BLR(x) (0x94 + ((x) << 6)) /* Burst length Registers */ -#define DMA_RTOR(x) (0x98 + ((x) << 6)) /* Request timeout Registers */ -#define DMA_BUCR(x) (0x98 + ((x) << 6)) /* Bus Utilization Registers */ -#define DMA_CCNR(x) (0x9C + ((x) << 6)) /* Channel counter Registers */ - -#define DCR_DRST (1<<1) -#define DCR_DEN (1<<0) -#define DBTOCR_EN (1<<15) -#define DBTOCR_CNT(x) ((x) & 0x7fff) -#define CNTR_CNT(x) ((x) & 0xffffff) -#define CCR_ACRPT (1<<14) -#define CCR_DMOD_LINEAR (0x0 << 12) -#define CCR_DMOD_2D (0x1 << 12) -#define CCR_DMOD_FIFO (0x2 << 12) -#define CCR_DMOD_EOBFIFO (0x3 << 12) -#define CCR_SMOD_LINEAR (0x0 << 10) -#define CCR_SMOD_2D (0x1 << 10) -#define CCR_SMOD_FIFO (0x2 << 10) -#define CCR_SMOD_EOBFIFO (0x3 << 10) -#define CCR_MDIR_DEC (1<<9) -#define CCR_MSEL_B (1<<8) -#define CCR_DSIZ_32 (0x0 << 6) -#define CCR_DSIZ_8 (0x1 << 6) -#define CCR_DSIZ_16 (0x2 << 6) -#define CCR_SSIZ_32 (0x0 << 4) -#define CCR_SSIZ_8 (0x1 << 4) -#define CCR_SSIZ_16 (0x2 << 4) -#define CCR_REN (1<<3) -#define CCR_RPT (1<<2) -#define CCR_FRC (1<<1) -#define CCR_CEN (1<<0) -#define RTOR_EN (1<<15) -#define RTOR_CLK (1<<14) -#define RTOR_PSC (1<<13) - -/* - * struct imx_dma_channel - i.MX specific DMA extension - * @name: name specified by DMA client - * @irq_handler: client callback for end of transfer - * @err_handler: client callback for error condition - * @data: clients context data for callbacks - * @dma_mode: direction of the transfer %DMA_MODE_READ or %DMA_MODE_WRITE - * @sg: pointer to the actual read/written chunk for scatter-gather emulation - * @resbytes: total residual number of bytes to transfer - * (it can be lower or same as sum of SG mapped chunk sizes) - * @sgcount: number of chunks to be read/written - * - * Structure is used for IMX DMA processing. It would be probably good - * @struct dma_struct in the future for external interfacing and use - * @struct imx_dma_channel only as extension to it. - */ - -struct imx_dma_channel { - const char *name; - void (*irq_handler) (int, void *); - void (*err_handler) (int, void *, int errcode); - void (*prog_handler) (int, void *, struct scatterlist *); - void *data; - unsigned int dma_mode; - struct scatterlist *sg; - unsigned int resbytes; - int dma_num; - - int in_use; - - u32 ccr_from_device; - u32 ccr_to_device; - - struct timer_list watchdog; - - int hw_chaining; -}; - -static void __iomem *imx_dmav1_baseaddr; - -static void imx_dmav1_writel(unsigned val, unsigned offset) -{ - __raw_writel(val, imx_dmav1_baseaddr + offset); -} - -static unsigned imx_dmav1_readl(unsigned offset) -{ - return __raw_readl(imx_dmav1_baseaddr + offset); -} - -static struct imx_dma_channel imx_dma_channels[IMX_DMA_CHANNELS]; - -static struct clk *dma_clk; - -static int imx_dma_hw_chain(struct imx_dma_channel *imxdma) -{ - if (cpu_is_mx27()) - return imxdma->hw_chaining; - else - return 0; -} - -/* - * imx_dma_sg_next - prepare next chunk for scatter-gather DMA emulation - */ -static inline int imx_dma_sg_next(int channel, struct scatterlist *sg) -{ - struct imx_dma_channel *imxdma = &imx_dma_channels[channel]; - unsigned long now; - - if (!imxdma->name) { - printk(KERN_CRIT "%s: called for not allocated channel %d\n", - __func__, channel); - return 0; - } - - now = min(imxdma->resbytes, sg->length); - if (imxdma->resbytes != IMX_DMA_LENGTH_LOOP) - imxdma->resbytes -= now; - - if ((imxdma->dma_mode & DMA_MODE_MASK) == DMA_MODE_READ) - imx_dmav1_writel(sg->dma_address, DMA_DAR(channel)); - else - imx_dmav1_writel(sg->dma_address, DMA_SAR(channel)); - - imx_dmav1_writel(now, DMA_CNTR(channel)); - - pr_debug("imxdma%d: next sg chunk dst 0x%08x, src 0x%08x, " - "size 0x%08x\n", channel, - imx_dmav1_readl(DMA_DAR(channel)), - imx_dmav1_readl(DMA_SAR(channel)), - imx_dmav1_readl(DMA_CNTR(channel))); - - return now; -} - -/** - * imx_dma_setup_single - setup i.MX DMA channel for linear memory to/from - * device transfer - * - * @channel: i.MX DMA channel number - * @dma_address: the DMA/physical memory address of the linear data block - * to transfer - * @dma_length: length of the data block in bytes - * @dev_addr: physical device port address - * @dmamode: DMA transfer mode, %DMA_MODE_READ from the device to the memory - * or %DMA_MODE_WRITE from memory to the device - * - * Return value: if incorrect parameters are provided -%EINVAL. - * Zero indicates success. - */ -int -imx_dma_setup_single(int channel, dma_addr_t dma_address, - unsigned int dma_length, unsigned int dev_addr, - unsigned int dmamode) -{ - struct imx_dma_channel *imxdma = &imx_dma_channels[channel]; - - imxdma->sg = NULL; - imxdma->dma_mode = dmamode; - - if (!dma_address) { - printk(KERN_ERR "imxdma%d: imx_dma_setup_single null address\n", - channel); - return -EINVAL; - } - - if (!dma_length) { - printk(KERN_ERR "imxdma%d: imx_dma_setup_single zero length\n", - channel); - return -EINVAL; - } - - if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) { - pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d " - "dev_addr=0x%08x for read\n", - channel, __func__, (unsigned int)dma_address, - dma_length, dev_addr); - - imx_dmav1_writel(dev_addr, DMA_SAR(channel)); - imx_dmav1_writel(dma_address, DMA_DAR(channel)); - imx_dmav1_writel(imxdma->ccr_from_device, DMA_CCR(channel)); - } else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) { - pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d " - "dev_addr=0x%08x for write\n", - channel, __func__, (unsigned int)dma_address, - dma_length, dev_addr); - - imx_dmav1_writel(dma_address, DMA_SAR(channel)); - imx_dmav1_writel(dev_addr, DMA_DAR(channel)); - imx_dmav1_writel(imxdma->ccr_to_device, - DMA_CCR(channel)); - } else { - printk(KERN_ERR "imxdma%d: imx_dma_setup_single bad dmamode\n", - channel); - return -EINVAL; - } - - imx_dmav1_writel(dma_length, DMA_CNTR(channel)); - - return 0; -} -EXPORT_SYMBOL(imx_dma_setup_single); - -/** - * imx_dma_setup_sg - setup i.MX DMA channel SG list to/from device transfer - * @channel: i.MX DMA channel number - * @sg: pointer to the scatter-gather list/vector - * @sgcount: scatter-gather list hungs count - * @dma_length: total length of the transfer request in bytes - * @dev_addr: physical device port address - * @dmamode: DMA transfer mode, %DMA_MODE_READ from the device to the memory - * or %DMA_MODE_WRITE from memory to the device - * - * The function sets up DMA channel state and registers to be ready for - * transfer specified by provided parameters. The scatter-gather emulation - * is set up according to the parameters. - * - * The full preparation of the transfer requires setup of more register - * by the caller before imx_dma_enable() can be called. - * - * %BLR(channel) holds transfer burst length in bytes, 0 means 64 bytes - * - * %RSSR(channel) has to be set to the DMA request line source %DMA_REQ_xxx - * - * %CCR(channel) has to specify transfer parameters, the next settings is - * typical for linear or simple scatter-gather transfers if %DMA_MODE_READ is - * specified - * - * %CCR_DMOD_LINEAR | %CCR_DSIZ_32 | %CCR_SMOD_FIFO | %CCR_SSIZ_x - * - * The typical setup for %DMA_MODE_WRITE is specified by next options - * combination - * - * %CCR_SMOD_LINEAR | %CCR_SSIZ_32 | %CCR_DMOD_FIFO | %CCR_DSIZ_x - * - * Be careful here and do not mistakenly mix source and target device - * port sizes constants, they are really different: - * %CCR_SSIZ_8, %CCR_SSIZ_16, %CCR_SSIZ_32, - * %CCR_DSIZ_8, %CCR_DSIZ_16, %CCR_DSIZ_32 - * - * Return value: if incorrect parameters are provided -%EINVAL. - * Zero indicates success. - */ -int -imx_dma_setup_sg(int channel, - struct scatterlist *sg, unsigned int sgcount, - unsigned int dma_length, unsigned int dev_addr, - unsigned int dmamode) -{ - struct imx_dma_channel *imxdma = &imx_dma_channels[channel]; - - if (imxdma->in_use) - return -EBUSY; - - imxdma->sg = sg; - imxdma->dma_mode = dmamode; - imxdma->resbytes = dma_length; - - if (!sg || !sgcount) { - printk(KERN_ERR "imxdma%d: imx_dma_setup_sg epty sg list\n", - channel); - return -EINVAL; - } - - if (!sg->length) { - printk(KERN_ERR "imxdma%d: imx_dma_setup_sg zero length\n", - channel); - return -EINVAL; - } - - if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) { - pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d " - "dev_addr=0x%08x for read\n", - channel, __func__, sg, sgcount, dma_length, dev_addr); - - imx_dmav1_writel(dev_addr, DMA_SAR(channel)); - imx_dmav1_writel(imxdma->ccr_from_device, DMA_CCR(channel)); - } else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) { - pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d " - "dev_addr=0x%08x for write\n", - channel, __func__, sg, sgcount, dma_length, dev_addr); - - imx_dmav1_writel(dev_addr, DMA_DAR(channel)); - imx_dmav1_writel(imxdma->ccr_to_device, DMA_CCR(channel)); - } else { - printk(KERN_ERR "imxdma%d: imx_dma_setup_sg bad dmamode\n", - channel); - return -EINVAL; - } - - imx_dma_sg_next(channel, sg); - - return 0; -} -EXPORT_SYMBOL(imx_dma_setup_sg); - -int -imx_dma_config_channel(int channel, unsigned int config_port, - unsigned int config_mem, unsigned int dmareq, int hw_chaining) -{ - struct imx_dma_channel *imxdma = &imx_dma_channels[channel]; - u32 dreq = 0; - - imxdma->hw_chaining = 0; - - if (hw_chaining) { - imxdma->hw_chaining = 1; - if (!imx_dma_hw_chain(imxdma)) - return -EINVAL; - } - - if (dmareq) - dreq = CCR_REN; - - imxdma->ccr_from_device = config_port | (config_mem << 2) | dreq; - imxdma->ccr_to_device = config_mem | (config_port << 2) | dreq; - - imx_dmav1_writel(dmareq, DMA_RSSR(channel)); - - return 0; -} -EXPORT_SYMBOL(imx_dma_config_channel); - -void imx_dma_config_burstlen(int channel, unsigned int burstlen) -{ - imx_dmav1_writel(burstlen, DMA_BLR(channel)); -} -EXPORT_SYMBOL(imx_dma_config_burstlen); - -/** - * imx_dma_setup_handlers - setup i.MX DMA channel end and error notification - * handlers - * @channel: i.MX DMA channel number - * @irq_handler: the pointer to the function called if the transfer - * ends successfully - * @err_handler: the pointer to the function called if the premature - * end caused by error occurs - * @data: user specified value to be passed to the handlers - */ -int -imx_dma_setup_handlers(int channel, - void (*irq_handler) (int, void *), - void (*err_handler) (int, void *, int), - void *data) -{ - struct imx_dma_channel *imxdma = &imx_dma_channels[channel]; - unsigned long flags; - - if (!imxdma->name) { - printk(KERN_CRIT "%s: called for not allocated channel %d\n", - __func__, channel); - return -ENODEV; - } - - local_irq_save(flags); - imx_dmav1_writel(1 << channel, DMA_DISR); - imxdma->irq_handler = irq_handler; - imxdma->err_handler = err_handler; - imxdma->data = data; - local_irq_restore(flags); - return 0; -} -EXPORT_SYMBOL(imx_dma_setup_handlers); - -/** - * imx_dma_setup_progression_handler - setup i.MX DMA channel progression - * handlers - * @channel: i.MX DMA channel number - * @prog_handler: the pointer to the function called if the transfer progresses - */ -int -imx_dma_setup_progression_handler(int channel, - void (*prog_handler) (int, void*, struct scatterlist*)) -{ - struct imx_dma_channel *imxdma = &imx_dma_channels[channel]; - unsigned long flags; - - if (!imxdma->name) { - printk(KERN_CRIT "%s: called for not allocated channel %d\n", - __func__, channel); - return -ENODEV; - } - - local_irq_save(flags); - imxdma->prog_handler = prog_handler; - local_irq_restore(flags); - return 0; -} -EXPORT_SYMBOL(imx_dma_setup_progression_handler); - -/** - * imx_dma_enable - function to start i.MX DMA channel operation - * @channel: i.MX DMA channel number - * - * The channel has to be allocated by driver through imx_dma_request() - * or imx_dma_request_by_prio() function. - * The transfer parameters has to be set to the channel registers through - * call of the imx_dma_setup_single() or imx_dma_setup_sg() function - * and registers %BLR(channel), %RSSR(channel) and %CCR(channel) has to - * be set prior this function call by the channel user. - */ -void imx_dma_enable(int channel) -{ - struct imx_dma_channel *imxdma = &imx_dma_channels[channel]; - unsigned long flags; - - pr_debug("imxdma%d: imx_dma_enable\n", channel); - - if (!imxdma->name) { - printk(KERN_CRIT "%s: called for not allocated channel %d\n", - __func__, channel); - return; - } - - if (imxdma->in_use) - return; - - local_irq_save(flags); - - imx_dmav1_writel(1 << channel, DMA_DISR); - imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) & ~(1 << channel), DMA_DIMR); - imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) | CCR_CEN | - CCR_ACRPT, DMA_CCR(channel)); - -#ifdef CONFIG_ARCH_MX2 - if ((cpu_is_mx21() || cpu_is_mx27()) && - imxdma->sg && imx_dma_hw_chain(imxdma)) { - imxdma->sg = sg_next(imxdma->sg); - if (imxdma->sg) { - u32 tmp; - imx_dma_sg_next(channel, imxdma->sg); - tmp = imx_dmav1_readl(DMA_CCR(channel)); - imx_dmav1_writel(tmp | CCR_RPT | CCR_ACRPT, - DMA_CCR(channel)); - } - } -#endif - imxdma->in_use = 1; - - local_irq_restore(flags); -} -EXPORT_SYMBOL(imx_dma_enable); - -/** - * imx_dma_disable - stop, finish i.MX DMA channel operatin - * @channel: i.MX DMA channel number - */ -void imx_dma_disable(int channel) -{ - struct imx_dma_channel *imxdma = &imx_dma_channels[channel]; - unsigned long flags; - - pr_debug("imxdma%d: imx_dma_disable\n", channel); - - if (imx_dma_hw_chain(imxdma)) - del_timer(&imxdma->watchdog); - - local_irq_save(flags); - imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) | (1 << channel), DMA_DIMR); - imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) & ~CCR_CEN, - DMA_CCR(channel)); - imx_dmav1_writel(1 << channel, DMA_DISR); - imxdma->in_use = 0; - local_irq_restore(flags); -} -EXPORT_SYMBOL(imx_dma_disable); - -#ifdef CONFIG_ARCH_MX2 -static void imx_dma_watchdog(unsigned long chno) -{ - struct imx_dma_channel *imxdma = &imx_dma_channels[chno]; - - imx_dmav1_writel(0, DMA_CCR(chno)); - imxdma->in_use = 0; - imxdma->sg = NULL; - - if (imxdma->err_handler) - imxdma->err_handler(chno, imxdma->data, IMX_DMA_ERR_TIMEOUT); -} -#endif - -static irqreturn_t dma_err_handler(int irq, void *dev_id) -{ - int i, disr; - struct imx_dma_channel *imxdma; - unsigned int err_mask; - int errcode; - - disr = imx_dmav1_readl(DMA_DISR); - - err_mask = imx_dmav1_readl(DMA_DBTOSR) | - imx_dmav1_readl(DMA_DRTOSR) | - imx_dmav1_readl(DMA_DSESR) | - imx_dmav1_readl(DMA_DBOSR); - - if (!err_mask) - return IRQ_HANDLED; - - imx_dmav1_writel(disr & err_mask, DMA_DISR); - - for (i = 0; i < IMX_DMA_CHANNELS; i++) { - if (!(err_mask & (1 << i))) - continue; - imxdma = &imx_dma_channels[i]; - errcode = 0; - - if (imx_dmav1_readl(DMA_DBTOSR) & (1 << i)) { - imx_dmav1_writel(1 << i, DMA_DBTOSR); - errcode |= IMX_DMA_ERR_BURST; - } - if (imx_dmav1_readl(DMA_DRTOSR) & (1 << i)) { - imx_dmav1_writel(1 << i, DMA_DRTOSR); - errcode |= IMX_DMA_ERR_REQUEST; - } - if (imx_dmav1_readl(DMA_DSESR) & (1 << i)) { - imx_dmav1_writel(1 << i, DMA_DSESR); - errcode |= IMX_DMA_ERR_TRANSFER; - } - if (imx_dmav1_readl(DMA_DBOSR) & (1 << i)) { - imx_dmav1_writel(1 << i, DMA_DBOSR); - errcode |= IMX_DMA_ERR_BUFFER; - } - if (imxdma->name && imxdma->err_handler) { - imxdma->err_handler(i, imxdma->data, errcode); - continue; - } - - imx_dma_channels[i].sg = NULL; - - printk(KERN_WARNING - "DMA timeout on channel %d (%s) -%s%s%s%s\n", - i, imxdma->name, - errcode & IMX_DMA_ERR_BURST ? " burst" : "", - errcode & IMX_DMA_ERR_REQUEST ? " request" : "", - errcode & IMX_DMA_ERR_TRANSFER ? " transfer" : "", - errcode & IMX_DMA_ERR_BUFFER ? " buffer" : ""); - } - return IRQ_HANDLED; -} - -static void dma_irq_handle_channel(int chno) -{ - struct imx_dma_channel *imxdma = &imx_dma_channels[chno]; - - if (!imxdma->name) { - /* - * IRQ for an unregistered DMA channel: - * let's clear the interrupts and disable it. - */ - printk(KERN_WARNING - "spurious IRQ for DMA channel %d\n", chno); - return; - } - - if (imxdma->sg) { - u32 tmp; - struct scatterlist *current_sg = imxdma->sg; - imxdma->sg = sg_next(imxdma->sg); - - if (imxdma->sg) { - imx_dma_sg_next(chno, imxdma->sg); - - tmp = imx_dmav1_readl(DMA_CCR(chno)); - - if (imx_dma_hw_chain(imxdma)) { - /* FIXME: The timeout should probably be - * configurable - */ - mod_timer(&imxdma->watchdog, - jiffies + msecs_to_jiffies(500)); - - tmp |= CCR_CEN | CCR_RPT | CCR_ACRPT; - imx_dmav1_writel(tmp, DMA_CCR(chno)); - } else { - imx_dmav1_writel(tmp & ~CCR_CEN, DMA_CCR(chno)); - tmp |= CCR_CEN; - } - - imx_dmav1_writel(tmp, DMA_CCR(chno)); - - if (imxdma->prog_handler) - imxdma->prog_handler(chno, imxdma->data, - current_sg); - - return; - } - - if (imx_dma_hw_chain(imxdma)) { - del_timer(&imxdma->watchdog); - return; - } - } - - imx_dmav1_writel(0, DMA_CCR(chno)); - imxdma->in_use = 0; - if (imxdma->irq_handler) - imxdma->irq_handler(chno, imxdma->data); -} - -static irqreturn_t dma_irq_handler(int irq, void *dev_id) -{ - int i, disr; - -#ifdef CONFIG_ARCH_MX2 - if (cpu_is_mx21() || cpu_is_mx27()) - dma_err_handler(irq, dev_id); -#endif - - disr = imx_dmav1_readl(DMA_DISR); - - pr_debug("imxdma: dma_irq_handler called, disr=0x%08x\n", - disr); - - imx_dmav1_writel(disr, DMA_DISR); - for (i = 0; i < IMX_DMA_CHANNELS; i++) { - if (disr & (1 << i)) - dma_irq_handle_channel(i); - } - - return IRQ_HANDLED; -} - -/** - * imx_dma_request - request/allocate specified channel number - * @channel: i.MX DMA channel number - * @name: the driver/caller own non-%NULL identification - */ -int imx_dma_request(int channel, const char *name) -{ - struct imx_dma_channel *imxdma = &imx_dma_channels[channel]; - unsigned long flags; - int ret = 0; - - /* basic sanity checks */ - if (!name) - return -EINVAL; - - if (channel >= IMX_DMA_CHANNELS) { - printk(KERN_CRIT "%s: called for non-existed channel %d\n", - __func__, channel); - return -EINVAL; - } - - local_irq_save(flags); - if (imxdma->name) { - local_irq_restore(flags); - return -EBUSY; - } - memset(imxdma, 0, sizeof(imxdma)); - imxdma->name = name; - local_irq_restore(flags); /* request_irq() can block */ - -#ifdef CONFIG_ARCH_MX2 - if (cpu_is_mx21() || cpu_is_mx27()) { - ret = request_irq(MX2x_INT_DMACH0 + channel, - dma_irq_handler, 0, "DMA", NULL); - if (ret) { - imxdma->name = NULL; - pr_crit("Can't register IRQ %d for DMA channel %d\n", - MX2x_INT_DMACH0 + channel, channel); - return ret; - } - init_timer(&imxdma->watchdog); - imxdma->watchdog.function = &imx_dma_watchdog; - imxdma->watchdog.data = channel; - } -#endif - - return ret; -} -EXPORT_SYMBOL(imx_dma_request); - -/** - * imx_dma_free - release previously acquired channel - * @channel: i.MX DMA channel number - */ -void imx_dma_free(int channel) -{ - unsigned long flags; - struct imx_dma_channel *imxdma = &imx_dma_channels[channel]; - - if (!imxdma->name) { - printk(KERN_CRIT - "%s: trying to free free channel %d\n", - __func__, channel); - return; - } - - local_irq_save(flags); - /* Disable interrupts */ - imx_dma_disable(channel); - imxdma->name = NULL; - -#ifdef CONFIG_ARCH_MX2 - if (cpu_is_mx21() || cpu_is_mx27()) - free_irq(MX2x_INT_DMACH0 + channel, NULL); -#endif - - local_irq_restore(flags); -} -EXPORT_SYMBOL(imx_dma_free); - -/** - * imx_dma_request_by_prio - find and request some of free channels best - * suiting requested priority - * @channel: i.MX DMA channel number - * @name: the driver/caller own non-%NULL identification - * - * This function tries to find a free channel in the specified priority group - * This function tries to find a free channel in the specified priority group - * if the priority cannot be achieved it tries to look for free channel - * in the higher and then even lower priority groups. - * - * Return value: If there is no free channel to allocate, -%ENODEV is returned. - * On successful allocation channel is returned. - */ -int imx_dma_request_by_prio(const char *name, enum imx_dma_prio prio) -{ - int i; - int best; - - switch (prio) { - case (DMA_PRIO_HIGH): - best = 8; - break; - case (DMA_PRIO_MEDIUM): - best = 4; - break; - case (DMA_PRIO_LOW): - default: - best = 0; - break; - } - - for (i = best; i < IMX_DMA_CHANNELS; i++) - if (!imx_dma_request(i, name)) - return i; - - for (i = best - 1; i >= 0; i--) - if (!imx_dma_request(i, name)) - return i; - - printk(KERN_ERR "%s: no free DMA channel found\n", __func__); - - return -ENODEV; -} -EXPORT_SYMBOL(imx_dma_request_by_prio); - -static int __init imx_dma_init(void) -{ - int ret = 0; - int i; - -#ifdef CONFIG_ARCH_MX1 - if (cpu_is_mx1()) - imx_dmav1_baseaddr = MX1_IO_ADDRESS(MX1_DMA_BASE_ADDR); - else -#endif -#ifdef CONFIG_MACH_MX21 - if (cpu_is_mx21()) - imx_dmav1_baseaddr = MX21_IO_ADDRESS(MX21_DMA_BASE_ADDR); - else -#endif -#ifdef CONFIG_MACH_MX27 - if (cpu_is_mx27()) - imx_dmav1_baseaddr = MX27_IO_ADDRESS(MX27_DMA_BASE_ADDR); - else -#endif - BUG(); - - dma_clk = clk_get(NULL, "dma"); - clk_enable(dma_clk); - - /* reset DMA module */ - imx_dmav1_writel(DCR_DRST, DMA_DCR); - -#ifdef CONFIG_ARCH_MX1 - if (cpu_is_mx1()) { - ret = request_irq(MX1_DMA_INT, dma_irq_handler, 0, "DMA", NULL); - if (ret) { - pr_crit("Wow! Can't register IRQ for DMA\n"); - return ret; - } - - ret = request_irq(MX1_DMA_ERR, dma_err_handler, 0, "DMA", NULL); - if (ret) { - pr_crit("Wow! Can't register ERRIRQ for DMA\n"); - free_irq(MX1_DMA_INT, NULL); - return ret; - } - } -#endif - /* enable DMA module */ - imx_dmav1_writel(DCR_DEN, DMA_DCR); - - /* clear all interrupts */ - imx_dmav1_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_DISR); - - /* disable interrupts */ - imx_dmav1_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_DIMR); - - for (i = 0; i < IMX_DMA_CHANNELS; i++) { - imx_dma_channels[i].sg = NULL; - imx_dma_channels[i].dma_num = i; - } - - return ret; -} - -arch_initcall(imx_dma_init); diff --git a/arch/arm/plat-mxc/ehci.c b/arch/arm/plat-mxc/ehci.c index 618479258bb..35a064ff02b 100644 --- a/arch/arm/plat-mxc/ehci.c +++ b/arch/arm/plat-mxc/ehci.c @@ -11,10 +11,6 @@ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License * for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software Foundation, - * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ #include <linux/platform_device.h> diff --git a/arch/arm/plat-mxc/include/mach/board-armadillo5x0.h b/arch/arm/plat-mxc/include/mach/board-armadillo5x0.h deleted file mode 100644 index 0376c133c9f..00000000000 --- a/arch/arm/plat-mxc/include/mach/board-armadillo5x0.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright 2009 Alberto Panizzo <maramaopercheseimorto@gmail.com>. - * All Rights Reserved. - */ - -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ASM_ARCH_MXC_BOARD_ARMADILLO5X0_H__ -#define __ASM_ARCH_MXC_BOARD_ARMADILLO5X0_H__ - -#endif diff --git a/arch/arm/plat-mxc/include/mach/board-eukrea_cpuimx27.h b/arch/arm/plat-mxc/include/mach/board-eukrea_cpuimx27.h index a1fd5830af4..45b2fb8bed6 100644 --- a/arch/arm/plat-mxc/include/mach/board-eukrea_cpuimx27.h +++ b/arch/arm/plat-mxc/include/mach/board-eukrea_cpuimx27.h @@ -25,7 +25,7 @@ #ifndef __ASSEMBLY__ /* * This CPU module needs a baseboard to work. After basic initializing - * its own devices, it calls baseboard's init function. + * its own devices, it calls the baseboard's init function. * TODO: Add your own baseboard init function and call it from * inside eukrea_cpuimx27_init(). * diff --git a/arch/arm/plat-mxc/include/mach/board-kzmarm11.h b/arch/arm/plat-mxc/include/mach/board-kzmarm11.h deleted file mode 100644 index 93cc66f104c..00000000000 --- a/arch/arm/plat-mxc/include/mach/board-kzmarm11.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright (C) 2009 Yoichi Yuasa <yuasa@linux-mips.org> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - */ -#ifndef __ARM_ARCH_BOARD_KZM_ARM11_H -#define __ARM_ARCH_BOARD_KZM_ARM11_H - -/* - * KZM-ARM11-01 Board Control Registers on FPGA - */ -#define KZM_ARM11_CTL1 (MX31_CS4_BASE_ADDR + 0x1000) -#define KZM_ARM11_CTL2 (MX31_CS4_BASE_ADDR + 0x1001) -#define KZM_ARM11_RSW1 (MX31_CS4_BASE_ADDR + 0x1002) -#define KZM_ARM11_BACK_LIGHT (MX31_CS4_BASE_ADDR + 0x1004) -#define KZM_ARM11_FPGA_REV (MX31_CS4_BASE_ADDR + 0x1008) -#define KZM_ARM11_7SEG_LED (MX31_CS4_BASE_ADDR + 0x1010) -#define KZM_ARM11_LEDS (MX31_CS4_BASE_ADDR + 0x1020) -#define KZM_ARM11_DIPSW2 (MX31_CS4_BASE_ADDR + 0x1003) - -/* - * External UART for touch panel on FPGA - */ -#define KZM_ARM11_16550 (MX31_CS4_BASE_ADDR + 0x1050) - -#endif /* __ARM_ARCH_BOARD_KZM_ARM11_H */ - diff --git a/arch/arm/plat-mxc/include/mach/board-mx21ads.h b/arch/arm/plat-mxc/include/mach/board-mx21ads.h deleted file mode 100644 index 0cf4fa29510..00000000000 --- a/arch/arm/plat-mxc/include/mach/board-mx21ads.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#ifndef __ASM_ARCH_MXC_BOARD_MX21ADS_H__ -#define __ASM_ARCH_MXC_BOARD_MX21ADS_H__ - -/* - * Memory-mapped I/O on MX21ADS base board - */ -#define MX21ADS_MMIO_BASE_ADDR 0xF5000000 -#define MX21ADS_MMIO_SIZE SZ_16M - -#define MX21ADS_REG_ADDR(offset) (void __force __iomem *) \ - (MX21ADS_MMIO_BASE_ADDR + (offset)) - -#define MX21ADS_CS8900A_IRQ IRQ_GPIOE(11) -#define MX21ADS_CS8900A_IOBASE_REG MX21ADS_REG_ADDR(0x000000) -#define MX21ADS_ST16C255_IOBASE_REG MX21ADS_REG_ADDR(0x200000) -#define MX21ADS_VERSION_REG MX21ADS_REG_ADDR(0x400000) -#define MX21ADS_IO_REG MX21ADS_REG_ADDR(0x800000) - -/* MX21ADS_IO_REG bit definitions */ -#define MX21ADS_IO_SD_WP 0x0001 /* read */ -#define MX21ADS_IO_TP6 0x0001 /* write */ -#define MX21ADS_IO_SW_SEL 0x0002 /* read */ -#define MX21ADS_IO_TP7 0x0002 /* write */ -#define MX21ADS_IO_RESET_E_UART 0x0004 -#define MX21ADS_IO_RESET_BASE 0x0008 -#define MX21ADS_IO_CSI_CTL2 0x0010 -#define MX21ADS_IO_CSI_CTL1 0x0020 -#define MX21ADS_IO_CSI_CTL0 0x0040 -#define MX21ADS_IO_UART1_EN 0x0080 -#define MX21ADS_IO_UART4_EN 0x0100 -#define MX21ADS_IO_LCDON 0x0200 -#define MX21ADS_IO_IRDA_EN 0x0400 -#define MX21ADS_IO_IRDA_FIR_SEL 0x0800 -#define MX21ADS_IO_IRDA_MD0_B 0x1000 -#define MX21ADS_IO_IRDA_MD1 0x2000 -#define MX21ADS_IO_LED4_ON 0x4000 -#define MX21ADS_IO_LED3_ON 0x8000 - -#endif /* __ASM_ARCH_MXC_BOARD_MX21ADS_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/board-mx27ads.h b/arch/arm/plat-mxc/include/mach/board-mx27ads.h deleted file mode 100644 index 7776d230327..00000000000 --- a/arch/arm/plat-mxc/include/mach/board-mx27ads.h +++ /dev/null @@ -1,344 +0,0 @@ -/* - * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#ifndef __ASM_ARCH_MXC_BOARD_MX27ADS_H__ -#define __ASM_ARCH_MXC_BOARD_MX27ADS_H__ - -/* external interrupt multiplexer */ -#define MXC_EXP_IO_BASE (MXC_BOARD_IRQ_START) - -#define MXC_VIRTUAL_INTS_BASE (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES) -#define MXC_SDIO1_CARD_IRQ MXC_VIRTUAL_INTS_BASE -#define MXC_SDIO2_CARD_IRQ (MXC_VIRTUAL_INTS_BASE + 1) -#define MXC_SDIO3_CARD_IRQ (MXC_VIRTUAL_INTS_BASE + 2) - -#define MXC_MAX_BOARD_INTS (MXC_MAX_EXP_IO_LINES + \ - MXC_MAX_VIRTUAL_INTS) - -/* - * @name Memory Size parameters - */ - -/* - * Size of SDRAM memory - */ -#define SDRAM_MEM_SIZE SZ_128M - -/* - * PBC Controller parameters - */ - -/* - * Base address of PBC controller, CS4 - */ -#define PBC_BASE_ADDRESS 0xf4300000 -#define PBC_REG_ADDR(offset) (void __force __iomem *) \ - (PBC_BASE_ADDRESS + (offset)) - -/* - * PBC Interupt name definitions - */ -#define PBC_GPIO1_0 0 -#define PBC_GPIO1_1 1 -#define PBC_GPIO1_2 2 -#define PBC_GPIO1_3 3 -#define PBC_GPIO1_4 4 -#define PBC_GPIO1_5 5 - -#define PBC_INTR_MAX_NUM 6 -#define PBC_INTR_SHARED_MAX_NUM 8 - -/* When the PBC address connection is fixed in h/w, defined as 1 */ -#define PBC_ADDR_SH 0 - -/* Offsets for the PBC Controller register */ -/* - * PBC Board version register offset - */ -#define PBC_VERSION_REG PBC_REG_ADDR(0x00000 >> PBC_ADDR_SH) -/* - * PBC Board control register 1 set address. - */ -#define PBC_BCTRL1_SET_REG PBC_REG_ADDR(0x00008 >> PBC_ADDR_SH) -/* - * PBC Board control register 1 clear address. - */ -#define PBC_BCTRL1_CLEAR_REG PBC_REG_ADDR(0x0000C >> PBC_ADDR_SH) -/* - * PBC Board control register 2 set address. - */ -#define PBC_BCTRL2_SET_REG PBC_REG_ADDR(0x00010 >> PBC_ADDR_SH) -/* - * PBC Board control register 2 clear address. - */ -#define PBC_BCTRL2_CLEAR_REG PBC_REG_ADDR(0x00014 >> PBC_ADDR_SH) -/* - * PBC Board control register 3 set address. - */ -#define PBC_BCTRL3_SET_REG PBC_REG_ADDR(0x00018 >> PBC_ADDR_SH) -/* - * PBC Board control register 3 clear address. - */ -#define PBC_BCTRL3_CLEAR_REG PBC_REG_ADDR(0x0001C >> PBC_ADDR_SH) -/* - * PBC Board control register 3 set address. - */ -#define PBC_BCTRL4_SET_REG PBC_REG_ADDR(0x00020 >> PBC_ADDR_SH) -/* - * PBC Board control register 4 clear address. - */ -#define PBC_BCTRL4_CLEAR_REG PBC_REG_ADDR(0x00024 >> PBC_ADDR_SH) -/*PBC_ADDR_SH - * PBC Board status register 1. - */ -#define PBC_BSTAT1_REG PBC_REG_ADDR(0x00028 >> PBC_ADDR_SH) -/* - * PBC Board interrupt status register. - */ -#define PBC_INTSTATUS_REG PBC_REG_ADDR(0x0002C >> PBC_ADDR_SH) -/* - * PBC Board interrupt current status register. - */ -#define PBC_INTCURR_STATUS_REG PBC_REG_ADDR(0x00034 >> PBC_ADDR_SH) -/* - * PBC Interrupt mask register set address. - */ -#define PBC_INTMASK_SET_REG PBC_REG_ADDR(0x00038 >> PBC_ADDR_SH) -/* - * PBC Interrupt mask register clear address. - */ -#define PBC_INTMASK_CLEAR_REG PBC_REG_ADDR(0x0003C >> PBC_ADDR_SH) -/* - * External UART A. - */ -#define PBC_SC16C652_UARTA_REG PBC_REG_ADDR(0x20000 >> PBC_ADDR_SH) -/* - * UART 4 Expanding Signal Status. - */ -#define PBC_UART_STATUS_REG PBC_REG_ADDR(0x22000 >> PBC_ADDR_SH) -/* - * UART 4 Expanding Signal Control Set. - */ -#define PBC_UCTRL_SET_REG PBC_REG_ADDR(0x24000 >> PBC_ADDR_SH) -/* - * UART 4 Expanding Signal Control Clear. - */ -#define PBC_UCTRL_CLR_REG PBC_REG_ADDR(0x26000 >> PBC_ADDR_SH) -/* - * Ethernet Controller IO base address. - */ -#define PBC_CS8900A_IOBASE_REG PBC_REG_ADDR(0x40000 >> PBC_ADDR_SH) -/* - * Ethernet Controller Memory base address. - */ -#define PBC_CS8900A_MEMBASE_REG PBC_REG_ADDR(0x42000 >> PBC_ADDR_SH) -/* - * Ethernet Controller DMA base address. - */ -#define PBC_CS8900A_DMABASE_REG PBC_REG_ADDR(0x44000 >> PBC_ADDR_SH) - -/* PBC Board Version Register bit definition */ -#define PBC_VERSION_ADS 0x8000 /* Bit15=1 means version for ads */ -#define PBC_VERSION_EVB_REVB 0x4000 /* BIT14=1 means version for evb revb */ - -/* PBC Board Control Register 1 bit definitions */ -#define PBC_BCTRL1_ERST 0x0001 /* Ethernet Reset */ -#define PBC_BCTRL1_URST 0x0002 /* Reset External UART controller */ -#define PBC_BCTRL1_FRST 0x0004 /* FEC Reset */ -#define PBC_BCTRL1_ESLEEP 0x0010 /* Enable ethernet Sleep */ -#define PBC_BCTRL1_LCDON 0x0800 /* Enable the LCD */ - -/* PBC Board Control Register 2 bit definitions */ -#define PBC_BCTRL2_VCC_EN 0x0004 /* Enable VCC */ -#define PBC_BCTRL2_VPP_EN 0x0008 /* Enable Vpp */ -#define PBC_BCTRL2_ATAFEC_EN 0X0010 -#define PBC_BCTRL2_ATAFEC_SEL 0X0020 -#define PBC_BCTRL2_ATA_EN 0X0040 -#define PBC_BCTRL2_IRDA_SD 0X0080 -#define PBC_BCTRL2_IRDA_EN 0X0100 -#define PBC_BCTRL2_CCTL10 0X0200 -#define PBC_BCTRL2_CCTL11 0X0400 - -/* PBC Board Control Register 3 bit definitions */ -#define PBC_BCTRL3_HSH_EN 0X0020 -#define PBC_BCTRL3_FSH_MOD 0X0040 -#define PBC_BCTRL3_OTG_HS_EN 0X0080 -#define PBC_BCTRL3_OTG_VBUS_EN 0X0100 -#define PBC_BCTRL3_FSH_VBUS_EN 0X0200 -#define PBC_BCTRL3_USB_OTG_ON 0X0800 -#define PBC_BCTRL3_USB_FSH_ON 0X1000 - -/* PBC Board Control Register 4 bit definitions */ -#define PBC_BCTRL4_REGEN_SEL 0X0001 -#define PBC_BCTRL4_USER_OFF 0X0002 -#define PBC_BCTRL4_VIB_EN 0X0004 -#define PBC_BCTRL4_PWRGT1_EN 0X0008 -#define PBC_BCTRL4_PWRGT2_EN 0X0010 -#define PBC_BCTRL4_STDBY_PRI 0X0020 - -#ifndef __ASSEMBLY__ -/* - * Enumerations for SD cards and memory stick card. This corresponds to - * the card EN bits in the IMR: SD1_EN | MS_EN | SD3_EN | SD2_EN. - */ -enum mxc_card_no { - MXC_CARD_SD2 = 0, - MXC_CARD_SD3, - MXC_CARD_MS, - MXC_CARD_SD1, - MXC_CARD_MIN = MXC_CARD_SD2, - MXC_CARD_MAX = MXC_CARD_SD1, -}; -#endif - -#define MXC_CPLD_VER_1_50 0x01 - -/* - * PBC BSTAT Register bit definitions - */ -#define PBC_BSTAT_PRI_INT 0X0001 -#define PBC_BSTAT_USB_BYP 0X0002 -#define PBC_BSTAT_ATA_IOCS16 0X0004 -#define PBC_BSTAT_ATA_CBLID 0X0008 -#define PBC_BSTAT_ATA_DASP 0X0010 -#define PBC_BSTAT_PWR_RDY 0X0020 -#define PBC_BSTAT_SD3_WP 0X0100 -#define PBC_BSTAT_SD2_WP 0X0200 -#define PBC_BSTAT_SD1_WP 0X0400 -#define PBC_BSTAT_SD3_DET 0X0800 -#define PBC_BSTAT_SD2_DET 0X1000 -#define PBC_BSTAT_SD1_DET 0X2000 -#define PBC_BSTAT_MS_DET 0X4000 -#define PBC_BSTAT_SD3_DET_BIT 11 -#define PBC_BSTAT_SD2_DET_BIT 12 -#define PBC_BSTAT_SD1_DET_BIT 13 -#define PBC_BSTAT_MS_DET_BIT 14 -#define MXC_BSTAT_BIT(n) ((n == MXC_CARD_SD2) ? PBC_BSTAT_SD2_DET : \ - ((n == MXC_CARD_SD3) ? PBC_BSTAT_SD3_DET : \ - ((n == MXC_CARD_SD1) ? PBC_BSTAT_SD1_DET : \ - ((n == MXC_CARD_MS) ? PBC_BSTAT_MS_DET : \ - 0x0)))) - -/* - * PBC UART Control Register bit definitions - */ -#define PBC_UCTRL_DCE_DCD 0X0001 -#define PBC_UCTRL_DCE_DSR 0X0002 -#define PBC_UCTRL_DCE_RI 0X0004 -#define PBC_UCTRL_DTE_DTR 0X0100 - -/* - * PBC UART Status Register bit definitions - */ -#define PBC_USTAT_DTE_DCD 0X0001 -#define PBC_USTAT_DTE_DSR 0X0002 -#define PBC_USTAT_DTE_RI 0X0004 -#define PBC_USTAT_DCE_DTR 0X0100 - -/* - * PBC Interupt mask register bit definitions - */ -#define PBC_INTR_SD3_R_EN_BIT 4 -#define PBC_INTR_SD2_R_EN_BIT 0 -#define PBC_INTR_SD1_R_EN_BIT 6 -#define PBC_INTR_MS_R_EN_BIT 5 -#define PBC_INTR_SD3_EN_BIT 13 -#define PBC_INTR_SD2_EN_BIT 12 -#define PBC_INTR_MS_EN_BIT 14 -#define PBC_INTR_SD1_EN_BIT 15 - -#define PBC_INTR_SD2_R_EN 0x0001 -#define PBC_INTR_LOW_BAT 0X0002 -#define PBC_INTR_OTG_FSOVER 0X0004 -#define PBC_INTR_FSH_OVER 0X0008 -#define PBC_INTR_SD3_R_EN 0x0010 -#define PBC_INTR_MS_R_EN 0x0020 -#define PBC_INTR_SD1_R_EN 0x0040 -#define PBC_INTR_FEC_INT 0X0080 -#define PBC_INTR_ENET_INT 0X0100 -#define PBC_INTR_OTGFS_INT 0X0200 -#define PBC_INTR_XUART_INT 0X0400 -#define PBC_INTR_CCTL12 0X0800 -#define PBC_INTR_SD2_EN 0x1000 -#define PBC_INTR_SD3_EN 0x2000 -#define PBC_INTR_MS_EN 0x4000 -#define PBC_INTR_SD1_EN 0x8000 - - - -/* For interrupts like xuart, enet etc */ -#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX27_PIN_TIN) -#define MXC_MAX_EXP_IO_LINES 16 - -/* - * This corresponds to PBC_INTMASK_SET_REG at offset 0x38. - * - */ -#define EXPIO_INT_LOW_BAT (MXC_EXP_IO_BASE + 1) -#define EXPIO_INT_OTG_FS_OVR (MXC_EXP_IO_BASE + 2) -#define EXPIO_INT_FSH_OVR (MXC_EXP_IO_BASE + 3) -#define EXPIO_INT_RES4 (MXC_EXP_IO_BASE + 4) -#define EXPIO_INT_RES5 (MXC_EXP_IO_BASE + 5) -#define EXPIO_INT_RES6 (MXC_EXP_IO_BASE + 6) -#define EXPIO_INT_FEC (MXC_EXP_IO_BASE + 7) -#define EXPIO_INT_ENET_INT (MXC_EXP_IO_BASE + 8) -#define EXPIO_INT_OTG_FS_INT (MXC_EXP_IO_BASE + 9) -#define EXPIO_INT_XUART_INTA (MXC_EXP_IO_BASE + 10) -#define EXPIO_INT_CCTL12_INT (MXC_EXP_IO_BASE + 11) -#define EXPIO_INT_SD2_EN (MXC_EXP_IO_BASE + 12) -#define EXPIO_INT_SD3_EN (MXC_EXP_IO_BASE + 13) -#define EXPIO_INT_MS_EN (MXC_EXP_IO_BASE + 14) -#define EXPIO_INT_SD1_EN (MXC_EXP_IO_BASE + 15) - -/* - * This is System IRQ used by CS8900A for interrupt generation - * taken from platform.h - */ -#define CS8900AIRQ EXPIO_INT_ENET_INT -/* This is I/O Base address used to access registers of CS8900A on MXC ADS */ -#define CS8900A_BASE_ADDRESS (PBC_CS8900A_IOBASE_REG + 0x300) - -#define MXC_PMIC_INT_LINE IOMUX_TO_IRQ(MX27_PIN_TOUT) - -/* -* This is used to detect if the CPLD version is for mx27 evb board rev-a -*/ -#define PBC_CPLD_VERSION_IS_REVA() \ - ((__raw_readw(PBC_VERSION_REG) & \ - (PBC_VERSION_ADS | PBC_VERSION_EVB_REVB))\ - == 0) - -/* This is used to active or inactive ata signal in CPLD . - * It is dependent with hardware - */ -#define PBC_ATA_SIGNAL_ACTIVE() \ - __raw_writew( \ - PBC_BCTRL2_ATAFEC_EN|PBC_BCTRL2_ATAFEC_SEL|PBC_BCTRL2_ATA_EN, \ - PBC_BCTRL2_CLEAR_REG) - -#define PBC_ATA_SIGNAL_INACTIVE() \ - __raw_writew( \ - PBC_BCTRL2_ATAFEC_EN|PBC_BCTRL2_ATAFEC_SEL|PBC_BCTRL2_ATA_EN, \ - PBC_BCTRL2_SET_REG) - -#define MXC_BD_LED1 (1 << 5) -#define MXC_BD_LED2 (1 << 6) -#define MXC_BD_LED_ON(led) \ - __raw_writew(led, PBC_BCTRL1_SET_REG) -#define MXC_BD_LED_OFF(led) \ - __raw_writew(led, PBC_BCTRL1_CLEAR_REG) - -/* to determine the correct external crystal reference */ -#define CKIH_27MHZ_BIT_SET (1 << 3) - -#endif /* __ASM_ARCH_MXC_BOARD_MX27ADS_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/board-mx27lite.h b/arch/arm/plat-mxc/include/mach/board-mx27lite.h deleted file mode 100644 index ea87551d273..00000000000 --- a/arch/arm/plat-mxc/include/mach/board-mx27lite.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved. - */ - -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ASM_ARCH_MXC_BOARD_MX27LITE_H__ -#define __ASM_ARCH_MXC_BOARD_MX27LITE_H__ - -#endif /* __ASM_ARCH_MXC_BOARD_MX27LITE_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/board-mx27pdk.h b/arch/arm/plat-mxc/include/mach/board-mx27pdk.h deleted file mode 100644 index fec1bcfa916..00000000000 --- a/arch/arm/plat-mxc/include/mach/board-mx27pdk.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved. - */ - -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ASM_ARCH_MXC_BOARD_MX27PDK_H__ -#define __ASM_ARCH_MXC_BOARD_MX27PDK_H__ - -#endif /* __ASM_ARCH_MXC_BOARD_MX27PDK_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/board-mx31_3ds.h b/arch/arm/plat-mxc/include/mach/board-mx31_3ds.h deleted file mode 100644 index da92933a233..00000000000 --- a/arch/arm/plat-mxc/include/mach/board-mx31_3ds.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - */ - -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ASM_ARCH_MXC_BOARD_MX31_3DS_H__ -#define __ASM_ARCH_MXC_BOARD_MX31_3DS_H__ - -/* Definitions for components on the Debug board */ - -/* Base address of CPLD controller on the Debug board */ -#define DEBUG_BASE_ADDRESS CS5_IO_ADDRESS(CS5_BASE_ADDR) - -/* LAN9217 ethernet base address */ -#define LAN9217_BASE_ADDR CS5_BASE_ADDR - -/* CPLD config and interrupt base address */ -#define CPLD_ADDR (DEBUG_BASE_ADDRESS + 0x20000) - -/* LED switchs */ -#define CPLD_LED_REG (CPLD_ADDR + 0x00) -/* buttons */ -#define CPLD_SWITCH_BUTTONS_REG (EXPIO_ADDR + 0x08) -/* status, interrupt */ -#define CPLD_INT_STATUS_REG (CPLD_ADDR + 0x10) -#define CPLD_INT_MASK_REG (CPLD_ADDR + 0x38) -#define CPLD_INT_RESET_REG (CPLD_ADDR + 0x20) -/* magic word for debug CPLD */ -#define CPLD_MAGIC_NUMBER1_REG (CPLD_ADDR + 0x40) -#define CPLD_MAGIC_NUMBER2_REG (CPLD_ADDR + 0x48) -/* CPLD code version */ -#define CPLD_CODE_VER_REG (CPLD_ADDR + 0x50) -/* magic word for debug CPLD */ -#define CPLD_MAGIC_NUMBER3_REG (CPLD_ADDR + 0x58) -/* module reset register */ -#define CPLD_MODULE_RESET_REG (CPLD_ADDR + 0x60) -/* CPU ID and Personality ID */ -#define CPLD_MCU_BOARD_ID_REG (CPLD_ADDR + 0x68) - -/* CPLD IRQ line for external uart, external ethernet etc */ -#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_1) - -#define MXC_EXP_IO_BASE (MXC_BOARD_IRQ_START) -#define MXC_IRQ_TO_EXPIO(irq) ((irq) - MXC_EXP_IO_BASE) - -#define EXPIO_INT_ENET (MXC_EXP_IO_BASE + 0) -#define EXPIO_INT_XUART_A (MXC_EXP_IO_BASE + 1) -#define EXPIO_INT_XUART_B (MXC_EXP_IO_BASE + 2) -#define EXPIO_INT_BUTTON_A (MXC_EXP_IO_BASE + 3) -#define EXPIO_INT_BUTTON_B (MXC_EXP_IO_BASE + 4) - -#define MXC_MAX_EXP_IO_LINES 16 - -#endif /* __ASM_ARCH_MXC_BOARD_MX31_3DS_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/board-mx31ads.h b/arch/arm/plat-mxc/include/mach/board-mx31ads.h deleted file mode 100644 index 095a199591c..00000000000 --- a/arch/arm/plat-mxc/include/mach/board-mx31ads.h +++ /dev/null @@ -1,117 +0,0 @@ -/* - * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. - */ - -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ASM_ARCH_MXC_BOARD_MX31ADS_H__ -#define __ASM_ARCH_MXC_BOARD_MX31ADS_H__ - -#include <mach/hardware.h> - -/* Base address of PBC controller */ -#define PBC_BASE_ADDRESS MX31_CS4_BASE_ADDR_VIRT -/* Offsets for the PBC Controller register */ - -/* PBC Board status register offset */ -#define PBC_BSTAT 0x000002 - -/* PBC Board control register 1 set address */ -#define PBC_BCTRL1_SET 0x000004 - -/* PBC Board control register 1 clear address */ -#define PBC_BCTRL1_CLEAR 0x000006 - -/* PBC Board control register 2 set address */ -#define PBC_BCTRL2_SET 0x000008 - -/* PBC Board control register 2 clear address */ -#define PBC_BCTRL2_CLEAR 0x00000A - -/* PBC Board control register 3 set address */ -#define PBC_BCTRL3_SET 0x00000C - -/* PBC Board control register 3 clear address */ -#define PBC_BCTRL3_CLEAR 0x00000E - -/* PBC Board control register 4 set address */ -#define PBC_BCTRL4_SET 0x000010 - -/* PBC Board control register 4 clear address */ -#define PBC_BCTRL4_CLEAR 0x000012 - -/* PBC Board status register 1 */ -#define PBC_BSTAT1 0x000014 - -/* PBC Board interrupt status register */ -#define PBC_INTSTATUS 0x000016 - -/* PBC Board interrupt current status register */ -#define PBC_INTCURR_STATUS 0x000018 - -/* PBC Interrupt mask register set address */ -#define PBC_INTMASK_SET 0x00001A - -/* PBC Interrupt mask register clear address */ -#define PBC_INTMASK_CLEAR 0x00001C - -/* External UART A */ -#define PBC_SC16C652_UARTA 0x010000 - -/* External UART B */ -#define PBC_SC16C652_UARTB 0x010010 - -/* Ethernet Controller IO base address */ -#define PBC_CS8900A_IOBASE 0x020000 - -/* Ethernet Controller Memory base address */ -#define PBC_CS8900A_MEMBASE 0x021000 - -/* Ethernet Controller DMA base address */ -#define PBC_CS8900A_DMABASE 0x022000 - -/* External chip select 0 */ -#define PBC_XCS0 0x040000 - -/* LCD Display enable */ -#define PBC_LCD_EN_B 0x060000 - -/* Code test debug enable */ -#define PBC_CODE_B 0x070000 - -/* PSRAM memory select */ -#define PBC_PSRAM_B 0x5000000 - -#define PBC_INTSTATUS_REG (PBC_INTSTATUS + PBC_BASE_ADDRESS) -#define PBC_INTCURR_STATUS_REG (PBC_INTCURR_STATUS + PBC_BASE_ADDRESS) -#define PBC_INTMASK_SET_REG (PBC_INTMASK_SET + PBC_BASE_ADDRESS) -#define PBC_INTMASK_CLEAR_REG (PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS) -#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_4) - -#define MXC_EXP_IO_BASE (MXC_BOARD_IRQ_START) -#define MXC_IRQ_TO_EXPIO(irq) ((irq) - MXC_EXP_IO_BASE) - -#define EXPIO_INT_LOW_BAT (MXC_EXP_IO_BASE + 0) -#define EXPIO_INT_PB_IRQ (MXC_EXP_IO_BASE + 1) -#define EXPIO_INT_OTG_FS_OVR (MXC_EXP_IO_BASE + 2) -#define EXPIO_INT_FSH_OVR (MXC_EXP_IO_BASE + 3) -#define EXPIO_INT_RES4 (MXC_EXP_IO_BASE + 4) -#define EXPIO_INT_RES5 (MXC_EXP_IO_BASE + 5) -#define EXPIO_INT_RES6 (MXC_EXP_IO_BASE + 6) -#define EXPIO_INT_RES7 (MXC_EXP_IO_BASE + 7) -#define EXPIO_INT_ENET_INT (MXC_EXP_IO_BASE + 8) -#define EXPIO_INT_OTG_FS_INT (MXC_EXP_IO_BASE + 9) -#define EXPIO_INT_XUART_INTA (MXC_EXP_IO_BASE + 10) -#define EXPIO_INT_XUART_INTB (MXC_EXP_IO_BASE + 11) -#define EXPIO_INT_SYNTH_IRQ (MXC_EXP_IO_BASE + 12) -#define EXPIO_INT_CE_INT1 (MXC_EXP_IO_BASE + 13) -#define EXPIO_INT_CE_INT2 (MXC_EXP_IO_BASE + 14) -#define EXPIO_INT_RES15 (MXC_EXP_IO_BASE + 15) - -#define MXC_MAX_EXP_IO_LINES 16 - -#endif /* __ASM_ARCH_MXC_BOARD_MX31ADS_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/board-mx31lilly.h b/arch/arm/plat-mxc/include/mach/board-mx31lilly.h index eb5a5024622..0df71bfefbb 100644 --- a/arch/arm/plat-mxc/include/mach/board-mx31lilly.h +++ b/arch/arm/plat-mxc/include/mach/board-mx31lilly.h @@ -31,7 +31,7 @@ enum mx31lilly_boards { /* * This CPU module needs a baseboard to work. After basic initializing - * its own devices, it calls baseboard's init function. + * its own devices, it calls the baseboard's init function. */ extern void mx31lilly_db_init(void); diff --git a/arch/arm/plat-mxc/include/mach/board-mx31lite.h b/arch/arm/plat-mxc/include/mach/board-mx31lite.h index 2b2da036757..c1ad0ae807c 100644 --- a/arch/arm/plat-mxc/include/mach/board-mx31lite.h +++ b/arch/arm/plat-mxc/include/mach/board-mx31lite.h @@ -32,7 +32,7 @@ enum mx31lite_boards { /* * This CPU module needs a baseboard to work. After basic initializing - * its own devices, it calls baseboard's init function. + * its own devices, it calls the baseboard's init function. */ extern void mx31lite_db_init(void); diff --git a/arch/arm/plat-mxc/include/mach/board-mx31moboard.h b/arch/arm/plat-mxc/include/mach/board-mx31moboard.h index 36ff3cedee1..de14543891c 100644 --- a/arch/arm/plat-mxc/include/mach/board-mx31moboard.h +++ b/arch/arm/plat-mxc/include/mach/board-mx31moboard.h @@ -31,7 +31,7 @@ enum mx31moboard_boards { /* * This CPU module needs a baseboard to work. After basic initializing - * its own devices, it calls baseboard's init function. + * its own devices, it calls the baseboard's init function. */ extern void mx31moboard_devboard_init(void); diff --git a/arch/arm/plat-mxc/include/mach/board-mx35pdk.h b/arch/arm/plat-mxc/include/mach/board-mx35pdk.h deleted file mode 100644 index 383f1c04df0..00000000000 --- a/arch/arm/plat-mxc/include/mach/board-mx35pdk.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#ifndef __ASM_ARCH_MXC_BOARD_MX35PDK_H__ -#define __ASM_ARCH_MXC_BOARD_MX35PDK_H__ - -#endif /* __ASM_ARCH_MXC_BOARD_MX35PDK_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/board-pcm037.h b/arch/arm/plat-mxc/include/mach/board-pcm037.h deleted file mode 100644 index 13411709b13..00000000000 --- a/arch/arm/plat-mxc/include/mach/board-pcm037.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Copyright (C) 2008 Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#ifndef __ASM_ARCH_MXC_BOARD_PCM037_H__ -#define __ASM_ARCH_MXC_BOARD_PCM037_H__ - -#endif /* __ASM_ARCH_MXC_BOARD_PCM037_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/board-pcm038.h b/arch/arm/plat-mxc/include/mach/board-pcm038.h index 410f9786ed2..6f371e35753 100644 --- a/arch/arm/plat-mxc/include/mach/board-pcm038.h +++ b/arch/arm/plat-mxc/include/mach/board-pcm038.h @@ -22,7 +22,7 @@ #ifndef __ASSEMBLY__ /* * This CPU module needs a baseboard to work. After basic initializing - * its own devices, it calls baseboard's init function. + * its own devices, it calls the baseboard's init function. * TODO: Add your own baseboard init function and call it from * inside pcm038_init(). * diff --git a/arch/arm/plat-mxc/include/mach/board-pcm043.h b/arch/arm/plat-mxc/include/mach/board-pcm043.h deleted file mode 100644 index 1ac4e1682e5..00000000000 --- a/arch/arm/plat-mxc/include/mach/board-pcm043.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Copyright (C) 2008 Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#ifndef __ASM_ARCH_MXC_BOARD_PCM043_H__ -#define __ASM_ARCH_MXC_BOARD_PCM043_H__ - -#endif /* __ASM_ARCH_MXC_BOARD_PCM043_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/board-qong.h b/arch/arm/plat-mxc/include/mach/board-qong.h deleted file mode 100644 index 6d88c7af4b2..00000000000 --- a/arch/arm/plat-mxc/include/mach/board-qong.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - * Copyright 2009 Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com> - */ - -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ASM_ARCH_MXC_BOARD_QONG_H__ -#define __ASM_ARCH_MXC_BOARD_QONG_H__ - -/* NOR FLASH */ -#define QONG_NOR_SIZE (128*1024*1024) - -#endif /* __ASM_ARCH_MXC_BOARD_QONG_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h new file mode 100644 index 00000000000..05c8d3f0a08 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/devices-common.h @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2009-2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <linux/kernel.h> +#include <linux/platform_device.h> +#include <linux/init.h> + +struct platform_device *imx_add_platform_device(const char *name, int id, + const struct resource *res, unsigned int num_resources, + const void *data, size_t size_data); + +#include <mach/i2c.h> +struct platform_device *__init imx_add_imx_i2c(int id, + resource_size_t iobase, resource_size_t iosize, int irq, + const struct imxi2c_platform_data *pdata); + +#include <mach/imx-uart.h> +struct platform_device *__init imx_add_imx_uart_3irq(int id, + resource_size_t iobase, resource_size_t iosize, + resource_size_t irqrx, resource_size_t irqtx, + resource_size_t irqrts, + const struct imxuart_platform_data *pdata); +struct platform_device *__init imx_add_imx_uart_1irq(int id, + resource_size_t iobase, resource_size_t iosize, + resource_size_t irq, + const struct imxuart_platform_data *pdata); + +#include <mach/mxc_nand.h> +struct platform_device *__init imx_add_mxc_nand_v1(resource_size_t iobase, + int irq, const struct mxc_nand_platform_data *pdata); +struct platform_device *__init imx_add_mxc_nand_v21(resource_size_t iobase, + int irq, const struct mxc_nand_platform_data *pdata); + +#include <mach/spi.h> +struct platform_device *__init imx_add_spi_imx(int id, + resource_size_t iobase, resource_size_t iosize, int irq, + const struct spi_imx_master *pdata); diff --git a/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h b/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h deleted file mode 100644 index 7c4870bd5a2..00000000000 --- a/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h +++ /dev/null @@ -1,105 +0,0 @@ -/* - * linux/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h - * - * i.MX DMA registration and IRQ dispatching - * - * Copyright 2006 Pavel Pisa <pisa@cmp.felk.cvut.cz> - * Copyright 2008 Juergen Beisert, <kernel@pengutronix.de> - * Copyright 2008 Sascha Hauer, <s.hauer@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#ifndef __ASM_ARCH_MXC_DMA_H -#define __ASM_ARCH_MXC_DMA_H - -#define IMX_DMA_CHANNELS 16 - -#define DMA_MODE_READ 0 -#define DMA_MODE_WRITE 1 -#define DMA_MODE_MASK 1 - -#define MX1_DMA_REG(offset) MX1_IO_ADDRESS(MX1_DMA_BASE_ADDR + (offset)) - -/* DMA Interrupt Mask Register */ -#define MX1_DMA_DIMR MX1_DMA_REG(0x08) - -/* Channel Control Register */ -#define MX1_DMA_CCR(x) MX1_DMA_REG(0x8c + ((x) << 6)) - -#define IMX_DMA_MEMSIZE_32 (0 << 4) -#define IMX_DMA_MEMSIZE_8 (1 << 4) -#define IMX_DMA_MEMSIZE_16 (2 << 4) -#define IMX_DMA_TYPE_LINEAR (0 << 10) -#define IMX_DMA_TYPE_2D (1 << 10) -#define IMX_DMA_TYPE_FIFO (2 << 10) - -#define IMX_DMA_ERR_BURST (1 << 0) -#define IMX_DMA_ERR_REQUEST (1 << 1) -#define IMX_DMA_ERR_TRANSFER (1 << 2) -#define IMX_DMA_ERR_BUFFER (1 << 3) -#define IMX_DMA_ERR_TIMEOUT (1 << 4) - -int -imx_dma_config_channel(int channel, unsigned int config_port, - unsigned int config_mem, unsigned int dmareq, int hw_chaining); - -void -imx_dma_config_burstlen(int channel, unsigned int burstlen); - -int -imx_dma_setup_single(int channel, dma_addr_t dma_address, - unsigned int dma_length, unsigned int dev_addr, - unsigned int dmamode); - - -/* - * Use this flag as the dma_length argument to imx_dma_setup_sg() - * to create an endless running dma loop. The end of the scatterlist - * must be linked to the beginning for this to work. - */ -#define IMX_DMA_LENGTH_LOOP ((unsigned int)-1) - -int -imx_dma_setup_sg(int channel, struct scatterlist *sg, - unsigned int sgcount, unsigned int dma_length, - unsigned int dev_addr, unsigned int dmamode); - -int -imx_dma_setup_handlers(int channel, - void (*irq_handler) (int, void *), - void (*err_handler) (int, void *, int), void *data); - -int -imx_dma_setup_progression_handler(int channel, - void (*prog_handler) (int, void*, struct scatterlist*)); - -void imx_dma_enable(int channel); - -void imx_dma_disable(int channel); - -int imx_dma_request(int channel, const char *name); - -void imx_dma_free(int channel); - -enum imx_dma_prio { - DMA_PRIO_HIGH = 0, - DMA_PRIO_MEDIUM = 1, - DMA_PRIO_LOW = 2 -}; - -int imx_dma_request_by_prio(const char *name, enum imx_dma_prio prio); - -#endif /* _ASM_ARCH_MXC_DMA_H */ diff --git a/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h b/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h index 3887f3fe29d..15d59510f59 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h @@ -12,10 +12,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #ifndef __MACH_IOMUX_MXC91231_H__ diff --git a/arch/arm/plat-mxc/include/mach/mx1.h b/arch/arm/plat-mxc/include/mach/mx1.h index 5eba7e6785d..641b2461823 100644 --- a/arch/arm/plat-mxc/include/mach/mx1.h +++ b/arch/arm/plat-mxc/include/mach/mx1.h @@ -91,24 +91,24 @@ #define MX1_SIM_DATA_INT 16 #define MX1_RTC_INT 17 #define MX1_RTC_SAMINT 18 -#define MX1_UART2_MINT_PFERR 19 -#define MX1_UART2_MINT_RTS 20 -#define MX1_UART2_MINT_DTR 21 -#define MX1_UART2_MINT_UARTC 22 -#define MX1_UART2_MINT_TX 23 -#define MX1_UART2_MINT_RX 24 -#define MX1_UART1_MINT_PFERR 25 -#define MX1_UART1_MINT_RTS 26 -#define MX1_UART1_MINT_DTR 27 -#define MX1_UART1_MINT_UARTC 28 -#define MX1_UART1_MINT_TX 29 -#define MX1_UART1_MINT_RX 30 +#define MX1_INT_UART2PFERR 19 +#define MX1_INT_UART2RTS 20 +#define MX1_INT_UART2DTR 21 +#define MX1_INT_UART2UARTC 22 +#define MX1_INT_UART2TX 23 +#define MX1_INT_UART2RX 24 +#define MX1_INT_UART1PFERR 25 +#define MX1_INT_UART1RTS 26 +#define MX1_INT_UART1DTR 27 +#define MX1_INT_UART1UARTC 28 +#define MX1_INT_UART1TX 29 +#define MX1_INT_UART1RX 30 #define MX1_VOICE_DAC_INT 31 #define MX1_VOICE_ADC_INT 32 #define MX1_PEN_DATA_INT 33 #define MX1_PWM_INT 34 #define MX1_SDHC_INT 35 -#define MX1_I2C_INT 39 +#define MX1_INT_I2C 39 #define MX1_CSPI_INT 41 #define MX1_SSI_TX_INT 42 #define MX1_SSI_TX_ERR_INT 43 @@ -245,7 +245,7 @@ #define PEN_DATA_INT MX1_PEN_DATA_INT #define PWM_INT MX1_PWM_INT #define SDHC_INT MX1_SDHC_INT -#define I2C_INT MX1_I2C_INT +#define I2C_INT MX1_INT_I2C #define CSPI_INT MX1_CSPI_INT #define SSI_TX_INT MX1_SSI_TX_INT #define SSI_TX_ERR_INT MX1_SSI_TX_ERR_INT diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h index 7516f2949af..2f2aad1032c 100644 --- a/arch/arm/plat-mxc/include/mach/mx25.h +++ b/arch/arm/plat-mxc/include/mach/mx25.h @@ -11,6 +11,10 @@ #define MX25_AVIC_BASE_ADDR_VIRT 0xfc400000 #define MX25_AVIC_SIZE SZ_1M +#define MX25_I2C1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x80000) +#define MX25_I2C3_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x84000) +#define MX25_I2C2_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x98000) +#define MX25_CSPI1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xa4000) #define MX25_IOMUXC_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xac000) #define MX25_CRM_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x80000) @@ -30,7 +34,12 @@ #define MX25_UART1_BASE_ADDR 0x43f90000 #define MX25_UART2_BASE_ADDR 0x43f94000 #define MX25_AUDMUX_BASE_ADDR 0x43fb0000 +#define MX25_UART3_BASE_ADDR 0x5000c000 +#define MX25_UART4_BASE_ADDR 0x50008000 +#define MX25_UART5_BASE_ADDR 0x5002c000 +#define MX25_CSPI3_BASE_ADDR 0x50004000 +#define MX25_CSPI2_BASE_ADDR 0x50010000 #define MX25_FEC_BASE_ADDR 0x50038000 #define MX25_SSI2_BASE_ADDR 0x50014000 #define MX25_SSI1_BASE_ADDR 0x50034000 @@ -41,14 +50,25 @@ #define MX25_OTG_BASE_ADDR 0x53ff4000 #define MX25_CSI_BASE_ADDR 0x53ff8000 -#define MX25_INT_SSI2 11 -#define MX25_INT_SSI1 12 -#define MX25_INT_CSI 17 -#define MX25_INT_DRYICE 25 -#define MX25_INT_NANDFC 33 -#define MX25_INT_LCDC 39 -#define MX25_INT_KPP 24 -#define MX25_INT_FEC 57 +#define MX25_INT_CSPI3 0 +#define MX25_INT_I2C1 3 +#define MX25_INT_I2C2 4 +#define MX25_INT_UART4 5 +#define MX25_INT_I2C3 10 +#define MX25_INT_SSI2 11 +#define MX25_INT_SSI1 12 +#define MX25_INT_CSPI2 13 +#define MX25_INT_CSPI1 14 +#define MX25_INT_CSI 17 +#define MX25_INT_UART3 18 +#define MX25_INT_KPP 24 +#define MX25_INT_DRYICE 25 +#define MX25_INT_UART2 32 +#define MX25_INT_NANDFC 33 +#define MX25_INT_LCDC 39 +#define MX25_INT_UART5 40 +#define MX25_INT_UART1 45 +#define MX25_INT_FEC 57 #if defined(IMX_NEEDS_DEPRECATED_SYMBOLS) #define UART1_BASE_ADDR MX25_UART1_BASE_ADDR diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h index bae9cd75bee..a8ab2e02a8c 100644 --- a/arch/arm/plat-mxc/include/mach/mx27.h +++ b/arch/arm/plat-mxc/include/mach/mx27.h @@ -48,7 +48,7 @@ #define MX27_CSPI2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0f000) #define MX27_SSI1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x10000) #define MX27_SSI2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x11000) -#define MX27_I2C_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x12000) +#define MX27_I2C1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x12000) #define MX27_SDHC1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x13000) #define MX27_SDHC2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x14000) #define MX27_GPIO_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x15000) @@ -150,7 +150,7 @@ static inline void mx27_setup_weimcs(size_t cs, #define MX27_INT_SDHC3 9 #define MX27_INT_SDHC2 10 #define MX27_INT_SDHC1 11 -#define MX27_INT_I2C 12 +#define MX27_INT_I2C1 12 #define MX27_INT_SSI2 13 #define MX27_INT_SSI1 14 #define MX27_INT_CSPI2 15 diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h index fb90e119c2b..afee3ab9d62 100644 --- a/arch/arm/plat-mxc/include/mach/mx31.h +++ b/arch/arm/plat-mxc/include/mach/mx31.h @@ -23,7 +23,7 @@ #define MX31_ETB_SLOT4_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x10000) #define MX31_ETB_SLOT5_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x14000) #define MX31_ECT_CTIO_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x18000) -#define MX31_I2C_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x80000) +#define MX31_I2C1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x80000) #define MX31_I2C3_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x84000) #define MX31_OTG_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x88000) #define MX31_ATA_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x8c000) @@ -145,7 +145,7 @@ static inline void mx31_setup_weimcs(size_t cs, #define MX31_INT_FIRI 7 #define MX31_INT_MMC_SDHC2 8 #define MX31_INT_MMC_SDHC1 9 -#define MX31_INT_I2C 10 +#define MX31_INT_I2C1 10 #define MX31_INT_SSI2 11 #define MX31_INT_SSI1 12 #define MX31_INT_CSPI2 13 diff --git a/arch/arm/plat-mxc/include/mach/mx35.h b/arch/arm/plat-mxc/include/mach/mx35.h index 526a55842ae..cda60c71512 100644 --- a/arch/arm/plat-mxc/include/mach/mx35.h +++ b/arch/arm/plat-mxc/include/mach/mx35.h @@ -18,7 +18,7 @@ #define MX35_ETB_SLOT4_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x10000) #define MX35_ETB_SLOT5_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x14000) #define MX35_ECT_CTIO_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x18000) -#define MX35_I2C_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x80000) +#define MX35_I2C1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x80000) #define MX35_I2C3_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x84000) #define MX35_UART1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x90000) #define MX35_UART2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x94000) @@ -123,7 +123,7 @@ #define MX35_INT_MMC_SDHC1 7 #define MX35_INT_MMC_SDHC2 8 #define MX35_INT_MMC_SDHC3 9 -#define MX35_INT_I2C 10 +#define MX35_INT_I2C1 10 #define MX35_INT_SSI1 11 #define MX35_INT_SSI2 12 #define MX35_INT_CSPI2 13 diff --git a/arch/arm/plat-mxc/include/mach/mx3_camera.h b/arch/arm/plat-mxc/include/mach/mx3_camera.h index 36d7ff27b5e..f226ee3777e 100644 --- a/arch/arm/plat-mxc/include/mach/mx3_camera.h +++ b/arch/arm/plat-mxc/include/mach/mx3_camera.h @@ -12,10 +12,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ #ifndef _MX3_CAMERA_H_ diff --git a/arch/arm/plat-mxc/include/mach/mxc91231.h b/arch/arm/plat-mxc/include/mach/mxc91231.h index 5182b986b78..0ca3101ebf3 100644 --- a/arch/arm/plat-mxc/include/mach/mxc91231.h +++ b/arch/arm/plat-mxc/include/mach/mxc91231.h @@ -13,10 +13,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #ifndef __MACH_MXC91231_H__ #define __MACH_MXC91231_H__ diff --git a/arch/arm/plat-mxc/include/mach/mxc_nand.h b/arch/arm/plat-mxc/include/mach/mxc_nand.h index 2d74748c5db..04c0d060d81 100644 --- a/arch/arm/plat-mxc/include/mach/mxc_nand.h +++ b/arch/arm/plat-mxc/include/mach/mxc_nand.h @@ -23,9 +23,9 @@ #include <linux/mtd/partitions.h> struct mxc_nand_platform_data { - int width; /* data bus width in bytes */ - int hw_ecc:1; /* 0 if supress hardware ECC */ - int flash_bbt:1; /* set to 1 to use a flash based bbt */ + unsigned int width; /* data bus width in bytes */ + unsigned int hw_ecc:1; /* 0 if supress hardware ECC */ + unsigned int flash_bbt:1; /* set to 1 to use a flash based bbt */ struct mtd_partition *parts; /* partition table */ int nr_parts; /* size of parts */ }; diff --git a/arch/arm/plat-mxc/include/mach/system.h b/arch/arm/plat-mxc/include/mach/system.h index ef00199568d..4acd1143a9b 100644 --- a/arch/arm/plat-mxc/include/mach/system.h +++ b/arch/arm/plat-mxc/include/mach/system.h @@ -12,10 +12,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #ifndef __ASM_ARCH_MXC_SYSTEM_H__ diff --git a/arch/arm/plat-mxc/include/mach/timex.h b/arch/arm/plat-mxc/include/mach/timex.h index 024416ed11c..2d9624697cc 100644 --- a/arch/arm/plat-mxc/include/mach/timex.h +++ b/arch/arm/plat-mxc/include/mach/timex.h @@ -11,10 +11,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #ifndef __ASM_ARCH_MXC_TIMEX_H__ diff --git a/arch/arm/plat-mxc/include/mach/uncompress.h b/arch/arm/plat-mxc/include/mach/uncompress.h index b6d3d0fddc4..d9bd37e4667 100644 --- a/arch/arm/plat-mxc/include/mach/uncompress.h +++ b/arch/arm/plat-mxc/include/mach/uncompress.h @@ -13,10 +13,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #ifndef __ASM_ARCH_MXC_UNCOMPRESS_H__ #define __ASM_ARCH_MXC_UNCOMPRESS_H__ diff --git a/arch/arm/plat-mxc/include/mach/vmalloc.h b/arch/arm/plat-mxc/include/mach/vmalloc.h index 44243a27843..ef6379c474b 100644 --- a/arch/arm/plat-mxc/include/mach/vmalloc.h +++ b/arch/arm/plat-mxc/include/mach/vmalloc.h @@ -11,10 +11,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #ifndef __ASM_ARCH_MXC_VMALLOC_H__ diff --git a/arch/arm/plat-mxc/irq.c b/arch/arm/plat-mxc/irq.c index 778ddfe57d8..7331f2ace5f 100644 --- a/arch/arm/plat-mxc/irq.c +++ b/arch/arm/plat-mxc/irq.c @@ -142,9 +142,6 @@ void __init mxc_init_irq(void __iomem *irqbase) for (i = 0; i < 8; i++) __raw_writel(0, avic_base + AVIC_NIPRIORITY(i)); - /* init architectures chained interrupt handler */ - mxc_register_gpios(); - #ifdef CONFIG_FIQ /* Initialize FIQ */ init_FIQ(); diff --git a/arch/arm/plat-mxc/system.c b/arch/arm/plat-mxc/system.c index 97f42799fa5..925bce4607e 100644 --- a/arch/arm/plat-mxc/system.c +++ b/arch/arm/plat-mxc/system.c @@ -14,10 +14,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #include <linux/kernel.h> diff --git a/arch/arm/plat-mxc/tzic.c b/arch/arm/plat-mxc/tzic.c index 9b86d2a60d4..b3da9aad429 100644 --- a/arch/arm/plat-mxc/tzic.c +++ b/arch/arm/plat-mxc/tzic.c @@ -145,8 +145,6 @@ void __init tzic_init_irq(void __iomem *irqbase) set_irq_handler(i, handle_level_irq); set_irq_flags(i, IRQF_VALID); } - mxc_register_gpios(); - pr_info("TrustZone Interrupt Controller (TZIC) initialized\n"); } |