diff options
| author | Rajendra Nayak <rnayak@ti.com> | 2009-06-09 22:30:41 +0530 |
|---|---|---|
| committer | Kevin Hilman <khilman@deeprootsystems.com> | 2009-11-11 14:42:28 -0800 |
| commit | f265dc4c5d39f2bd369d97c87a7bd89061b159d4 (patch) | |
| tree | db16053ad7010c141a054ab0c8b5c243c311962f /arch/arm/plat-omap/include/plat/sdrc.h | |
| parent | 3a7ec26bb44988051d97479f6dfcfd4942a99049 (diff) | |
OMAP3: PM: Program SDRC to send self refresh on timeout of AUTO_CNT
Due to an OMAP3 errata (1.142), on HS/EMU devices SDRC should be
programed to issue automatic self refresh on timeout
of AUTO_CNT = 1 prior to any transition to OFF mode.
This is needed only on sil rev's ES3.0 and above.
This patch enables the above needed WA in the SDRC power register
value stored in scratchpad, so that ROM code restores this value
in SDRC POWER on the wakeup path.
The original SDRC POWER register value is stored and restored back
in omap_sram_idle() function.
This fixes some random crashes observed while stressing suspend
on HS/EMU devices.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Kalle Jokiniemi <kalle.jokiniemi@digia.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Diffstat (limited to 'arch/arm/plat-omap/include/plat/sdrc.h')
| -rw-r--r-- | arch/arm/plat-omap/include/plat/sdrc.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/plat-omap/include/plat/sdrc.h b/arch/arm/plat-omap/include/plat/sdrc.h index 772b71e8b44..f704030d2a7 100644 --- a/arch/arm/plat-omap/include/plat/sdrc.h +++ b/arch/arm/plat-omap/include/plat/sdrc.h @@ -44,6 +44,12 @@ #define SDRC_RFR_CTRL_1 0x0D4 #define SDRC_MANUAL_1 0x0D8 +#define SDRC_POWER_AUTOCOUNT_SHIFT 8 +#define SDRC_POWER_AUTOCOUNT_MASK (0xffff << SDRC_POWER_AUTOCOUNT_SHIFT) +#define SDRC_POWER_CLKCTRL_SHIFT 4 +#define SDRC_POWER_CLKCTRL_MASK (0x3 << SDRC_POWER_CLKCTRL_SHIFT) +#define SDRC_SELF_REFRESH_ON_AUTOCOUNT (0x2 << SDRC_POWER_CLKCTRL_SHIFT) + /* * These values represent the number of memory clock cycles between * autorefresh initiation. They assume 1 refresh per 64 ms (JEDEC), 8192 |