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authorkishore kadiyala <kishore.kadiyala@ti.com>2010-05-15 18:21:25 +0000
committerTony Lindgren <tony@atomide.com>2010-05-20 11:21:22 -0700
commitc83c8e6cde35c51a120952f54b4e4ecda6fa58a5 (patch)
treefa92fc248a25905730352d317bbf67a0c0e20602 /arch/arm/plat-omap/include
parent717c1fbf7c139c3c5d5920b29bdf196d07a40c8a (diff)
omap4: Adding PBIAS Configuration for MMC1 Controller
In OMAP4, MMC1 PBIAS and its associated IO is software-controlled by CONTROL_PBIAS and CONTROL_MMC1 registers. This patch adds PBIAS configuration for MMC1 Controller during power-ON and power-OFF of regulator. Signed-off-by: Kishore Kadiyala <kishore.kadiyala@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/plat-omap/include')
-rw-r--r--arch/arm/plat-omap/include/plat/control.h20
1 files changed, 20 insertions, 0 deletions
diff --git a/arch/arm/plat-omap/include/plat/control.h b/arch/arm/plat-omap/include/plat/control.h
index a56deee9767..131bf405c2f 100644
--- a/arch/arm/plat-omap/include/plat/control.h
+++ b/arch/arm/plat-omap/include/plat/control.h
@@ -207,6 +207,9 @@
/* 44xx control status register offset */
#define OMAP44XX_CONTROL_STATUS 0x2c4
+/* 44xx-only CONTROL_GENERAL register offsets */
+#define OMAP44XX_CONTROL_MMC1 0x628
+#define OMAP44XX_CONTROL_PBIAS_LITE 0x600
/*
* REVISIT: This list of registers is not comprehensive - there are more
* that should be added.
@@ -252,6 +255,23 @@
#define OMAP2_PBIASLITEPWRDNZ0 (1 << 1)
#define OMAP2_PBIASLITEVMODE0 (1 << 0)
+/* CONTROL_PBIAS_LITE bits for OMAP4 */
+#define OMAP4_MMC1_PWRDNZ (1 << 26)
+#define OMAP4_MMC1_PBIASLITE_HIZ_MODE (1 << 25)
+#define OMAP4_MMC1_PBIASLITE_SUPPLY_HI_OUT (1 << 24)
+#define OMAP4_MMC1_PBIASLITE_VMODE_ERROR (1 << 23)
+#define OMAP4_MMC1_PBIASLITE_PWRDNZ (1 << 22)
+#define OMAP4_MMC1_PBIASLITE_VMODE (1 << 21)
+#define OMAP4_USBC1_ICUSB_PWRDNZ (1 << 20)
+
+#define OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP0 (1 << 31)
+#define OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP1 (1 << 30)
+#define OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP2 (1 << 29)
+#define OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP3 (1 << 28)
+#define OMAP4_CONTROL_SDMMC1_DR0_SPEEDCTRL (1 << 27)
+#define OMAP4_CONTROL_SDMMC1_DR1_SPEEDCTRL (1 << 26)
+#define OMAP4_CONTROL_SDMMC1_DR2_SPEEDCTRL (1 << 25)
+
/* CONTROL_PROG_IO1 bits */
#define OMAP3630_PRG_SDMMC1_SPEEDCTRL (1 << 20)