diff options
| author | Peter Ujfalusi <peter.ujfalusi@nokia.com> | 2010-08-31 08:11:44 +0000 |
|---|---|---|
| committer | Tony Lindgren <tony@atomide.com> | 2010-09-27 10:15:25 -0700 |
| commit | ce3f054bdd4e022fa0ee9d11a215ec32f1caa12d (patch) | |
| tree | b7a916e40d672e49361a4b258aee1d0550388a7b /arch/arm/plat-omap/mcbsp.c | |
| parent | 813f6c5850521fec8917f61813be59691b60fcdf (diff) | |
omap: McBSP: Do not enable SRG in slave mode
McBSP SRG (Sample Rate Generator) and FSG (Frame Sync
Generator) is only needed to be enabled, when McBSP
is master.
In McBSP slave mode, the SRG, and FSG can be kept disabled,
which might save some power at the end in this configuration.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Jarkko Nikula <jhnikula@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/plat-omap/mcbsp.c')
| -rw-r--r-- | arch/arm/plat-omap/mcbsp.c | 13 |
1 files changed, 8 insertions, 5 deletions
diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c index e31496e35b0..ecbfe398a30 100644 --- a/arch/arm/plat-omap/mcbsp.c +++ b/arch/arm/plat-omap/mcbsp.c @@ -878,7 +878,7 @@ EXPORT_SYMBOL(omap_mcbsp_free); void omap_mcbsp_start(unsigned int id, int tx, int rx) { struct omap_mcbsp *mcbsp; - int idle; + int enable_srg = 0; u16 w; if (!omap_mcbsp_check_valid_id(id)) { @@ -893,10 +893,13 @@ void omap_mcbsp_start(unsigned int id, int tx, int rx) mcbsp->rx_word_length = (MCBSP_READ_CACHE(mcbsp, RCR1) >> 5) & 0x7; mcbsp->tx_word_length = (MCBSP_READ_CACHE(mcbsp, XCR1) >> 5) & 0x7; - idle = !((MCBSP_READ_CACHE(mcbsp, SPCR2) | - MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1); + /* Only enable SRG, if McBSP is master */ + w = MCBSP_READ_CACHE(mcbsp, PCR0); + if (w & (FSXM | FSRM | CLKXM | CLKRM)) + enable_srg = !((MCBSP_READ_CACHE(mcbsp, SPCR2) | + MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1); - if (idle) { + if (enable_srg) { /* Start the sample generator */ w = MCBSP_READ_CACHE(mcbsp, SPCR2); MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 6)); @@ -919,7 +922,7 @@ void omap_mcbsp_start(unsigned int id, int tx, int rx) */ udelay(500); - if (idle) { + if (enable_srg) { /* Start frame sync */ w = MCBSP_READ_CACHE(mcbsp, SPCR2); MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7)); |