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| author | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2013-03-21 16:07:34 -0700 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2013-03-21 16:07:34 -0700 |
| commit | 23a376f98c5dcfc392d47e8d1872884ff44e585d (patch) | |
| tree | dbe476151bbd6530369c40746f2ec2365f7b500a /arch/arm/plat-orion/addr-map.c | |
| parent | 8358f6242dd447a4f694c7bc949bbfc842ca5db1 (diff) | |
| parent | a937536b868b8369b98967929045f1df54234323 (diff) | |
Merge 3.9-rc3 into tty-next
Diffstat (limited to 'arch/arm/plat-orion/addr-map.c')
| -rw-r--r-- | arch/arm/plat-orion/addr-map.c | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/arch/arm/plat-orion/addr-map.c b/arch/arm/plat-orion/addr-map.c index febe3862873..807ac8e5cbc 100644 --- a/arch/arm/plat-orion/addr-map.c +++ b/arch/arm/plat-orion/addr-map.c @@ -157,9 +157,12 @@ void __init orion_setup_cpu_mbus_target(const struct orion_addr_map_cfg *cfg, u32 size = readl(ddr_window_cpu_base + DDR_SIZE_CS_OFF(i)); /* - * Chip select enabled? + * We only take care of entries for which the chip + * select is enabled, and that don't have high base + * address bits set (devices can only access the first + * 32 bits of the memory). */ - if (size & 1) { + if ((size & 1) && !(base & 0xF)) { struct mbus_dram_window *w; w = &orion_mbus_dram_info.cs[cs++]; |