diff options
| author | Kukjin Kim <kgene.kim@samsung.com> | 2011-10-04 20:18:36 +0900 |
|---|---|---|
| committer | Kukjin Kim <kgene.kim@samsung.com> | 2011-10-04 20:18:36 +0900 |
| commit | db3c94a7edc6b29f8d52ba5884dec6a15feeadad (patch) | |
| tree | ac9207a44cecafb9104ca4e1f46aecb9fe01383d /arch/arm/plat-s5p/include/plat | |
| parent | c9477f38cba225870862fd9e08868ae3d4abdfe0 (diff) | |
| parent | 568f0e278c6dd33dc11bd19c4ad781d1f8d86800 (diff) | |
Merge branch 'next-samsung-devel' into next-samsung-devel-2
Conflicts:
arch/arm/mach-exynos4/clock.c
arch/arm/mach-s3c2412/gpio.c
arch/arm/mach-s5p64x0/dma.c
arch/arm/mach-s5p64x0/gpiolib.c
Diffstat (limited to 'arch/arm/plat-s5p/include/plat')
| -rw-r--r-- | arch/arm/plat-s5p/include/plat/pll.h | 14 |
1 files changed, 12 insertions, 2 deletions
diff --git a/arch/arm/plat-s5p/include/plat/pll.h b/arch/arm/plat-s5p/include/plat/pll.h index 3e21b9444cc..002ec9f28f1 100644 --- a/arch/arm/plat-s5p/include/plat/pll.h +++ b/arch/arm/plat-s5p/include/plat/pll.h @@ -97,15 +97,24 @@ static inline unsigned long s5p_get_pll45xx(unsigned long baseclk, u32 pll_con, return (unsigned long)fvco; } -#define PLL46XX_KDIV_MASK (0xFFFF) -#define PLL4650C_KDIV_MASK (0xFFF) +/* CON0 bit-fields */ #define PLL46XX_MDIV_MASK (0x1FF) #define PLL46XX_PDIV_MASK (0x3F) #define PLL46XX_SDIV_MASK (0x7) +#define PLL46XX_LOCKED_SHIFT (29) #define PLL46XX_MDIV_SHIFT (16) #define PLL46XX_PDIV_SHIFT (8) #define PLL46XX_SDIV_SHIFT (0) +/* CON1 bit-fields */ +#define PLL46XX_MRR_MASK (0x1F) +#define PLL46XX_MFR_MASK (0x3F) +#define PLL46XX_KDIV_MASK (0xFFFF) +#define PLL4650C_KDIV_MASK (0xFFF) +#define PLL46XX_MRR_SHIFT (24) +#define PLL46XX_MFR_SHIFT (16) +#define PLL46XX_KDIV_SHIFT (0) + enum pll46xx_type_t { pll_4600, pll_4650, @@ -148,6 +157,7 @@ static inline unsigned long s5p_get_pll46xx(unsigned long baseclk, #define PLL90XX_PDIV_MASK (0x3F) #define PLL90XX_SDIV_MASK (0x7) #define PLL90XX_KDIV_MASK (0xffff) +#define PLL90XX_LOCKED_SHIFT (29) #define PLL90XX_MDIV_SHIFT (16) #define PLL90XX_PDIV_SHIFT (8) #define PLL90XX_SDIV_SHIFT (0) |