Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm

* 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm: (272 commits)
  Fix soc_common PCMCIA configuration
  ARM: 5827/1: SA1100: h3100/h3600: emit messages on failed gpio_request
  ARM: 5826/1: SA1100: h3100/h3600: always build htc-egpio driver
  ARM: 5825/1: SA1100: h3600: update defconfig
  ARM: 5824/1: SA1100: reuse h3600 PCMCIA driver on h3100
  ARM: 5823/1: SA1100: h3100/h3600: add support for gpio-keys
  ARM: 5822/1: SA1100: h3100/h3600: clean up #includes
  ARM: 5821/1: SA1100: h3100/h3600: revise copyright boilerplates
  ARM: 5820/1: SA1100: h3100/h3600: split h3600.c
  ARM: 5819/1: SA1100: h3100/h3600: merge h3600.h and h3600_gpio.h into h3xxx.h
  ARM: 5818/1: SA1100: h3100/h3600: drop old GPIO definitions
  ARM: 5817/1: SA1100: h3100/h3600: configure all unused gpios as inputs
  ARM: 5816/1: SA1100: h3600: remove IRQ_GPIO_* definitions
  ARM: 5815/1: SA1100: h3100/h3600: remove now unused assign_h3600_egpio handlers
  ARM: 5814/1: SA1100: h3100/h3600: convert all users of assign_h3600_egpio to gpiolib
  ARM: 5813/1: SA1100: h3100/h3600: add htc-egpio driver
  ARM: 5812/1: SA1100: h3100/h3600: separate machine-specific LCD helpers
  ARM: 5811/2: pcmcia: convert sa1100_h3600 driver to gpiolib
  ARM: 5799/1: SA1100: h3600: stop setting direction for LCD pins
  ARM: 5798/1: SA1100: h3600: remove unused cruft from h3600.h
  ...

1 files changed, 75 insertions, 137 deletions

diff --git a/arch/arm/plat-s5pc1xx/include/plat/regs-clock.h b/arch/arm/plat-s5pc1xx/include/plat/regs-clock.h
index 75c8390cb82..c5cc86e92d6 100644
--- a/arch/arm/plat-s5pc1xx/include/plat/regs-clock.h
+++ b/arch/arm/plat-s5pc1xx/include/plat/regs-clock.h
@@ -13,68 +13,69 @@
 #ifndef __PLAT_REGS_CLOCK_H
 #define __PLAT_REGS_CLOCK_H __FILE__
 
-#define S5PC1XX_CLKREG(x)		(S5PC1XX_VA_CLK + (x))
-
-#define S5PC1XX_APLL_LOCK		S5PC1XX_CLKREG(0x00)
-#define S5PC1XX_MPLL_LOCK		S5PC1XX_CLKREG(0x04)
-#define S5PC1XX_EPLL_LOCK		S5PC1XX_CLKREG(0x08)
-#define S5PC100_HPLL_LOCK		S5PC1XX_CLKREG(0x0C)
-
-#define S5PC1XX_APLL_CON		S5PC1XX_CLKREG(0x100)
-#define S5PC1XX_MPLL_CON		S5PC1XX_CLKREG(0x104)
-#define S5PC1XX_EPLL_CON		S5PC1XX_CLKREG(0x108)
-#define S5PC100_HPLL_CON		S5PC1XX_CLKREG(0x10C)
-
-#define S5PC1XX_CLK_SRC0		S5PC1XX_CLKREG(0x200)
-#define S5PC1XX_CLK_SRC1		S5PC1XX_CLKREG(0x204)
-#define S5PC1XX_CLK_SRC2		S5PC1XX_CLKREG(0x208)
-#define S5PC1XX_CLK_SRC3		S5PC1XX_CLKREG(0x20C)
-
-#define S5PC1XX_CLK_DIV0		S5PC1XX_CLKREG(0x300)
-#define S5PC1XX_CLK_DIV1		S5PC1XX_CLKREG(0x304)
-#define S5PC1XX_CLK_DIV2		S5PC1XX_CLKREG(0x308)
-#define S5PC1XX_CLK_DIV3		S5PC1XX_CLKREG(0x30C)
-#define S5PC1XX_CLK_DIV4		S5PC1XX_CLKREG(0x310)
-
-#define S5PC100_CLK_OUT			S5PC1XX_CLKREG(0x400)
-
-#define S5PC100_CLKGATE_D00		S5PC1XX_CLKREG(0x500)
-#define S5PC100_CLKGATE_D01		S5PC1XX_CLKREG(0x504)
-#define S5PC100_CLKGATE_D02		S5PC1XX_CLKREG(0x508)
-
-#define S5PC100_CLKGATE_D10		S5PC1XX_CLKREG(0x520)
-#define S5PC100_CLKGATE_D11		S5PC1XX_CLKREG(0x524)
-#define S5PC100_CLKGATE_D12		S5PC1XX_CLKREG(0x528)
-#define S5PC100_CLKGATE_D13		S5PC1XX_CLKREG(0x52C)
-#define S5PC100_CLKGATE_D14		S5PC1XX_CLKREG(0x530)
-#define S5PC100_CLKGATE_D15		S5PC1XX_CLKREG(0x534)
-
-#define S5PC100_CLKGATE_D20		S5PC1XX_CLKREG(0x540)
-
-#define S5PC100_SCLKGATE0		S5PC1XX_CLKREG(0x560)
-#define S5PC100_SCLKGATE1		S5PC1XX_CLKREG(0x564)
-
-#define S5PC100_OTHERS          S5PC1XX_CLKREG(0x8200)
-
-#define S5PC1XX_EPLL_EN     (1<<31)
-#define S5PC1XX_EPLL_MASK   0xffffffff
-#define S5PC1XX_EPLLVAL(_m, _p, _s)   ((_m) << 16 | ((_p) << 8) | ((_s)))
+#define S5PC100_CLKREG(x)		(S5PC1XX_VA_CLK + (x))
+#define S5PC100_CLKREG_OTHER(x)		(S5PC1XX_VA_CLK_OTHER + (x))
+
+/* s5pc100 register for clock */
+#define S5PC100_APLL_LOCK		S5PC100_CLKREG(0x00)
+#define S5PC100_MPLL_LOCK		S5PC100_CLKREG(0x04)
+#define S5PC100_EPLL_LOCK		S5PC100_CLKREG(0x08)
+#define S5PC100_HPLL_LOCK		S5PC100_CLKREG(0x0C)
+
+#define S5PC100_APLL_CON		S5PC100_CLKREG(0x100)
+#define S5PC100_MPLL_CON		S5PC100_CLKREG(0x104)
+#define S5PC100_EPLL_CON		S5PC100_CLKREG(0x108)
+#define S5PC100_HPLL_CON		S5PC100_CLKREG(0x10C)
+
+#define S5PC100_CLKSRC0			S5PC100_CLKREG(0x200)
+#define S5PC100_CLKSRC1			S5PC100_CLKREG(0x204)
+#define S5PC100_CLKSRC2			S5PC100_CLKREG(0x208)
+#define S5PC100_CLKSRC3			S5PC100_CLKREG(0x20C)
+
+#define S5PC100_CLKDIV0			S5PC100_CLKREG(0x300)
+#define S5PC100_CLKDIV1			S5PC100_CLKREG(0x304)
+#define S5PC100_CLKDIV2			S5PC100_CLKREG(0x308)
+#define S5PC100_CLKDIV3			S5PC100_CLKREG(0x30C)
+#define S5PC100_CLKDIV4			S5PC100_CLKREG(0x310)
+
+#define S5PC100_CLK_OUT			S5PC100_CLKREG(0x400)
+
+#define S5PC100_CLKGATE_D00		S5PC100_CLKREG(0x500)
+#define S5PC100_CLKGATE_D01		S5PC100_CLKREG(0x504)
+#define S5PC100_CLKGATE_D02		S5PC100_CLKREG(0x508)
+
+#define S5PC100_CLKGATE_D10		S5PC100_CLKREG(0x520)
+#define S5PC100_CLKGATE_D11		S5PC100_CLKREG(0x524)
+#define S5PC100_CLKGATE_D12		S5PC100_CLKREG(0x528)
+#define S5PC100_CLKGATE_D13		S5PC100_CLKREG(0x52C)
+#define S5PC100_CLKGATE_D14		S5PC100_CLKREG(0x530)
+#define S5PC100_CLKGATE_D15		S5PC100_CLKREG(0x534)
+
+#define S5PC100_CLKGATE_D20		S5PC100_CLKREG(0x540)
+
+#define S5PC100_SCLKGATE0		S5PC100_CLKREG(0x560)
+#define S5PC100_SCLKGATE1		S5PC100_CLKREG(0x564)
+
+/* EPLL_CON */
+#define S5PC100_EPLL_EN			(1<<31)
+#define S5PC100_EPLL_MASK		0xffffffff
+#define S5PC100_EPLLVAL(_m, _p, _s)	((_m) << 16 | ((_p) << 8) | ((_s)))
 
 /* CLKSRC0 */
-#define S5PC1XX_CLKSRC0_APLL_MASK		(0x1<<0)
-#define S5PC1XX_CLKSRC0_APLL_SHIFT		(0)
-#define S5PC1XX_CLKSRC0_MPLL_MASK		(0x1<<4)
-#define S5PC1XX_CLKSRC0_MPLL_SHIFT		(4)
-#define S5PC1XX_CLKSRC0_EPLL_MASK		(0x1<<8)
-#define S5PC1XX_CLKSRC0_EPLL_SHIFT		(8)
+#define S5PC100_CLKSRC0_APLL_MASK		(0x1<<0)
+#define S5PC100_CLKSRC0_APLL_SHIFT		(0)
+#define S5PC100_CLKSRC0_MPLL_MASK		(0x1<<4)
+#define S5PC100_CLKSRC0_MPLL_SHIFT		(4)
+#define S5PC100_CLKSRC0_EPLL_MASK		(0x1<<8)
+#define S5PC100_CLKSRC0_EPLL_SHIFT		(8)
 #define S5PC100_CLKSRC0_HPLL_MASK		(0x1<<12)
 #define S5PC100_CLKSRC0_HPLL_SHIFT		(12)
 #define S5PC100_CLKSRC0_AMMUX_MASK		(0x1<<16)
 #define S5PC100_CLKSRC0_AMMUX_SHIFT		(16)
 #define S5PC100_CLKSRC0_HREF_MASK		(0x1<<20)
 #define S5PC100_CLKSRC0_HREF_SHIFT		(20)
-#define S5PC1XX_CLKSRC0_ONENAND_MASK	(0x1<<24)
-#define S5PC1XX_CLKSRC0_ONENAND_SHIFT	(24)
+#define S5PC100_CLKSRC0_ONENAND_MASK	(0x1<<24)
+#define S5PC100_CLKSRC0_ONENAND_SHIFT	(24)
 
 
 /* CLKSRC1 */
@@ -127,10 +128,9 @@
 #define S5PC100_CLKSRC3_SPDIF_MASK		(0x3<<24)
 #define S5PC100_CLKSRC3_SPDIF_SHIFT		(24)
 
-
 /* CLKDIV0 */
-#define S5PC1XX_CLKDIV0_APLL_MASK		(0x1<<0)
-#define S5PC1XX_CLKDIV0_APLL_SHIFT		(0)
+#define S5PC100_CLKDIV0_APLL_MASK		(0x1<<0)
+#define S5PC100_CLKDIV0_APLL_SHIFT		(0)
 #define S5PC100_CLKDIV0_ARM_MASK		(0x7<<4)
 #define S5PC100_CLKDIV0_ARM_SHIFT		(4)
 #define S5PC100_CLKDIV0_D0_MASK		(0x7<<8)
@@ -141,8 +141,8 @@
 #define S5PC100_CLKDIV0_SECSS_SHIFT		(16)
 
 /* CLKDIV1 */
-#define S5PC100_CLKDIV1_AM_MASK		(0x7<<0)
-#define S5PC100_CLKDIV1_AM_SHIFT		(0)
+#define S5PC100_CLKDIV1_APLL2_MASK		(0x7<<0)
+#define S5PC100_CLKDIV1_APLL2_SHIFT		(0)
 #define S5PC100_CLKDIV1_MPLL_MASK		(0x3<<4)
 #define S5PC100_CLKDIV1_MPLL_SHIFT		(4)
 #define S5PC100_CLKDIV1_MPLL2_MASK		(0x1<<8)
@@ -202,7 +202,6 @@
 #define S5PC100_CLKDIV4_AUDIO2_MASK		(0xf<<20)
 #define S5PC100_CLKDIV4_AUDIO2_SHIFT	(20)
 
-
 /* HCLKD0/PCLKD0 Clock Gate 0 Registers */
 #define S5PC100_CLKGATE_D00_INTC		(1<<0)
 #define S5PC100_CLKGATE_D00_TZIC		(1<<1)
@@ -295,8 +294,8 @@
 #define S5PC100_CLKGATE_D20_I2SD2		(1<<1)
 
 /* Special Clock Gate 0 Registers */
-#define	S5PC1XX_CLKGATE_SCLK0_HPM		(1<<0)
-#define	S5PC1XX_CLKGATE_SCLK0_PWI		(1<<1)
+#define	S5PC100_CLKGATE_SCLK0_HPM		(1<<0)
+#define	S5PC100_CLKGATE_SCLK0_PWI		(1<<1)
 #define	S5PC100_CLKGATE_SCLK0_ONENAND	(1<<2)
 #define	S5PC100_CLKGATE_SCLK0_UART		(1<<3)
 #define	S5PC100_CLKGATE_SCLK0_SPI0		(1<<4)
@@ -329,89 +328,28 @@
 #define	S5PC100_CLKGATE_SCLK1_SPDIF		(1<<11)
 #define	S5PC100_CLKGATE_SCLK1_CAM		(1<<12)
 
-/* register for power management */
-#define S5PC100_PWR_CFG 		S5PC1XX_CLKREG(0x8000)
-#define S5PC100_EINT_WAKEUP_MASK 	S5PC1XX_CLKREG(0x8004)
-#define S5PC100_NORMAL_CFG 		S5PC1XX_CLKREG(0x8010)
-#define S5PC100_STOP_CFG 		S5PC1XX_CLKREG(0x8014)
-#define S5PC100_SLEEP_CFG 		S5PC1XX_CLKREG(0x8018)
-#define S5PC100_STOP_MEM_CFG 	S5PC1XX_CLKREG(0x801C)
-#define S5PC100_OSC_FREQ 		S5PC1XX_CLKREG(0x8100)
-#define S5PC100_OSC_STABLE 		S5PC1XX_CLKREG(0x8104)
-#define S5PC100_PWR_STABLE 		S5PC1XX_CLKREG(0x8108)
-#define S5PC100_MTC_STABLE 		S5PC1XX_CLKREG(0x8110)
-#define S5PC100_CLAMP_STABLE 	S5PC1XX_CLKREG(0x8114)
-#define S5PC100_OTHERS 		S5PC1XX_CLKREG(0x8200)
-#define S5PC100_RST_STAT 		S5PC1XX_CLKREG(0x8300)
-#define S5PC100_WAKEUP_STAT 	S5PC1XX_CLKREG(0x8304)
-#define S5PC100_BLK_PWR_STAT 	S5PC1XX_CLKREG(0x8308)
-#define S5PC100_INFORM0 		S5PC1XX_CLKREG(0x8400)
-#define S5PC100_INFORM1 		S5PC1XX_CLKREG(0x8404)
-#define S5PC100_INFORM2 		S5PC1XX_CLKREG(0x8408)
-#define S5PC100_INFORM3 		S5PC1XX_CLKREG(0x840C)
-#define S5PC100_INFORM4 		S5PC1XX_CLKREG(0x8410)
-#define S5PC100_INFORM5 		S5PC1XX_CLKREG(0x8414)
-#define S5PC100_INFORM6 		S5PC1XX_CLKREG(0x8418)
-#define S5PC100_INFORM7 		S5PC1XX_CLKREG(0x841C)
-#define S5PC100_DCGIDX_MAP0 	S5PC1XX_CLKREG(0x8500)
-#define S5PC100_DCGIDX_MAP1 	S5PC1XX_CLKREG(0x8504)
-#define S5PC100_DCGIDX_MAP2 	S5PC1XX_CLKREG(0x8508)
-#define S5PC100_DCGPERF_MAP0 	S5PC1XX_CLKREG(0x850C)
-#define S5PC100_DCGPERF_MAP1 	S5PC1XX_CLKREG(0x8510)
-#define S5PC100_DVCIDX_MAP 		S5PC1XX_CLKREG(0x8514)
-#define S5PC100_FREQ_CPU 		S5PC1XX_CLKREG(0x8518)
-#define S5PC100_FREQ_DPM 		S5PC1XX_CLKREG(0x851C)
-#define S5PC100_DVSEMCLK_EN 	S5PC1XX_CLKREG(0x8520)
-#define S5PC100_APLL_CON_L8 	S5PC1XX_CLKREG(0x8600)
-#define S5PC100_APLL_CON_L7 	S5PC1XX_CLKREG(0x8604)
-#define S5PC100_APLL_CON_L6 	S5PC1XX_CLKREG(0x8608)
-#define S5PC100_APLL_CON_L5 	S5PC1XX_CLKREG(0x860C)
-#define S5PC100_APLL_CON_L4 	S5PC1XX_CLKREG(0x8610)
-#define S5PC100_APLL_CON_L3 	S5PC1XX_CLKREG(0x8614)
-#define S5PC100_APLL_CON_L2 	S5PC1XX_CLKREG(0x8618)
-#define S5PC100_APLL_CON_L1 	S5PC1XX_CLKREG(0x861C)
-#define S5PC100_IEM_CONTROL 	S5PC1XX_CLKREG(0x8620)
-#define S5PC100_CLKDIV_IEM_L8 	S5PC1XX_CLKREG(0x8700)
-#define S5PC100_CLKDIV_IEM_L7 	S5PC1XX_CLKREG(0x8704)
-#define S5PC100_CLKDIV_IEM_L6 	S5PC1XX_CLKREG(0x8708)
-#define S5PC100_CLKDIV_IEM_L5 	S5PC1XX_CLKREG(0x870C)
-#define S5PC100_CLKDIV_IEM_L4 	S5PC1XX_CLKREG(0x8710)
-#define S5PC100_CLKDIV_IEM_L3 	S5PC1XX_CLKREG(0x8714)
-#define S5PC100_CLKDIV_IEM_L2 	S5PC1XX_CLKREG(0x8718)
-#define S5PC100_CLKDIV_IEM_L1 	S5PC1XX_CLKREG(0x871C)
-#define S5PC100_IEM_HPMCLK_DIV 	S5PC1XX_CLKREG(0x8724)
-
-#define S5PC100_SWRESET		S5PC1XX_CLKREG(0x100000)
-#define S5PC100_OND_SWRESET		S5PC1XX_CLKREG(0x100008)
-#define S5PC100_GEN_CTRL		S5PC1XX_CLKREG(0x100100)
-#define S5PC100_GEN_STATUS		S5PC1XX_CLKREG(0x100104)
-#define S5PC100_MEM_SYS_CFG		S5PC1XX_CLKREG(0x100200)
-#define S5PC100_CAM_MUX_SEL		S5PC1XX_CLKREG(0x100300)
-#define S5PC100_MIXER_OUT_SEL	S5PC1XX_CLKREG(0x100304)
-#define S5PC100_LPMP_MODE_SEL	S5PC1XX_CLKREG(0x100308)
-#define S5PC100_MIPI_PHY_CON0	S5PC1XX_CLKREG(0x100400)
-#define S5PC100_MIPI_PHY_CON1	S5PC1XX_CLKREG(0x100414)
-#define S5PC100_HDMI_PHY_CON0	S5PC1XX_CLKREG(0x100420)
-
-#define S5PC100_CFG_WFI_CLEAN	(~(3<<5))
-#define S5PC100_CFG_WFI_IDLE	(1<<5)
-#define S5PC100_CFG_WFI_STOP	(2<<5)
-#define S5PC100_CFG_WFI_SLEEP	(3<<5)
-
+#define S5PC100_SWRESET		S5PC100_CLKREG_OTHER(0x000)
+#define S5PC100_OND_SWRESET	S5PC100_CLKREG_OTHER(0x008)
+#define S5PC100_GEN_CTRL	S5PC100_CLKREG_OTHER(0x100)
+#define S5PC100_GEN_STATUS	S5PC100_CLKREG_OTHER(0x104)
+#define S5PC100_MEM_SYS_CFG	S5PC100_CLKREG_OTHER(0x200)
+#define S5PC100_CAM_MUX_SEL	S5PC100_CLKREG_OTHER(0x300)
+#define S5PC100_MIXER_OUT_SEL	S5PC100_CLKREG_OTHER(0x304)
+#define S5PC100_LPMP_MODE_SEL	S5PC100_CLKREG_OTHER(0x308)
+#define S5PC100_MIPI_PHY_CON0	S5PC100_CLKREG_OTHER(0x400)
+#define S5PC100_MIPI_PHY_CON1	S5PC100_CLKREG_OTHER(0x414)
+#define S5PC100_HDMI_PHY_CON0	S5PC100_CLKREG_OTHER(0x420)
+
+#define S5PC100_SWRESET_RESETVAL	0xc100
 #define S5PC100_OTHER_SYS_INT	24
 #define S5PC100_OTHER_STA_TYPE	23
 #define STA_TYPE_EXPON		0
 #define STA_TYPE_SFR		1
 
-#define S5PC100_PWR_STA_EXP_SCALE	0
-#define S5PC100_PWR_STA_CNT		4
-
-#define S5PC100_PWR_STABLE_COUNT	85500
-
 #define S5PC100_SLEEP_CFG_OSC_EN	0
 
 /* OTHERS Resgister */
-#define S5PC100_OTHERS_USB_SIG_MASK 	(1 << 16)
+#define S5PC100_OTHERS_USB_SIG_MASK	(1 << 16)
 #define S5PC100_OTHERS_MIPI_DPHY_EN		(1 << 28)
 
 /* MIPI D-PHY Control Register 0 */