diff options
| author | Ben Dooks <ben-linux@fluff.org> | 2010-01-18 15:57:42 +0900 |
|---|---|---|
| committer | Ben Dooks <ben-linux@fluff.org> | 2010-01-18 16:00:56 +0900 |
| commit | f9e011b6b305d38445bbd4a1e7a8814e056de37b (patch) | |
| tree | e468845831a2061edd25f1f41b57b0b111e3d9d3 /arch/arm/plat-samsung/clock-clksrc.c | |
| parent | f3b464cca94c4a8f54fbc11ec5af8b143fd1750b (diff) | |
ARM: SAMSUNG: Fix bug in clksrc-clk round_rate call.
The call has been assuming all clksrc-clks' divider size is 4 bits, but
this may not be the case anymore. Use the reg_div.size parameter to
calculate the maximum value it can take and check against that.
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Diffstat (limited to 'arch/arm/plat-samsung/clock-clksrc.c')
| -rw-r--r-- | arch/arm/plat-samsung/clock-clksrc.c | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/arch/arm/plat-samsung/clock-clksrc.c b/arch/arm/plat-samsung/clock-clksrc.c index 656c70e0400..ae8b8507663 100644 --- a/arch/arm/plat-samsung/clock-clksrc.c +++ b/arch/arm/plat-samsung/clock-clksrc.c @@ -60,7 +60,7 @@ static int s3c_setrate_clksrc(struct clk *clk, unsigned long rate) rate = clk_round_rate(clk, rate); div = clk_get_rate(clk->parent) / rate; - if (div > 16) + if (div > (1 << sclk->reg_div.size)) return -EINVAL; val = __raw_readl(reg); @@ -102,7 +102,9 @@ static int s3c_setparent_clksrc(struct clk *clk, struct clk *parent) static unsigned long s3c_roundrate_clksrc(struct clk *clk, unsigned long rate) { + struct clksrc_clk *sclk = to_clksrc(clk); unsigned long parent_rate = clk_get_rate(clk->parent); + int max_div = 1 << sclk->reg_div.size; int div; if (rate >= parent_rate) @@ -114,8 +116,8 @@ static unsigned long s3c_roundrate_clksrc(struct clk *clk, if (div == 0) div = 1; - if (div > 16) - div = 16; + if (div > max_div) + div = max_div; rate = parent_rate / div; } |