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authorJassi Brar <jassi.brar@samsung.com>2010-01-18 17:45:52 +0900
committerBen Dooks <ben-linux@fluff.org>2010-01-18 18:27:15 +0900
commit398ccccb770e6ed3e138925404f0746cbe57c5a1 (patch)
tree0aa7b8a4d8181d8a84ab4f6a8fce4b503c479fb8 /arch/arm/plat-samsung/include/plat
parent87315a802a8aab9d986858fcf2230726c1b5c598 (diff)
ARM: S3C64XX: SPI: Header for passing platform data
We need a way to pass controller specific information to the SPI driver. For that purpose new headers are made. SPI Controller is assumed 'type-s3c64xx' and can be defined for newer SoCs. Hence, that part is placed under plat-samsung to be shared across newer SoCs. SoC specific part - spi source clocks, will be placed under plat-<soc>/include/plat/ Signed-off-by: Jassi Brar <jassi.brar@samsung.com> Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Diffstat (limited to 'arch/arm/plat-samsung/include/plat')
-rw-r--r--arch/arm/plat-samsung/include/plat/s3c64xx-spi.h67
1 files changed, 67 insertions, 0 deletions
diff --git a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
new file mode 100644
index 00000000000..d1772414931
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
@@ -0,0 +1,67 @@
+/* linux/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
+ *
+ * Copyright (C) 2009 Samsung Electronics Ltd.
+ * Jaswinder Singh <jassi.brar@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __S3C64XX_PLAT_SPI_H
+#define __S3C64XX_PLAT_SPI_H
+
+/**
+ * struct s3c64xx_spi_csinfo - ChipSelect description
+ * @fb_delay: Slave specific feedback delay.
+ * Refer to FB_CLK_SEL register definition in SPI chapter.
+ * @line: Custom 'identity' of the CS line.
+ * @set_level: CS line control.
+ *
+ * This is per SPI-Slave Chipselect information.
+ * Allocate and initialize one in machine init code and make the
+ * spi_board_info.controller_data point to it.
+ */
+struct s3c64xx_spi_csinfo {
+ u8 fb_delay;
+ unsigned line;
+ void (*set_level)(unsigned line_id, int lvl);
+};
+
+/**
+ * struct s3c64xx_spi_info - SPI Controller defining structure
+ * @src_clk_nr: Clock source index for the CLK_CFG[SPI_CLKSEL] field.
+ * @src_clk_name: Platform name of the corresponding clock.
+ * @num_cs: Number of CS this controller emulates.
+ * @cfg_gpio: Configure pins for this SPI controller.
+ * @fifo_lvl_mask: All tx fifo_lvl fields start at offset-6
+ * @rx_lvl_offset: Depends on tx fifo_lvl field and bus number
+ * @high_speed: If the controller supports HIGH_SPEED_EN bit
+ */
+struct s3c64xx_spi_info {
+ int src_clk_nr;
+ char *src_clk_name;
+
+ int num_cs;
+
+ int (*cfg_gpio)(struct platform_device *pdev);
+
+ /* Following two fields are for future compatibility */
+ int fifo_lvl_mask;
+ int rx_lvl_offset;
+ int high_speed;
+};
+
+/**
+ * s3c64xx_spi_set_info - SPI Controller configure callback by the board
+ * initialization code.
+ * @cntrlr: SPI controller number the configuration is for.
+ * @src_clk_nr: Clock the SPI controller is to use to generate SPI clocks.
+ * @num_cs: Number of elements in the 'cs' array.
+ *
+ * Call this from machine init code for each SPI Controller that
+ * has some chips attached to it.
+ */
+extern void s3c64xx_spi_set_info(int cntrlr, int src_clk_nr, int num_cs);
+
+#endif /* __S3C64XX_PLAT_SPI_H */