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authorArnd Bergmann <arnd@arndb.de>2012-03-15 21:22:00 +0000
committerArnd Bergmann <arnd@arndb.de>2012-03-15 21:22:00 +0000
commit853a0231e057c04255a848f6998f84faaa635c58 (patch)
treef9aef1ce29410437f39746515bc7fbab9ef90a52 /arch/arm/plat-samsung/include
parente7051e9dab77ddeaddbe12364939ae239d92ca73 (diff)
parent4d2e4d7f2c2b1a4382286821a59fa2f4012cb748 (diff)
Merge branch 'samsung/soc' into next/soc2
* samsung/soc: ARM: EXYNOS: fix cycle count for periodic mode of clock event timers ARM: EXYNOS: add support JPEG ARM: EXYNOS: Add DMC1, allow PPMU access for DMC ARM: SAMSUNG: Correct MIPI-CSIS io memory resource definition ARM: SAMSUNG: fix __init attribute on regarding s3c_set_platdata() ARM: SAMSUNG: Add __init attribute to samsung_bl_set() ARM: S5PV210: Add usb otg phy control ARM: S3C64XX: Add usb otg phy control ARM: EXYNOS: Enable l2 configuration through device tree ARM: EXYNOS: remove useless code to save/restore L2 ARM: EXYNOS: save L2 settings during bootup ARM: S5P: add L2 early resume code ARM: EXYNOS: Add support AFTR mode on EXYNOS4210 ARM: SAMSUNG: use spin_lock_irqsave() in clk_{enable,disable} ARM: S3C64XX: Define some additional always off clocks ARM: S3C64XX: Reduce residency requirement for cpuidle WFI mode ARM: SAMSUNG: Add a callback 'notify_after' for PWM backlight control ARM: SAMSUNG: add G2D to plat-s5p and mach-exynos ARM: S3C64XX: Gate some more clocks by default ARM: S3C64XX: Add basic cpuidle driver Conflicts: arch/arm/mach-exynos/clock.c arch/arm/mach-exynos/common.c This merges the earlier samsung support into the next/soc2 branch to resolve conflicts between commits in the earlier work and the exynos5 branch. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/plat-samsung/include')
-rw-r--r--arch/arm/plat-samsung/include/plat/devs.h2
-rw-r--r--arch/arm/plat-samsung/include/plat/regs-usb-hsotg-phy.h7
-rw-r--r--arch/arm/plat-samsung/include/plat/udc-hs.h5
3 files changed, 11 insertions, 3 deletions
diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h
index 32cc67e6be1..2155d4af62a 100644
--- a/arch/arm/plat-samsung/include/plat/devs.h
+++ b/arch/arm/plat-samsung/include/plat/devs.h
@@ -81,6 +81,8 @@ extern struct platform_device s5p_device_fimc1;
extern struct platform_device s5p_device_fimc2;
extern struct platform_device s5p_device_fimc3;
extern struct platform_device s5p_device_fimc_md;
+extern struct platform_device s5p_device_jpeg;
+extern struct platform_device s5p_device_g2d;
extern struct platform_device s5p_device_fimd0;
extern struct platform_device s5p_device_hdmi;
extern struct platform_device s5p_device_i2c_hdmiphy;
diff --git a/arch/arm/plat-samsung/include/plat/regs-usb-hsotg-phy.h b/arch/arm/plat-samsung/include/plat/regs-usb-hsotg-phy.h
index a111ad87183..fcf27966206 100644
--- a/arch/arm/plat-samsung/include/plat/regs-usb-hsotg-phy.h
+++ b/arch/arm/plat-samsung/include/plat/regs-usb-hsotg-phy.h
@@ -25,8 +25,9 @@
#define S3C_HSOTG_PHYREG(x) ((x) + S3C_VA_USB_HSPHY)
#define S3C_PHYPWR S3C_HSOTG_PHYREG(0x00)
-#define SRC_PHYPWR_OTG_DISABLE (1 << 4)
-#define SRC_PHYPWR_ANALOG_POWERDOWN (1 << 3)
+#define S3C_PHYPWR_NORMAL_MASK (0x19 << 0)
+#define S3C_PHYPWR_OTG_DISABLE (1 << 4)
+#define S3C_PHYPWR_ANALOG_POWERDOWN (1 << 3)
#define SRC_PHYPWR_FORCE_SUSPEND (1 << 1)
#define S3C_PHYCLK S3C_HSOTG_PHYREG(0x04)
@@ -42,7 +43,7 @@
#define S3C_RSTCON S3C_HSOTG_PHYREG(0x08)
#define S3C_RSTCON_PHYCLK (1 << 2)
-#define S3C_RSTCON_HCLK (1 << 2)
+#define S3C_RSTCON_HCLK (1 << 1)
#define S3C_RSTCON_PHY (1 << 0)
#define S3C_PHYTUNE S3C_HSOTG_PHYREG(0x20)
diff --git a/arch/arm/plat-samsung/include/plat/udc-hs.h b/arch/arm/plat-samsung/include/plat/udc-hs.h
index a22a4f2eea9..c9e3667cb2b 100644
--- a/arch/arm/plat-samsung/include/plat/udc-hs.h
+++ b/arch/arm/plat-samsung/include/plat/udc-hs.h
@@ -26,4 +26,9 @@ enum s3c_hsotg_dmamode {
struct s3c_hsotg_plat {
enum s3c_hsotg_dmamode dma;
unsigned int is_osc : 1;
+
+ int (*phy_init)(struct platform_device *pdev, int type);
+ int (*phy_exit)(struct platform_device *pdev, int type);
};
+
+extern void s3c_hsotg_set_platdata(struct s3c_hsotg_plat *pd);