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| author | Russell King <rmk+kernel@arm.linux.org.uk> | 2010-10-19 22:06:36 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2010-10-19 22:06:36 +0100 |
| commit | 809b4e00baf006a990a73329ba381d536c6fa277 (patch) | |
| tree | e949e0efd019d6f932537aba762792b07a84351c /arch/arm/plat-tcc/include/mach/hardware.h | |
| parent | a0a55682b83fd5f012afadcf415b030d7424ae68 (diff) | |
| parent | 79a94c3538bda6869d7bb150b5e02dd3a72314dd (diff) | |
Merge branch 'devel-stable' into devel
Diffstat (limited to 'arch/arm/plat-tcc/include/mach/hardware.h')
| -rw-r--r-- | arch/arm/plat-tcc/include/mach/hardware.h | 43 |
1 files changed, 43 insertions, 0 deletions
diff --git a/arch/arm/plat-tcc/include/mach/hardware.h b/arch/arm/plat-tcc/include/mach/hardware.h new file mode 100644 index 00000000000..e70d126ccaf --- /dev/null +++ b/arch/arm/plat-tcc/include/mach/hardware.h @@ -0,0 +1,43 @@ +/* + * Author: RidgeRun, Inc. Greg Lonnon <glonnon@ridgerun.com> + * Reorganized for Linux-2.6 by Tony Lindgren <tony@atomide.com> + * and Dirk Behme <dirk.behme@de.bosch.com> + * Rewritten by: <linux@telechips.com> + * Description: Hardware definitions for TCC8300 processors and boards + * + * Copyright (C) 2001 RidgeRun, Inc. + * Copyright (C) 2008-2009 Telechips + * + * Modifications for mainline (C) 2009 Hans J. Koch <hjk@linutronix.de> + * + * Licensed under the terms of the GNU Pulic License version 2. + */ + +#ifndef __ASM_ARCH_TCC_HARDWARE_H +#define __ASM_ARCH_TCC_HARDWARE_H + +#include <asm/sizes.h> +#ifndef __ASSEMBLER__ +#include <asm/types.h> +#endif +#include <mach/io.h> + +/* + * ---------------------------------------------------------------------------- + * Clocks + * ---------------------------------------------------------------------------- + */ +#define CLKGEN_REG_BASE 0xfffece00 +#define ARM_CKCTL (CLKGEN_REG_BASE + 0x0) +#define ARM_IDLECT1 (CLKGEN_REG_BASE + 0x4) +#define ARM_IDLECT2 (CLKGEN_REG_BASE + 0x8) +#define ARM_EWUPCT (CLKGEN_REG_BASE + 0xC) +#define ARM_RSTCT1 (CLKGEN_REG_BASE + 0x10) +#define ARM_RSTCT2 (CLKGEN_REG_BASE + 0x14) +#define ARM_SYSST (CLKGEN_REG_BASE + 0x18) +#define ARM_IDLECT3 (CLKGEN_REG_BASE + 0x24) + +/* DPLL control registers */ +#define DPLL_CTL 0xfffecf00 + +#endif /* __ASM_ARCH_TCC_HARDWARE_H */ |