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authorWill Deacon <will.deacon@arm.com>2014-05-02 16:24:10 +0100
committerCatalin Marinas <catalin.marinas@arm.com>2014-05-09 17:03:15 +0100
commit98f7685ee69f871ba991089cb9685f0da07517ea (patch)
treef62bfc6c13d2e54c70349f47f85438f8d596fe36 /arch/arm64/include/asm/cacheflush.h
parentfa48e6f780a681cdbc7820e33259edfe1a79b9e3 (diff)
arm64: barriers: make use of barrier options with explicit barriers
When calling our low-level barrier macros directly, we can often suffice with more relaxed behaviour than the default "all accesses, full system" option. This patch updates the users of dsb() to specify the option which they actually require. Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm64/include/asm/cacheflush.h')
-rw-r--r--arch/arm64/include/asm/cacheflush.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm64/include/asm/cacheflush.h b/arch/arm64/include/asm/cacheflush.h
index 4c60e64a801..a5176cf32da 100644
--- a/arch/arm64/include/asm/cacheflush.h
+++ b/arch/arm64/include/asm/cacheflush.h
@@ -123,7 +123,7 @@ extern void flush_dcache_page(struct page *);
static inline void __flush_icache_all(void)
{
asm("ic ialluis");
- dsb();
+ dsb(ish);
}
#define flush_dcache_mmap_lock(mapping) \
@@ -150,7 +150,7 @@ static inline void flush_cache_vmap(unsigned long start, unsigned long end)
* set_pte_at() called from vmap_pte_range() does not
* have a DSB after cleaning the cache line.
*/
- dsb();
+ dsb(ish);
}
static inline void flush_cache_vunmap(unsigned long start, unsigned long end)