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authorMarc Zyngier <marc.zyngier@arm.com>2014-12-12 10:51:24 +0000
committerThomas Gleixner <tglx@linutronix.de>2014-12-13 13:41:06 +0100
commitc848126734e8621e81659d819922b20d93a2aa6d (patch)
treec3c7ffded7bc94951587318dd40a19641587d47b /arch/arm64/include/asm/irq.h
parentaca268df8a576ad11ce5ecd55d1eabe00c69e3c6 (diff)
irqchip: gicv3-its: Fix ITT allocation
When issuing a MAPD command, one of the parameters passed to the ITS is the number of EventID bits used to index the per-device Interrupt Translation Table (ITT). Crucially, this is the number of bits *minus one*. This has two consequences: - The size of the ITT has to be a strict power of two, no matter how many different events the device is actually going to generate. - It is impossible to express an ITT with a single entry, as you would have to tell the ITS to "use zero bit from the EventID", and that clashes with "minus one" above. Fix this by allocating the ITT with the number of vectors rounded up to the next power of two, with a minimum of two entries. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Cc: linux-arm-kernel@lists.infradead.org Cc: Yun Wu (Abel) <wuyun.wu@huawei.com> Cc: Robert Richter <robert.richter@caviumnetworks.com> Cc: Jason Cooper <jason@lakedaemon.net> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'arch/arm64/include/asm/irq.h')
0 files changed, 0 insertions, 0 deletions