diff options
| author | Will Deacon <will.deacon@arm.com> | 2014-05-02 16:24:15 +0100 |
|---|---|---|
| committer | Catalin Marinas <catalin.marinas@arm.com> | 2014-05-09 17:21:24 +0100 |
| commit | dc60b777fcdddbadab111028e266fd69d4702b34 (patch) | |
| tree | d839ce1021b5f64b2925d8f20230cb9564f3e11e /arch/arm64/mm/proc.S | |
| parent | ee9e101c11478680d579bd20bb38a4d3e2514fe3 (diff) | |
arm64: mm: use inner-shareable barriers for inner-shareable maintenance
In order to ensure ordering and completion of inner-shareable maintenance
instructions (cache and TLB) on AArch64, we can use the -ish suffix to
the dmb and dsb instructions respectively.
This patch updates our low-level cache and tlb maintenance routines to
use the inner-shareable barrier variants where appropriate.
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm64/mm/proc.S')
| -rw-r--r-- | arch/arm64/mm/proc.S | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S index 9042aff5e9e..7736779c980 100644 --- a/arch/arm64/mm/proc.S +++ b/arch/arm64/mm/proc.S @@ -182,7 +182,7 @@ ENDPROC(cpu_do_switch_mm) ENTRY(__cpu_setup) ic iallu // I+BTB cache invalidate tlbi vmalle1is // invalidate I + D TLBs - dsb sy + dsb ish mov x0, #3 << 20 msr cpacr_el1, x0 // Enable FP/ASIMD |