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authorStepan Moskovchenko <stepanm@codeaurora.org>2010-11-12 19:29:48 -0800
committerDaniel Walker <dwalker@codeaurora.org>2010-11-30 13:53:45 -0800
commitc4bd2eebee37b885b47ec48961923b671148703f (patch)
treea0257c00f0aa720608ff6f173fa4f2566d33fc4b /arch/arm
parent23513c3b39207c569da2c8afdced62ec43b4a272 (diff)
msm: iomap: Addresses and IRQs for 2nd GFX core IOMMU
Add register addresses and IRQ numbers for the IOMMU used for the second 2D graphics core. Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org> Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/mach-msm/include/mach/irqs-8x60.h7
-rw-r--r--arch/arm/mach-msm/include/mach/msm_iomap-8x60.h3
2 files changed, 9 insertions, 1 deletions
diff --git a/arch/arm/mach-msm/include/mach/irqs-8x60.h b/arch/arm/mach-msm/include/mach/irqs-8x60.h
index 36074cfc9ad..f65841c74c0 100644
--- a/arch/arm/mach-msm/include/mach/irqs-8x60.h
+++ b/arch/arm/mach-msm/include/mach/irqs-8x60.h
@@ -237,7 +237,12 @@
#define GSBI11_QUP_IRQ (GIC_SPI_START + 194)
#define INT_UART12DM_IRQ (GIC_SPI_START + 195)
#define GSBI12_QUP_IRQ (GIC_SPI_START + 196)
-/*SPI 197 to 216 arent used in 8x60*/
+
+/*SPI 197 to 209 arent used in 8x60*/
+#define SMMU_GFX2D1_CB_SC_SECURE_IRQ (GIC_SPI_START + 210)
+#define SMMU_GFX2D1_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 211)
+
+/*SPI 212 to 216 arent used in 8x60*/
#define SMPSS_SPARE_1 (GIC_SPI_START + 217)
#define SMPSS_SPARE_2 (GIC_SPI_START + 218)
#define SMPSS_SPARE_3 (GIC_SPI_START + 219)
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
index 45bab50e3ee..7c43a9bff1a 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
@@ -98,4 +98,7 @@
#define MSM_IOMMU_GFX2D0_PHYS 0x07D00000
#define MSM_IOMMU_GFX2D0_SIZE SZ_1M
+#define MSM_IOMMU_GFX2D1_PHYS 0x07E00000
+#define MSM_IOMMU_GFX2D1_SIZE SZ_1M
+
#endif