diff options
| author | Russell King <rmk+kernel@arm.linux.org.uk> | 2013-06-18 17:19:32 +0100 |
|---|---|---|
| committer | Wim Van Sebroeck <wim@iguana.be> | 2013-07-11 22:17:56 +0200 |
| commit | fa142ff5b3f67fab01f3d02a501b041b4266afdd (patch) | |
| tree | 349eefb8a6b56714b8ff898c8d179980736d96d9 /arch/arm | |
| parent | 938d0a840d0f97b627111fd038a735f3924fd987 (diff) | |
Watchdog: allow orion_wdt to be built for Dove
The watchdog infrastructure in Dove is no different from that in
Orion5x or Kirkwood, so let's enable it for Dove. The only things
missing are a few register settings in Dove's bridge-regs.h.
Rather than duplicating the same register bit masks for the RSTOUTn_MASK
and BRIDGE_CAUSE registers, move the definitions into the watchdog
driver itself.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Acked-by: Jason Cooper <jason@lakedaemon.net>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/mach-dove/include/mach/bridge-regs.h | 1 | ||||
| -rw-r--r-- | arch/arm/mach-kirkwood/include/mach/bridge-regs.h | 2 | ||||
| -rw-r--r-- | arch/arm/mach-orion5x/include/mach/bridge-regs.h | 3 |
3 files changed, 1 insertions, 5 deletions
diff --git a/arch/arm/mach-dove/include/mach/bridge-regs.h b/arch/arm/mach-dove/include/mach/bridge-regs.h index 99f259e8cf3..5362df3df89 100644 --- a/arch/arm/mach-dove/include/mach/bridge-regs.h +++ b/arch/arm/mach-dove/include/mach/bridge-regs.h @@ -26,6 +26,7 @@ #define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE + 0x010c) #define SOFT_RESET 0x00000001 +#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE + 0x0110) #define BRIDGE_INT_TIMER1_CLR (~0x0004) #define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0200) diff --git a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h index d4cbe5e81bb..91242c944d7 100644 --- a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h +++ b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h @@ -21,14 +21,12 @@ #define CPU_RESET 0x00000002 #define RSTOUTn_MASK (BRIDGE_VIRT_BASE + 0x0108) -#define WDT_RESET_OUT_EN 0x00000002 #define SOFT_RESET_OUT_EN 0x00000004 #define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE + 0x010c) #define SOFT_RESET 0x00000001 #define BRIDGE_CAUSE (BRIDGE_VIRT_BASE + 0x0110) -#define WDT_INT_REQ 0x0008 #define BRIDGE_INT_TIMER1_CLR (~0x0004) diff --git a/arch/arm/mach-orion5x/include/mach/bridge-regs.h b/arch/arm/mach-orion5x/include/mach/bridge-regs.h index 461fd69a10a..f727d03f168 100644 --- a/arch/arm/mach-orion5x/include/mach/bridge-regs.h +++ b/arch/arm/mach-orion5x/include/mach/bridge-regs.h @@ -18,7 +18,6 @@ #define CPU_CTRL (ORION5X_BRIDGE_VIRT_BASE + 0x104) #define RSTOUTn_MASK (ORION5X_BRIDGE_VIRT_BASE + 0x108) -#define WDT_RESET_OUT_EN 0x0002 #define CPU_SOFT_RESET (ORION5X_BRIDGE_VIRT_BASE + 0x10c) @@ -26,8 +25,6 @@ #define POWER_MNG_CTRL_REG (ORION5X_BRIDGE_VIRT_BASE + 0x11C) -#define WDT_INT_REQ 0x0008 - #define BRIDGE_INT_TIMER1_CLR (~0x0004) #define MAIN_IRQ_CAUSE (ORION5X_BRIDGE_VIRT_BASE + 0x200) |