diff options
| author | Huang Shijie <b32955@freescale.com> | 2013-07-08 17:14:21 +0800 |
|---|---|---|
| committer | Shawn Guo <shawn.guo@linaro.org> | 2013-08-22 23:29:08 +0800 |
| commit | a0bffd0cac3ad661acee3653361b3092a86e4650 (patch) | |
| tree | dc818e234f790b087c37de6eb76414e038a8f6d2 /arch/arm | |
| parent | 0b7a76aaa8d2d9d581f90c9e0a1f51e815d13242 (diff) | |
ARM: dts: imx6q{dl}: add a DTE uart pinctrl for uart2
In the arm2 board, the UART2 works in the dte mode.
So add a pinctrl for both the imx6q{dl} boards.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/boot/dts/imx6dl.dtsi | 9 | ||||
| -rw-r--r-- | arch/arm/boot/dts/imx6q.dtsi | 9 |
2 files changed, 18 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi index 4505109de7d..d75e32c93f0 100644 --- a/arch/arm/boot/dts/imx6dl.dtsi +++ b/arch/arm/boot/dts/imx6dl.dtsi @@ -230,6 +230,15 @@ MX6DL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 >; }; + + pinctrl_uart2_2: uart2grp-2 { /* DTE mode */ + fsl,pins = < + MX6DL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1 + MX6DL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1 + MX6DL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1 + MX6DL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1 + >; + }; }; uart4 { diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index 6f4d6ab9c25..e0b7bad7f78 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi @@ -266,6 +266,15 @@ MX6Q_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 >; }; + + pinctrl_uart2_2: uart2grp-2 { /* DTE mode */ + fsl,pins = < + MX6Q_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1 + MX6Q_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1 + MX6Q_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1 + MX6Q_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1 + >; + }; }; uart4 { |