diff options
| author | Russell King <rmk+kernel@arm.linux.org.uk> | 2012-01-13 15:00:22 +0000 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2012-01-13 15:00:22 +0000 |
| commit | 4de3a8e101150feaefa1139611a50ff37467f33e (patch) | |
| tree | daada742542518b02d7db7c5d32e715eaa5f166d /arch/arm | |
| parent | 294064f58953f9964e5945424b09c51800330a83 (diff) | |
| parent | 099469502f62fbe0d7e4f0b83a2f22538367f734 (diff) | |
Merge branch 'master' into fixes
Diffstat (limited to 'arch/arm')
674 files changed, 23970 insertions, 8570 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 444822526a0..24626b0419e 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -16,6 +16,7 @@ config ARM select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL) select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL) + select ARCH_BINFMT_ELF_RANDOMIZE_PIE select HAVE_GENERIC_DMA_COHERENT select HAVE_KERNEL_GZIP select HAVE_KERNEL_LZO @@ -30,6 +31,7 @@ config ARM select HAVE_SPARSE_IRQ select GENERIC_IRQ_SHOW select CPU_PM if (SUSPEND || CPU_IDLE) + select GENERIC_PCI_IOMAP help The ARM series is a line of low-power-consumption RISC chip designs licensed by ARM Ltd and targeted at embedded applications and @@ -447,6 +449,7 @@ config ARCH_MXS select ARCH_REQUIRE_GPIOLIB select CLKDEV_LOOKUP select CLKSRC_MMIO + select HAVE_CLK_PREPARE help Support for Freescale MXS-based family of processors @@ -597,6 +600,7 @@ config ARCH_MMP select ARCH_REQUIRE_GPIOLIB select CLKDEV_LOOKUP select GENERIC_CLOCKEVENTS + select GPIO_PXA select HAVE_SCHED_CLOCK select TICK_ONESHOT select PLAT_PXA @@ -658,6 +662,7 @@ config ARCH_PICOXCELL select HAVE_SCHED_CLOCK select HAVE_TCM select NO_IOPORT + select SPARSE_IRQ select USE_OF help This enables support for systems based on the Picochip picoXcell @@ -681,6 +686,7 @@ config ARCH_PXA select CLKSRC_MMIO select ARCH_REQUIRE_GPIOLIB select GENERIC_CLOCKEVENTS + select GPIO_PXA select HAVE_SCHED_CLOCK select TICK_ONESHOT select PLAT_PXA @@ -748,7 +754,7 @@ config ARCH_SA1100 select ARCH_HAS_CPUFREQ select CPU_FREQ select GENERIC_CLOCKEVENTS - select HAVE_CLK + select CLKDEV_LOOKUP select HAVE_SCHED_CLOCK select TICK_ONESHOT select ARCH_REQUIRE_GPIOLIB @@ -892,7 +898,6 @@ config ARCH_U300 select HAVE_MACH_CLKDEV select GENERIC_GPIO select ARCH_REQUIRE_GPIOLIB - select NEED_MACH_MEMORY_H help Support for ST-Ericsson U300 series mobile platforms. @@ -1140,10 +1145,9 @@ config IWMMXT Enable support for iWMMXt context switching at run time if running on a CPU that supports it. -# bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER config XSCALE_PMU bool - depends on CPU_XSCALE && !XSCALE_PMU_TIMER + depends on CPU_XSCALE default y config CPU_HAS_PMU diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index c5213e78606..e0d236d7ff7 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -100,6 +100,14 @@ choice Note that the system will appear to hang during boot if there is nothing connected to read from the DCC. + config AT91_DEBUG_LL_DBGU0 + bool "Kernel low-level debugging on rm9200, 9260/9g20, 9261/9g10 and 9rl" + depends on HAVE_AT91_DBGU0 + + config AT91_DEBUG_LL_DBGU1 + bool "Kernel low-level debugging on 9263, 9g45 and cap9" + depends on HAVE_AT91_DBGU1 + config DEBUG_FOOTBRIDGE_COM1 bool "Kernel low-level debugging messages via footbridge 8250 at PCI COM1" depends on FOOTBRIDGE @@ -247,6 +255,43 @@ choice their output to the standard serial port on the RealView PB1176 platform. + config DEBUG_MSM_UART1 + bool "Kernel low-level debugging messages via MSM UART1" + depends on ARCH_MSM7X00A || ARCH_MSM7X30 || ARCH_QSD8X50 + help + Say Y here if you want the debug print routines to direct + their output to the first serial port on MSM devices. + + config DEBUG_MSM_UART2 + bool "Kernel low-level debugging messages via MSM UART2" + depends on ARCH_MSM7X00A || ARCH_MSM7X30 || ARCH_QSD8X50 + help + Say Y here if you want the debug print routines to direct + their output to the second serial port on MSM devices. + + config DEBUG_MSM_UART3 + bool "Kernel low-level debugging messages via MSM UART3" + depends on ARCH_MSM7X00A || ARCH_MSM7X30 || ARCH_QSD8X50 + help + Say Y here if you want the debug print routines to direct + their output to the third serial port on MSM devices. + + config DEBUG_MSM8660_UART + bool "Kernel low-level debugging messages via MSM 8660 UART" + depends on ARCH_MSM8X60 + select MSM_HAS_DEBUG_UART_HS + help + Say Y here if you want the debug print routines to direct + their output to the serial port on MSM 8660 devices. + + config DEBUG_MSM8960_UART + bool "Kernel low-level debugging messages via MSM 8960 UART" + depends on ARCH_MSM8960 + select MSM_HAS_DEBUG_UART_HS + help + Say Y here if you want the debug print routines to direct + their output to the serial port on MSM 8960 devices. + endchoice config EARLY_PRINTK diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/at91sam9g20.dtsi index aeef04269cf..07603b8c950 100644 --- a/arch/arm/boot/dts/at91sam9g20.dtsi +++ b/arch/arm/boot/dts/at91sam9g20.dtsi @@ -114,6 +114,13 @@ atmel,use-dma-tx; status = "disabled"; }; + + macb0: ethernet@fffc4000 { + compatible = "cdns,at32ap7000-macb", "cdns,macb"; + reg = <0xfffc4000 0x100>; + interrupts = <21>; + status = "disabled"; + }; }; }; }; diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi index db6a45202f2..fffa005300a 100644 --- a/arch/arm/boot/dts/at91sam9g45.dtsi +++ b/arch/arm/boot/dts/at91sam9g45.dtsi @@ -101,6 +101,13 @@ atmel,use-dma-tx; status = "disabled"; }; + + macb0: ethernet@fffbc000 { + compatible = "cdns,at32ap7000-macb", "cdns,macb"; + reg = <0xfffbc000 0x100>; + interrupts = <25>; + status = "disabled"; + }; }; }; }; diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts index 85b34f59cd8..a387e7704ce 100644 --- a/arch/arm/boot/dts/at91sam9m10g45ek.dts +++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts @@ -30,6 +30,11 @@ usart1: serial@fff90000 { status = "okay"; }; + + macb0: ethernet@fffbc000 { + phy-mode = "rmii"; + status = "okay"; + }; }; }; }; diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts new file mode 100644 index 00000000000..b8c476384ee --- /dev/null +++ b/arch/arm/boot/dts/exynos4210-origen.dts @@ -0,0 +1,137 @@ +/* + * Samsung's Exynos4210 based Origen board device tree source + * + * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * Copyright (c) 2010-2011 Linaro Ltd. + * www.linaro.org + * + * Device tree source file for Insignal's Origen board which is based on + * Samsung's Exynos4210 SoC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/dts-v1/; +/include/ "exynos4210.dtsi" + +/ { + model = "Insignal Origen evaluation board based on Exynos4210"; + compatible = "insignal,origen", "samsung,exynos4210"; + + memory { + reg = <0x40000000 0x40000000>; + }; + + chosen { + bootargs ="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC2,115200 init=/linuxrc"; + }; + + sdhci@12530000 { + samsung,sdhci-bus-width = <4>; + linux,mmc_cap_4_bit_data; + samsung,sdhci-cd-internal; + gpio-cd = <&gpk2 2 2 3 3>; + gpios = <&gpk2 0 2 0 3>, + <&gpk2 1 2 0 3>, + <&gpk2 3 2 3 3>, + <&gpk2 4 2 3 3>, + <&gpk2 5 2 3 3>, + <&gpk2 6 2 3 3>; + }; + + sdhci@12510000 { + samsung,sdhci-bus-width = <4>; + linux,mmc_cap_4_bit_data; + samsung,sdhci-cd-internal; + gpio-cd = <&gpk0 2 2 3 3>; + gpios = <&gpk0 0 2 0 3>, + <&gpk0 1 2 0 3>, + <&gpk0 3 2 3 3>, + <&gpk0 4 2 3 3>, + <&gpk0 5 2 3 3>, + <&gpk0 6 2 3 3>; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + up { + label = "Up"; + gpios = <&gpx2 0 0 0 2>; + linux,code = <103>; + }; + + down { + label = "Down"; + gpios = <&gpx2 1 0 0 2>; + linux,code = <108>; + }; + + back { + label = "Back"; + gpios = <&gpx1 7 0 0 2>; + linux,code = <158>; + }; + + home { + label = "Home"; + gpios = <&gpx1 6 0 0 2>; + linux,code = <102>; + }; + + menu { + label = "Menu"; + gpios = <&gpx1 5 0 0 2>; + linux,code = <139>; + }; + }; + + keypad@100A0000 { + status = "disabled"; + }; + + sdhci@12520000 { + status = "disabled"; + }; + + sdhci@12540000 { + status = "disabled"; + }; + + i2c@13860000 { + status = "disabled"; + }; + + i2c@13870000 { + status = "disabled"; + }; + + i2c@13880000 { + status = "disabled"; + }; + + i2c@13890000 { + status = "disabled"; + }; + + i2c@138A0000 { + status = "disabled"; + }; + + i2c@138B0000 { + status = "disabled"; + }; + + i2c@138C0000 { + status = "disabled"; + }; + + i2c@138D0000 { + status = "disabled"; + }; +}; diff --git a/arch/arm/boot/dts/exynos4210-smdkv310.dts b/arch/arm/boot/dts/exynos4210-smdkv310.dts new file mode 100644 index 00000000000..27afc8e535c --- /dev/null +++ b/arch/arm/boot/dts/exynos4210-smdkv310.dts @@ -0,0 +1,182 @@ +/* + * Samsung's Exynos4210 based SMDKV310 board device tree source + * + * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * Copyright (c) 2010-2011 Linaro Ltd. + * www.linaro.org + * + * Device tree source file for Samsung's SMDKV310 board which is based on + * Samsung's Exynos4210 SoC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/dts-v1/; +/include/ "exynos4210.dtsi" + +/ { + model = "Samsung smdkv310 evaluation board based on Exynos4210"; + compatible = "samsung,smdkv310", "samsung,exynos4210"; + + memory { + reg = <0x40000000 0x80000000>; + }; + + chosen { + bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc"; + }; + + sdhci@12530000 { + samsung,sdhci-bus-width = <4>; + linux,mmc_cap_4_bit_data; + samsung,sdhci-cd-internal; + gpio-cd = <&gpk2 2 2 3 3>; + gpios = <&gpk2 0 2 0 3>, + <&gpk2 1 2 0 3>, + <&gpk2 3 2 3 3>, + <&gpk2 4 2 3 3>, + <&gpk2 5 2 3 3>, + <&gpk2 6 2 3 3>; + }; + + keypad@100A0000 { + samsung,keypad-num-rows = <2>; + samsung,keypad-num-columns = <8>; + linux,keypad-no-autorepeat; + linux,keypad-wakeup; + + row-gpios = <&gpx2 0 3 3 0>, + <&gpx2 1 3 3 0>; + + col-gpios = <&gpx1 0 3 0 0>, + <&gpx1 1 3 0 0>, + <&gpx1 2 3 0 0>, + <&gpx1 3 3 0 0>, + <&gpx1 4 3 0 0>, + <&gpx1 5 3 0 0>, + <&gpx1 6 3 0 0>, + <&gpx1 7 3 0 0>; + + key_1 { + keypad,row = <0>; + keypad,column = <3>; + linux,code = <2>; + }; + + key_2 { + keypad,row = <0>; + keypad,column = <4>; + linux,code = <3>; + }; + + key_3 { + keypad,row = <0>; + keypad,column = <5>; + linux,code = <4>; + }; + + key_4 { + keypad,row = <0>; + keypad,column = <6>; + linux,code = <5>; + }; + + key_5 { + keypad,row = <0>; + keypad,column = <7>; + linux,code = <6>; + }; + + key_a { + keypad,row = <1>; + keypad,column = <3>; + linux,code = <30>; + }; + + key_b { + keypad,row = <1>; + keypad,column = <4>; + linux,code = <48>; + }; + + key_c { + keypad,row = <1>; + keypad,column = <5>; + linux,code = <46>; + }; + + key_d { + keypad,row = <1>; + keypad,column = <6>; + linux,code = <32>; + }; + + key_e { + keypad,row = <1>; + keypad,column = <7>; + linux,code = <18>; + }; + }; + + i2c@13860000 { + #address-cells = <1>; + #size-cells = <0>; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <20000>; + gpios = <&gpd1 0 2 3 0>, + <&gpd1 1 2 3 0>; + + eeprom@50 { + compatible = "samsung,24ad0xd1"; + reg = <0x50>; + }; + + eeprom@52 { + compatible = "samsung,24ad0xd1"; + reg = <0x52>; + }; + }; + + sdhci@12510000 { + status = "disabled"; + }; + + sdhci@12520000 { + status = "disabled"; + }; + + sdhci@12540000 { + status = "disabled"; + }; + + i2c@13870000 { + status = "disabled"; + }; + + i2c@13880000 { + status = "disabled"; + }; + + i2c@13890000 { + status = "disabled"; + }; + + i2c@138A0000 { + status = "disabled"; + }; + + i2c@138B0000 { + status = "disabled"; + }; + + i2c@138C0000 { + status = "disabled"; + }; + + i2c@138D0000 { + status = "disabled"; + }; +}; diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi new file mode 100644 index 00000000000..63d7578856c --- /dev/null +++ b/arch/arm/boot/dts/exynos4210.dtsi @@ -0,0 +1,397 @@ +/* + * Samsung's Exynos4210 SoC device tree source + * + * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * Copyright (c) 2010-2011 Linaro Ltd. + * www.linaro.org + * + * Samsung's Exynos4210 SoC device nodes are listed in this file. Exynos4210 + * based board files can include this file and provide values for board specfic + * bindings. + * + * Note: This file does not include device nodes for all the controllers in + * Exynos4210 SoC. As device tree coverage for Exynos4210 increases, additional + * nodes can be added to this file. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/include/ "skeleton.dtsi" + +/ { + compatible = "samsung,exynos4210"; + interrupt-parent = <&gic>; + + gic:interrupt-controller@10490000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x10490000 0x1000>, <0x10480000 0x100>; + }; + + watchdog@10060000 { + compatible = "samsung,s3c2410-wdt"; + reg = <0x10060000 0x100>; + interrupts = <0 43 0>; + }; + + rtc@10070000 { + compatible = "samsung,s3c6410-rtc"; + reg = <0x10070000 0x100>; + interrupts = <0 44 0>, <0 45 0>; + }; + + keypad@100A0000 { + compatible = "samsung,s5pv210-keypad"; + reg = <0x100A0000 0x100>; + interrupts = <0 109 0>; + }; + + sdhci@12510000 { + compatible = "samsung,exynos4210-sdhci"; + reg = <0x12510000 0x100>; + interrupts = <0 73 0>; + }; + + sdhci@12520000 { + compatible = "samsung,exynos4210-sdhci"; + reg = <0x12520000 0x100>; + interrupts = <0 74 0>; + }; + + sdhci@12530000 { + compatible = "samsung,exynos4210-sdhci"; + reg = <0x12530000 0x100>; + interrupts = <0 75 0>; + }; + + sdhci@12540000 { + compatible = "samsung,exynos4210-sdhci"; + reg = <0x12540000 0x100>; + interrupts = <0 76 0>; + }; + + serial@13800000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x13800000 0x100>; + interrupts = <0 52 0>; + }; + + serial@13810000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x13810000 0x100>; + interrupts = <0 53 0>; + }; + + serial@13820000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x13820000 0x100>; + interrupts = <0 54 0>; + }; + + serial@13830000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x13830000 0x100>; + interrupts = <0 55 0>; + }; + + i2c@13860000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x13860000 0x100>; + interrupts = <0 58 0>; + }; + + i2c@13870000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x13870000 0x100>; + interrupts = <0 59 0>; + }; + + i2c@13880000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x13880000 0x100>; + interrupts = <0 60 0>; + }; + + i2c@13890000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x13890000 0x100>; + interrupts = <0 61 0>; + }; + + i2c@138A0000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x138A0000 0x100>; + interrupts = <0 62 0>; + }; + + i2c@138B0000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x138B0000 0x100>; + interrupts = <0 63 0>; + }; + + i2c@138C0000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x138C0000 0x100>; + interrupts = <0 64 0>; + }; + + i2c@138D0000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x138D0000 0x100>; + interrupts = <0 65 0>; + }; + + amba { + #address-cells = <1>; + #size-cells = <1>; + compatible = "arm,amba-bus"; + interrupt-parent = <&gic>; + ranges; + + pdma0: pdma@12680000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x12680000 0x1000>; + interrupts = <0 35 0>; + }; + + pdma1: pdma@12690000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x12690000 0x1000>; + interrupts = <0 36 0>; + }; + }; + + gpio-controllers { + #address-cells = <1>; + #size-cells = <1>; + gpio-controller; + ranges; + + gpa0: gpio-controller@11400000 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400000 0x20>; + #gpio-cells = <4>; + }; + + gpa1: gpio-controller@11400020 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400020 0x20>; + #gpio-cells = <4>; + }; + + gpb: gpio-controller@11400040 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400040 0x20>; + #gpio-cells = <4>; + }; + + gpc0: gpio-controller@11400060 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400060 0x20>; + #gpio-cells = <4>; + }; + + gpc1: gpio-controller@11400080 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400080 0x20>; + #gpio-cells = <4>; + }; + + gpd0: gpio-controller@114000A0 { + compatible = "samsung,exynos4-gpio"; + reg = <0x114000A0 0x20>; + #gpio-cells = <4>; + }; + + gpd1: gpio-controller@114000C0 { + compatible = "samsung,exynos4-gpio"; + reg = <0x114000C0 0x20>; + #gpio-cells = <4>; + }; + + gpe0: gpio-controller@114000E0 { + compatible = "samsung,exynos4-gpio"; + reg = <0x114000E0 0x20>; + #gpio-cells = <4>; + }; + + gpe1: gpio-controller@11400100 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400100 0x20>; + #gpio-cells = <4>; + }; + + gpe2: gpio-controller@11400120 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400120 0x20>; + #gpio-cells = <4>; + }; + + gpe3: gpio-controller@11400140 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400140 0x20>; + #gpio-cells = <4>; + }; + + gpe4: gpio-controller@11400160 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400160 0x20>; + #gpio-cells = <4>; + }; + + gpf0: gpio-controller@11400180 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400180 0x20>; + #gpio-cells = <4>; + }; + + gpf1: gpio-controller@114001A0 { + compatible = "samsung,exynos4-gpio"; + reg = <0x114001A0 0x20>; + #gpio-cells = <4>; + }; + + gpf2: gpio-controller@114001C0 { + compatible = "samsung,exynos4-gpio"; + reg = <0x114001C0 0x20>; + #gpio-cells = <4>; + }; + + gpf3: gpio-controller@114001E0 { + compatible = "samsung,exynos4-gpio"; + reg = <0x114001E0 0x20>; + #gpio-cells = <4>; + }; + + gpj0: gpio-controller@11000000 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11000000 0x20>; + #gpio-cells = <4>; + }; + + gpj1: gpio-controller@11000020 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11000020 0x20>; + #gpio-cells = <4>; + }; + + gpk0: gpio-controller@11000040 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11000040 0x20>; + #gpio-cells = <4>; + }; + + gpk1: gpio-controller@11000060 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11000060 0x20>; + #gpio-cells = <4>; + }; + + gpk2: gpio-controller@11000080 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11000080 0x20>; + #gpio-cells = <4>; + }; + + gpk3: gpio-controller@110000A0 { + compatible = "samsung,exynos4-gpio"; + reg = <0x110000A0 0x20>; + #gpio-cells = <4>; + }; + + gpl0: gpio-controller@110000C0 { + compatible = "samsung,exynos4-gpio"; + reg = <0x110000C0 0x20>; + #gpio-cells = <4>; + }; + + gpl1: gpio-controller@110000E0 { + compatible = "samsung,exynos4-gpio"; + reg = <0x110000E0 0x20>; + #gpio-cells = <4>; + }; + + gpl2: gpio-controller@11000100 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11000100 0x20>; + #gpio-cells = <4>; + }; + + gpy0: gpio-controller@11000120 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11000120 0x20>; + #gpio-cells = <4>; + }; + + gpy1: gpio-controller@11000140 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11000140 0x20>; + #gpio-cells = <4>; + }; + + gpy2: gpio-controller@11000160 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11000160 0x20>; + #gpio-cells = <4>; + }; + + gpy3: gpio-controller@11000180 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11000180 0x20>; + #gpio-cells = <4>; + }; + + gpy4: gpio-controller@110001A0 { + compatible = "samsung,exynos4-gpio"; + reg = <0x110001A0 0x20>; + #gpio-cells = <4>; + }; + + gpy5: gpio-controller@110001C0 { + compatible = "samsung,exynos4-gpio"; + reg = <0x110001C0 0x20>; + #gpio-cells = <4>; + }; + + gpy6: gpio-controller@110001E0 { + compatible = "samsung,exynos4-gpio"; + reg = <0x110001E0 0x20>; + #gpio-cells = <4>; + }; + + gpx0: gpio-controller@11000C00 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11000C00 0x20>; + #gpio-cells = <4>; + }; + + gpx1: gpio-controller@11000C20 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11000C20 0x20>; + #gpio-cells = <4>; + }; + + gpx2: gpio-controller@11000C40 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11000C40 0x20>; + #gpio-cells = <4>; + }; + + gpx3: gpio-controller@11000C60 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11000C60 0x20>; + #gpio-cells = <4>; + }; + + gpz: gpio-controller@03860000 { + compatible = "samsung,exynos4-gpio"; + reg = <0x03860000 0x20>; + #gpio-cells = <4>; + }; + }; +}; diff --git a/arch/arm/boot/dts/highbank.dts b/arch/arm/boot/dts/highbank.dts index aeb1a7578fa..305635bd45c 100644 --- a/arch/arm/boot/dts/highbank.dts +++ b/arch/arm/boot/dts/highbank.dts @@ -194,5 +194,17 @@ reg = <0xfff3d000 0x1000>; interrupts = <0 92 4>; }; + + ethernet@fff50000 { + compatible = "calxeda,hb-xgmac"; + reg = <0xfff50000 0x1000>; + interrupts = <0 77 4 0 78 4 0 79 4>; + }; + + ethernet@fff51000 { + compatible = "calxeda,hb-xgmac"; + reg = <0xfff51000 0x1000>; + interrupts = <0 80 4 0 81 4 0 82 4>; + }; }; }; diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts index f8766af1121..564cb8c19f1 100644 --- a/arch/arm/boot/dts/imx51-babbage.dts +++ b/arch/arm/boot/dts/imx51-babbage.dts @@ -35,20 +35,19 @@ }; esdhc@70008000 { /* ESDHC2 */ - cd-gpios = <&gpio0 6 0>; /* GPIO1_6 */ - wp-gpios = <&gpio0 5 0>; /* GPIO1_5 */ + cd-gpios = <&gpio1 6 0>; + wp-gpios = <&gpio1 5 0>; status = "okay"; }; - uart2: uart@7000c000 { /* UART3 */ + uart3: uart@7000c000 { fsl,uart-has-rtscts; status = "okay"; }; ecspi@70010000 { /* ECSPI1 */ fsl,spi-num-chipselects = <2>; - cs-gpios = <&gpio3 24 0>, /* GPIO4_24 */ - <&gpio3 25 0>; /* GPIO4_25 */ + cs-gpios = <&gpio4 24 0>, <&gpio4 25 0>; status = "okay"; pmic: mc13892@0 { @@ -57,7 +56,7 @@ compatible = "fsl,mc13892"; spi-max-frequency = <6000000>; reg = <0>; - mc13xxx-irq-gpios = <&gpio0 8 0>; /* GPIO1_8 */ + mc13xxx-irq-gpios = <&gpio1 8 0>; fsl,mc13xxx-uses-regulator; }; @@ -91,12 +90,12 @@ reg = <0x73fa8000 0x4000>; }; - uart0: uart@73fbc000 { + uart1: uart@73fbc000 { fsl,uart-has-rtscts; status = "okay"; }; - uart1: uart@73fc0000 { + uart2: uart@73fc0000 { status = "okay"; }; }; @@ -127,7 +126,7 @@ power { label = "Power Button"; - gpios = <&gpio1 21 0>; + gpios = <&gpio2 21 0>; linux,code = <116>; /* KEY_POWER */ gpio-key,wakeup; }; diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index 327ab8e3a4c..6663986fe1c 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi @@ -14,9 +14,9 @@ / { aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; }; tzic: tz-interrupt-controller@e0000000 { @@ -86,7 +86,7 @@ status = "disabled"; }; - uart2: uart@7000c000 { /* UART3 */ + uart3: uart@7000c000 { compatible = "fsl,imx51-uart", "fsl,imx21-uart"; reg = <0x7000c000 0x4000>; interrupts = <33>; @@ -117,7 +117,7 @@ }; }; - gpio0: gpio@73f84000 { /* GPIO1 */ + gpio1: gpio@73f84000 { compatible = "fsl,imx51-gpio", "fsl,imx31-gpio"; reg = <0x73f84000 0x4000>; interrupts = <50 51>; @@ -127,7 +127,7 @@ #interrupt-cells = <1>; }; - gpio1: gpio@73f88000 { /* GPIO2 */ + gpio2: gpio@73f88000 { compatible = "fsl,imx51-gpio", "fsl,imx31-gpio"; reg = <0x73f88000 0x4000>; interrupts = <52 53>; @@ -137,7 +137,7 @@ #interrupt-cells = <1>; }; - gpio2: gpio@73f8c000 { /* GPIO3 */ + gpio3: gpio@73f8c000 { compatible = "fsl,imx51-gpio", "fsl,imx31-gpio"; reg = <0x73f8c000 0x4000>; interrupts = <54 55>; @@ -147,7 +147,7 @@ #interrupt-cells = <1>; }; - gpio3: gpio@73f90000 { /* GPIO4 */ + gpio4: gpio@73f90000 { compatible = "fsl,imx51-gpio", "fsl,imx31-gpio"; reg = <0x73f90000 0x4000>; interrupts = <56 57>; @@ -171,14 +171,14 @@ status = "disabled"; }; - uart0: uart@73fbc000 { + uart1: uart@73fbc000 { compatible = "fsl,imx51-uart", "fsl,imx21-uart"; reg = <0x73fbc000 0x4000>; interrupts = <31>; status = "disabled"; }; - uart1: uart@73fc0000 { + uart2: uart@73fc0000 { compatible = "fsl,imx51-uart", "fsl,imx21-uart"; reg = <0x73fc0000 0x4000>; interrupts = <32>; diff --git a/arch/arm/boot/dts/imx53-ard.dts b/arch/arm/boot/dts/imx53-ard.dts index 2ab7f80a0a3..2dccce46ed8 100644 --- a/arch/arm/boot/dts/imx53-ard.dts +++ b/arch/arm/boot/dts/imx53-ard.dts @@ -29,8 +29,8 @@ aips@50000000 { /* AIPS1 */ spba@50000000 { esdhc@50004000 { /* ESDHC1 */ - cd-gpios = <&gpio0 1 0>; /* GPIO1_1 */ - wp-gpios = <&gpio0 9 0>; /* GPIO1_9 */ + cd-gpios = <&gpio1 1 0>; + wp-gpios = <&gpio1 9 0>; status = "okay"; }; }; @@ -44,7 +44,7 @@ reg = <0x53fa8000 0x4000>; }; - uart0: uart@53fbc000 { /* UART1 */ + uart1: uart@53fbc000 { status = "okay"; }; }; @@ -67,7 +67,7 @@ compatible = "smsc,lan9220", "smsc,lan9115"; reg = <0xf4000000 0x2000000>; phy-mode = "mii"; - interrupt-parent = <&gpio1>; + interrupt-parent = <&gpio2>; interrupts = <31>; reg-io-width = <4>; smsc,irq-push-pull; @@ -79,34 +79,34 @@ home { label = "Home"; - gpios = <&gpio4 10 0>; /* GPIO5_10 */ + gpios = <&gpio5 10 0>; linux,code = <102>; /* KEY_HOME */ gpio-key,wakeup; }; back { label = "Back"; - gpios = <&gpio4 11 0>; /* GPIO5_11 */ + gpios = <&gpio5 11 0>; linux,code = <158>; /* KEY_BACK */ gpio-key,wakeup; }; program { label = "Program"; - gpios = <&gpio4 12 0>; /* GPIO5_12 */ + gpios = <&gpio5 12 0>; linux,code = <362>; /* KEY_PROGRAM */ gpio-key,wakeup; }; volume-up { label = "Volume Up"; - gpios = <&gpio4 13 0>; /* GPIO5_13 */ + gpios = <&gpio5 13 0>; linux,code = <115>; /* KEY_VOLUMEUP */ }; volume-down { label = "Volume Down"; - gpios = <&gpio3 0 0>; /* GPIO4_0 */ + gpios = <&gpio4 0 0>; linux,code = <114>; /* KEY_VOLUMEDOWN */ }; }; diff --git a/arch/arm/boot/dts/imx53-evk.dts b/arch/arm/boot/dts/imx53-evk.dts index 3f3a88185ff..5bac4aa4800 100644 --- a/arch/arm/boot/dts/imx53-evk.dts +++ b/arch/arm/boot/dts/imx53-evk.dts @@ -29,15 +29,14 @@ aips@50000000 { /* AIPS1 */ spba@50000000 { esdhc@50004000 { /* ESDHC1 */ - cd-gpios = <&gpio2 13 0>; /* GPIO3_13 */ - wp-gpios = <&gpio2 14 0>; /* GPIO3_14 */ + cd-gpios = <&gpio3 13 0>; + wp-gpios = <&gpio3 14 0>; status = "okay"; }; ecspi@50010000 { /* ECSPI1 */ fsl,spi-num-chipselects = <2>; - cs-gpios = <&gpio1 30 0>, /* GPIO2_30 */ - <&gpio2 19 0>; /* GPIO3_19 */ + cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>; status = "okay"; flash: at45db321d@1 { @@ -61,8 +60,8 @@ }; esdhc@50020000 { /* ESDHC3 */ - cd-gpios = <&gpio2 11 0>; /* GPIO3_11 */ - wp-gpios = <&gpio2 12 0>; /* GPIO3_12 */ + cd-gpios = <&gpio3 11 0>; + wp-gpios = <&gpio3 12 0>; status = "okay"; }; }; @@ -76,7 +75,7 @@ reg = <0x53fa8000 0x4000>; }; - uart0: uart@53fbc000 { /* UART1 */ + uart1: uart@53fbc000 { status = "okay"; }; }; @@ -102,7 +101,7 @@ fec@63fec000 { phy-mode = "rmii"; - phy-reset-gpios = <&gpio6 6 0>; /* GPIO7_6 */ + phy-reset-gpios = <&gpio7 6 0>; status = "okay"; }; }; @@ -113,7 +112,7 @@ green { label = "Heartbeat"; - gpios = <&gpio6 7 0>; /* GPIO7_7 */ + gpios = <&gpio7 7 0>; linux,default-trigger = "heartbeat"; }; }; diff --git a/arch/arm/boot/dts/imx53-qsb.dts b/arch/arm/boot/dts/imx53-qsb.dts index ae6de6d0c3f..5c57c8672c3 100644 --- a/arch/arm/boot/dts/imx53-qsb.dts +++ b/arch/arm/boot/dts/imx53-qsb.dts @@ -29,13 +29,13 @@ aips@50000000 { /* AIPS1 */ spba@50000000 { esdhc@50004000 { /* ESDHC1 */ - cd-gpios = <&gpio2 13 0>; /* GPIO3_13 */ + cd-gpios = <&gpio3 13 0>; status = "okay"; }; esdhc@50020000 { /* ESDHC3 */ - cd-gpios = <&gpio2 11 0>; /* GPIO3_11 */ - wp-gpios = <&gpio2 12 0>; /* GPIO3_12 */ + cd-gpios = <&gpio3 11 0>; + wp-gpios = <&gpio3 12 0>; status = "okay"; }; }; @@ -49,7 +49,7 @@ reg = <0x53fa8000 0x4000>; }; - uart0: uart@53fbc000 { /* UART1 */ + uart1: uart@53fbc000 { status = "okay"; }; }; @@ -84,7 +84,7 @@ fec@63fec000 { phy-mode = "rmii"; - phy-reset-gpios = <&gpio6 6 0>; /* GPIO7_6 */ + phy-reset-gpios = <&gpio7 6 0>; status = "okay"; }; }; @@ -95,20 +95,20 @@ power { label = "Power Button"; - gpios = <&gpio0 8 0>; /* GPIO1_8 */ + gpios = <&gpio1 8 0>; linux,code = <116>; /* KEY_POWER */ gpio-key,wakeup; }; volume-up { label = "Volume Up"; - gpios = <&gpio1 14 0>; /* GPIO2_14 */ + gpios = <&gpio2 14 0>; linux,code = <115>; /* KEY_VOLUMEUP */ }; volume-down { label = "Volume Down"; - gpios = <&gpio1 15 0>; /* GPIO2_15 */ + gpios = <&gpio2 15 0>; linux,code = <114>; /* KEY_VOLUMEDOWN */ }; }; @@ -118,7 +118,7 @@ user { label = "Heartbeat"; - gpios = <&gpio6 7 0>; /* GPIO7_7 */ + gpios = <&gpio7 7 0>; linux,default-trigger = "heartbeat"; }; }; diff --git a/arch/arm/boot/dts/imx53-smd.dts b/arch/arm/boot/dts/imx53-smd.dts index b1c062eea71..c7ee86c2dfb 100644 --- a/arch/arm/boot/dts/imx53-smd.dts +++ b/arch/arm/boot/dts/imx53-smd.dts @@ -29,8 +29,8 @@ aips@50000000 { /* AIPS1 */ spba@50000000 { esdhc@50004000 { /* ESDHC1 */ - cd-gpios = <&gpio2 13 0>; /* GPIO3_13 */ - wp-gpios = <&gpio3 11 0>; /* GPIO4_11 */ + cd-gpios = <&gpio3 13 0>; + wp-gpios = <&gpio4 11 0>; status = "okay"; }; @@ -39,15 +39,14 @@ status = "okay"; }; - uart2: uart@5000c000 { /* UART3 */ + uart3: uart@5000c000 { fsl,uart-has-rtscts; status = "okay"; }; ecspi@50010000 { /* ECSPI1 */ fsl,spi-num-chipselects = <2>; - cs-gpios = <&gpio1 30 0>, /* GPIO2_30 */ - <&gpio2 19 0>; /* GPIO3_19 */ + cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>; status = "okay"; zigbee: mc1323@0 { @@ -91,11 +90,11 @@ reg = <0x53fa8000 0x4000>; }; - uart0: uart@53fbc000 { /* UART1 */ + uart1: uart@53fbc000 { status = "okay"; }; - uart1: uart@53fc0000 { /* UART2 */ + uart2: uart@53fc0000 { status = "okay"; }; }; @@ -145,7 +144,7 @@ fec@63fec000 { phy-mode = "rmii"; - phy-reset-gpios = <&gpio6 6 0>; /* GPIO7_6 */ + phy-reset-gpios = <&gpio7 6 0>; status = "okay"; }; }; @@ -156,13 +155,13 @@ volume-up { label = "Volume Up"; - gpios = <&gpio1 14 0>; /* GPIO2_14 */ + gpios = <&gpio2 14 0>; linux,code = <115>; /* KEY_VOLUMEUP */ }; volume-down { label = "Volume Down"; - gpios = <&gpio1 15 0>; /* GPIO2_15 */ + gpios = <&gpio2 15 0>; linux,code = <114>; /* KEY_VOLUMEDOWN */ }; }; diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index 099cd84ee37..5dd91b942c9 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi @@ -14,11 +14,11 @@ / { aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - serial4 = &uart4; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; }; tzic: tz-interrupt-controller@0fffc000 { @@ -88,7 +88,7 @@ status = "disabled"; }; - uart2: uart@5000c000 { /* UART3 */ + uart3: uart@5000c000 { compatible = "fsl,imx53-uart", "fsl,imx21-uart"; reg = <0x5000c000 0x4000>; interrupts = <33>; @@ -119,7 +119,7 @@ }; }; - gpio0: gpio@53f84000 { /* GPIO1 */ + gpio1: gpio@53f84000 { compatible = "fsl,imx53-gpio", "fsl,imx31-gpio"; reg = <0x53f84000 0x4000>; interrupts = <50 51>; @@ -129,7 +129,7 @@ #interrupt-cells = <1>; }; - gpio1: gpio@53f88000 { /* GPIO2 */ + gpio2: gpio@53f88000 { compatible = "fsl,imx53-gpio", "fsl,imx31-gpio"; reg = <0x53f88000 0x4000>; interrupts = <52 53>; @@ -139,7 +139,7 @@ #interrupt-cells = <1>; }; - gpio2: gpio@53f8c000 { /* GPIO3 */ + gpio3: gpio@53f8c000 { compatible = "fsl,imx53-gpio", "fsl,imx31-gpio"; reg = <0x53f8c000 0x4000>; interrupts = <54 55>; @@ -149,7 +149,7 @@ #interrupt-cells = <1>; }; - gpio3: gpio@53f90000 { /* GPIO4 */ + gpio4: gpio@53f90000 { compatible = "fsl,imx53-gpio", "fsl,imx31-gpio"; reg = <0x53f90000 0x4000>; interrupts = <56 57>; @@ -173,21 +173,21 @@ status = "disabled"; }; - uart0: uart@53fbc000 { /* UART1 */ + uart1: uart@53fbc000 { compatible = "fsl,imx53-uart", "fsl,imx21-uart"; reg = <0x53fbc000 0x4000>; interrupts = <31>; status = "disabled"; }; - uart1: uart@53fc0000 { /* UART2 */ + uart2: uart@53fc0000 { compatible = "fsl,imx53-uart", "fsl,imx21-uart"; reg = <0x53fc0000 0x4000>; interrupts = <32>; status = "disabled"; }; - gpio4: gpio@53fdc000 { /* GPIO5 */ + gpio5: gpio@53fdc000 { compatible = "fsl,imx53-gpio", "fsl,imx31-gpio"; reg = <0x53fdc000 0x4000>; interrupts = <103 104>; @@ -197,7 +197,7 @@ #interrupt-cells = <1>; }; - gpio5: gpio@53fe0000 { /* GPIO6 */ + gpio6: gpio@53fe0000 { compatible = "fsl,imx53-gpio", "fsl,imx31-gpio"; reg = <0x53fe0000 0x4000>; interrupts = <105 106>; @@ -207,7 +207,7 @@ #interrupt-cells = <1>; }; - gpio6: gpio@53fe4000 { /* GPIO7 */ + gpio7: gpio@53fe4000 { compatible = "fsl,imx53-gpio", "fsl,imx31-gpio"; reg = <0x53fe4000 0x4000>; interrupts = <107 108>; @@ -226,7 +226,7 @@ status = "disabled"; }; - uart3: uart@53ff0000 { /* UART4 */ + uart4: uart@53ff0000 { compatible = "fsl,imx53-uart", "fsl,imx21-uart"; reg = <0x53ff0000 0x4000>; interrupts = <13>; @@ -241,7 +241,7 @@ reg = <0x60000000 0x10000000>; ranges; - uart4: uart@63f90000 { /* UART5 */ + uart5: uart@63f90000 { compatible = "fsl,imx53-uart", "fsl,imx21-uart"; reg = <0x63f90000 0x4000>; interrupts = <86>; diff --git a/arch/arm/boot/dts/imx6q-sabreauto.dts b/arch/arm/boot/dts/imx6q-arm2.dts index 072974e443f..c3977e0478b 100644 --- a/arch/arm/boot/dts/imx6q-sabreauto.dts +++ b/arch/arm/boot/dts/imx6q-arm2.dts @@ -14,8 +14,8 @@ /include/ "imx6q.dtsi" / { - model = "Freescale i.MX6 Quad SABRE Automotive Board"; - compatible = "fsl,imx6q-sabreauto", "fsl,imx6q"; + model = "Freescale i.MX6 Quad Armadillo2 Board"; + compatible = "fsl,imx6q-arm2", "fsl,imx6q"; chosen { bootargs = "console=ttymxc0,115200 root=/dev/mmcblk3p3 rootwait"; @@ -34,8 +34,8 @@ }; usdhc@02198000 { /* uSDHC3 */ - cd-gpios = <&gpio5 11 0>; /* GPIO6_11 */ - wp-gpios = <&gpio5 14 0>; /* GPIO6_14 */ + cd-gpios = <&gpio6 11 0>; + wp-gpios = <&gpio6 14 0>; status = "okay"; }; @@ -44,7 +44,7 @@ status = "okay"; }; - uart3: uart@021f0000 { /* UART4 */ + uart4: uart@021f0000 { status = "okay"; }; }; @@ -55,7 +55,7 @@ debug-led { label = "Heartbeat"; - gpios = <&gpio2 25 0>; /* GPIO3_25 */ + gpios = <&gpio3 25 0>; linux,default-trigger = "heartbeat"; }; }; diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts new file mode 100644 index 00000000000..08d920de728 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-sabrelite.dts @@ -0,0 +1,49 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "imx6q.dtsi" + +/ { + model = "Freescale i.MX6 Quad SABRE Lite Board"; + compatible = "fsl,imx6q-sabrelite", "fsl,imx6q"; + + memory { + reg = <0x10000000 0x40000000>; + }; + + soc { + aips-bus@02100000 { /* AIPS2 */ + enet@02188000 { + phy-mode = "rgmii"; + phy-reset-gpios = <&gpio3 23 0>; + status = "okay"; + }; + + usdhc@02198000 { /* uSDHC3 */ + cd-gpios = <&gpio7 0 0>; + wp-gpios = <&gpio7 1 0>; + status = "okay"; + }; + + usdhc@0219c000 { /* uSDHC4 */ + cd-gpios = <&gpio2 6 0>; + wp-gpios = <&gpio2 7 0>; + status = "okay"; + }; + + uart2: uart@021e8000 { + status = "okay"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index 7dda599558c..263e8f3664b 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi @@ -14,11 +14,11 @@ / { aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - serial4 = &uart4; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; }; cpus { @@ -165,7 +165,7 @@ status = "disabled"; }; - uart0: uart@02020000 { /* UART1 */ + uart1: uart@02020000 { compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x02020000 0x4000>; interrupts = <0 26 0x04>; @@ -247,7 +247,7 @@ interrupts = <0 55 0x04>; }; - gpio0: gpio@0209c000 { /* GPIO1 */ + gpio1: gpio@0209c000 { compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio"; reg = <0x0209c000 0x4000>; interrupts = <0 66 0x04 0 67 0x04>; @@ -257,7 +257,7 @@ #interrupt-cells = <1>; }; - gpio1: gpio@020a0000 { /* GPIO2 */ + gpio2: gpio@020a0000 { compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio"; reg = <0x020a0000 0x4000>; interrupts = <0 68 0x04 0 69 0x04>; @@ -267,7 +267,7 @@ #interrupt-cells = <1>; }; - gpio2: gpio@020a4000 { /* GPIO3 */ + gpio3: gpio@020a4000 { compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio"; reg = <0x020a4000 0x4000>; interrupts = <0 70 0x04 0 71 0x04>; @@ -277,7 +277,7 @@ #interrupt-cells = <1>; }; - gpio3: gpio@020a8000 { /* GPIO4 */ + gpio4: gpio@020a8000 { compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio"; reg = <0x020a8000 0x4000>; interrupts = <0 72 0x04 0 73 0x04>; @@ -287,7 +287,7 @@ #interrupt-cells = <1>; }; - gpio4: gpio@020ac000 { /* GPIO5 */ + gpio5: gpio@020ac000 { compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio"; reg = <0x020ac000 0x4000>; interrupts = <0 74 0x04 0 75 0x04>; @@ -297,7 +297,7 @@ #interrupt-cells = <1>; }; - gpio5: gpio@020b0000 { /* GPIO6 */ + gpio6: gpio@020b0000 { compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio"; reg = <0x020b0000 0x4000>; interrupts = <0 76 0x04 0 77 0x04>; @@ -307,7 +307,7 @@ #interrupt-cells = <1>; }; - gpio6: gpio@020b4000 { /* GPIO7 */ + gpio7: gpio@020b4000 { compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio"; reg = <0x020b4000 0x4000>; interrupts = <0 78 0x04 0 79 0x04>; @@ -543,28 +543,28 @@ interrupts = <0 18 0x04>; }; - uart1: uart@021e8000 { /* UART2 */ + uart2: uart@021e8000 { compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x021e8000 0x4000>; interrupts = <0 27 0x04>; status = "disabled"; }; - uart2: uart@021ec000 { /* UART3 */ + uart3: uart@021ec000 { compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x021ec000 0x4000>; interrupts = <0 28 0x04>; status = "disabled"; }; - uart3: uart@021f0000 { /* UART4 */ + uart4: uart@021f0000 { compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x021f0000 0x4000>; interrupts = <0 29 0x04>; status = "disabled"; }; - uart4: uart@021f4000 { /* UART5 */ + uart5: uart@021f4000 { compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x021f4000 0x4000>; interrupts = <0 30 0x04>; diff --git a/arch/arm/boot/dts/omap2.dtsi b/arch/arm/boot/dts/omap2.dtsi new file mode 100644 index 00000000000..f2ab4ea7cc0 --- /dev/null +++ b/arch/arm/boot/dts/omap2.dtsi @@ -0,0 +1,67 @@ +/* + * Device Tree Source for OMAP2 SoC + * + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/include/ "skeleton.dtsi" + +/ { + compatible = "ti,omap2430", "ti,omap2420", "ti,omap2"; + + aliases { + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + }; + + cpus { + cpu@0 { + compatible = "arm,arm1136jf-s"; + }; + }; + + soc { + compatible = "ti,omap-infra"; + mpu { + compatible = "ti,omap2-mpu"; + ti,hwmods = "mpu"; + }; + }; + + ocp { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + ti,hwmods = "l3_main"; + + intc: interrupt-controller@1 { + compatible = "ti,omap2-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + + uart1: serial@4806a000 { + compatible = "ti,omap2-uart"; + ti,hwmods = "uart1"; + clock-frequency = <48000000>; + }; + + uart2: serial@4806c000 { + compatible = "ti,omap2-uart"; + ti,hwmods = "uart2"; + clock-frequency = <48000000>; + }; + + uart3: serial@4806e000 { + compatible = "ti,omap2-uart"; + ti,hwmods = "uart3"; + clock-frequency = <48000000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi index d202bb5ec7e..216c3317461 100644 --- a/arch/arm/boot/dts/omap3.dtsi +++ b/arch/arm/boot/dts/omap3.dtsi @@ -13,6 +13,13 @@ / { compatible = "ti,omap3430", "ti,omap3"; + aliases { + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + }; + cpus { cpu@0 { compatible = "arm,cortex-a8"; @@ -59,5 +66,29 @@ interrupt-controller; #interrupt-cells = <1>; }; + + uart1: serial@0x4806a000 { + compatible = "ti,omap3-uart"; + ti,hwmods = "uart1"; + clock-frequency = <48000000>; + }; + + uart2: serial@0x4806c000 { + compatible = "ti,omap3-uart"; + ti,hwmods = "uart2"; + clock-frequency = <48000000>; + }; + + uart3: serial@0x49020000 { + compatible = "ti,omap3-uart"; + ti,hwmods = "uart3"; + clock-frequency = <48000000>; + }; + + uart4: serial@0x49042000 { + compatible = "ti,omap3-uart"; + ti,hwmods = "uart4"; + clock-frequency = <48000000>; + }; }; }; diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 4c61c829043..e8fe75fac7c 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -21,6 +21,10 @@ interrupt-parent = <&gic>; aliases { + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; }; cpus { @@ -99,5 +103,29 @@ reg = <0x48241000 0x1000>, <0x48240100 0x0100>; }; + + uart1: serial@0x4806a000 { + compatible = "ti,omap4-uart"; + ti,hwmods = "uart1"; + clock-frequency = <48000000>; + }; + + uart2: serial@0x4806c000 { + compatible = "ti,omap4-uart"; + ti,hwmods = "uart2"; + clock-frequency = <48000000>; + }; + + uart3: serial@0x48020000 { + compatible = "ti,omap4-uart"; + ti,hwmods = "uart3"; + clock-frequency = <48000000>; + }; + + uart4: serial@0x4806e000 { + compatible = "ti,omap4-uart"; + ti,hwmods = "uart4"; + clock-frequency = <48000000>; + }; }; }; diff --git a/arch/arm/boot/dts/tegra-cardhu.dts b/arch/arm/boot/dts/tegra-cardhu.dts new file mode 100644 index 00000000000..70c41fc897d --- /dev/null +++ b/arch/arm/boot/dts/tegra-cardhu.dts @@ -0,0 +1,36 @@ +/dts-v1/; + +/include/ "tegra30.dtsi" + +/ { + model = "NVIDIA Tegra30 Cardhu evaluation board"; + compatible = "nvidia,cardhu", "nvidia,tegra30"; + + memory { + reg = < 0x80000000 0x40000000 >; + }; + + serial@70006000 { + clock-frequency = < 408000000 >; + }; + + i2c@7000c000 { + clock-frequency = <100000>; + }; + + i2c@7000c400 { + clock-frequency = <100000>; + }; + + i2c@7000c500 { + clock-frequency = <100000>; + }; + + i2c@7000c700 { + clock-frequency = <100000>; + }; + + i2c@7000d000 { + clock-frequency = <100000>; + }; +}; diff --git a/arch/arm/boot/dts/tegra-harmony.dts b/arch/arm/boot/dts/tegra-harmony.dts index 0e225b86b65..80afa1b70b8 100644 --- a/arch/arm/boot/dts/tegra-harmony.dts +++ b/arch/arm/boot/dts/tegra-harmony.dts @@ -1,16 +1,11 @@ /dts-v1/; -/memreserve/ 0x1c000000 0x04000000; /include/ "tegra20.dtsi" / { model = "NVIDIA Tegra2 Harmony evaluation board"; compatible = "nvidia,harmony", "nvidia,tegra20"; - chosen { - bootargs = "vmalloc=192M video=tegrafb console=ttyS0,115200n8 root=/dev/mmcblk0p2 rw rootwait"; - }; - memory@0 { reg = < 0x00000000 0x40000000 >; }; @@ -52,16 +47,40 @@ ext-mic-en-gpios = <&gpio 185 0>; }; + serial@70006000 { + status = "disable"; + }; + + serial@70006040 { + status = "disable"; + }; + + serial@70006200 { + status = "disable"; + }; + serial@70006300 { clock-frequency = < 216000000 >; }; + serial@70006400 { + status = "disable"; + }; + + sdhci@c8000000 { + status = "disable"; + }; + sdhci@c8000200 { cd-gpios = <&gpio 69 0>; /* gpio PI5 */ wp-gpios = <&gpio 57 0>; /* gpio PH1 */ power-gpios = <&gpio 155 0>; /* gpio PT3 */ }; + sdhci@c8000400 { + status = "disable"; + }; + sdhci@c8000600 { cd-gpios = <&gpio 58 0>; /* gpio PH2 */ wp-gpios = <&gpio 59 0>; /* gpio PH3 */ diff --git a/arch/arm/boot/dts/tegra-paz00.dts b/arch/arm/boot/dts/tegra-paz00.dts new file mode 100644 index 00000000000..1a1d7023b69 --- /dev/null +++ b/arch/arm/boot/dts/tegra-paz00.dts @@ -0,0 +1,77 @@ +/dts-v1/; + +/include/ "tegra20.dtsi" + +/ { + model = "Toshiba AC100 / Dynabook AZ"; + compatible = "compal,paz00", "nvidia,tegra20"; + + memory@0 { + reg = <0x00000000 0x20000000>; + }; + + i2c@7000c000 { + clock-frequency = <400000>; + }; + + i2c@7000c400 { + clock-frequency = <400000>; + }; + + i2c@7000c500 { + status = "disable"; + }; + + nvec@7000c500 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,nvec"; + reg = <0x7000C500 0x100>; + interrupts = <0 92 0x04>; + clock-frequency = <80000>; + request-gpios = <&gpio 170 0>; + slave-addr = <138>; + }; + + i2c@7000d000 { + clock-frequency = <400000>; + }; + + serial@70006000 { + clock-frequency = <216000000>; + }; + + serial@70006040 { + status = "disable"; + }; + + serial@70006200 { + status = "disable"; + }; + + serial@70006300 { + clock-frequency = <216000000>; + }; + + serial@70006400 { + status = "disable"; + }; + + sdhci@c8000000 { + cd-gpios = <&gpio 173 0>; /* gpio PV5 */ + wp-gpios = <&gpio 57 0>; /* gpio PH1 */ + power-gpios = <&gpio 155 0>; /* gpio PT3 */ + }; + + sdhci@c8000200 { + status = "disable"; + }; + + sdhci@c8000400 { + status = "disable"; + }; + + sdhci@c8000600 { + support-8bit; + }; +}; diff --git a/arch/arm/boot/dts/tegra-seaboard.dts b/arch/arm/boot/dts/tegra-seaboard.dts index a72299b8e66..b55a02e34ba 100644 --- a/arch/arm/boot/dts/tegra-seaboard.dts +++ b/arch/arm/boot/dts/tegra-seaboard.dts @@ -1,25 +1,65 @@ /dts-v1/; -/memreserve/ 0x1c000000 0x04000000; /include/ "tegra20.dtsi" / { model = "NVIDIA Seaboard"; compatible = "nvidia,seaboard", "nvidia,tegra20"; - chosen { - bootargs = "vmalloc=192M video=tegrafb console=ttyS0,115200n8 root=/dev/mmcblk1p3 rw rootwait"; - }; - memory { device_type = "memory"; reg = < 0x00000000 0x40000000 >; }; + i2c@7000c000 { + clock-frequency = <400000>; + }; + + i2c@7000c400 { + clock-frequency = <400000>; + }; + + i2c@7000c500 { + clock-frequency = <400000>; + }; + + i2c@7000d000 { + clock-frequency = <400000>; + + adt7461@4c { + compatible = "adt7461"; + reg = <0x4c>; + }; + }; + + serial@70006000 { + status = "disable"; + }; + + serial@70006040 { + status = "disable"; + }; + + serial@70006200 { + status = "disable"; + }; + serial@70006300 { clock-frequency = < 216000000 >; }; + serial@70006400 { + status = "disable"; + }; + + sdhci@c8000000 { + status = "disable"; + }; + + sdhci@c8000200 { + status = "disable"; + }; + sdhci@c8000400 { cd-gpios = <&gpio 69 0>; /* gpio PI5 */ wp-gpios = <&gpio 57 0>; /* gpio PH1 */ @@ -29,4 +69,28 @@ sdhci@c8000600 { support-8bit; }; + + usb@c5000000 { + nvidia,vbus-gpio = <&gpio 24 0>; /* PD0 */ + }; + + gpio-keys { + compatible = "gpio-keys"; + + power { + label = "Power"; + gpios = <&gpio 170 1>; /* gpio PV2, active low */ + linux,code = <116>; /* KEY_POWER */ + gpio-key,wakeup; + }; + + lid { + label = "Lid"; + gpios = <&gpio 23 0>; /* gpio PC7 */ + linux,input-type = <5>; /* EV_SW */ + linux,code = <0>; /* SW_LID */ + debounce-interval = <1>; + gpio-key,wakeup; + }; + }; }; diff --git a/arch/arm/boot/dts/tegra-trimslice.dts b/arch/arm/boot/dts/tegra-trimslice.dts new file mode 100644 index 00000000000..3b3ee7db99f --- /dev/null +++ b/arch/arm/boot/dts/tegra-trimslice.dts @@ -0,0 +1,65 @@ +/dts-v1/; + +/include/ "tegra20.dtsi" + +/ { + model = "Compulab TrimSlice board"; + compatible = "compulab,trimslice", "nvidia,tegra20"; + + memory@0 { + reg = < 0x00000000 0x40000000 >; + }; + + i2c@7000c000 { + clock-frequency = <400000>; + }; + + i2c@7000c400 { + clock-frequency = <400000>; + }; + + i2c@7000c500 { + clock-frequency = <400000>; + }; + + i2c@7000d000 { + status = "disable"; + }; + + serial@70006000 { + clock-frequency = < 216000000 >; + }; + + serial@70006040 { + status = "disable"; + }; + + serial@70006200 { + status = "disable"; + }; + + serial@70006300 { + status = "disable"; + }; + + serial@70006400 { + status = "disable"; + }; + + sdhci@c8000000 { + status = "disable"; + }; + + sdhci@c8000200 { + status = "disable"; + }; + + sdhci@c8000400 { + status = "disable"; + }; + + sdhci@c8000600 { + cd-gpios = <&gpio 121 0>; + wp-gpios = <&gpio 122 0>; + }; +}; diff --git a/arch/arm/boot/dts/tegra-ventana.dts b/arch/arm/boot/dts/tegra-ventana.dts index 3f9abd6b696..c7d3b87f29d 100644 --- a/arch/arm/boot/dts/tegra-ventana.dts +++ b/arch/arm/boot/dts/tegra-ventana.dts @@ -1,24 +1,59 @@ /dts-v1/; -/memreserve/ 0x1c000000 0x04000000; /include/ "tegra20.dtsi" / { model = "NVIDIA Tegra2 Ventana evaluation board"; compatible = "nvidia,ventana", "nvidia,tegra20"; - chosen { - bootargs = "vmalloc=192M video=tegrafb console=ttyS0,115200n8 root=/dev/ram rdinit=/sbin/init"; - }; - memory { reg = < 0x00000000 0x40000000 >; }; + i2c@7000c000 { + clock-frequency = <400000>; + }; + + i2c@7000c400 { + clock-frequency = <400000>; + }; + + i2c@7000c500 { + clock-frequency = <400000>; + }; + + i2c@7000d000 { + clock-frequency = <400000>; + }; + + serial@70006000 { + status = "disable"; + }; + + serial@70006040 { + status = "disable"; + }; + + serial@70006200 { + status = "disable"; + }; + serial@70006300 { clock-frequency = < 216000000 >; }; + serial@70006400 { + status = "disable"; + }; + + sdhci@c8000000 { + status = "disable"; + }; + + sdhci@c8000200 { + status = "disable"; + }; + sdhci@c8000400 { cd-gpios = <&gpio 69 0>; /* gpio PI5 */ wp-gpios = <&gpio 57 0>; /* gpio PH1 */ diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 65d7e6a333e..3da7afd4532 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -5,9 +5,9 @@ interrupt-parent = <&intc>; intc: interrupt-controller@50041000 { - compatible = "nvidia,tegra20-gic"; + compatible = "arm,cortex-a9-gic"; interrupt-controller; - #interrupt-cells = <1>; + #interrupt-cells = <3>; reg = < 0x50041000 0x1000 >, < 0x50040100 0x0100 >; }; @@ -17,7 +17,7 @@ #size-cells = <0>; compatible = "nvidia,tegra20-i2c"; reg = <0x7000C000 0x100>; - interrupts = < 70 >; + interrupts = < 0 38 0x04 >; }; i2c@7000c400 { @@ -25,7 +25,7 @@ #size-cells = <0>; compatible = "nvidia,tegra20-i2c"; reg = <0x7000C400 0x100>; - interrupts = < 116 >; + interrupts = < 0 84 0x04 >; }; i2c@7000c500 { @@ -33,38 +33,32 @@ #size-cells = <0>; compatible = "nvidia,tegra20-i2c"; reg = <0x7000C500 0x100>; - interrupts = < 124 >; + interrupts = < 0 92 0x04 >; }; i2c@7000d000 { #address-cells = <1>; #size-cells = <0>; - compatible = "nvidia,tegra20-i2c"; + compatible = "nvidia,tegra20-i2c-dvc"; reg = <0x7000D000 0x200>; - interrupts = < 85 >; + interrupts = < 0 53 0x04 >; }; i2s@70002800 { - #address-cells = <1>; - #size-cells = <0>; compatible = "nvidia,tegra20-i2s"; reg = <0x70002800 0x200>; - interrupts = < 45 >; + interrupts = < 0 13 0x04 >; dma-channel = < 2 >; }; i2s@70002a00 { - #address-cells = <1>; - #size-cells = <0>; compatible = "nvidia,tegra20-i2s"; reg = <0x70002a00 0x200>; - interrupts = < 35 >; + interrupts = < 0 3 0x04 >; dma-channel = < 1 >; }; das@70000c00 { - #address-cells = <1>; - #size-cells = <0>; compatible = "nvidia,tegra20-das"; reg = <0x70000c00 0x80>; }; @@ -72,7 +66,13 @@ gpio: gpio@6000d000 { compatible = "nvidia,tegra20-gpio"; reg = < 0x6000d000 0x1000 >; - interrupts = < 64 65 66 67 87 119 121 >; + interrupts = < 0 32 0x04 + 0 33 0x04 + 0 34 0x04 + 0 35 0x04 + 0 55 0x04 + 0 87 0x04 + 0 89 0x04 >; #gpio-cells = <2>; gpio-controller; }; @@ -89,59 +89,80 @@ compatible = "nvidia,tegra20-uart"; reg = <0x70006000 0x40>; reg-shift = <2>; - interrupts = < 68 >; + interrupts = < 0 36 0x04 >; }; serial@70006040 { compatible = "nvidia,tegra20-uart"; reg = <0x70006040 0x40>; reg-shift = <2>; - interrupts = < 69 >; + interrupts = < 0 37 0x04 >; }; serial@70006200 { compatible = "nvidia,tegra20-uart"; reg = <0x70006200 0x100>; reg-shift = <2>; - interrupts = < 78 >; + interrupts = < 0 46 0x04 >; }; serial@70006300 { compatible = "nvidia,tegra20-uart"; reg = <0x70006300 0x100>; reg-shift = <2>; - interrupts = < 122 >; + interrupts = < 0 90 0x04 >; }; serial@70006400 { compatible = "nvidia,tegra20-uart"; reg = <0x70006400 0x100>; reg-shift = <2>; - interrupts = < 123 >; + interrupts = < 0 91 0x04 >; }; sdhci@c8000000 { compatible = "nvidia,tegra20-sdhci"; reg = <0xc8000000 0x200>; - interrupts = < 46 >; + interrupts = < 0 14 0x04 >; }; sdhci@c8000200 { compatible = "nvidia,tegra20-sdhci"; reg = <0xc8000200 0x200>; - interrupts = < 47 >; + interrupts = < 0 15 0x04 >; }; sdhci@c8000400 { compatible = "nvidia,tegra20-sdhci"; reg = <0xc8000400 0x200>; - interrupts = < 51 >; + interrupts = < 0 19 0x04 >; }; sdhci@c8000600 { compatible = "nvidia,tegra20-sdhci"; reg = <0xc8000600 0x200>; - interrupts = < 63 >; + interrupts = < 0 31 0x04 >; + }; + + usb@c5000000 { + compatible = "nvidia,tegra20-ehci", "usb-ehci"; + reg = <0xc5000000 0x4000>; + interrupts = < 0 20 0x04 >; + phy_type = "utmi"; + }; + + usb@c5004000 { + compatible = "nvidia,tegra20-ehci", "usb-ehci"; + reg = <0xc5004000 0x4000>; + interrupts = < 0 21 0x04 >; + phy_type = "ulpi"; + }; + + usb@c5008000 { + compatible = "nvidia,tegra20-ehci", "usb-ehci"; + reg = <0xc5008000 0x4000>; + interrupts = < 0 97 0x04 >; + phy_type = "utmi"; }; }; diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi new file mode 100644 index 00000000000..ee7db9892e0 --- /dev/null +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -0,0 +1,127 @@ +/include/ "skeleton.dtsi" + +/ { + compatible = "nvidia,tegra30"; + interrupt-parent = <&intc>; + + intc: interrupt-controller@50041000 { + compatible = "arm,cortex-a9-gic"; + interrupt-controller; + #interrupt-cells = <3>; + reg = < 0x50041000 0x1000 >, + < 0x50040100 0x0100 >; + }; + + i2c@7000c000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; + reg = <0x7000C000 0x100>; + interrupts = < 0 38 0x04 >; + }; + + i2c@7000c400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; + reg = <0x7000C400 0x100>; + interrupts = < 0 84 0x04 >; + }; + + i2c@7000c500 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; + reg = <0x7000C500 0x100>; + interrupts = < 0 92 0x04 >; + }; + + i2c@7000c700 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; + reg = <0x7000c700 0x100>; + interrupts = < 0 120 0x04 >; + }; + + i2c@7000d000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; + reg = <0x7000D000 0x100>; + interrupts = < 0 53 0x04 >; + }; + + gpio: gpio@6000d000 { + compatible = "nvidia,tegra30-gpio", "nvidia,tegra20-gpio"; + reg = < 0x6000d000 0x1000 >; + interrupts = < 0 32 0x04 0 33 0x04 0 34 0x04 0 35 0x04 0 55 0x04 0 87 0x04 0 89 0x04 >; + #gpio-cells = <2>; + gpio-controller; + }; + + serial@70006000 { + compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; + reg = <0x70006000 0x40>; + reg-shift = <2>; + interrupts = < 0 36 0x04 >; + }; + + serial@70006040 { + compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; + reg = <0x70006040 0x40>; + reg-shift = <2>; + interrupts = < 0 37 0x04 >; + }; + + serial@70006200 { + compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; + reg = <0x70006200 0x100>; + reg-shift = <2>; + interrupts = < 0 46 0x04 >; + }; + + serial@70006300 { + compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; + reg = <0x70006300 0x100>; + reg-shift = <2>; + interrupts = < 0 90 0x04 >; + }; + + serial@70006400 { + compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; + reg = <0x70006400 0x100>; + reg-shift = <2>; + interrupts = < 0 91 0x04 >; + }; + + sdhci@78000000 { + compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; + reg = <0x78000000 0x200>; + interrupts = < 0 14 0x04 >; + }; + + sdhci@78000200 { + compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; + reg = <0x78000200 0x200>; + interrupts = < 0 15 0x04 >; + }; + + sdhci@78000400 { + compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; + reg = <0x78000400 0x200>; + interrupts = < 0 19 0x04 >; + }; + + sdhci@78000600 { + compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; + reg = <0x78000600 0x200>; + interrupts = < 0 31 0x04 >; + }; + + pinmux: pinmux@70000000 { + compatible = "nvidia,tegra30-pinmux"; + reg = < 0x70000868 0xd0 /* Pad control registers */ + 0x70003000 0x3e0 >; /* Mux registers */ + }; +}; diff --git a/arch/arm/boot/dts/testcases/tests-phandle.dtsi b/arch/arm/boot/dts/testcases/tests-phandle.dtsi new file mode 100644 index 00000000000..ec0c4e6212c --- /dev/null +++ b/arch/arm/boot/dts/testcases/tests-phandle.dtsi @@ -0,0 +1,37 @@ + +/ { + testcase-data { + phandle-tests { + provider0: provider0 { + #phandle-cells = <0>; + }; + + provider1: provider1 { + #phandle-cells = <1>; + }; + + provider2: provider2 { + #phandle-cells = <2>; + }; + + provider3: provider3 { + #phandle-cells = <3>; + }; + + consumer-a { + phandle-list = <&provider1 1>, + <&provider2 2 0>, + <0>, + <&provider3 4 4 3>, + <&provider2 5 100>, + <&provider0>, + <&provider1 7>; + phandle-list-names = "first", "second", "third"; + + phandle-list-bad-phandle = <12345678 0 0>; + phandle-list-bad-args = <&provider2 1 0>, + <&provider3 0>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/testcases/tests.dtsi b/arch/arm/boot/dts/testcases/tests.dtsi new file mode 100644 index 00000000000..a7c5067622e --- /dev/null +++ b/arch/arm/boot/dts/testcases/tests.dtsi @@ -0,0 +1 @@ +/include/ "tests-phandle.dtsi" diff --git a/arch/arm/boot/dts/usb_a9g20.dts b/arch/arm/boot/dts/usb_a9g20.dts index d66e2c00ac3..f04b535477f 100644 --- a/arch/arm/boot/dts/usb_a9g20.dts +++ b/arch/arm/boot/dts/usb_a9g20.dts @@ -25,6 +25,11 @@ dbgu: serial@fffff200 { status = "okay"; }; + + macb0: ethernet@fffc4000 { + phy-mode = "rmii"; + status = "okay"; + }; }; }; }; diff --git a/arch/arm/boot/dts/versatile-pb.dts b/arch/arm/boot/dts/versatile-pb.dts index 8a614e39800..166461073b7 100644 --- a/arch/arm/boot/dts/versatile-pb.dts +++ b/arch/arm/boot/dts/versatile-pb.dts @@ -46,3 +46,5 @@ }; }; }; + +/include/ "testcases/tests.dtsi" diff --git a/arch/arm/common/it8152.c b/arch/arm/common/it8152.c index b539ec855e1..d1bcd7b13eb 100644 --- a/arch/arm/common/it8152.c +++ b/arch/arm/common/it8152.c @@ -299,8 +299,8 @@ int __init it8152_pci_setup(int nr, struct pci_sys_data *sys) goto err1; } - sys->resource[0] = &it8152_io; - sys->resource[1] = &it8152_mem; + pci_add_resource(&sys->resources, &it8152_io); + pci_add_resource(&sys->resources, &it8152_mem); if (platform_notify || platform_notify_remove) { printk(KERN_ERR "PCI: Can't use platform_notify\n"); @@ -327,6 +327,9 @@ err0: */ unsigned int pcibios_max_latency = 255; +/* ITE bridge requires setting latency timer to avoid early bus access + termination by PCI bus master devices +*/ void pcibios_set_master(struct pci_dev *dev) { u8 lat; @@ -352,7 +355,7 @@ void pcibios_set_master(struct pci_dev *dev) struct pci_bus * __init it8152_pci_scan_bus(int nr, struct pci_sys_data *sys) { - return pci_scan_bus(nr, &it8152_ops, sys); + return pci_scan_root_bus(NULL, nr, &it8152_ops, sys, &sys->resources); } EXPORT_SYMBOL(dma_set_coherent_mask); diff --git a/arch/arm/common/via82c505.c b/arch/arm/common/via82c505.c index 8421d39109b..67dd2affc57 100644 --- a/arch/arm/common/via82c505.c +++ b/arch/arm/common/via82c505.c @@ -86,7 +86,8 @@ int __init via82c505_setup(int nr, struct pci_sys_data *sys) struct pci_bus * __init via82c505_scan_bus(int nr, struct pci_sys_data *sysdata) { if (nr == 0) - return pci_scan_bus(0, &via82c505_ops, sysdata); + return pci_scan_root_bus(NULL, 0, &via82c505_ops, sysdata, + &sysdata->resources); return NULL; } diff --git a/arch/arm/configs/bonito_defconfig b/arch/arm/configs/bonito_defconfig new file mode 100644 index 00000000000..54571082d92 --- /dev/null +++ b/arch/arm/configs/bonito_defconfig @@ -0,0 +1,72 @@ +CONFIG_EXPERIMENTAL=y +CONFIG_SYSVIPC=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=16 +# CONFIG_UTS_NS is not set +# CONFIG_IPC_NS is not set +# CONFIG_USER_NS is not set +# CONFIG_PID_NS is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SLAB=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +CONFIG_ARCH_SHMOBILE=y +CONFIG_ARCH_R8A7740=y +CONFIG_MACH_BONITO=y +# CONFIG_SH_TIMER_TMU is not set +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +CONFIG_FORCE_MAX_ZONEORDER=12 +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="console=ttySC5,115200 earlyprintk=sh-sci.5,115200 ignore_loglevel" +CONFIG_KEXEC=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_SUSPEND is not set +CONFIG_PM_RUNTIME=y +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_FIRMWARE_IN_KERNEL is not set +CONFIG_MTD=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_ARM_INTEGRATOR=y +CONFIG_MTD_BLOCK2MTD=y +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y +# CONFIG_SCSI_LOWLEVEL is not set +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_LEGACY_PTYS is not set +CONFIG_SERIAL_SH_SCI=y +CONFIG_SERIAL_SH_SCI_NR_UARTS=9 +CONFIG_SERIAL_SH_SCI_CONSOLE=y +# CONFIG_HW_RANDOM is not set +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_SH_MOBILE=y +CONFIG_GPIO_SYSFS=y +# CONFIG_HWMON is not set +# CONFIG_MFD_SUPPORT is not set +# CONFIG_HID_SUPPORT is not set +# CONFIG_USB_SUPPORT is not set +CONFIG_UIO=y +CONFIG_UIO_PDRV=y +CONFIG_UIO_PDRV_GENIRQ=y +# CONFIG_DNOTIFY is not set +# CONFIG_INOTIFY_USER is not set +CONFIG_TMPFS=y +# CONFIG_MISC_FILESYSTEMS is not set +# CONFIG_ENABLE_WARN_DEPRECATED is not set +# CONFIG_ENABLE_MUST_CHECK is not set +# CONFIG_ARM_UNWIND is not set diff --git a/arch/arm/configs/imx_v4_v5_defconfig b/arch/arm/configs/imx_v4_v5_defconfig index cf497ce41df..a22e9307906 100644 --- a/arch/arm/configs/imx_v4_v5_defconfig +++ b/arch/arm/configs/imx_v4_v5_defconfig @@ -68,7 +68,6 @@ CONFIG_MTD_CFI=y CONFIG_MTD_CFI_ADV_OPTIONS=y CONFIG_MTD_CFI_GEOMETRY=y # CONFIG_MTD_MAP_BANK_WIDTH_1 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set # CONFIG_MTD_CFI_I2 is not set CONFIG_MTD_CFI_INTELEXT=y CONFIG_MTD_PHYSMAP=y diff --git a/arch/arm/configs/kota2_defconfig b/arch/arm/configs/kota2_defconfig new file mode 100644 index 00000000000..b7735d6347a --- /dev/null +++ b/arch/arm/configs/kota2_defconfig @@ -0,0 +1,122 @@ +# CONFIG_ARM_PATCH_PHYS_VIRT is not set +CONFIG_EXPERIMENTAL=y +CONFIG_SYSVIPC=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=16 +CONFIG_CGROUPS=y +CONFIG_CPUSETS=y +CONFIG_NAMESPACES=y +# CONFIG_UTS_NS is not set +# CONFIG_IPC_NS is not set +# CONFIG_USER_NS is not set +# CONFIG_PID_NS is not set +CONFIG_SYSCTL_SYSCALL=y +CONFIG_EMBEDDED=y +CONFIG_SLAB=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +CONFIG_ARCH_SHMOBILE=y +CONFIG_KEYBOARD_GPIO_POLLED=y +CONFIG_ARCH_SH73A0=y +CONFIG_MACH_KOTA2=y +CONFIG_MEMORY_SIZE=0x1e0000000 +# CONFIG_SH_TIMER_TMU is not set +# CONFIG_SWP_EMULATE is not set +CONFIG_CPU_BPREDICT_DISABLE=y +CONFIG_ARM_ERRATA_460075=y +CONFIG_ARM_ERRATA_742230=y +CONFIG_ARM_ERRATA_742231=y +CONFIG_PL310_ERRATA_588369=y +CONFIG_ARM_ERRATA_720789=y +CONFIG_PL310_ERRATA_727915=y +CONFIG_ARM_ERRATA_743622=y +CONFIG_ARM_ERRATA_751472=y +CONFIG_PL310_ERRATA_753970=y +CONFIG_ARM_ERRATA_754322=y +CONFIG_PL310_ERRATA_769419=y +CONFIG_NO_HZ=y +CONFIG_SMP=y +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +CONFIG_HIGHMEM=y +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="console=ttySC2,115200 earlyprintk=sh-sci.2,115200 ignore_loglevel" +CONFIG_CMDLINE_FORCE=y +CONFIG_KEXEC=y +CONFIG_CPU_IDLE=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_PM_RUNTIME=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +# CONFIG_INET_DIAG is not set +# CONFIG_IPV6 is not set +CONFIG_CFG80211=y +CONFIG_WIRELESS_EXT_SYSFS=y +CONFIG_MAC80211=y +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_BLK_DEV is not set +CONFIG_NETDEVICES=y +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CHELSIO is not set +# CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_SEEQ is not set +CONFIG_SMSC911X=y +# CONFIG_NET_VENDOR_STMICRO is not set +CONFIG_B43=y +CONFIG_B43_PHY_N=y +CONFIG_B43_DEBUG=y +CONFIG_INPUT_SPARSEKMAP=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_KEYBOARD_ATKBD is not set +CONFIG_KEYBOARD_GPIO=y +CONFIG_KEYBOARD_SH_KEYSC=y +# CONFIG_INPUT_MOUSE is not set +# CONFIG_LEGACY_PTYS is not set +CONFIG_SERIAL_SH_SCI=y +CONFIG_SERIAL_SH_SCI_NR_UARTS=9 +CONFIG_SERIAL_SH_SCI_CONSOLE=y +# CONFIG_HW_RANDOM is not set +CONFIG_I2C_SH_MOBILE=y +# CONFIG_HWMON is not set +CONFIG_BCMA=y +CONFIG_BCMA_DEBUG=y +CONFIG_FB=y +CONFIG_FB_SH_MOBILE_LCDC=y +CONFIG_LCD_PLATFORM=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +# CONFIG_HID_SUPPORT is not set +# CONFIG_USB_SUPPORT is not set +CONFIG_MMC=y +CONFIG_MMC_SDHI=y +CONFIG_MMC_SH_MMCIF=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_RENESAS_TPU=y +CONFIG_LEDS_TRIGGERS=y +# CONFIG_DNOTIFY is not set +# CONFIG_INOTIFY_USER is not set +CONFIG_TMPFS=y +# CONFIG_MISC_FILESYSTEMS is not set +CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_INFO_REDUCED=y +# CONFIG_FTRACE is not set +CONFIG_DEBUG_USER=y diff --git a/arch/arm/configs/marzen_defconfig b/arch/arm/configs/marzen_defconfig new file mode 100644 index 00000000000..864f9a5c39d --- /dev/null +++ b/arch/arm/configs/marzen_defconfig @@ -0,0 +1,87 @@ +# CONFIG_ARM_PATCH_PHYS_VIRT is not set +CONFIG_EXPERIMENTAL=y +CONFIG_KERNEL_LZMA=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=16 +CONFIG_SYSCTL_SYSCALL=y +CONFIG_EMBEDDED=y +CONFIG_SLAB=y +# CONFIG_BLOCK is not set +CONFIG_ARCH_SHMOBILE=y +CONFIG_ARCH_R8A7779=y +CONFIG_MACH_MARZEN=y +CONFIG_MEMORY_START=0x60000000 +CONFIG_MEMORY_SIZE=0x10000000 +CONFIG_SHMOBILE_TIMER_HZ=1024 +# CONFIG_SH_TIMER_CMT is not set +# CONFIG_SWP_EMULATE is not set +CONFIG_ARM_ERRATA_430973=y +CONFIG_ARM_ERRATA_458693=y +CONFIG_ARM_ERRATA_460075=y +CONFIG_ARM_ERRATA_743622=y +CONFIG_ARM_ERRATA_754322=y +CONFIG_NO_HZ=y +CONFIG_SMP=y +# CONFIG_ARM_CPU_TOPOLOGY is not set +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +CONFIG_HIGHMEM=y +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="console=ttySC2,115200 earlyprintk=sh-sci.2,115200 ignore_loglevel" +CONFIG_CMDLINE_FORCE=y +CONFIG_KEXEC=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_PM_RUNTIME=y +CONFIG_NET=y +CONFIG_INET=y +# CONFIG_IPV6 is not set +# CONFIG_WIRELESS is not set +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_STANDALONE is not set +# CONFIG_PREVENT_FIRMWARE_BUILD is not set +# CONFIG_FW_LOADER is not set +CONFIG_NETDEVICES=y +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_SEEQ is not set +CONFIG_SMC911X=y +CONFIG_SMSC911X=y +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_WLAN is not set +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_SERIO is not set +# CONFIG_VT is not set +# CONFIG_LEGACY_PTYS is not set +# CONFIG_DEVKMEM is not set +CONFIG_SERIAL_SH_SCI=y +CONFIG_SERIAL_SH_SCI_NR_UARTS=6 +CONFIG_SERIAL_SH_SCI_CONSOLE=y +# CONFIG_HW_RANDOM is not set +CONFIG_GPIO_SYSFS=y +# CONFIG_HWMON is not set +CONFIG_SSB=y +# CONFIG_HID_SUPPORT is not set +# CONFIG_USB_SUPPORT is not set +CONFIG_UIO=y +CONFIG_UIO_PDRV_GENIRQ=y +# CONFIG_IOMMU_SUPPORT is not set +# CONFIG_FILE_LOCKING is not set +# CONFIG_DNOTIFY is not set +# CONFIG_INOTIFY_USER is not set +CONFIG_TMPFS=y +# CONFIG_MISC_FILESYSTEMS is not set +CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_INFO_REDUCED=y +# CONFIG_FTRACE is not set +CONFIG_DEBUG_USER=y +CONFIG_AVERAGE=y diff --git a/arch/arm/configs/omap1_defconfig b/arch/arm/configs/omap1_defconfig index 945a34f2a34..dde2a1af7b3 100644 --- a/arch/arm/configs/omap1_defconfig +++ b/arch/arm/configs/omap1_defconfig @@ -48,7 +48,6 @@ CONFIG_MACH_SX1=y CONFIG_MACH_NOKIA770=y CONFIG_MACH_AMS_DELTA=y CONFIG_MACH_OMAP_GENERIC=y -CONFIG_OMAP_ARM_182MHZ=y # CONFIG_ARM_THUMB is not set CONFIG_PCCARD=y CONFIG_OMAP_CF=y diff --git a/arch/arm/configs/pcontrol_g20_defconfig b/arch/arm/configs/pcontrol_g20_defconfig deleted file mode 100644 index c75c9fcede5..00000000000 --- a/arch/arm/configs/pcontrol_g20_defconfig +++ /dev/null @@ -1,175 +0,0 @@ -CONFIG_EXPERIMENTAL=y -CONFIG_CROSS_COMPILE="/opt/arm-2010q1/bin/arm-none-linux-gnueabi-" -# CONFIG_LOCALVERSION_AUTO is not set -# CONFIG_SWAP is not set -CONFIG_SYSVIPC=y -CONFIG_POSIX_MQUEUE=y -CONFIG_TREE_PREEMPT_RCU=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_NAMESPACES=y -CONFIG_BLK_DEV_INITRD=y -CONFIG_EXPERT=y -# CONFIG_SYSCTL_SYSCALL is not set -# CONFIG_KALLSYMS is not set -# CONFIG_VM_EVENT_COUNTERS is not set -# CONFIG_COMPAT_BRK is not set -CONFIG_SLAB=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_LBDAF is not set -# CONFIG_BLK_DEV_BSG is not set -CONFIG_DEFAULT_DEADLINE=y -CONFIG_ARCH_AT91=y -CONFIG_ARCH_AT91SAM9G20=y -CONFIG_MACH_PCONTROL_G20=y -CONFIG_AT91_PROGRAMMABLE_CLOCKS=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_PREEMPT=y -CONFIG_AEABI=y -# CONFIG_OABI_COMPAT is not set -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE="console=ttyS0,115200 mem=128M mtdparts=atmel_nand:128k(bootstrap)ro,256k(uboot)ro,128k(env1)ro,128k(env2)ro,2M(linux),-(root) root=/dev/mmcblk0p1 rootwait rw" -CONFIG_VFP=y -CONFIG_BINFMT_MISC=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET_XFRM_MODE_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_LRO is not set -# CONFIG_IPV6 is not set -CONFIG_VLAN_8021Q=y -# CONFIG_WIRELESS is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -# CONFIG_FW_LOADER is not set -CONFIG_MTD=y -CONFIG_MTD_PARTITIONS=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_CHAR=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_COMPLEX_MAPPINGS=y -CONFIG_MTD_PHRAM=m -CONFIG_MTD_NAND=y -CONFIG_MTD_NAND_ATMEL=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=8192 -CONFIG_ATMEL_TCLIB=y -CONFIG_EEPROM_AT24=m -CONFIG_SCSI=m -# CONFIG_SCSI_PROC_FS is not set -CONFIG_BLK_DEV_SD=m -CONFIG_SCSI_MULTI_LUN=y -# CONFIG_SCSI_LOWLEVEL is not set -CONFIG_NETDEVICES=y -CONFIG_MACVLAN=m -CONFIG_TUN=m -CONFIG_SMSC_PHY=m -CONFIG_BROADCOM_PHY=m -CONFIG_NET_ETHERNET=y -CONFIG_MII=y -CONFIG_MACB=y -CONFIG_SMSC911X=m -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set -# CONFIG_WLAN is not set -CONFIG_PPP=m -CONFIG_PPP_ASYNC=m -CONFIG_PPP_DEFLATE=m -CONFIG_PPP_MPPE=m -CONFIG_INPUT_POLLDEV=y -CONFIG_INPUT_SPARSEKMAP=y -# CONFIG_INPUT_MOUSEDEV is not set -CONFIG_INPUT_EVDEV=m -CONFIG_INPUT_EVBUG=m -# CONFIG_KEYBOARD_ATKBD is not set -CONFIG_KEYBOARD_GPIO=m -CONFIG_KEYBOARD_MATRIX=m -# CONFIG_INPUT_MOUSE is not set -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_INPUT_MISC=y -CONFIG_INPUT_UINPUT=m -CONFIG_INPUT_GPIO_ROTARY_ENCODER=m -# CONFIG_SERIO is not set -# CONFIG_DEVKMEM is not set -CONFIG_SERIAL_ATMEL=y -CONFIG_SERIAL_ATMEL_CONSOLE=y -CONFIG_SERIAL_MAX3100=m -# CONFIG_LEGACY_PTYS is not set -# CONFIG_HW_RANDOM is not set -CONFIG_R3964=m -CONFIG_I2C=m -CONFIG_I2C_CHARDEV=m -# CONFIG_I2C_HELPER_AUTO is not set -CONFIG_I2C_GPIO=m -CONFIG_SPI=y -CONFIG_SPI_ATMEL=m -CONFIG_SPI_SPIDEV=m -CONFIG_GPIO_SYSFS=y -CONFIG_W1=m -CONFIG_W1_MASTER_GPIO=m -CONFIG_W1_SLAVE_DS2431=m -# CONFIG_HWMON is not set -CONFIG_WATCHDOG=y -CONFIG_AT91SAM9X_WATCHDOG=y -# CONFIG_MFD_SUPPORT is not set -# CONFIG_HID_SUPPORT is not set -CONFIG_USB=y -# CONFIG_USB_DEVICE_CLASS is not set -CONFIG_USB_OHCI_HCD=y -CONFIG_USB_STORAGE=m -CONFIG_USB_LIBUSUAL=y -CONFIG_USB_SERIAL=m -CONFIG_USB_SERIAL_GENERIC=y -CONFIG_USB_SERIAL_FTDI_SIO=m -CONFIG_USB_SERIAL_PL2303=m -CONFIG_USB_GADGET=y -CONFIG_USB_ZERO=m -CONFIG_USB_ETH=m -CONFIG_USB_FILE_STORAGE=m -CONFIG_USB_G_SERIAL=m -CONFIG_USB_G_HID=m -CONFIG_MMC=y -CONFIG_MMC_UNSAFE_RESUME=y -CONFIG_MMC_ATMELMCI=y -CONFIG_NEW_LEDS=y -CONFIG_LEDS_CLASS=y -CONFIG_LEDS_GPIO=y -CONFIG_LEDS_TRIGGERS=y -CONFIG_LEDS_TRIGGER_TIMER=y -CONFIG_LEDS_TRIGGER_HEARTBEAT=y -CONFIG_LEDS_TRIGGER_DEFAULT_ON=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_AT91SAM9=y -CONFIG_AUXDISPLAY=y -CONFIG_UIO=y -CONFIG_UIO_PDRV=y -CONFIG_STAGING=y -# CONFIG_STAGING_EXCLUDE_BUILD is not set -CONFIG_IIO=y -CONFIG_EXT2_FS=y -CONFIG_EXT3_FS=y -# CONFIG_EXT3_FS_XATTR is not set -CONFIG_VFAT_FS=y -CONFIG_TMPFS=y -CONFIG_JFFS2_FS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_NFS_V4=y -CONFIG_PARTITION_ADVANCED=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_CODEPAGE_850=y -CONFIG_NLS_ISO8859_1=y -CONFIG_NLS_ISO8859_15=y -CONFIG_NLS_UTF8=y -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -CONFIG_CRYPTO=y -CONFIG_CRYPTO_ANSI_CPRNG=y -# CONFIG_CRYPTO_HW is not set -CONFIG_CRC_CCITT=y diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig index 195729760ae..fd5d3041d71 100644 --- a/arch/arm/configs/tegra_defconfig +++ b/arch/arm/configs/tegra_defconfig @@ -9,9 +9,8 @@ CONFIG_RESOURCE_COUNTERS=y CONFIG_CGROUP_SCHED=y CONFIG_RT_GROUP_SCHED=y CONFIG_BLK_DEV_INITRD=y -CONFIG_EMBEDDED=y -# CONFIG_SYSCTL_SYSCALL is not set # CONFIG_ELF_CORE is not set +CONFIG_EMBEDDED=y CONFIG_SLAB=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y @@ -20,6 +19,8 @@ CONFIG_MODULE_FORCE_UNLOAD=y # CONFIG_IOSCHED_DEADLINE is not set # CONFIG_IOSCHED_CFQ is not set CONFIG_ARCH_TEGRA=y +CONFIG_ARCH_TEGRA_2x_SOC=y +CONFIG_ARCH_TEGRA_3x_SOC=y CONFIG_MACH_HARMONY=y CONFIG_MACH_KAEN=y CONFIG_MACH_PAZ00=y @@ -78,14 +79,12 @@ CONFIG_BLK_DEV_SD=y # CONFIG_SCSI_LOWLEVEL is not set CONFIG_NETDEVICES=y CONFIG_DUMMY=y -CONFIG_NET_ETHERNET=y CONFIG_R8169=y -# CONFIG_NETDEV_10000 is not set -# CONFIG_WLAN is not set CONFIG_USB_PEGASUS=y CONFIG_USB_USBNET=y CONFIG_USB_NET_SMSC75XX=y CONFIG_USB_NET_SMSC95XX=y +# CONFIG_WLAN is not set # CONFIG_INPUT is not set # CONFIG_SERIO is not set # CONFIG_VT is not set diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h index 065d100fa63..9275828feb3 100644 --- a/arch/arm/include/asm/io.h +++ b/arch/arm/include/asm/io.h @@ -27,6 +27,7 @@ #include <asm/byteorder.h> #include <asm/memory.h> #include <asm/system.h> +#include <asm-generic/pci_iomap.h> /* * ISA I/O bus memory addresses are 1:1 with the physical address. @@ -306,7 +307,6 @@ extern void ioport_unmap(void __iomem *addr); struct pci_dev; -extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen); extern void pci_iounmap(struct pci_dev *dev, void __iomem *addr); /* diff --git a/arch/arm/include/asm/ipcbuf.h b/arch/arm/include/asm/ipcbuf.h index 97683975f7d..84c7e51cb6d 100644 --- a/arch/arm/include/asm/ipcbuf.h +++ b/arch/arm/include/asm/ipcbuf.h @@ -1,29 +1 @@ -#ifndef __ASMARM_IPCBUF_H -#define __ASMARM_IPCBUF_H - -/* - * The ipc64_perm structure for arm architecture. - * Note extra padding because this structure is passed back and forth - * between kernel and user space. - * - * Pad space is left for: - * - 32-bit mode_t and seq - * - 2 miscellaneous 32-bit values - */ - -struct ipc64_perm -{ - __kernel_key_t key; - __kernel_uid32_t uid; - __kernel_gid32_t gid; - __kernel_uid32_t cuid; - __kernel_gid32_t cgid; - __kernel_mode_t mode; - unsigned short __pad1; - unsigned short seq; - unsigned short __pad2; - unsigned long __unused1; - unsigned long __unused2; -}; - -#endif /* __ASMARM_IPCBUF_H */ +#include <asm-generic/ipcbuf.h> diff --git a/arch/arm/include/asm/mach/arch.h b/arch/arm/include/asm/mach/arch.h index bcb0c883e21..d7692cafde7 100644 --- a/arch/arm/include/asm/mach/arch.h +++ b/arch/arm/include/asm/mach/arch.h @@ -19,7 +19,7 @@ struct machine_desc { unsigned int nr; /* architecture number */ const char *name; /* architecture name */ unsigned long atag_offset; /* tagged list (relative) */ - const char **dt_compat; /* array of device tree + const char *const *dt_compat; /* array of device tree * 'compatible' strings */ unsigned int nr_irqs; /* number of IRQs */ diff --git a/arch/arm/include/asm/mach/pci.h b/arch/arm/include/asm/mach/pci.h index 186efd4e05c..d943b7d20f1 100644 --- a/arch/arm/include/asm/mach/pci.h +++ b/arch/arm/include/asm/mach/pci.h @@ -40,7 +40,7 @@ struct pci_sys_data { u64 mem_offset; /* bus->cpu memory mapping offset */ unsigned long io_offset; /* bus->cpu IO mapping offset */ struct pci_bus *bus; /* PCI bus */ - struct resource *resource[3]; /* Primary PCI bus resources */ + struct list_head resources; /* root bus resources (apertures) */ /* Bridge swizzling */ u8 (*swizzle)(struct pci_dev *, u8 *); /* IRQ mapping */ diff --git a/arch/arm/include/asm/mach/time.h b/arch/arm/include/asm/mach/time.h index d5adaae5ee2..f73c908b7fa 100644 --- a/arch/arm/include/asm/mach/time.h +++ b/arch/arm/include/asm/mach/time.h @@ -10,8 +10,6 @@ #ifndef __ASM_ARM_MACH_TIME_H #define __ASM_ARM_MACH_TIME_H -#include <linux/sysdev.h> - /* * This is our kernel timer structure. * diff --git a/arch/arm/include/asm/pci.h b/arch/arm/include/asm/pci.h index 2b1f245db0c..da337ba57ff 100644 --- a/arch/arm/include/asm/pci.h +++ b/arch/arm/include/asm/pci.h @@ -31,18 +31,6 @@ static inline int pci_proc_domain(struct pci_bus *bus) } #endif /* CONFIG_PCI_DOMAINS */ -#ifdef CONFIG_PCI_HOST_ITE8152 -/* ITE bridge requires setting latency timer to avoid early bus access - termination by PIC bus mater devices -*/ -extern void pcibios_set_master(struct pci_dev *dev); -#else -static inline void pcibios_set_master(struct pci_dev *dev) -{ - /* No special bus mastering setup handling */ -} -#endif - static inline void pcibios_penalize_isa_irq(int irq, int active) { /* We don't do dynamic PCI IRQ allocation */ diff --git a/arch/arm/include/asm/prom.h b/arch/arm/include/asm/prom.h index 6f65ca86a5e..ee036330791 100644 --- a/arch/arm/include/asm/prom.h +++ b/arch/arm/include/asm/prom.h @@ -13,7 +13,6 @@ #ifdef CONFIG_OF -#include <asm/setup.h> #include <asm/irq.h> extern struct machine_desc *setup_machine_fdt(unsigned int dt_phys); diff --git a/arch/arm/include/asm/thread_info.h b/arch/arm/include/asm/thread_info.h index 7b5cc8dae06..0f30c3a78fc 100644 --- a/arch/arm/include/asm/thread_info.h +++ b/arch/arm/include/asm/thread_info.h @@ -142,7 +142,6 @@ extern void vfp_flush_hwstate(struct thread_info *); #define TIF_POLLING_NRFLAG 16 #define TIF_USING_IWMMXT 17 #define TIF_MEMDIE 18 /* is terminating due to OOM killer */ -#define TIF_FREEZE 19 #define TIF_RESTORE_SIGMASK 20 #define TIF_SECCOMP 21 @@ -152,7 +151,6 @@ extern void vfp_flush_hwstate(struct thread_info *); #define _TIF_SYSCALL_TRACE (1 << TIF_SYSCALL_TRACE) #define _TIF_POLLING_NRFLAG (1 << TIF_POLLING_NRFLAG) #define _TIF_USING_IWMMXT (1 << TIF_USING_IWMMXT) -#define _TIF_FREEZE (1 << TIF_FREEZE) #define _TIF_RESTORE_SIGMASK (1 << TIF_RESTORE_SIGMASK) #define _TIF_SECCOMP (1 << TIF_SECCOMP) diff --git a/arch/arm/include/asm/types.h b/arch/arm/include/asm/types.h index 48192ac3a23..28beab917ff 100644 --- a/arch/arm/include/asm/types.h +++ b/arch/arm/include/asm/types.h @@ -3,12 +3,6 @@ #include <asm-generic/int-ll64.h> -#ifndef __ASSEMBLY__ - -typedef unsigned short umode_t; - -#endif /* __ASSEMBLY__ */ - /* * These aren't exported outside the kernel to avoid name space clashes */ diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c index b530e9116a0..f58ba358990 100644 --- a/arch/arm/kernel/bios32.c +++ b/arch/arm/kernel/bios32.c @@ -316,21 +316,6 @@ pdev_fixup_device_resources(struct pci_sys_data *root, struct pci_dev *dev) } } -static void __devinit -pbus_assign_bus_resources(struct pci_bus *bus, struct pci_sys_data *root) -{ - struct pci_dev *dev = bus->self; - int i; - - if (!dev) { - /* - * Assign root bus resources. - */ - for (i = 0; i < 3; i++) - bus->resource[i] = root->resource[i]; - } -} - /* * pcibios_fixup_bus - Called after each bus is probed, * but before its children are examined. @@ -341,8 +326,6 @@ void pcibios_fixup_bus(struct pci_bus *bus) struct pci_dev *dev; u16 features = PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_FAST_BACK; - pbus_assign_bus_resources(bus, root); - /* * Walk the devices on this bus, working out what we can * and can't support. @@ -508,12 +491,18 @@ static void __init pcibios_init_hw(struct hw_pci *hw) sys->busnr = busnr; sys->swizzle = hw->swizzle; sys->map_irq = hw->map_irq; - sys->resource[0] = &ioport_resource; - sys->resource[1] = &iomem_resource; + INIT_LIST_HEAD(&sys->resources); ret = hw->setup(nr, sys); if (ret > 0) { + if (list_empty(&sys->resources)) { + pci_add_resource(&sys->resources, + &ioport_resource); + pci_add_resource(&sys->resources, + &iomem_resource); + } + sys->bus = hw->scan(nr, sys); if (!sys->bus) @@ -571,6 +560,13 @@ void __init pci_common_init(struct hw_pci *hw) } } +#ifndef CONFIG_PCI_HOST_ITE8152 +void pcibios_set_master(struct pci_dev *dev) +{ + /* No special bus mastering setup handling */ +} +#endif + char * __init pcibios_setup(char *str) { if (!strcmp(str, "debug")) { diff --git a/arch/arm/kernel/leds.c b/arch/arm/kernel/leds.c index 0bcd3834157..1911dae19e4 100644 --- a/arch/arm/kernel/leds.c +++ b/arch/arm/kernel/leds.c @@ -9,7 +9,7 @@ */ #include <linux/export.h> #include <linux/init.h> -#include <linux/sysdev.h> +#include <linux/device.h> #include <linux/syscore_ops.h> #include <linux/string.h> @@ -34,8 +34,8 @@ static const struct leds_evt_name evt_names[] = { { "red", led_red_on, led_red_off }, }; -static ssize_t leds_store(struct sys_device *dev, - struct sysdev_attribute *attr, +static ssize_t leds_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t size) { int ret = -EINVAL, len = strcspn(buf, " "); @@ -69,15 +69,16 @@ static ssize_t leds_store(struct sys_device *dev, return ret; } -static SYSDEV_ATTR(event, 0200, NULL, leds_store); +static DEVICE_ATTR(event, 0200, NULL, leds_store); -static struct sysdev_class leds_sysclass = { +static struct bus_type leds_subsys = { .name = "leds", + .dev_name = "leds", }; -static struct sys_device leds_device = { +static struct device leds_device = { .id = 0, - .cls = &leds_sysclass, + .bus = &leds_subsys, }; static int leds_suspend(void) @@ -105,11 +106,11 @@ static struct syscore_ops leds_syscore_ops = { static int __init leds_init(void) { int ret; - ret = sysdev_class_register(&leds_sysclass); + ret = subsys_system_register(&leds_subsys, NULL); if (ret == 0) - ret = sysdev_register(&leds_device); + ret = device_register(&leds_device); if (ret == 0) - ret = sysdev_create_file(&leds_device, &attr_event); + ret = device_create_file(&leds_device, &dev_attr_event); if (ret == 0) register_syscore_ops(&leds_syscore_ops); return ret; diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index d111c3e9924..4f991f29528 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -3,6 +3,12 @@ if ARCH_AT91 config HAVE_AT91_DATAFLASH_CARD bool +config HAVE_AT91_DBGU0 + bool + +config HAVE_AT91_DBGU1 + bool + config HAVE_AT91_USART3 bool @@ -21,12 +27,14 @@ config ARCH_AT91RM9200 bool "AT91RM9200" select CPU_ARM920T select GENERIC_CLOCKEVENTS + select HAVE_AT91_DBGU0 select HAVE_AT91_USART3 config ARCH_AT91SAM9260 bool "AT91SAM9260 or AT91SAM9XE" select CPU_ARM926T select GENERIC_CLOCKEVENTS + select HAVE_AT91_DBGU0 select HAVE_AT91_USART3 select HAVE_AT91_USART4 select HAVE_AT91_USART5 @@ -37,11 +45,13 @@ config ARCH_AT91SAM9261 select CPU_ARM926T select GENERIC_CLOCKEVENTS select HAVE_FB_ATMEL + select HAVE_AT91_DBGU0 config ARCH_AT91SAM9G10 bool "AT91SAM9G10" select CPU_ARM926T select GENERIC_CLOCKEVENTS + select HAVE_AT91_DBGU0 select HAVE_FB_ATMEL config ARCH_AT91SAM9263 @@ -50,6 +60,7 @@ config ARCH_AT91SAM9263 select GENERIC_CLOCKEVENTS select HAVE_FB_ATMEL select HAVE_NET_MACB + select HAVE_AT91_DBGU1 config ARCH_AT91SAM9RL bool "AT91SAM9RL" @@ -57,11 +68,13 @@ config ARCH_AT91SAM9RL select GENERIC_CLOCKEVENTS select HAVE_AT91_USART3 select HAVE_FB_ATMEL + select HAVE_AT91_DBGU0 config ARCH_AT91SAM9G20 bool "AT91SAM9G20" select CPU_ARM926T select GENERIC_CLOCKEVENTS + select HAVE_AT91_DBGU0 select HAVE_AT91_USART3 select HAVE_AT91_USART4 select HAVE_AT91_USART5 @@ -74,6 +87,7 @@ config ARCH_AT91SAM9G45 select HAVE_AT91_USART3 select HAVE_FB_ATMEL select HAVE_NET_MACB + select HAVE_AT91_DBGU1 config ARCH_AT91CAP9 bool "AT91CAP9" @@ -81,6 +95,7 @@ config ARCH_AT91CAP9 select GENERIC_CLOCKEVENTS select HAVE_FB_ATMEL select HAVE_NET_MACB + select HAVE_AT91_DBGU1 config ARCH_AT91X40 bool "AT91x40" @@ -510,8 +525,13 @@ config AT91_TIMER_HZ choice prompt "Select a UART for early kernel messages" -config AT91_EARLY_DBGU - bool "DBGU" +config AT91_EARLY_DBGU0 + bool "DBGU on rm9200, 9260/9g20, 9261/9g10 and 9rl" + depends on HAVE_AT91_DBGU0 + +config AT91_EARLY_DBGU1 + bool "DBGU on 9263, 9g45 and cap9" + depends on HAVE_AT91_DBGU1 config AT91_EARLY_USART0 bool "USART0" diff --git a/arch/arm/mach-at91/at91cap9.c b/arch/arm/mach-at91/at91cap9.c index 29373397d2d..edb879ac04c 100644 --- a/arch/arm/mach-at91/at91cap9.c +++ b/arch/arm/mach-at91/at91cap9.c @@ -13,7 +13,6 @@ */ #include <linux/module.h> -#include <linux/pm.h> #include <asm/irq.h> #include <asm/mach/arch.h> @@ -23,11 +22,11 @@ #include <mach/at91cap9.h> #include <mach/at91_pmc.h> #include <mach/at91_rstc.h> -#include <mach/at91_shdwc.h> #include "soc.h" #include "generic.h" #include "clock.h" +#include "sam9_smc.h" /* -------------------------------------------------------------------- * Clocks @@ -137,7 +136,7 @@ static struct clk pwm_clk = { .type = CLK_TYPE_PERIPHERAL, }; static struct clk macb_clk = { - .name = "macb_clk", + .name = "pclk", .pmc_mask = 1 << AT91CAP9_ID_EMAC, .type = CLK_TYPE_PERIPHERAL, }; @@ -210,6 +209,8 @@ static struct clk *periph_clocks[] __initdata = { }; static struct clk_lookup periph_clocks_lookups[] = { + /* One additional fake clock for macb_hclk */ + CLKDEV_CON_ID("hclk", &macb_clk), CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk), CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk), CLKDEV_CON_DEV_ID("mci_clk", "at91_mci.0", &mmc0_clk), @@ -221,6 +222,10 @@ static struct clk_lookup periph_clocks_lookups[] = { CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk), /* fake hclk clock */ CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk), + CLKDEV_CON_ID("pioA", &pioABCD_clk), + CLKDEV_CON_ID("pioB", &pioABCD_clk), + CLKDEV_CON_ID("pioC", &pioABCD_clk), + CLKDEV_CON_ID("pioD", &pioABCD_clk), }; static struct clk_lookup usart_clocks_lookups[] = { @@ -293,23 +298,19 @@ void __init at91cap9_set_console_clock(int id) * GPIO * -------------------------------------------------------------------- */ -static struct at91_gpio_bank at91cap9_gpio[] = { +static struct at91_gpio_bank at91cap9_gpio[] __initdata = { { .id = AT91CAP9_ID_PIOABCD, - .offset = AT91_PIOA, - .clock = &pioABCD_clk, + .regbase = AT91CAP9_BASE_PIOA, }, { .id = AT91CAP9_ID_PIOABCD, - .offset = AT91_PIOB, - .clock = &pioABCD_clk, + .regbase = AT91CAP9_BASE_PIOB, }, { .id = AT91CAP9_ID_PIOABCD, - .offset = AT91_PIOC, - .clock = &pioABCD_clk, + .regbase = AT91CAP9_BASE_PIOC, }, { .id = AT91CAP9_ID_PIOABCD, - .offset = AT91_PIOD, - .clock = &pioABCD_clk, + .regbase = AT91CAP9_BASE_PIOD, } }; @@ -318,12 +319,6 @@ static void at91cap9_restart(char mode, const char *cmd) at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST); } -static void at91cap9_poweroff(void) -{ - at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW); -} - - /* -------------------------------------------------------------------- * AT91CAP9 processor initialization * -------------------------------------------------------------------- */ @@ -333,10 +328,16 @@ static void __init at91cap9_map_io(void) at91_init_sram(0, AT91CAP9_SRAM_BASE, AT91CAP9_SRAM_SIZE); } +static void __init at91cap9_ioremap_registers(void) +{ + at91_ioremap_shdwc(AT91CAP9_BASE_SHDWC); + at91sam926x_ioremap_pit(AT91CAP9_BASE_PIT); + at91sam9_ioremap_smc(0, AT91CAP9_BASE_SMC); +} + static void __init at91cap9_initialize(void) { arm_pm_restart = at91cap9_restart; - pm_power_off = at91cap9_poweroff; at91_extern_irq = (1 << AT91CAP9_ID_IRQ0) | (1 << AT91CAP9_ID_IRQ1); /* Register GPIO subsystem */ @@ -394,6 +395,7 @@ static unsigned int at91cap9_default_irq_priority[NR_AIC_IRQS] __initdata = { struct at91_init_soc __initdata at91cap9_soc = { .map_io = at91cap9_map_io, .default_irq_priority = at91cap9_default_irq_priority, + .ioremap_registers = at91cap9_ioremap_registers, .register_clocks = at91cap9_register_clocks, .init = at91cap9_initialize, }; diff --git a/arch/arm/mach-at91/at91cap9_devices.c b/arch/arm/mach-at91/at91cap9_devices.c index adad70db70e..d298fb7cb21 100644 --- a/arch/arm/mach-at91/at91cap9_devices.c +++ b/arch/arm/mach-at91/at91cap9_devices.c @@ -76,7 +76,7 @@ void __init at91_add_device_usbh(struct at91_usbh_data *data) /* Enable VBus control for UHP ports */ for (i = 0; i < data->ports; i++) { - if (data->vbus_pin[i]) + if (gpio_is_valid(data->vbus_pin[i])) at91_set_gpio_output(data->vbus_pin[i], 0); } @@ -179,7 +179,7 @@ void __init at91_add_device_usba(struct usba_platform_data *data) usba_udc_data.pdata.num_ep = ARRAY_SIZE(usba_udc_ep); memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep)); - if (data && data->vbus_pin > 0) { + if (data && gpio_is_valid(data->vbus_pin)) { at91_set_gpio_input(data->vbus_pin, 0); at91_set_deglitch(data->vbus_pin, 1); usba_udc_data.pdata.vbus_pin = data->vbus_pin; @@ -200,7 +200,7 @@ void __init at91_add_device_usba(struct usba_platform_data *data) {} #if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE) static u64 eth_dmamask = DMA_BIT_MASK(32); -static struct at91_eth_data eth_data; +static struct macb_platform_data eth_data; static struct resource eth_resources[] = { [0] = { @@ -227,12 +227,12 @@ static struct platform_device at91cap9_eth_device = { .num_resources = ARRAY_SIZE(eth_resources), }; -void __init at91_add_device_eth(struct at91_eth_data *data) +void __init at91_add_device_eth(struct macb_platform_data *data) { if (!data) return; - if (data->phy_irq_pin) { + if (gpio_is_valid(data->phy_irq_pin)) { at91_set_gpio_input(data->phy_irq_pin, 0); at91_set_deglitch(data->phy_irq_pin, 1); } @@ -264,7 +264,7 @@ void __init at91_add_device_eth(struct at91_eth_data *data) platform_device_register(&at91cap9_eth_device); } #else -void __init at91_add_device_eth(struct at91_eth_data *data) {} +void __init at91_add_device_eth(struct macb_platform_data *data) {} #endif @@ -332,13 +332,13 @@ void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) return; /* input/irq */ - if (data->det_pin) { + if (gpio_is_valid(data->det_pin)) { at91_set_gpio_input(data->det_pin, 1); at91_set_deglitch(data->det_pin, 1); } - if (data->wp_pin) + if (gpio_is_valid(data->wp_pin)) at91_set_gpio_input(data->wp_pin, 1); - if (data->vcc_pin) + if (gpio_is_valid(data->vcc_pin)) at91_set_gpio_output(data->vcc_pin, 0); if (mmc_id == 0) { /* MCI0 */ @@ -398,8 +398,8 @@ static struct resource nand_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = AT91_BASE_SYS + AT91_ECC, - .end = AT91_BASE_SYS + AT91_ECC + SZ_512 - 1, + .start = AT91CAP9_BASE_ECC, + .end = AT91CAP9_BASE_ECC + SZ_512 - 1, .flags = IORESOURCE_MEM, } }; @@ -425,15 +425,15 @@ void __init at91_add_device_nand(struct atmel_nand_data *data) at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA); /* enable pin */ - if (data->enable_pin) + if (gpio_is_valid(data->enable_pin)) at91_set_gpio_output(data->enable_pin, 1); /* ready/busy pin */ - if (data->rdy_pin) + if (gpio_is_valid(data->rdy_pin)) at91_set_gpio_input(data->rdy_pin, 1); /* card detect pin */ - if (data->det_pin) + if (gpio_is_valid(data->det_pin)) at91_set_gpio_input(data->det_pin, 1); nand_data = *data; @@ -670,8 +670,8 @@ static void __init at91_add_device_tc(void) { } static struct resource rtt_resources[] = { { - .start = AT91_BASE_SYS + AT91_RTT, - .end = AT91_BASE_SYS + AT91_RTT + SZ_16 - 1, + .start = AT91CAP9_BASE_RTT, + .end = AT91CAP9_BASE_RTT + SZ_16 - 1, .flags = IORESOURCE_MEM, } }; @@ -694,10 +694,19 @@ static void __init at91_add_device_rtt(void) * -------------------------------------------------------------------- */ #if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE) +static struct resource wdt_resources[] = { + { + .start = AT91CAP9_BASE_WDT, + .end = AT91CAP9_BASE_WDT + SZ_16 - 1, + .flags = IORESOURCE_MEM, + } +}; + static struct platform_device at91cap9_wdt_device = { .name = "at91_wdt", .id = -1, - .num_resources = 0, + .resource = wdt_resources, + .num_resources = ARRAY_SIZE(wdt_resources), }; static void __init at91_add_device_watchdog(void) @@ -807,7 +816,7 @@ void __init at91_add_device_ac97(struct ac97c_platform_data *data) at91_set_A_periph(AT91_PIN_PA9, 0); /* AC97RX */ /* reset */ - if (data->reset_pin) + if (gpio_is_valid(data->reset_pin)) at91_set_gpio_output(data->reset_pin, 0); ac97_data = *data; @@ -1021,8 +1030,8 @@ void __init at91_add_device_ssc(unsigned id, unsigned pins) {} #if defined(CONFIG_SERIAL_ATMEL) static struct resource dbgu_resources[] = { [0] = { - .start = AT91_BASE_SYS + AT91_DBGU, - .end = AT91_BASE_SYS + AT91_DBGU + SZ_512 - 1, + .start = AT91CAP9_BASE_DBGU, + .end = AT91CAP9_BASE_DBGU + SZ_512 - 1, .flags = IORESOURCE_MEM, }, [1] = { diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c index 430a9fdc3db..99c3174e24a 100644 --- a/arch/arm/mach-at91/at91rm9200.c +++ b/arch/arm/mach-at91/at91rm9200.c @@ -23,6 +23,7 @@ #include "soc.h" #include "generic.h" #include "clock.h" +#include "sam9_smc.h" static struct map_desc at91rm9200_io_desc[] __initdata = { { @@ -195,6 +196,10 @@ static struct clk_lookup periph_clocks_lookups[] = { CLKDEV_CON_DEV_ID("pclk", "ssc.2", &ssc2_clk), /* fake hclk clock */ CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk), + CLKDEV_CON_ID("pioA", &pioA_clk), + CLKDEV_CON_ID("pioB", &pioB_clk), + CLKDEV_CON_ID("pioC", &pioC_clk), + CLKDEV_CON_ID("pioD", &pioD_clk), }; static struct clk_lookup usart_clocks_lookups[] = { @@ -268,23 +273,19 @@ void __init at91rm9200_set_console_clock(int id) * GPIO * -------------------------------------------------------------------- */ -static struct at91_gpio_bank at91rm9200_gpio[] = { +static struct at91_gpio_bank at91rm9200_gpio[] __initdata = { { .id = AT91RM9200_ID_PIOA, - .offset = AT91_PIOA, - .clock = &pioA_clk, + .regbase = AT91RM9200_BASE_PIOA, }, { .id = AT91RM9200_ID_PIOB, - .offset = AT91_PIOB, - .clock = &pioB_clk, + .regbase = AT91RM9200_BASE_PIOB, }, { .id = AT91RM9200_ID_PIOC, - .offset = AT91_PIOC, - .clock = &pioC_clk, + .regbase = AT91RM9200_BASE_PIOC, }, { .id = AT91RM9200_ID_PIOD, - .offset = AT91_PIOD, - .clock = &pioD_clk, + .regbase = AT91RM9200_BASE_PIOD, } }; @@ -307,6 +308,10 @@ static void __init at91rm9200_map_io(void) iotable_init(at91rm9200_io_desc, ARRAY_SIZE(at91rm9200_io_desc)); } +static void __init at91rm9200_ioremap_registers(void) +{ +} + static void __init at91rm9200_initialize(void) { arm_pm_restart = at91rm9200_restart; @@ -366,6 +371,7 @@ static unsigned int at91rm9200_default_irq_priority[NR_AIC_IRQS] __initdata = { struct at91_init_soc __initdata at91rm9200_soc = { .map_io = at91rm9200_map_io, .default_irq_priority = at91rm9200_default_irq_priority, + .ioremap_registers = at91rm9200_ioremap_registers, .register_clocks = at91rm9200_register_clocks, .init = at91rm9200_initialize, }; diff --git a/arch/arm/mach-at91/at91rm9200_devices.c b/arch/arm/mach-at91/at91rm9200_devices.c index ad930688358..18bacec2b09 100644 --- a/arch/arm/mach-at91/at91rm9200_devices.c +++ b/arch/arm/mach-at91/at91rm9200_devices.c @@ -114,11 +114,11 @@ void __init at91_add_device_udc(struct at91_udc_data *data) if (!data) return; - if (data->vbus_pin) { + if (gpio_is_valid(data->vbus_pin)) { at91_set_gpio_input(data->vbus_pin, 0); at91_set_deglitch(data->vbus_pin, 1); } - if (data->pullup_pin) + if (gpio_is_valid(data->pullup_pin)) at91_set_gpio_output(data->pullup_pin, 0); udc_data = *data; @@ -135,7 +135,7 @@ void __init at91_add_device_udc(struct at91_udc_data *data) {} #if defined(CONFIG_ARM_AT91_ETHER) || defined(CONFIG_ARM_AT91_ETHER_MODULE) static u64 eth_dmamask = DMA_BIT_MASK(32); -static struct at91_eth_data eth_data; +static struct macb_platform_data eth_data; static struct resource eth_resources[] = { [0] = { @@ -162,12 +162,12 @@ static struct platform_device at91rm9200_eth_device = { .num_resources = ARRAY_SIZE(eth_resources), }; -void __init at91_add_device_eth(struct at91_eth_data *data) +void __init at91_add_device_eth(struct macb_platform_data *data) { if (!data) return; - if (data->phy_irq_pin) { + if (gpio_is_valid(data->phy_irq_pin)) { at91_set_gpio_input(data->phy_irq_pin, 0); at91_set_deglitch(data->phy_irq_pin, 1); } @@ -199,7 +199,7 @@ void __init at91_add_device_eth(struct at91_eth_data *data) platform_device_register(&at91rm9200_eth_device); } #else -void __init at91_add_device_eth(struct at91_eth_data *data) {} +void __init at91_add_device_eth(struct macb_platform_data *data) {} #endif @@ -260,7 +260,7 @@ void __init at91_add_device_cf(struct at91_cf_data *data) ); /* input/irq */ - if (data->irq_pin) { + if (gpio_is_valid(data->irq_pin)) { at91_set_gpio_input(data->irq_pin, 1); at91_set_deglitch(data->irq_pin, 1); } @@ -268,7 +268,7 @@ void __init at91_add_device_cf(struct at91_cf_data *data) at91_set_deglitch(data->det_pin, 1); /* outputs, initially off */ - if (data->vcc_pin) + if (gpio_is_valid(data->vcc_pin)) at91_set_gpio_output(data->vcc_pin, 0); at91_set_gpio_output(data->rst_pin, 0); @@ -328,13 +328,13 @@ void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) return; /* input/irq */ - if (data->det_pin) { + if (gpio_is_valid(data->det_pin)) { at91_set_gpio_input(data->det_pin, 1); at91_set_deglitch(data->det_pin, 1); } - if (data->wp_pin) + if (gpio_is_valid(data->wp_pin)) at91_set_gpio_input(data->wp_pin, 1); - if (data->vcc_pin) + if (gpio_is_valid(data->vcc_pin)) at91_set_gpio_output(data->vcc_pin, 0); /* CLK */ @@ -419,15 +419,15 @@ void __init at91_add_device_nand(struct atmel_nand_data *data) ); /* enable pin */ - if (data->enable_pin) + if (gpio_is_valid(data->enable_pin)) at91_set_gpio_output(data->enable_pin, 1); /* ready/busy pin */ - if (data->rdy_pin) + if (gpio_is_valid(data->rdy_pin)) at91_set_gpio_input(data->rdy_pin, 1); /* card detect pin */ - if (data->det_pin) + if (gpio_is_valid(data->det_pin)) at91_set_gpio_input(data->det_pin, 1); at91_set_A_periph(AT91_PIN_PC1, 0); /* SMOE */ @@ -665,10 +665,24 @@ static void __init at91_add_device_tc(void) { } * -------------------------------------------------------------------- */ #if defined(CONFIG_RTC_DRV_AT91RM9200) || defined(CONFIG_RTC_DRV_AT91RM9200_MODULE) +static struct resource rtc_resources[] = { + [0] = { + .start = AT91RM9200_BASE_RTC, + .end = AT91RM9200_BASE_RTC + SZ_256 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AT91_ID_SYS, + .end = AT91_ID_SYS, + .flags = IORESOURCE_IRQ, + }, +}; + static struct platform_device at91rm9200_rtc_device = { .name = "at91_rtc", .id = -1, - .num_resources = 0, + .resource = rtc_resources, + .num_resources = ARRAY_SIZE(rtc_resources), }; static void __init at91_add_device_rtc(void) @@ -877,8 +891,8 @@ void __init at91_add_device_ssc(unsigned id, unsigned pins) {} #if defined(CONFIG_SERIAL_ATMEL) static struct resource dbgu_resources[] = { [0] = { - .start = AT91_BASE_SYS + AT91_DBGU, - .end = AT91_BASE_SYS + AT91_DBGU + SZ_512 - 1, + .start = AT91RM9200_BASE_DBGU, + .end = AT91RM9200_BASE_DBGU + SZ_512 - 1, .flags = IORESOURCE_MEM, }, [1] = { diff --git a/arch/arm/mach-at91/at91rm9200_time.c b/arch/arm/mach-at91/at91rm9200_time.c index 1dd69c85dfe..a028cdf8f97 100644 --- a/arch/arm/mach-at91/at91rm9200_time.c +++ b/arch/arm/mach-at91/at91rm9200_time.c @@ -32,6 +32,8 @@ static unsigned long last_crtr; static u32 irqmask; static struct clock_event_device clkevt; +#define RM9200_TIMER_LATCH ((AT91_SLOW_CLOCK + HZ/2) / HZ) + /* * The ST_CRTR is updated asynchronously to the master clock ... but * the updates as seen by the CPU don't seem to be strictly monotonic. @@ -74,8 +76,8 @@ static irqreturn_t at91rm9200_timer_interrupt(int irq, void *dev_id) if (sr & AT91_ST_PITS) { u32 crtr = read_CRTR(); - while (((crtr - last_crtr) & AT91_ST_CRTV) >= LATCH) { - last_crtr += LATCH; + while (((crtr - last_crtr) & AT91_ST_CRTV) >= RM9200_TIMER_LATCH) { + last_crtr += RM9200_TIMER_LATCH; clkevt.event_handler(&clkevt); } return IRQ_HANDLED; @@ -116,7 +118,7 @@ clkevt32k_mode(enum clock_event_mode mode, struct clock_event_device *dev) case CLOCK_EVT_MODE_PERIODIC: /* PIT for periodic irqs; fixed rate of 1/HZ */ irqmask = AT91_ST_PITS; - at91_sys_write(AT91_ST_PIMR, LATCH); + at91_sys_write(AT91_ST_PIMR, RM9200_TIMER_LATCH); break; case CLOCK_EVT_MODE_ONESHOT: /* ALM for oneshot irqs, set by next_event() diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c index e76cd49ebc9..5e46e4a9643 100644 --- a/arch/arm/mach-at91/at91sam9260.c +++ b/arch/arm/mach-at91/at91sam9260.c @@ -11,7 +11,6 @@ */ #include <linux/module.h> -#include <linux/pm.h> #include <asm/irq.h> #include <asm/mach/arch.h> @@ -21,11 +20,11 @@ #include <mach/at91sam9260.h> #include <mach/at91_pmc.h> #include <mach/at91_rstc.h> -#include <mach/at91_shdwc.h> #include "soc.h" #include "generic.h" #include "clock.h" +#include "sam9_smc.h" /* -------------------------------------------------------------------- * Clocks @@ -120,7 +119,7 @@ static struct clk ohci_clk = { .type = CLK_TYPE_PERIPHERAL, }; static struct clk macb_clk = { - .name = "macb_clk", + .name = "pclk", .pmc_mask = 1 << AT91SAM9260_ID_EMAC, .type = CLK_TYPE_PERIPHERAL, }; @@ -190,6 +189,8 @@ static struct clk *periph_clocks[] __initdata = { }; static struct clk_lookup periph_clocks_lookups[] = { + /* One additional fake clock for macb_hclk */ + CLKDEV_CON_ID("hclk", &macb_clk), CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk), CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk), CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk), @@ -209,6 +210,9 @@ static struct clk_lookup periph_clocks_lookups[] = { CLKDEV_CON_DEV_ID("usart", "fffd8000.serial", &usart5_clk), /* fake hclk clock */ CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk), + CLKDEV_CON_ID("pioA", &pioA_clk), + CLKDEV_CON_ID("pioB", &pioB_clk), + CLKDEV_CON_ID("pioC", &pioC_clk), }; static struct clk_lookup usart_clocks_lookups[] = { @@ -270,28 +274,19 @@ void __init at91sam9260_set_console_clock(int id) * GPIO * -------------------------------------------------------------------- */ -static struct at91_gpio_bank at91sam9260_gpio[] = { +static struct at91_gpio_bank at91sam9260_gpio[] __initdata = { { .id = AT91SAM9260_ID_PIOA, - .offset = AT91_PIOA, - .clock = &pioA_clk, + .regbase = AT91SAM9260_BASE_PIOA, }, { .id = AT91SAM9260_ID_PIOB, - .offset = AT91_PIOB, - .clock = &pioB_clk, + .regbase = AT91SAM9260_BASE_PIOB, }, { .id = AT91SAM9260_ID_PIOC, - .offset = AT91_PIOC, - .clock = &pioC_clk, + .regbase = AT91SAM9260_BASE_PIOC, } }; -static void at91sam9260_poweroff(void) -{ - at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW); -} - - /* -------------------------------------------------------------------- * AT91SAM9260 processor initialization * -------------------------------------------------------------------- */ @@ -325,10 +320,16 @@ static void __init at91sam9260_map_io(void) } } +static void __init at91sam9260_ioremap_registers(void) +{ + at91_ioremap_shdwc(AT91SAM9260_BASE_SHDWC); + at91sam926x_ioremap_pit(AT91SAM9260_BASE_PIT); + at91sam9_ioremap_smc(0, AT91SAM9260_BASE_SMC); +} + static void __init at91sam9260_initialize(void) { arm_pm_restart = at91sam9_alt_restart; - pm_power_off = at91sam9260_poweroff; at91_extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1) | (1 << AT91SAM9260_ID_IRQ2); @@ -381,6 +382,7 @@ static unsigned int at91sam9260_default_irq_priority[NR_AIC_IRQS] __initdata = { struct at91_init_soc __initdata at91sam9260_soc = { .map_io = at91sam9260_map_io, .default_irq_priority = at91sam9260_default_irq_priority, + .ioremap_registers = at91sam9260_ioremap_registers, .register_clocks = at91sam9260_register_clocks, .init = at91sam9260_initialize, }; diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c index 629fa977497..642ccb6d26b 100644 --- a/arch/arm/mach-at91/at91sam9260_devices.c +++ b/arch/arm/mach-at91/at91sam9260_devices.c @@ -115,7 +115,7 @@ void __init at91_add_device_udc(struct at91_udc_data *data) if (!data) return; - if (data->vbus_pin) { + if (gpio_is_valid(data->vbus_pin)) { at91_set_gpio_input(data->vbus_pin, 0); at91_set_deglitch(data->vbus_pin, 1); } @@ -136,7 +136,7 @@ void __init at91_add_device_udc(struct at91_udc_data *data) {} #if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE) static u64 eth_dmamask = DMA_BIT_MASK(32); -static struct at91_eth_data eth_data; +static struct macb_platform_data eth_data; static struct resource eth_resources[] = { [0] = { @@ -163,12 +163,12 @@ static struct platform_device at91sam9260_eth_device = { .num_resources = ARRAY_SIZE(eth_resources), }; -void __init at91_add_device_eth(struct at91_eth_data *data) +void __init at91_add_device_eth(struct macb_platform_data *data) { if (!data) return; - if (data->phy_irq_pin) { + if (gpio_is_valid(data->phy_irq_pin)) { at91_set_gpio_input(data->phy_irq_pin, 0); at91_set_deglitch(data->phy_irq_pin, 1); } @@ -200,7 +200,7 @@ void __init at91_add_device_eth(struct at91_eth_data *data) platform_device_register(&at91sam9260_eth_device); } #else -void __init at91_add_device_eth(struct at91_eth_data *data) {} +void __init at91_add_device_eth(struct macb_platform_data *data) {} #endif @@ -243,13 +243,13 @@ void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) return; /* input/irq */ - if (data->det_pin) { + if (gpio_is_valid(data->det_pin)) { at91_set_gpio_input(data->det_pin, 1); at91_set_deglitch(data->det_pin, 1); } - if (data->wp_pin) + if (gpio_is_valid(data->wp_pin)) at91_set_gpio_input(data->wp_pin, 1); - if (data->vcc_pin) + if (gpio_is_valid(data->vcc_pin)) at91_set_gpio_output(data->vcc_pin, 0); /* CLK */ @@ -330,11 +330,11 @@ void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data) for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) { if (data->slot[i].bus_width) { /* input/irq */ - if (data->slot[i].detect_pin) { + if (gpio_is_valid(data->slot[i].detect_pin)) { at91_set_gpio_input(data->slot[i].detect_pin, 1); at91_set_deglitch(data->slot[i].detect_pin, 1); } - if (data->slot[i].wp_pin) + if (gpio_is_valid(data->slot[i].wp_pin)) at91_set_gpio_input(data->slot[i].wp_pin, 1); switch (i) { @@ -399,8 +399,8 @@ static struct resource nand_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = AT91_BASE_SYS + AT91_ECC, - .end = AT91_BASE_SYS + AT91_ECC + SZ_512 - 1, + .start = AT91SAM9260_BASE_ECC, + .end = AT91SAM9260_BASE_ECC + SZ_512 - 1, .flags = IORESOURCE_MEM, } }; @@ -426,15 +426,15 @@ void __init at91_add_device_nand(struct atmel_nand_data *data) at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA); /* enable pin */ - if (data->enable_pin) + if (gpio_is_valid(data->enable_pin)) at91_set_gpio_output(data->enable_pin, 1); /* ready/busy pin */ - if (data->rdy_pin) + if (gpio_is_valid(data->rdy_pin)) at91_set_gpio_input(data->rdy_pin, 1); /* card detect pin */ - if (data->det_pin) + if (gpio_is_valid(data->det_pin)) at91_set_gpio_input(data->det_pin, 1); nand_data = *data; @@ -714,8 +714,8 @@ static void __init at91_add_device_tc(void) { } static struct resource rtt_resources[] = { { - .start = AT91_BASE_SYS + AT91_RTT, - .end = AT91_BASE_SYS + AT91_RTT + SZ_16 - 1, + .start = AT91SAM9260_BASE_RTT, + .end = AT91SAM9260_BASE_RTT + SZ_16 - 1, .flags = IORESOURCE_MEM, } }; @@ -738,10 +738,19 @@ static void __init at91_add_device_rtt(void) * -------------------------------------------------------------------- */ #if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE) +static struct resource wdt_resources[] = { + { + .start = AT91SAM9260_BASE_WDT, + .end = AT91SAM9260_BASE_WDT + SZ_16 - 1, + .flags = IORESOURCE_MEM, + } +}; + static struct platform_device at91sam9260_wdt_device = { .name = "at91_wdt", .id = -1, - .num_resources = 0, + .resource = wdt_resources, + .num_resources = ARRAY_SIZE(wdt_resources), }; static void __init at91_add_device_watchdog(void) @@ -837,8 +846,8 @@ void __init at91_add_device_ssc(unsigned id, unsigned pins) {} #if defined(CONFIG_SERIAL_ATMEL) static struct resource dbgu_resources[] = { [0] = { - .start = AT91_BASE_SYS + AT91_DBGU, - .end = AT91_BASE_SYS + AT91_DBGU + SZ_512 - 1, + .start = AT91SAM9260_BASE_DBGU, + .end = AT91SAM9260_BASE_DBGU + SZ_512 - 1, .flags = IORESOURCE_MEM, }, [1] = { @@ -1281,17 +1290,17 @@ void __init at91_add_device_cf(struct at91_cf_data *data) at91_sys_write(AT91_MATRIX_EBICSA, csa); - if (data->rst_pin) { + if (gpio_is_valid(data->rst_pin)) { at91_set_multi_drive(data->rst_pin, 0); at91_set_gpio_output(data->rst_pin, 1); } - if (data->irq_pin) { + if (gpio_is_valid(data->irq_pin)) { at91_set_gpio_input(data->irq_pin, 0); at91_set_deglitch(data->irq_pin, 1); } - if (data->det_pin) { + if (gpio_is_valid(data->det_pin)) { at91_set_gpio_input(data->det_pin, 0); at91_set_deglitch(data->det_pin, 1); } diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c index 19ac7c0729a..b85b9ea6017 100644 --- a/arch/arm/mach-at91/at91sam9261.c +++ b/arch/arm/mach-at91/at91sam9261.c @@ -11,7 +11,6 @@ */ #include <linux/module.h> -#include <linux/pm.h> #include <asm/irq.h> #include <asm/mach/arch.h> @@ -20,11 +19,11 @@ #include <mach/at91sam9261.h> #include <mach/at91_pmc.h> #include <mach/at91_rstc.h> -#include <mach/at91_shdwc.h> #include "soc.h" #include "generic.h" #include "clock.h" +#include "sam9_smc.h" /* -------------------------------------------------------------------- * Clocks @@ -176,6 +175,9 @@ static struct clk_lookup periph_clocks_lookups[] = { CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk), CLKDEV_CON_DEV_ID("pclk", "ssc.2", &ssc2_clk), CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &hck0), + CLKDEV_CON_ID("pioA", &pioA_clk), + CLKDEV_CON_ID("pioB", &pioB_clk), + CLKDEV_CON_ID("pioC", &pioC_clk), }; static struct clk_lookup usart_clocks_lookups[] = { @@ -251,28 +253,19 @@ void __init at91sam9261_set_console_clock(int id) * GPIO * -------------------------------------------------------------------- */ -static struct at91_gpio_bank at91sam9261_gpio[] = { +static struct at91_gpio_bank at91sam9261_gpio[] __initdata = { { .id = AT91SAM9261_ID_PIOA, - .offset = AT91_PIOA, - .clock = &pioA_clk, + .regbase = AT91SAM9261_BASE_PIOA, }, { .id = AT91SAM9261_ID_PIOB, - .offset = AT91_PIOB, - .clock = &pioB_clk, + .regbase = AT91SAM9261_BASE_PIOB, }, { .id = AT91SAM9261_ID_PIOC, - .offset = AT91_PIOC, - .clock = &pioC_clk, + .regbase = AT91SAM9261_BASE_PIOC, } }; -static void at91sam9261_poweroff(void) -{ - at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW); -} - - /* -------------------------------------------------------------------- * AT91SAM9261 processor initialization * -------------------------------------------------------------------- */ @@ -285,10 +278,16 @@ static void __init at91sam9261_map_io(void) at91_init_sram(0, AT91SAM9261_SRAM_BASE, AT91SAM9261_SRAM_SIZE); } +static void __init at91sam9261_ioremap_registers(void) +{ + at91_ioremap_shdwc(AT91SAM9261_BASE_SHDWC); + at91sam926x_ioremap_pit(AT91SAM9261_BASE_PIT); + at91sam9_ioremap_smc(0, AT91SAM9261_BASE_SMC); +} + static void __init at91sam9261_initialize(void) { arm_pm_restart = at91sam9_alt_restart; - pm_power_off = at91sam9261_poweroff; at91_extern_irq = (1 << AT91SAM9261_ID_IRQ0) | (1 << AT91SAM9261_ID_IRQ1) | (1 << AT91SAM9261_ID_IRQ2); @@ -341,6 +340,7 @@ static unsigned int at91sam9261_default_irq_priority[NR_AIC_IRQS] __initdata = { struct at91_init_soc __initdata at91sam9261_soc = { .map_io = at91sam9261_map_io, .default_irq_priority = at91sam9261_default_irq_priority, + .ioremap_registers = at91sam9261_ioremap_registers, .register_clocks = at91sam9261_register_clocks, .init = at91sam9261_initialize, }; diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c index a178b58b0b9..fc59cbdb0e3 100644 --- a/arch/arm/mach-at91/at91sam9261_devices.c +++ b/arch/arm/mach-at91/at91sam9261_devices.c @@ -118,7 +118,7 @@ void __init at91_add_device_udc(struct at91_udc_data *data) if (!data) return; - if (data->vbus_pin) { + if (gpio_is_valid(data->vbus_pin)) { at91_set_gpio_input(data->vbus_pin, 0); at91_set_deglitch(data->vbus_pin, 1); } @@ -171,13 +171,13 @@ void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) return; /* input/irq */ - if (data->det_pin) { + if (gpio_is_valid(data->det_pin)) { at91_set_gpio_input(data->det_pin, 1); at91_set_deglitch(data->det_pin, 1); } - if (data->wp_pin) + if (gpio_is_valid(data->wp_pin)) at91_set_gpio_input(data->wp_pin, 1); - if (data->vcc_pin) + if (gpio_is_valid(data->vcc_pin)) at91_set_gpio_output(data->vcc_pin, 0); /* CLK */ @@ -240,15 +240,15 @@ void __init at91_add_device_nand(struct atmel_nand_data *data) at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA); /* enable pin */ - if (data->enable_pin) + if (gpio_is_valid(data->enable_pin)) at91_set_gpio_output(data->enable_pin, 1); /* ready/busy pin */ - if (data->rdy_pin) + if (gpio_is_valid(data->rdy_pin)) at91_set_gpio_input(data->rdy_pin, 1); /* card detect pin */ - if (data->det_pin) + if (gpio_is_valid(data->det_pin)) at91_set_gpio_input(data->det_pin, 1); at91_set_A_periph(AT91_PIN_PC0, 0); /* NANDOE */ @@ -600,8 +600,8 @@ static void __init at91_add_device_tc(void) { } static struct resource rtt_resources[] = { { - .start = AT91_BASE_SYS + AT91_RTT, - .end = AT91_BASE_SYS + AT91_RTT + SZ_16 - 1, + .start = AT91SAM9261_BASE_RTT, + .end = AT91SAM9261_BASE_RTT + SZ_16 - 1, .flags = IORESOURCE_MEM, } }; @@ -624,10 +624,19 @@ static void __init at91_add_device_rtt(void) * -------------------------------------------------------------------- */ #if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE) +static struct resource wdt_resources[] = { + { + .start = AT91SAM9261_BASE_WDT, + .end = AT91SAM9261_BASE_WDT + SZ_16 - 1, + .flags = IORESOURCE_MEM, + } +}; + static struct platform_device at91sam9261_wdt_device = { .name = "at91_wdt", .id = -1, - .num_resources = 0, + .resource = wdt_resources, + .num_resources = ARRAY_SIZE(wdt_resources), }; static void __init at91_add_device_watchdog(void) @@ -816,8 +825,8 @@ void __init at91_add_device_ssc(unsigned id, unsigned pins) {} #if defined(CONFIG_SERIAL_ATMEL) static struct resource dbgu_resources[] = { [0] = { - .start = AT91_BASE_SYS + AT91_DBGU, - .end = AT91_BASE_SYS + AT91_DBGU + SZ_512 - 1, + .start = AT91SAM9261_BASE_DBGU, + .end = AT91SAM9261_BASE_DBGU + SZ_512 - 1, .flags = IORESOURCE_MEM, }, [1] = { diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c index 50d01631003..79e3669b111 100644 --- a/arch/arm/mach-at91/at91sam9263.c +++ b/arch/arm/mach-at91/at91sam9263.c @@ -11,7 +11,6 @@ */ #include <linux/module.h> -#include <linux/pm.h> #include <asm/irq.h> #include <asm/mach/arch.h> @@ -19,11 +18,11 @@ #include <mach/at91sam9263.h> #include <mach/at91_pmc.h> #include <mach/at91_rstc.h> -#include <mach/at91_shdwc.h> #include "soc.h" #include "generic.h" #include "clock.h" +#include "sam9_smc.h" /* -------------------------------------------------------------------- * Clocks @@ -118,7 +117,7 @@ static struct clk pwm_clk = { .type = CLK_TYPE_PERIPHERAL, }; static struct clk macb_clk = { - .name = "macb_clk", + .name = "pclk", .pmc_mask = 1 << AT91SAM9263_ID_EMAC, .type = CLK_TYPE_PERIPHERAL, }; @@ -182,6 +181,8 @@ static struct clk *periph_clocks[] __initdata = { }; static struct clk_lookup periph_clocks_lookups[] = { + /* One additional fake clock for macb_hclk */ + CLKDEV_CON_ID("hclk", &macb_clk), CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk), CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk), CLKDEV_CON_DEV_ID("mci_clk", "at91_mci.0", &mmc0_clk), @@ -191,6 +192,11 @@ static struct clk_lookup periph_clocks_lookups[] = { CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb_clk), /* fake hclk clock */ CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk), + CLKDEV_CON_ID("pioA", &pioA_clk), + CLKDEV_CON_ID("pioB", &pioB_clk), + CLKDEV_CON_ID("pioC", &pioCDE_clk), + CLKDEV_CON_ID("pioD", &pioCDE_clk), + CLKDEV_CON_ID("pioE", &pioCDE_clk), }; static struct clk_lookup usart_clocks_lookups[] = { @@ -263,36 +269,25 @@ void __init at91sam9263_set_console_clock(int id) * GPIO * -------------------------------------------------------------------- */ -static struct at91_gpio_bank at91sam9263_gpio[] = { +static struct at91_gpio_bank at91sam9263_gpio[] __initdata = { { .id = AT91SAM9263_ID_PIOA, - .offset = AT91_PIOA, - .clock = &pioA_clk, + .regbase = AT91SAM9263_BASE_PIOA, }, { .id = AT91SAM9263_ID_PIOB, - .offset = AT91_PIOB, - .clock = &pioB_clk, + .regbase = AT91SAM9263_BASE_PIOB, }, { .id = AT91SAM9263_ID_PIOCDE, - .offset = AT91_PIOC, - .clock = &pioCDE_clk, + .regbase = AT91SAM9263_BASE_PIOC, }, { .id = AT91SAM9263_ID_PIOCDE, - .offset = AT91_PIOD, - .clock = &pioCDE_clk, + .regbase = AT91SAM9263_BASE_PIOD, }, { .id = AT91SAM9263_ID_PIOCDE, - .offset = AT91_PIOE, - .clock = &pioCDE_clk, + .regbase = AT91SAM9263_BASE_PIOE, } }; -static void at91sam9263_poweroff(void) -{ - at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW); -} - - /* -------------------------------------------------------------------- * AT91SAM9263 processor initialization * -------------------------------------------------------------------- */ @@ -303,10 +298,17 @@ static void __init at91sam9263_map_io(void) at91_init_sram(1, AT91SAM9263_SRAM1_BASE, AT91SAM9263_SRAM1_SIZE); } +static void __init at91sam9263_ioremap_registers(void) +{ + at91_ioremap_shdwc(AT91SAM9263_BASE_SHDWC); + at91sam926x_ioremap_pit(AT91SAM9263_BASE_PIT); + at91sam9_ioremap_smc(0, AT91SAM9263_BASE_SMC0); + at91sam9_ioremap_smc(1, AT91SAM9263_BASE_SMC1); +} + static void __init at91sam9263_initialize(void) { arm_pm_restart = at91sam9_alt_restart; - pm_power_off = at91sam9263_poweroff; at91_extern_irq = (1 << AT91SAM9263_ID_IRQ0) | (1 << AT91SAM9263_ID_IRQ1); /* Register GPIO subsystem */ @@ -358,6 +360,7 @@ static unsigned int at91sam9263_default_irq_priority[NR_AIC_IRQS] __initdata = { struct at91_init_soc __initdata at91sam9263_soc = { .map_io = at91sam9263_map_io, .default_irq_priority = at91sam9263_default_irq_priority, + .ioremap_registers = at91sam9263_ioremap_registers, .register_clocks = at91sam9263_register_clocks, .init = at91sam9263_initialize, }; diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c index d5fbac9ff4f..7b46b278702 100644 --- a/arch/arm/mach-at91/at91sam9263_devices.c +++ b/arch/arm/mach-at91/at91sam9263_devices.c @@ -70,7 +70,7 @@ void __init at91_add_device_usbh(struct at91_usbh_data *data) /* Enable VBus control for UHP ports */ for (i = 0; i < data->ports; i++) { - if (data->vbus_pin[i]) + if (gpio_is_valid(data->vbus_pin[i])) at91_set_gpio_output(data->vbus_pin[i], 0); } @@ -123,7 +123,7 @@ void __init at91_add_device_udc(struct at91_udc_data *data) if (!data) return; - if (data->vbus_pin) { + if (gpio_is_valid(data->vbus_pin)) { at91_set_gpio_input(data->vbus_pin, 0); at91_set_deglitch(data->vbus_pin, 1); } @@ -144,7 +144,7 @@ void __init at91_add_device_udc(struct at91_udc_data *data) {} #if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE) static u64 eth_dmamask = DMA_BIT_MASK(32); -static struct at91_eth_data eth_data; +static struct macb_platform_data eth_data; static struct resource eth_resources[] = { [0] = { @@ -171,12 +171,12 @@ static struct platform_device at91sam9263_eth_device = { .num_resources = ARRAY_SIZE(eth_resources), }; -void __init at91_add_device_eth(struct at91_eth_data *data) +void __init at91_add_device_eth(struct macb_platform_data *data) { if (!data) return; - if (data->phy_irq_pin) { + if (gpio_is_valid(data->phy_irq_pin)) { at91_set_gpio_input(data->phy_irq_pin, 0); at91_set_deglitch(data->phy_irq_pin, 1); } @@ -208,7 +208,7 @@ void __init at91_add_device_eth(struct at91_eth_data *data) platform_device_register(&at91sam9263_eth_device); } #else -void __init at91_add_device_eth(struct at91_eth_data *data) {} +void __init at91_add_device_eth(struct macb_platform_data *data) {} #endif @@ -276,13 +276,13 @@ void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) return; /* input/irq */ - if (data->det_pin) { + if (gpio_is_valid(data->det_pin)) { at91_set_gpio_input(data->det_pin, 1); at91_set_deglitch(data->det_pin, 1); } - if (data->wp_pin) + if (gpio_is_valid(data->wp_pin)) at91_set_gpio_input(data->wp_pin, 1); - if (data->vcc_pin) + if (gpio_is_valid(data->vcc_pin)) at91_set_gpio_output(data->vcc_pin, 0); if (mmc_id == 0) { /* MCI0 */ @@ -430,17 +430,17 @@ void __init at91_add_device_cf(struct at91_cf_data *data) } at91_sys_write(AT91_MATRIX_EBI0CSA, ebi0_csa); - if (data->det_pin) { + if (gpio_is_valid(data->det_pin)) { at91_set_gpio_input(data->det_pin, 1); at91_set_deglitch(data->det_pin, 1); } - if (data->irq_pin) { + if (gpio_is_valid(data->irq_pin)) { at91_set_gpio_input(data->irq_pin, 1); at91_set_deglitch(data->irq_pin, 1); } - if (data->vcc_pin) + if (gpio_is_valid(data->vcc_pin)) /* initially off */ at91_set_gpio_output(data->vcc_pin, 0); @@ -473,8 +473,8 @@ static struct resource nand_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = AT91_BASE_SYS + AT91_ECC0, - .end = AT91_BASE_SYS + AT91_ECC0 + SZ_512 - 1, + .start = AT91SAM9263_BASE_ECC0, + .end = AT91SAM9263_BASE_ECC0 + SZ_512 - 1, .flags = IORESOURCE_MEM, } }; @@ -500,15 +500,15 @@ void __init at91_add_device_nand(struct atmel_nand_data *data) at91_sys_write(AT91_MATRIX_EBI0CSA, csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA); /* enable pin */ - if (data->enable_pin) + if (gpio_is_valid(data->enable_pin)) at91_set_gpio_output(data->enable_pin, 1); /* ready/busy pin */ - if (data->rdy_pin) + if (gpio_is_valid(data->rdy_pin)) at91_set_gpio_input(data->rdy_pin, 1); /* card detect pin */ - if (data->det_pin) + if (gpio_is_valid(data->det_pin)) at91_set_gpio_input(data->det_pin, 1); nand_data = *data; @@ -749,7 +749,7 @@ void __init at91_add_device_ac97(struct ac97c_platform_data *data) at91_set_A_periph(AT91_PIN_PB3, 0); /* AC97RX */ /* reset */ - if (data->reset_pin) + if (gpio_is_valid(data->reset_pin)) at91_set_gpio_output(data->reset_pin, 0); ac97_data = *data; @@ -956,8 +956,8 @@ static void __init at91_add_device_tc(void) { } static struct resource rtt0_resources[] = { { - .start = AT91_BASE_SYS + AT91_RTT0, - .end = AT91_BASE_SYS + AT91_RTT0 + SZ_16 - 1, + .start = AT91SAM9263_BASE_RTT0, + .end = AT91SAM9263_BASE_RTT0 + SZ_16 - 1, .flags = IORESOURCE_MEM, } }; @@ -971,8 +971,8 @@ static struct platform_device at91sam9263_rtt0_device = { static struct resource rtt1_resources[] = { { - .start = AT91_BASE_SYS + AT91_RTT1, - .end = AT91_BASE_SYS + AT91_RTT1 + SZ_16 - 1, + .start = AT91SAM9263_BASE_RTT1, + .end = AT91SAM9263_BASE_RTT1 + SZ_16 - 1, .flags = IORESOURCE_MEM, } }; @@ -996,10 +996,19 @@ static void __init at91_add_device_rtt(void) * -------------------------------------------------------------------- */ #if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE) +static struct resource wdt_resources[] = { + { + .start = AT91SAM9263_BASE_WDT, + .end = AT91SAM9263_BASE_WDT + SZ_16 - 1, + .flags = IORESOURCE_MEM, + } +}; + static struct platform_device at91sam9263_wdt_device = { .name = "at91_wdt", .id = -1, - .num_resources = 0, + .resource = wdt_resources, + .num_resources = ARRAY_SIZE(wdt_resources), }; static void __init at91_add_device_watchdog(void) @@ -1196,8 +1205,8 @@ void __init at91_add_device_ssc(unsigned id, unsigned pins) {} static struct resource dbgu_resources[] = { [0] = { - .start = AT91_BASE_SYS + AT91_DBGU, - .end = AT91_BASE_SYS + AT91_DBGU + SZ_512 - 1, + .start = AT91SAM9263_BASE_DBGU, + .end = AT91SAM9263_BASE_DBGU + SZ_512 - 1, .flags = IORESOURCE_MEM, }, [1] = { diff --git a/arch/arm/mach-at91/at91sam926x_time.c b/arch/arm/mach-at91/at91sam926x_time.c index 4ba85499fa9..d89ead740a9 100644 --- a/arch/arm/mach-at91/at91sam926x_time.c +++ b/arch/arm/mach-at91/at91sam926x_time.c @@ -25,7 +25,17 @@ static u32 pit_cycle; /* write-once */ static u32 pit_cnt; /* access only w/system irq blocked */ +static void __iomem *pit_base_addr __read_mostly; +static inline unsigned int pit_read(unsigned int reg_offset) +{ + return __raw_readl(pit_base_addr + reg_offset); +} + +static inline void pit_write(unsigned int reg_offset, unsigned long value) +{ + __raw_writel(value, pit_base_addr + reg_offset); +} /* * Clocksource: just a monotonic counter of MCK/16 cycles. @@ -39,7 +49,7 @@ static cycle_t read_pit_clk(struct clocksource *cs) raw_local_irq_save(flags); elapsed = pit_cnt; - t = at91_sys_read(AT91_PIT_PIIR); + t = pit_read(AT91_PIT_PIIR); raw_local_irq_restore(flags); elapsed += PIT_PICNT(t) * pit_cycle; @@ -64,8 +74,8 @@ pit_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev) switch (mode) { case CLOCK_EVT_MODE_PERIODIC: /* update clocksource counter */ - pit_cnt += pit_cycle * PIT_PICNT(at91_sys_read(AT91_PIT_PIVR)); - at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN + pit_cnt += pit_cycle * PIT_PICNT(pit_read(AT91_PIT_PIVR)); + pit_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN | AT91_PIT_PITIEN); break; case CLOCK_EVT_MODE_ONESHOT: @@ -74,7 +84,7 @@ pit_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev) case CLOCK_EVT_MODE_SHUTDOWN: case CLOCK_EVT_MODE_UNUSED: /* disable irq, leaving the clocksource active */ - at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN); + pit_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN); break; case CLOCK_EVT_MODE_RESUME: break; @@ -103,11 +113,11 @@ static irqreturn_t at91sam926x_pit_interrupt(int irq, void *dev_id) /* The PIT interrupt may be disabled, and is shared */ if ((pit_clkevt.mode == CLOCK_EVT_MODE_PERIODIC) - && (at91_sys_read(AT91_PIT_SR) & AT91_PIT_PITS)) { + && (pit_read(AT91_PIT_SR) & AT91_PIT_PITS)) { unsigned nr_ticks; /* Get number of ticks performed before irq, and ack it */ - nr_ticks = PIT_PICNT(at91_sys_read(AT91_PIT_PIVR)); + nr_ticks = PIT_PICNT(pit_read(AT91_PIT_PIVR)); do { pit_cnt += pit_cycle; pit_clkevt.event_handler(&pit_clkevt); @@ -129,14 +139,14 @@ static struct irqaction at91sam926x_pit_irq = { static void at91sam926x_pit_reset(void) { /* Disable timer and irqs */ - at91_sys_write(AT91_PIT_MR, 0); + pit_write(AT91_PIT_MR, 0); /* Clear any pending interrupts, wait for PIT to stop counting */ - while (PIT_CPIV(at91_sys_read(AT91_PIT_PIVR)) != 0) + while (PIT_CPIV(pit_read(AT91_PIT_PIVR)) != 0) cpu_relax(); /* Start PIT but don't enable IRQ */ - at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN); + pit_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN); } /* @@ -178,7 +188,15 @@ static void __init at91sam926x_pit_init(void) static void at91sam926x_pit_suspend(void) { /* Disable timer */ - at91_sys_write(AT91_PIT_MR, 0); + pit_write(AT91_PIT_MR, 0); +} + +void __init at91sam926x_ioremap_pit(u32 addr) +{ + pit_base_addr = ioremap(addr, 16); + + if (!pit_base_addr) + panic("Impossible to ioremap PIT\n"); } struct sys_timer at91sam926x_timer = { diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c index ff21f7a60c6..7032dd32cdf 100644 --- a/arch/arm/mach-at91/at91sam9g45.c +++ b/arch/arm/mach-at91/at91sam9g45.c @@ -11,7 +11,6 @@ */ #include <linux/module.h> -#include <linux/pm.h> #include <linux/dma-mapping.h> #include <asm/irq.h> @@ -20,12 +19,12 @@ #include <mach/at91sam9g45.h> #include <mach/at91_pmc.h> #include <mach/at91_rstc.h> -#include <mach/at91_shdwc.h> #include <mach/cpu.h> #include "soc.h" #include "generic.h" #include "clock.h" +#include "sam9_smc.h" /* -------------------------------------------------------------------- * Clocks @@ -150,7 +149,7 @@ static struct clk ac97_clk = { .type = CLK_TYPE_PERIPHERAL, }; static struct clk macb_clk = { - .name = "macb_clk", + .name = "pclk", .pmc_mask = 1 << AT91SAM9G45_ID_EMAC, .type = CLK_TYPE_PERIPHERAL, }; @@ -209,6 +208,8 @@ static struct clk *periph_clocks[] __initdata = { }; static struct clk_lookup periph_clocks_lookups[] = { + /* One additional fake clock for macb_hclk */ + CLKDEV_CON_ID("hclk", &macb_clk), /* One additional fake clock for ohci */ CLKDEV_CON_ID("ohci_clk", &uhphs_clk), CLKDEV_CON_DEV_ID("ehci_clk", "atmel-ehci", &uhphs_clk), @@ -231,6 +232,11 @@ static struct clk_lookup periph_clocks_lookups[] = { CLKDEV_CON_DEV_ID("usart", "fff98000.serial", &usart3_clk), /* fake hclk clock */ CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &uhphs_clk), + CLKDEV_CON_ID("pioA", &pioA_clk), + CLKDEV_CON_ID("pioB", &pioB_clk), + CLKDEV_CON_ID("pioC", &pioC_clk), + CLKDEV_CON_ID("pioD", &pioDE_clk), + CLKDEV_CON_ID("pioE", &pioDE_clk), }; static struct clk_lookup usart_clocks_lookups[] = { @@ -293,27 +299,22 @@ void __init at91sam9g45_set_console_clock(int id) * GPIO * -------------------------------------------------------------------- */ -static struct at91_gpio_bank at91sam9g45_gpio[] = { +static struct at91_gpio_bank at91sam9g45_gpio[] __initdata = { { .id = AT91SAM9G45_ID_PIOA, - .offset = AT91_PIOA, - .clock = &pioA_clk, + .regbase = AT91SAM9G45_BASE_PIOA, }, { .id = AT91SAM9G45_ID_PIOB, - .offset = AT91_PIOB, - .clock = &pioB_clk, + .regbase = AT91SAM9G45_BASE_PIOB, }, { .id = AT91SAM9G45_ID_PIOC, - .offset = AT91_PIOC, - .clock = &pioC_clk, + .regbase = AT91SAM9G45_BASE_PIOC, }, { .id = AT91SAM9G45_ID_PIODE, - .offset = AT91_PIOD, - .clock = &pioDE_clk, + .regbase = AT91SAM9G45_BASE_PIOD, }, { .id = AT91SAM9G45_ID_PIODE, - .offset = AT91_PIOE, - .clock = &pioDE_clk, + .regbase = AT91SAM9G45_BASE_PIOE, } }; @@ -322,12 +323,6 @@ static void at91sam9g45_restart(char mode, const char *cmd) at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST); } -static void at91sam9g45_poweroff(void) -{ - at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW); -} - - /* -------------------------------------------------------------------- * AT91SAM9G45 processor initialization * -------------------------------------------------------------------- */ @@ -338,10 +333,16 @@ static void __init at91sam9g45_map_io(void) init_consistent_dma_size(SZ_4M); } +static void __init at91sam9g45_ioremap_registers(void) +{ + at91_ioremap_shdwc(AT91SAM9G45_BASE_SHDWC); + at91sam926x_ioremap_pit(AT91SAM9G45_BASE_PIT); + at91sam9_ioremap_smc(0, AT91SAM9G45_BASE_SMC); +} + static void __init at91sam9g45_initialize(void) { arm_pm_restart = at91sam9g45_restart; - pm_power_off = at91sam9g45_poweroff; at91_extern_irq = (1 << AT91SAM9G45_ID_IRQ0); /* Register GPIO subsystem */ @@ -393,6 +394,7 @@ static unsigned int at91sam9g45_default_irq_priority[NR_AIC_IRQS] __initdata = { struct at91_init_soc __initdata at91sam9g45_soc = { .map_io = at91sam9g45_map_io, .default_irq_priority = at91sam9g45_default_irq_priority, + .ioremap_registers = at91sam9g45_ioremap_registers, .register_clocks = at91sam9g45_register_clocks, .init = at91sam9g45_initialize, }; diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c index 09a16d6bd5c..b7582dd10dc 100644 --- a/arch/arm/mach-at91/at91sam9g45_devices.c +++ b/arch/arm/mach-at91/at91sam9g45_devices.c @@ -44,8 +44,8 @@ static struct at_dma_platform_data atdma_pdata = { static struct resource hdmac_resources[] = { [0] = { - .start = AT91_BASE_SYS + AT91_DMA, - .end = AT91_BASE_SYS + AT91_DMA + SZ_512 - 1, + .start = AT91SAM9G45_BASE_DMA, + .end = AT91SAM9G45_BASE_DMA + SZ_512 - 1, .flags = IORESOURCE_MEM, }, [1] = { @@ -120,7 +120,7 @@ void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data) /* Enable VBus control for UHP ports */ for (i = 0; i < data->ports; i++) { - if (data->vbus_pin[i]) + if (gpio_is_valid(data->vbus_pin[i])) at91_set_gpio_output(data->vbus_pin[i], 0); } @@ -181,7 +181,7 @@ void __init at91_add_device_usbh_ehci(struct at91_usbh_data *data) /* Enable VBus control for UHP ports */ for (i = 0; i < data->ports; i++) { - if (data->vbus_pin[i]) + if (gpio_is_valid(data->vbus_pin[i])) at91_set_gpio_output(data->vbus_pin[i], 0); } @@ -263,7 +263,7 @@ void __init at91_add_device_usba(struct usba_platform_data *data) usba_udc_data.pdata.num_ep = ARRAY_SIZE(usba_udc_ep); memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep)); - if (data && data->vbus_pin > 0) { + if (data && gpio_is_valid(data->vbus_pin)) { at91_set_gpio_input(data->vbus_pin, 0); at91_set_deglitch(data->vbus_pin, 1); usba_udc_data.pdata.vbus_pin = data->vbus_pin; @@ -284,7 +284,7 @@ void __init at91_add_device_usba(struct usba_platform_data *data) {} #if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE) static u64 eth_dmamask = DMA_BIT_MASK(32); -static struct at91_eth_data eth_data; +static struct macb_platform_data eth_data; static struct resource eth_resources[] = { [0] = { @@ -311,12 +311,12 @@ static struct platform_device at91sam9g45_eth_device = { .num_resources = ARRAY_SIZE(eth_resources), }; -void __init at91_add_device_eth(struct at91_eth_data *data) +void __init at91_add_device_eth(struct macb_platform_data *data) { if (!data) return; - if (data->phy_irq_pin) { + if (gpio_is_valid(data->phy_irq_pin)) { at91_set_gpio_input(data->phy_irq_pin, 0); at91_set_deglitch(data->phy_irq_pin, 1); } @@ -348,7 +348,7 @@ void __init at91_add_device_eth(struct at91_eth_data *data) platform_device_register(&at91sam9g45_eth_device); } #else -void __init at91_add_device_eth(struct at91_eth_data *data) {} +void __init at91_add_device_eth(struct macb_platform_data *data) {} #endif @@ -449,11 +449,11 @@ void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data) /* input/irq */ - if (data->slot[0].detect_pin) { + if (gpio_is_valid(data->slot[0].detect_pin)) { at91_set_gpio_input(data->slot[0].detect_pin, 1); at91_set_deglitch(data->slot[0].detect_pin, 1); } - if (data->slot[0].wp_pin) + if (gpio_is_valid(data->slot[0].wp_pin)) at91_set_gpio_input(data->slot[0].wp_pin, 1); if (mmc_id == 0) { /* MCI0 */ @@ -529,8 +529,8 @@ static struct resource nand_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = AT91_BASE_SYS + AT91_ECC, - .end = AT91_BASE_SYS + AT91_ECC + SZ_512 - 1, + .start = AT91SAM9G45_BASE_ECC, + .end = AT91SAM9G45_BASE_ECC + SZ_512 - 1, .flags = IORESOURCE_MEM, } }; @@ -556,15 +556,15 @@ void __init at91_add_device_nand(struct atmel_nand_data *data) at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA); /* enable pin */ - if (data->enable_pin) + if (gpio_is_valid(data->enable_pin)) at91_set_gpio_output(data->enable_pin, 1); /* ready/busy pin */ - if (data->rdy_pin) + if (gpio_is_valid(data->rdy_pin)) at91_set_gpio_input(data->rdy_pin, 1); /* card detect pin */ - if (data->det_pin) + if (gpio_is_valid(data->det_pin)) at91_set_gpio_input(data->det_pin, 1); nand_data = *data; @@ -859,7 +859,7 @@ void __init at91_add_device_ac97(struct ac97c_platform_data *data) at91_set_A_periph(AT91_PIN_PD6, 0); /* AC97RX */ /* reset */ - if (data->reset_pin) + if (gpio_is_valid(data->reset_pin)) at91_set_gpio_output(data->reset_pin, 0); ac97_data = *data; @@ -1009,10 +1009,24 @@ static void __init at91_add_device_tc(void) { } * -------------------------------------------------------------------- */ #if defined(CONFIG_RTC_DRV_AT91RM9200) || defined(CONFIG_RTC_DRV_AT91RM9200_MODULE) +static struct resource rtc_resources[] = { + [0] = { + .start = AT91SAM9G45_BASE_RTC, + .end = AT91SAM9G45_BASE_RTC + SZ_256 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AT91_ID_SYS, + .end = AT91_ID_SYS, + .flags = IORESOURCE_IRQ, + }, +}; + static struct platform_device at91sam9g45_rtc_device = { .name = "at91_rtc", .id = -1, - .num_resources = 0, + .resource = rtc_resources, + .num_resources = ARRAY_SIZE(rtc_resources), }; static void __init at91_add_device_rtc(void) @@ -1081,8 +1095,8 @@ void __init at91_add_device_tsadcc(struct at91_tsadcc_data *data) {} static struct resource rtt_resources[] = { { - .start = AT91_BASE_SYS + AT91_RTT, - .end = AT91_BASE_SYS + AT91_RTT + SZ_16 - 1, + .start = AT91SAM9G45_BASE_RTT, + .end = AT91SAM9G45_BASE_RTT + SZ_16 - 1, .flags = IORESOURCE_MEM, } }; @@ -1133,10 +1147,19 @@ static void __init at91_add_device_trng(void) {} * -------------------------------------------------------------------- */ #if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE) +static struct resource wdt_resources[] = { + { + .start = AT91SAM9G45_BASE_WDT, + .end = AT91SAM9G45_BASE_WDT + SZ_16 - 1, + .flags = IORESOURCE_MEM, + } +}; + static struct platform_device at91sam9g45_wdt_device = { .name = "at91_wdt", .id = -1, - .num_resources = 0, + .resource = wdt_resources, + .num_resources = ARRAY_SIZE(wdt_resources), }; static void __init at91_add_device_watchdog(void) @@ -1332,8 +1355,8 @@ void __init at91_add_device_ssc(unsigned id, unsigned pins) {} #if defined(CONFIG_SERIAL_ATMEL) static struct resource dbgu_resources[] = { [0] = { - .start = AT91_BASE_SYS + AT91_DBGU, - .end = AT91_BASE_SYS + AT91_DBGU + SZ_512 - 1, + .start = AT91SAM9G45_BASE_DBGU, + .end = AT91SAM9G45_BASE_DBGU + SZ_512 - 1, .flags = IORESOURCE_MEM, }, [1] = { diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c index 61cbb46f5b0..d6bcb1da11d 100644 --- a/arch/arm/mach-at91/at91sam9rl.c +++ b/arch/arm/mach-at91/at91sam9rl.c @@ -10,7 +10,6 @@ */ #include <linux/module.h> -#include <linux/pm.h> #include <asm/irq.h> #include <asm/mach/arch.h> @@ -20,11 +19,11 @@ #include <mach/at91sam9rl.h> #include <mach/at91_pmc.h> #include <mach/at91_rstc.h> -#include <mach/at91_shdwc.h> #include "soc.h" #include "generic.h" #include "clock.h" +#include "sam9_smc.h" /* -------------------------------------------------------------------- * Clocks @@ -184,6 +183,10 @@ static struct clk_lookup periph_clocks_lookups[] = { CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk), CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk), CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk), + CLKDEV_CON_ID("pioA", &pioA_clk), + CLKDEV_CON_ID("pioB", &pioB_clk), + CLKDEV_CON_ID("pioC", &pioC_clk), + CLKDEV_CON_ID("pioD", &pioD_clk), }; static struct clk_lookup usart_clocks_lookups[] = { @@ -243,32 +246,22 @@ void __init at91sam9rl_set_console_clock(int id) * GPIO * -------------------------------------------------------------------- */ -static struct at91_gpio_bank at91sam9rl_gpio[] = { +static struct at91_gpio_bank at91sam9rl_gpio[] __initdata = { { .id = AT91SAM9RL_ID_PIOA, - .offset = AT91_PIOA, - .clock = &pioA_clk, + .regbase = AT91SAM9RL_BASE_PIOA, }, { .id = AT91SAM9RL_ID_PIOB, - .offset = AT91_PIOB, - .clock = &pioB_clk, + .regbase = AT91SAM9RL_BASE_PIOB, }, { .id = AT91SAM9RL_ID_PIOC, - .offset = AT91_PIOC, - .clock = &pioC_clk, + .regbase = AT91SAM9RL_BASE_PIOC, }, { .id = AT91SAM9RL_ID_PIOD, - .offset = AT91_PIOD, - .clock = &pioD_clk, + .regbase = AT91SAM9RL_BASE_PIOD, } }; -static void at91sam9rl_poweroff(void) -{ - at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW); -} - - /* -------------------------------------------------------------------- * AT91SAM9RL processor initialization * -------------------------------------------------------------------- */ @@ -290,10 +283,16 @@ static void __init at91sam9rl_map_io(void) at91_init_sram(0, AT91SAM9RL_SRAM_BASE, sram_size); } +static void __init at91sam9rl_ioremap_registers(void) +{ + at91_ioremap_shdwc(AT91SAM9RL_BASE_SHDWC); + at91sam926x_ioremap_pit(AT91SAM9RL_BASE_PIT); + at91sam9_ioremap_smc(0, AT91SAM9RL_BASE_SMC); +} + static void __init at91sam9rl_initialize(void) { arm_pm_restart = at91sam9_alt_restart; - pm_power_off = at91sam9rl_poweroff; at91_extern_irq = (1 << AT91SAM9RL_ID_IRQ0); /* Register GPIO subsystem */ @@ -345,6 +344,7 @@ static unsigned int at91sam9rl_default_irq_priority[NR_AIC_IRQS] __initdata = { struct at91_init_soc __initdata at91sam9rl_soc = { .map_io = at91sam9rl_map_io, .default_irq_priority = at91sam9rl_default_irq_priority, + .ioremap_registers = at91sam9rl_ioremap_registers, .register_clocks = at91sam9rl_register_clocks, .init = at91sam9rl_initialize, }; diff --git a/arch/arm/mach-at91/at91sam9rl_devices.c b/arch/arm/mach-at91/at91sam9rl_devices.c index 628eb566d60..61908dce978 100644 --- a/arch/arm/mach-at91/at91sam9rl_devices.c +++ b/arch/arm/mach-at91/at91sam9rl_devices.c @@ -39,8 +39,8 @@ static struct at_dma_platform_data atdma_pdata = { static struct resource hdmac_resources[] = { [0] = { - .start = AT91_BASE_SYS + AT91_DMA, - .end = AT91_BASE_SYS + AT91_DMA + SZ_512 - 1, + .start = AT91SAM9RL_BASE_DMA, + .end = AT91SAM9RL_BASE_DMA + SZ_512 - 1, .flags = IORESOURCE_MEM, }, [2] = { @@ -147,7 +147,7 @@ void __init at91_add_device_usba(struct usba_platform_data *data) usba_udc_data.pdata.num_ep = ARRAY_SIZE(usba_udc_ep); memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep)); - if (data && data->vbus_pin > 0) { + if (data && gpio_is_valid(data->vbus_pin)) { at91_set_gpio_input(data->vbus_pin, 0); at91_set_deglitch(data->vbus_pin, 1); usba_udc_data.pdata.vbus_pin = data->vbus_pin; @@ -201,13 +201,13 @@ void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) return; /* input/irq */ - if (data->det_pin) { + if (gpio_is_valid(data->det_pin)) { at91_set_gpio_input(data->det_pin, 1); at91_set_deglitch(data->det_pin, 1); } - if (data->wp_pin) + if (gpio_is_valid(data->wp_pin)) at91_set_gpio_input(data->wp_pin, 1); - if (data->vcc_pin) + if (gpio_is_valid(data->vcc_pin)) at91_set_gpio_output(data->vcc_pin, 0); /* CLK */ @@ -248,8 +248,8 @@ static struct resource nand_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = AT91_BASE_SYS + AT91_ECC, - .end = AT91_BASE_SYS + AT91_ECC + SZ_512 - 1, + .start = AT91SAM9RL_BASE_ECC, + .end = AT91SAM9RL_BASE_ECC + SZ_512 - 1, .flags = IORESOURCE_MEM, } }; @@ -275,15 +275,15 @@ void __init at91_add_device_nand(struct atmel_nand_data *data) at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA); /* enable pin */ - if (data->enable_pin) + if (gpio_is_valid(data->enable_pin)) at91_set_gpio_output(data->enable_pin, 1); /* ready/busy pin */ - if (data->rdy_pin) + if (gpio_is_valid(data->rdy_pin)) at91_set_gpio_input(data->rdy_pin, 1); /* card detect pin */ - if (data->det_pin) + if (gpio_is_valid(data->det_pin)) at91_set_gpio_input(data->det_pin, 1); at91_set_A_periph(AT91_PIN_PB4, 0); /* NANDOE */ @@ -483,7 +483,7 @@ void __init at91_add_device_ac97(struct ac97c_platform_data *data) at91_set_A_periph(AT91_PIN_PD4, 0); /* AC97RX */ /* reset */ - if (data->reset_pin) + if (gpio_is_valid(data->reset_pin)) at91_set_gpio_output(data->reset_pin, 0); ac97_data = *data; @@ -685,8 +685,8 @@ static void __init at91_add_device_rtc(void) {} static struct resource rtt_resources[] = { { - .start = AT91_BASE_SYS + AT91_RTT, - .end = AT91_BASE_SYS + AT91_RTT + SZ_16 - 1, + .start = AT91SAM9RL_BASE_RTT, + .end = AT91SAM9RL_BASE_RTT + SZ_16 - 1, .flags = IORESOURCE_MEM, } }; @@ -709,10 +709,19 @@ static void __init at91_add_device_rtt(void) * -------------------------------------------------------------------- */ #if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE) +static struct resource wdt_resources[] = { + { + .start = AT91SAM9RL_BASE_WDT, + .end = AT91SAM9RL_BASE_WDT + SZ_16 - 1, + .flags = IORESOURCE_MEM, + } +}; + static struct platform_device at91sam9rl_wdt_device = { .name = "at91_wdt", .id = -1, - .num_resources = 0, + .resource = wdt_resources, + .num_resources = ARRAY_SIZE(wdt_resources), }; static void __init at91_add_device_watchdog(void) @@ -908,8 +917,8 @@ void __init at91_add_device_ssc(unsigned id, unsigned pins) {} #if defined(CONFIG_SERIAL_ATMEL) static struct resource dbgu_resources[] = { [0] = { - .start = AT91_BASE_SYS + AT91_DBGU, - .end = AT91_BASE_SYS + AT91_DBGU + SZ_512 - 1, + .start = AT91SAM9RL_BASE_DBGU, + .end = AT91SAM9RL_BASE_DBGU + SZ_512 - 1, .flags = IORESOURCE_MEM, }, [1] = { diff --git a/arch/arm/mach-at91/board-1arm.c b/arch/arm/mach-at91/board-1arm.c index 367d5cd5e36..2628384aaae 100644 --- a/arch/arm/mach-at91/board-1arm.c +++ b/arch/arm/mach-at91/board-1arm.c @@ -63,13 +63,15 @@ static void __init onearm_init_early(void) at91_set_serial_console(0); } -static struct at91_eth_data __initdata onearm_eth_data = { +static struct macb_platform_data __initdata onearm_eth_data = { .phy_irq_pin = AT91_PIN_PC4, .is_rmii = 1, }; static struct at91_usbh_data __initdata onearm_usbh_data = { .ports = 1, + .vbus_pin = {-EINVAL, -EINVAL}, + .overcurrent_pin= {-EINVAL, -EINVAL}, }; static struct at91_udc_data __initdata onearm_udc_data = { diff --git a/arch/arm/mach-at91/board-afeb-9260v1.c b/arch/arm/mach-at91/board-afeb-9260v1.c index 4282d96dffa..3bb40694b02 100644 --- a/arch/arm/mach-at91/board-afeb-9260v1.c +++ b/arch/arm/mach-at91/board-afeb-9260v1.c @@ -75,6 +75,8 @@ static void __init afeb9260_init_early(void) */ static struct at91_usbh_data __initdata afeb9260_usbh_data = { .ports = 1, + .vbus_pin = {-EINVAL, -EINVAL}, + .overcurrent_pin= {-EINVAL, -EINVAL}, }; /* @@ -82,7 +84,7 @@ static struct at91_usbh_data __initdata afeb9260_usbh_data = { */ static struct at91_udc_data __initdata afeb9260_udc_data = { .vbus_pin = AT91_PIN_PC5, - .pullup_pin = 0, /* pull-up driven by UDC */ + .pullup_pin = -EINVAL, /* pull-up driven by UDC */ }; @@ -103,7 +105,7 @@ static struct spi_board_info afeb9260_spi_devices[] = { /* * MACB Ethernet device */ -static struct at91_eth_data __initdata afeb9260_macb_data = { +static struct macb_platform_data __initdata afeb9260_macb_data = { .phy_irq_pin = AT91_PIN_PA9, .is_rmii = 0, }; @@ -138,6 +140,7 @@ static struct atmel_nand_data __initdata afeb9260_nand_data = { .bus_width_16 = 0, .parts = afeb9260_nand_partition, .num_parts = ARRAY_SIZE(afeb9260_nand_partition), + .det_pin = -EINVAL, }; @@ -149,6 +152,7 @@ static struct at91_mmc_data __initdata afeb9260_mmc_data = { .wp_pin = AT91_PIN_PC4, .slot_b = 1, .wire4 = 1, + .vcc_pin = -EINVAL, }; @@ -169,6 +173,8 @@ static struct i2c_board_info __initdata afeb9260_i2c_devices[] = { static struct at91_cf_data afeb9260_cf_data = { .chipselect = 4, .irq_pin = AT91_PIN_PA6, + .det_pin = -EINVAL, + .vcc_pin = -EINVAL, .rst_pin = AT91_PIN_PA7, .flags = AT91_CF_TRUE_IDE, }; diff --git a/arch/arm/mach-at91/board-cam60.c b/arch/arm/mach-at91/board-cam60.c index f90cfb32bad..8510e9e5498 100644 --- a/arch/arm/mach-at91/board-cam60.c +++ b/arch/arm/mach-at91/board-cam60.c @@ -62,6 +62,8 @@ static void __init cam60_init_early(void) */ static struct at91_usbh_data __initdata cam60_usbh_data = { .ports = 1, + .vbus_pin = {-EINVAL, -EINVAL}, + .overcurrent_pin= {-EINVAL, -EINVAL}, }; @@ -115,7 +117,7 @@ static struct spi_board_info cam60_spi_devices[] __initdata = { /* * MACB Ethernet device */ -static struct __initdata at91_eth_data cam60_macb_data = { +static struct __initdata macb_platform_data cam60_macb_data = { .phy_irq_pin = AT91_PIN_PB5, .is_rmii = 0, }; @@ -135,7 +137,7 @@ static struct mtd_partition __initdata cam60_nand_partition[] = { static struct atmel_nand_data __initdata cam60_nand_data = { .ale = 21, .cle = 22, - // .det_pin = ... not there + .det_pin = -EINVAL, .rdy_pin = AT91_PIN_PA9, .enable_pin = AT91_PIN_PA7, .parts = cam60_nand_partition, @@ -163,7 +165,7 @@ static struct sam9_smc_config __initdata cam60_nand_smc_config = { static void __init cam60_add_device_nand(void) { /* configure chip-select 3 (NAND) */ - sam9_smc_configure(3, &cam60_nand_smc_config); + sam9_smc_configure(0, 3, &cam60_nand_smc_config); at91_add_device_nand(&cam60_nand_data); } diff --git a/arch/arm/mach-at91/board-cap9adk.c b/arch/arm/mach-at91/board-cap9adk.c index 5dffd3be62d..ac3de4f7c31 100644 --- a/arch/arm/mach-at91/board-cap9adk.c +++ b/arch/arm/mach-at91/board-cap9adk.c @@ -70,6 +70,8 @@ static void __init cap9adk_init_early(void) */ static struct at91_usbh_data __initdata cap9adk_usbh_data = { .ports = 2, + .vbus_pin = {-EINVAL, -EINVAL}, + .overcurrent_pin= {-EINVAL, -EINVAL}, }; /* @@ -144,16 +146,17 @@ static struct spi_board_info cap9adk_spi_devices[] = { */ static struct at91_mmc_data __initdata cap9adk_mmc_data = { .wire4 = 1, -// .det_pin = ... not connected -// .wp_pin = ... not connected -// .vcc_pin = ... not connected + .det_pin = -EINVAL, + .wp_pin = -EINVAL, + .vcc_pin = -EINVAL, }; /* * MACB Ethernet device */ -static struct at91_eth_data __initdata cap9adk_macb_data = { +static struct macb_platform_data __initdata cap9adk_macb_data = { + .phy_irq_pin = -EINVAL, .is_rmii = 1, }; @@ -172,8 +175,8 @@ static struct mtd_partition __initdata cap9adk_nand_partitions[] = { static struct atmel_nand_data __initdata cap9adk_nand_data = { .ale = 21, .cle = 22, -// .det_pin = ... not connected -// .rdy_pin = ... not connected + .det_pin = -EINVAL, + .rdy_pin = -EINVAL, .enable_pin = AT91_PIN_PD15, .parts = cap9adk_nand_partitions, .num_parts = ARRAY_SIZE(cap9adk_nand_partitions), @@ -212,7 +215,7 @@ static void __init cap9adk_add_device_nand(void) cap9adk_nand_smc_config.mode |= AT91_SMC_DBW_8; /* configure chip-select 3 (NAND) */ - sam9_smc_configure(3, &cap9adk_nand_smc_config); + sam9_smc_configure(0, 3, &cap9adk_nand_smc_config); at91_add_device_nand(&cap9adk_nand_data); } @@ -282,7 +285,7 @@ static __init void cap9adk_add_device_nor(void) at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_VDDIOMSEL_3_3V); /* configure chip-select 0 (NOR) */ - sam9_smc_configure(0, &cap9adk_nor_smc_config); + sam9_smc_configure(0, 0, &cap9adk_nor_smc_config); platform_device_register(&cap9adk_nor_flash); } @@ -351,7 +354,7 @@ static struct atmel_lcdfb_info __initdata cap9adk_lcdc_data; * AC97 */ static struct ac97c_platform_data cap9adk_ac97_data = { -// .reset_pin = ... not connected + .reset_pin = -EINVAL, }; diff --git a/arch/arm/mach-at91/board-carmeva.c b/arch/arm/mach-at91/board-carmeva.c index 774c87fcbd5..59d9cf99753 100644 --- a/arch/arm/mach-at91/board-carmeva.c +++ b/arch/arm/mach-at91/board-carmeva.c @@ -57,13 +57,15 @@ static void __init carmeva_init_early(void) at91_set_serial_console(0); } -static struct at91_eth_data __initdata carmeva_eth_data = { +static struct macb_platform_data __initdata carmeva_eth_data = { .phy_irq_pin = AT91_PIN_PC4, .is_rmii = 1, }; static struct at91_usbh_data __initdata carmeva_usbh_data = { .ports = 2, + .vbus_pin = {-EINVAL, -EINVAL}, + .overcurrent_pin= {-EINVAL, -EINVAL}, }; static struct at91_udc_data __initdata carmeva_udc_data = { @@ -75,8 +77,8 @@ static struct at91_udc_data __initdata carmeva_udc_data = { // static struct at91_cf_data __initdata carmeva_cf_data = { // .det_pin = AT91_PIN_PB0, // .rst_pin = AT91_PIN_PC5, - // .irq_pin = ... not connected - // .vcc_pin = ... always powered + // .irq_pin = -EINVAL, + // .vcc_pin = -EINVAL, // }; static struct at91_mmc_data __initdata carmeva_mmc_data = { @@ -84,6 +86,7 @@ static struct at91_mmc_data __initdata carmeva_mmc_data = { .wire4 = 1, .det_pin = AT91_PIN_PB10, .wp_pin = AT91_PIN_PC14, + .vcc_pin = -EINVAL, }; static struct spi_board_info carmeva_spi_devices[] = { diff --git a/arch/arm/mach-at91/board-cpu9krea.c b/arch/arm/mach-at91/board-cpu9krea.c index fc885a4ce24..9ab3d1ea326 100644 --- a/arch/arm/mach-at91/board-cpu9krea.c +++ b/arch/arm/mach-at91/board-cpu9krea.c @@ -86,6 +86,8 @@ static void __init cpu9krea_init_early(void) */ static struct at91_usbh_data __initdata cpu9krea_usbh_data = { .ports = 2, + .vbus_pin = {-EINVAL, -EINVAL}, + .overcurrent_pin= {-EINVAL, -EINVAL}, }; /* @@ -93,13 +95,14 @@ static struct at91_usbh_data __initdata cpu9krea_usbh_data = { */ static struct at91_udc_data __initdata cpu9krea_udc_data = { .vbus_pin = AT91_PIN_PC8, - .pullup_pin = 0, /* pull-up driven by UDC */ + .pullup_pin = -EINVAL, /* pull-up driven by UDC */ }; /* * MACB Ethernet device */ -static struct at91_eth_data __initdata cpu9krea_macb_data = { +static struct macb_platform_data __initdata cpu9krea_macb_data = { + .phy_irq_pin = -EINVAL, .is_rmii = 1, }; @@ -112,6 +115,7 @@ static struct atmel_nand_data __initdata cpu9krea_nand_data = { .rdy_pin = AT91_PIN_PC13, .enable_pin = AT91_PIN_PC14, .bus_width_16 = 0, + .det_pin = -EINVAL, }; #ifdef CONFIG_MACH_CPU9260 @@ -156,7 +160,7 @@ static struct sam9_smc_config __initdata cpu9krea_nand_smc_config = { static void __init cpu9krea_add_device_nand(void) { - sam9_smc_configure(3, &cpu9krea_nand_smc_config); + sam9_smc_configure(0, 3, &cpu9krea_nand_smc_config); at91_add_device_nand(&cpu9krea_nand_data); } @@ -238,7 +242,7 @@ static __init void cpu9krea_add_device_nor(void) at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_VDDIOMSEL_3_3V); /* configure chip-select 0 (NOR) */ - sam9_smc_configure(0, &cpu9krea_nor_smc_config); + sam9_smc_configure(0, 0, &cpu9krea_nor_smc_config); platform_device_register(&cpu9krea_nor_flash); } @@ -337,6 +341,8 @@ static struct at91_mmc_data __initdata cpu9krea_mmc_data = { .slot_b = 0, .wire4 = 1, .det_pin = AT91_PIN_PA29, + .wp_pin = -EINVAL, + .vcc_pin = -EINVAL, }; static void __init cpu9krea_board_init(void) diff --git a/arch/arm/mach-at91/board-cpuat91.c b/arch/arm/mach-at91/board-cpuat91.c index d35e65b08cc..368e1427ad9 100644 --- a/arch/arm/mach-at91/board-cpuat91.c +++ b/arch/arm/mach-at91/board-cpuat91.c @@ -82,12 +82,15 @@ static void __init cpuat91_init_early(void) at91_set_serial_console(0); } -static struct at91_eth_data __initdata cpuat91_eth_data = { +static struct macb_platform_data __initdata cpuat91_eth_data = { + .phy_irq_pin = -EINVAL, .is_rmii = 1, }; static struct at91_usbh_data __initdata cpuat91_usbh_data = { .ports = 1, + .vbus_pin = {-EINVAL, -EINVAL}, + .overcurrent_pin= {-EINVAL, -EINVAL}, }; static struct at91_udc_data __initdata cpuat91_udc_data = { @@ -98,6 +101,8 @@ static struct at91_udc_data __initdata cpuat91_udc_data = { static struct at91_mmc_data __initdata cpuat91_mmc_data = { .det_pin = AT91_PIN_PC2, .wire4 = 1, + .wp_pin = -EINVAL, + .vcc_pin = -EINVAL, }; static struct physmap_flash_data cpuat91_flash_data = { diff --git a/arch/arm/mach-at91/board-csb337.c b/arch/arm/mach-at91/board-csb337.c index c3936665e64..1a1547b1ce4 100644 --- a/arch/arm/mach-at91/board-csb337.c +++ b/arch/arm/mach-at91/board-csb337.c @@ -58,18 +58,20 @@ static void __init csb337_init_early(void) at91_set_serial_console(0); } -static struct at91_eth_data __initdata csb337_eth_data = { +static struct macb_platform_data __initdata csb337_eth_data = { .phy_irq_pin = AT91_PIN_PC2, .is_rmii = 0, }; static struct at91_usbh_data __initdata csb337_usbh_data = { .ports = 2, + .vbus_pin = {-EINVAL, -EINVAL}, + .overcurrent_pin= {-EINVAL, -EINVAL}, }; static struct at91_udc_data __initdata csb337_udc_data = { - // this has no VBUS sensing pin .pullup_pin = AT91_PIN_PA24, + .vbus_pin = -EINVAL, }; static struct i2c_board_info __initdata csb337_i2c_devices[] = { @@ -98,6 +100,7 @@ static struct at91_mmc_data __initdata csb337_mmc_data = { .slot_b = 0, .wire4 = 1, .wp_pin = AT91_PIN_PD6, + .vcc_pin = -EINVAL, }; static struct spi_board_info csb337_spi_devices[] = { diff --git a/arch/arm/mach-at91/board-csb637.c b/arch/arm/mach-at91/board-csb637.c index 586100e2acb..f650bf39455 100644 --- a/arch/arm/mach-at91/board-csb637.c +++ b/arch/arm/mach-at91/board-csb637.c @@ -52,13 +52,15 @@ static void __init csb637_init_early(void) at91_set_serial_console(0); } -static struct at91_eth_data __initdata csb637_eth_data = { +static struct macb_platform_data __initdata csb637_eth_data = { .phy_irq_pin = AT91_PIN_PC0, .is_rmii = 0, }; static struct at91_usbh_data __initdata csb637_usbh_data = { .ports = 2, + .vbus_pin = {-EINVAL, -EINVAL}, + .overcurrent_pin= {-EINVAL, -EINVAL}, }; static struct at91_udc_data __initdata csb637_udc_data = { diff --git a/arch/arm/mach-at91/board-dt.c b/arch/arm/mach-at91/board-dt.c index 0b7d3277821..bb6b434ec0c 100644 --- a/arch/arm/mach-at91/board-dt.c +++ b/arch/arm/mach-at91/board-dt.c @@ -50,6 +50,7 @@ static void __init ek_init_early(void) static struct atmel_nand_data __initdata ek_nand_data = { .ale = 21, .cle = 22, + .det_pin = -EINVAL, .rdy_pin = AT91_PIN_PC8, .enable_pin = AT91_PIN_PC14, }; @@ -82,7 +83,7 @@ static void __init ek_add_device_nand(void) ek_nand_smc_config.mode |= AT91_SMC_DBW_8; /* configure chip-select 3 (NAND) */ - sam9_smc_configure(3, &ek_nand_smc_config); + sam9_smc_configure(0, 3, &ek_nand_smc_config); at91_add_device_nand(&ek_nand_data); } diff --git a/arch/arm/mach-at91/board-eb9200.c b/arch/arm/mach-at91/board-eb9200.c index 45db7a3dbef..d302ca3eeb6 100644 --- a/arch/arm/mach-at91/board-eb9200.c +++ b/arch/arm/mach-at91/board-eb9200.c @@ -60,13 +60,15 @@ static void __init eb9200_init_early(void) at91_set_serial_console(0); } -static struct at91_eth_data __initdata eb9200_eth_data = { +static struct macb_platform_data __initdata eb9200_eth_data = { .phy_irq_pin = AT91_PIN_PC4, .is_rmii = 1, }; static struct at91_usbh_data __initdata eb9200_usbh_data = { .ports = 2, + .vbus_pin = {-EINVAL, -EINVAL}, + .overcurrent_pin= {-EINVAL, -EINVAL}, }; static struct at91_udc_data __initdata eb9200_udc_data = { @@ -75,15 +77,18 @@ static struct at91_udc_data __initdata eb9200_udc_data = { }; static struct at91_cf_data __initdata eb9200_cf_data = { + .irq_pin = -EINVAL, .det_pin = AT91_PIN_PB0, + .vcc_pin = -EINVAL, .rst_pin = AT91_PIN_PC5, - // .irq_pin = ... not connected - // .vcc_pin = ... always powered }; static struct at91_mmc_data __initdata eb9200_mmc_data = { .slot_b = 0, .wire4 = 1, + .det_pin = -EINVAL, + .wp_pin = -EINVAL, + .vcc_pin = -EINVAL, }; static struct i2c_board_info __initdata eb9200_i2c_devices[] = { diff --git a/arch/arm/mach-at91/board-ecbat91.c b/arch/arm/mach-at91/board-ecbat91.c index 2f9c16d2921..69966ce4d77 100644 --- a/arch/arm/mach-at91/board-ecbat91.c +++ b/arch/arm/mach-at91/board-ecbat91.c @@ -64,18 +64,23 @@ static void __init ecb_at91init_early(void) at91_set_serial_console(0); } -static struct at91_eth_data __initdata ecb_at91eth_data = { +static struct macb_platform_data __initdata ecb_at91eth_data = { .phy_irq_pin = AT91_PIN_PC4, .is_rmii = 0, }; static struct at91_usbh_data __initdata ecb_at91usbh_data = { .ports = 1, + .vbus_pin = {-EINVAL, -EINVAL}, + .overcurrent_pin= {-EINVAL, -EINVAL}, }; static struct at91_mmc_data __initdata ecb_at91mmc_data = { .slot_b = 0, .wire4 = 1, + .det_pin = -EINVAL, + .wp_pin = -EINVAL, + .vcc_pin = -EINVAL, }; diff --git a/arch/arm/mach-at91/board-eco920.c b/arch/arm/mach-at91/board-eco920.c index 8252c722607..07ef35b0ec2 100644 --- a/arch/arm/mach-at91/board-eco920.c +++ b/arch/arm/mach-at91/board-eco920.c @@ -47,13 +47,15 @@ static void __init eco920_init_early(void) at91_set_serial_console(0); } -static struct at91_eth_data __initdata eco920_eth_data = { +static struct macb_platform_data __initdata eco920_eth_data = { .phy_irq_pin = AT91_PIN_PC2, .is_rmii = 1, }; static struct at91_usbh_data __initdata eco920_usbh_data = { .ports = 1, + .vbus_pin = {-EINVAL, -EINVAL}, + .overcurrent_pin= {-EINVAL, -EINVAL}, }; static struct at91_udc_data __initdata eco920_udc_data = { @@ -64,6 +66,9 @@ static struct at91_udc_data __initdata eco920_udc_data = { static struct at91_mmc_data __initdata eco920_mmc_data = { .slot_b = 0, .wire4 = 0, + .det_pin = -EINVAL, + .wp_pin = -EINVAL, + .vcc_pin = -EINVAL, }; static struct physmap_flash_data eco920_flash_data = { diff --git a/arch/arm/mach-at91/board-flexibity.c b/arch/arm/mach-at91/board-flexibity.c index 4c3f65d9c59..eec02cd57ce 100644 --- a/arch/arm/mach-at91/board-flexibity.c +++ b/arch/arm/mach-at91/board-flexibity.c @@ -52,12 +52,14 @@ static void __init flexibity_init_early(void) /* USB Host port */ static struct at91_usbh_data __initdata flexibity_usbh_data = { .ports = 2, + .vbus_pin = {-EINVAL, -EINVAL}, + .overcurrent_pin= {-EINVAL, -EINVAL}, }; /* USB Device port */ static struct at91_udc_data __initdata flexibity_udc_data = { .vbus_pin = AT91_PIN_PC5, - .pullup_pin = 0, /* pull-up driven by UDC */ + .pullup_pin = -EINVAL, /* pull-up driven by UDC */ }; /* SPI devices */ @@ -76,6 +78,7 @@ static struct at91_mmc_data __initdata flexibity_mmc_data = { .wire4 = 1, .det_pin = AT91_PIN_PC9, .wp_pin = AT91_PIN_PC4, + .vcc_pin = -EINVAL, }; /* LEDs */ diff --git a/arch/arm/mach-at91/board-foxg20.c b/arch/arm/mach-at91/board-foxg20.c index f27d1a780cf..caf017f0f4e 100644 --- a/arch/arm/mach-at91/board-foxg20.c +++ b/arch/arm/mach-at91/board-foxg20.c @@ -106,6 +106,8 @@ static void __init foxg20_init_early(void) */ static struct at91_usbh_data __initdata foxg20_usbh_data = { .ports = 2, + .vbus_pin = {-EINVAL, -EINVAL}, + .overcurrent_pin= {-EINVAL, -EINVAL}, }; /* @@ -113,7 +115,7 @@ static struct at91_usbh_data __initdata foxg20_usbh_data = { */ static struct at91_udc_data __initdata foxg20_udc_data = { .vbus_pin = AT91_PIN_PC6, - .pullup_pin = 0, /* pull-up driven by UDC */ + .pullup_pin = -EINVAL, /* pull-up driven by UDC */ }; @@ -135,7 +137,7 @@ static struct spi_board_info foxg20_spi_devices[] = { /* * MACB Ethernet device */ -static struct at91_eth_data __initdata foxg20_macb_data = { +static struct macb_platform_data __initdata foxg20_macb_data = { .phy_irq_pin = AT91_PIN_PA7, .is_rmii = 1, }; @@ -147,6 +149,9 @@ static struct at91_eth_data __initdata foxg20_macb_data = { static struct at91_mmc_data __initdata foxg20_mmc_data = { .slot_b = 1, .wire4 = 1, + .det_pin = -EINVAL, + .wp_pin = -EINVAL, + .vcc_pin = -EINVAL, }; diff --git a/arch/arm/mach-at91/board-gsia18s.c b/arch/arm/mach-at91/board-gsia18s.c index 2e95949737e..230e71969fb 100644 --- a/arch/arm/mach-at91/board-gsia18s.c +++ b/arch/arm/mach-at91/board-gsia18s.c @@ -80,6 +80,8 @@ static void __init gsia18s_init_early(void) */ static struct at91_usbh_data __initdata usbh_data = { .ports = 2, + .vbus_pin = {-EINVAL, -EINVAL}, + .overcurrent_pin= {-EINVAL, -EINVAL}, }; /* @@ -87,13 +89,13 @@ static struct at91_usbh_data __initdata usbh_data = { */ static struct at91_udc_data __initdata udc_data = { .vbus_pin = AT91_PIN_PA22, - .pullup_pin = 0, /* pull-up driven by UDC */ + .pullup_pin = -EINVAL, /* pull-up driven by UDC */ }; /* * MACB Ethernet device */ -static struct at91_eth_data __initdata macb_data = { +static struct macb_platform_data __initdata macb_data = { .phy_irq_pin = AT91_PIN_PA28, .is_rmii = 1, }; @@ -530,6 +532,7 @@ static struct i2c_board_info __initdata gsia18s_i2c_devices[] = { static struct at91_cf_data __initdata gsia18s_cf1_data = { .irq_pin = AT91_PIN_PA27, .det_pin = AT91_PIN_PB30, + .vcc_pin = -EINVAL, .rst_pin = AT91_PIN_PB31, .chipselect = 5, .flags = AT91_CF_TRUE_IDE, diff --git a/arch/arm/mach-at91/board-kafa.c b/arch/arm/mach-at91/board-kafa.c index 3bae73e6363..efde1b2327c 100644 --- a/arch/arm/mach-at91/board-kafa.c +++ b/arch/arm/mach-at91/board-kafa.c @@ -61,13 +61,15 @@ static void __init kafa_init_early(void) at91_set_serial_console(0); } -static struct at91_eth_data __initdata kafa_eth_data = { +static struct macb_platform_data __initdata kafa_eth_data = { .phy_irq_pin = AT91_PIN_PC4, .is_rmii = 0, }; static struct at91_usbh_data __initdata kafa_usbh_data = { .ports = 1, + .vbus_pin = {-EINVAL, -EINVAL}, + .overcurrent_pin= {-EINVAL, -EINVAL}, }; static struct at91_udc_data __initdata kafa_udc_data = { diff --git a/arch/arm/mach-at91/board-kb9202.c b/arch/arm/mach-at91/board-kb9202.c index e61351ffad5..d75a4a2ad9c 100644 --- a/arch/arm/mach-at91/board-kb9202.c +++ b/arch/arm/mach-at91/board-kb9202.c @@ -69,13 +69,15 @@ static void __init kb9202_init_early(void) at91_set_serial_console(0); } -static struct at91_eth_data __initdata kb9202_eth_data = { +static struct macb_platform_data __initdata kb9202_eth_data = { .phy_irq_pin = AT91_PIN_PB29, .is_rmii = 0, }; static struct at91_usbh_data __initdata kb9202_usbh_data = { .ports = 1, + .vbus_pin = {-EINVAL, -EINVAL}, + .overcurrent_pin= {-EINVAL, -EINVAL}, }; static struct at91_udc_data __initdata kb9202_udc_data = { @@ -87,6 +89,8 @@ static struct at91_mmc_data __initdata kb9202_mmc_data = { .det_pin = AT91_PIN_PB2, .slot_b = 0, .wire4 = 1, + .wp_pin = -EINVAL, + .vcc_pin = -EINVAL, }; static struct mtd_partition __initdata kb9202_nand_partition[] = { @@ -100,7 +104,7 @@ static struct mtd_partition __initdata kb9202_nand_partition[] = { static struct atmel_nand_data __initdata kb9202_nand_data = { .ale = 22, .cle = 21, - // .det_pin = ... not there + .det_pin = -EINVAL, .rdy_pin = AT91_PIN_PC29, .enable_pin = AT91_PIN_PC28, .parts = kb9202_nand_partition, diff --git a/arch/arm/mach-at91/board-neocore926.c b/arch/arm/mach-at91/board-neocore926.c index ef816c17dc6..3f8617c0e04 100644 --- a/arch/arm/mach-at91/board-neocore926.c +++ b/arch/arm/mach-at91/board-neocore926.c @@ -72,6 +72,7 @@ static void __init neocore926_init_early(void) static struct at91_usbh_data __initdata neocore926_usbh_data = { .ports = 2, .vbus_pin = { AT91_PIN_PA24, AT91_PIN_PA21 }, + .overcurrent_pin= {-EINVAL, -EINVAL}, }; /* @@ -79,7 +80,7 @@ static struct at91_usbh_data __initdata neocore926_usbh_data = { */ static struct at91_udc_data __initdata neocore926_udc_data = { .vbus_pin = AT91_PIN_PA25, - .pullup_pin = 0, /* pull-up driven by UDC */ + .pullup_pin = -EINVAL, /* pull-up driven by UDC */ }; @@ -149,13 +150,14 @@ static struct at91_mmc_data __initdata neocore926_mmc_data = { .wire4 = 1, .det_pin = AT91_PIN_PE18, .wp_pin = AT91_PIN_PE19, + .vcc_pin = -EINVAL, }; /* * MACB Ethernet device */ -static struct at91_eth_data __initdata neocore926_macb_data = { +static struct macb_platform_data __initdata neocore926_macb_data = { .phy_irq_pin = AT91_PIN_PE31, .is_rmii = 1, }; @@ -190,6 +192,7 @@ static struct atmel_nand_data __initdata neocore926_nand_data = { .enable_pin = AT91_PIN_PD15, .parts = neocore926_nand_partition, .num_parts = ARRAY_SIZE(neocore926_nand_partition), + .det_pin = -EINVAL, }; static struct sam9_smc_config __initdata neocore926_nand_smc_config = { @@ -213,7 +216,7 @@ static struct sam9_smc_config __initdata neocore926_nand_smc_config = { static void __init neocore926_add_device_nand(void) { /* configure chip-select 3 (NAND) */ - sam9_smc_configure(3, &neocore926_nand_smc_config); + sam9_smc_configure(0, 3, &neocore926_nand_smc_config); at91_add_device_nand(&neocore926_nand_data); } diff --git a/arch/arm/mach-at91/board-pcontrol-g20.c b/arch/arm/mach-at91/board-pcontrol-g20.c index 49e3f699b48..b4a12fc184c 100644 --- a/arch/arm/mach-at91/board-pcontrol-g20.c +++ b/arch/arm/mach-at91/board-pcontrol-g20.c @@ -96,9 +96,9 @@ static struct sam9_smc_config __initdata pcontrol_smc_config[2] = { { static void __init add_device_pcontrol(void) { /* configure chip-select 4 (IO compatible to 8051 X4 ) */ - sam9_smc_configure(4, &pcontrol_smc_config[0]); + sam9_smc_configure(0, 4, &pcontrol_smc_config[0]); /* configure chip-select 7 (FerroRAM 256KiBx16bit MR2A16A D4 ) */ - sam9_smc_configure(7, &pcontrol_smc_config[1]); + sam9_smc_configure(0, 7, &pcontrol_smc_config[1]); } @@ -107,6 +107,8 @@ static void __init add_device_pcontrol(void) */ static struct at91_usbh_data __initdata usbh_data = { .ports = 2, + .vbus_pin = {-EINVAL, -EINVAL}, + .overcurrent_pin= {-EINVAL, -EINVAL}, }; @@ -122,7 +124,7 @@ static struct at91_udc_data __initdata pcontrol_g20_udc_data = { /* * MACB Ethernet device */ -static struct at91_eth_data __initdata macb_data = { +static struct macb_platform_data __initdata macb_data = { .phy_irq_pin = AT91_PIN_PA28, .is_rmii = 1, }; diff --git a/arch/arm/mach-at91/board-picotux200.c b/arch/arm/mach-at91/board-picotux200.c index 0a8fe6a1b7c..ab024fa11d5 100644 --- a/arch/arm/mach-at91/board-picotux200.c +++ b/arch/arm/mach-at91/board-picotux200.c @@ -60,13 +60,15 @@ static void __init picotux200_init_early(void) at91_set_serial_console(0); } -static struct at91_eth_data __initdata picotux200_eth_data = { +static struct macb_platform_data __initdata picotux200_eth_data = { .phy_irq_pin = AT91_PIN_PC4, .is_rmii = 1, }; static struct at91_usbh_data __initdata picotux200_usbh_data = { .ports = 1, + .vbus_pin = {-EINVAL, -EINVAL}, + .overcurrent_pin= {-EINVAL, -EINVAL}, }; static struct at91_mmc_data __initdata picotux200_mmc_data = { @@ -74,6 +76,7 @@ static struct at91_mmc_data __initdata picotux200_mmc_data = { .slot_b = 0, .wire4 = 1, .wp_pin = AT91_PIN_PA17, + .vcc_pin = -EINVAL, }; #define PICOTUX200_FLASH_BASE AT91_CHIPSELECT_0 diff --git a/arch/arm/mach-at91/board-qil-a9260.c b/arch/arm/mach-at91/board-qil-a9260.c index 07421bdb88e..e029d220cb8 100644 --- a/arch/arm/mach-at91/board-qil-a9260.c +++ b/arch/arm/mach-at91/board-qil-a9260.c @@ -77,6 +77,8 @@ static void __init ek_init_early(void) */ static struct at91_usbh_data __initdata ek_usbh_data = { .ports = 2, + .vbus_pin = {-EINVAL, -EINVAL}, + .overcurrent_pin= {-EINVAL, -EINVAL}, }; /* @@ -84,7 +86,7 @@ static struct at91_usbh_data __initdata ek_usbh_data = { */ static struct at91_udc_data __initdata ek_udc_data = { .vbus_pin = AT91_PIN_PC5, - .pullup_pin = 0, /* pull-up driven by UDC */ + .pullup_pin = -EINVAL, /* pull-up driven by UDC */ }; /* @@ -104,7 +106,7 @@ static struct spi_board_info ek_spi_devices[] = { /* * MACB Ethernet device */ -static struct at91_eth_data __initdata ek_macb_data = { +static struct macb_platform_data __initdata ek_macb_data = { .phy_irq_pin = AT91_PIN_PA31, .is_rmii = 1, }; @@ -133,7 +135,7 @@ static struct mtd_partition __initdata ek_nand_partition[] = { static struct atmel_nand_data __initdata ek_nand_data = { .ale = 21, .cle = 22, -// .det_pin = ... not connected + .det_pin = -EINVAL, .rdy_pin = AT91_PIN_PC13, .enable_pin = AT91_PIN_PC14, .parts = ek_nand_partition, @@ -161,7 +163,7 @@ static struct sam9_smc_config __initdata ek_nand_smc_config = { static void __init ek_add_device_nand(void) { /* configure chip-select 3 (NAND) */ - sam9_smc_configure(3, &ek_nand_smc_config); + sam9_smc_configure(0, 3, &ek_nand_smc_config); at91_add_device_nand(&ek_nand_data); } @@ -172,9 +174,9 @@ static void __init ek_add_device_nand(void) static struct at91_mmc_data __initdata ek_mmc_data = { .slot_b = 0, .wire4 = 1, -// .det_pin = ... not connected -// .wp_pin = ... not connected -// .vcc_pin = ... not connected + .det_pin = -EINVAL, + .wp_pin = -EINVAL, + .vcc_pin = -EINVAL, }; /* @@ -251,7 +253,7 @@ static void __init ek_board_init(void) /* LEDs */ at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds)); /* shutdown controller, wakeup button (5 msec low) */ - at91_sys_write(AT91_SHDW_MR, AT91_SHDW_CPTWK0_(10) | AT91_SHDW_WKMODE0_LOW + at91_shdwc_write(AT91_SHDW_MR, AT91_SHDW_CPTWK0_(10) | AT91_SHDW_WKMODE0_LOW | AT91_SHDW_RTTWKEN); } diff --git a/arch/arm/mach-at91/board-rm9200dk.c b/arch/arm/mach-at91/board-rm9200dk.c index 80a8c9c6e92..782f37946af 100644 --- a/arch/arm/mach-at91/board-rm9200dk.c +++ b/arch/arm/mach-at91/board-rm9200dk.c @@ -65,13 +65,15 @@ static void __init dk_init_early(void) at91_set_serial_console(0); } -static struct at91_eth_data __initdata dk_eth_data = { +static struct macb_platform_data __initdata dk_eth_data = { .phy_irq_pin = AT91_PIN_PC4, .is_rmii = 1, }; static struct at91_usbh_data __initdata dk_usbh_data = { .ports = 2, + .vbus_pin = {-EINVAL, -EINVAL}, + .overcurrent_pin= {-EINVAL, -EINVAL}, }; static struct at91_udc_data __initdata dk_udc_data = { @@ -80,16 +82,19 @@ static struct at91_udc_data __initdata dk_udc_data = { }; static struct at91_cf_data __initdata dk_cf_data = { + .irq_pin = -EINVAL, .det_pin = AT91_PIN_PB0, + .vcc_pin = -EINVAL, .rst_pin = AT91_PIN_PC5, - // .irq_pin = ... not connected - // .vcc_pin = ... always powered }; #ifndef CONFIG_MTD_AT91_DATAFLASH_CARD static struct at91_mmc_data __initdata dk_mmc_data = { .slot_b = 0, .wire4 = 1, + .det_pin = -EINVAL, + .wp_pin = -EINVAL, + .vcc_pin = -EINVAL, }; #endif @@ -143,7 +148,7 @@ static struct atmel_nand_data __initdata dk_nand_data = { .cle = 21, .det_pin = AT91_PIN_PB1, .rdy_pin = AT91_PIN_PC2, - // .enable_pin = ... not there + .enable_pin = -EINVAL, .parts = dk_nand_partition, .num_parts = ARRAY_SIZE(dk_nand_partition), }; diff --git a/arch/arm/mach-at91/board-rm9200ek.c b/arch/arm/mach-at91/board-rm9200ek.c index 99fd7f8aee0..ef7c12a9224 100644 --- a/arch/arm/mach-at91/board-rm9200ek.c +++ b/arch/arm/mach-at91/board-rm9200ek.c @@ -65,13 +65,15 @@ static void __init ek_init_early(void) at91_set_serial_console(0); } -static struct at91_eth_data __initdata ek_eth_data = { +static struct macb_platform_data __initdata ek_eth_data = { .phy_irq_pin = AT91_PIN_PC4, .is_rmii = 1, }; static struct at91_usbh_data __initdata ek_usbh_data = { .ports = 2, + .vbus_pin = {-EINVAL, -EINVAL}, + .overcurrent_pin= {-EINVAL, -EINVAL}, }; static struct at91_udc_data __initdata ek_udc_data = { @@ -85,6 +87,7 @@ static struct at91_mmc_data __initdata ek_mmc_data = { .slot_b = 0, .wire4 = 1, .wp_pin = AT91_PIN_PA17, + .vcc_pin = -EINVAL, }; #endif diff --git a/arch/arm/mach-at91/board-rsi-ews.c b/arch/arm/mach-at91/board-rsi-ews.c index e927df0175d..af0750fafa2 100644 --- a/arch/arm/mach-at91/board-rsi-ews.c +++ b/arch/arm/mach-at91/board-rsi-ews.c @@ -60,7 +60,7 @@ static void __init rsi_ews_init_early(void) /* * Ethernet */ -static struct at91_eth_data rsi_ews_eth_data __initdata = { +static struct macb_platform_data rsi_ews_eth_data __initdata = { .phy_irq_pin = AT91_PIN_PC4, .is_rmii = 1, }; @@ -70,6 +70,8 @@ static struct at91_eth_data rsi_ews_eth_data __initdata = { */ static struct at91_usbh_data rsi_ews_usbh_data __initdata = { .ports = 1, + .vbus_pin = {-EINVAL, -EINVAL}, + .overcurrent_pin= {-EINVAL, -EINVAL}, }; /* diff --git a/arch/arm/mach-at91/board-sam9-l9260.c b/arch/arm/mach-at91/board-sam9-l9260.c index 072d53af98d..84bce587735 100644 --- a/arch/arm/mach-at91/board-sam9-l9260.c +++ b/arch/arm/mach-at91/board-sam9-l9260.c @@ -72,6 +72,8 @@ static void __init ek_init_early(void) */ static struct at91_usbh_data __initdata ek_usbh_data = { .ports = 2, + .vbus_pin = {-EINVAL, -EINVAL}, + .overcurrent_pin= {-EINVAL, -EINVAL}, }; /* @@ -79,7 +81,7 @@ static struct at91_usbh_data __initdata ek_usbh_data = { */ static struct at91_udc_data __initdata ek_udc_data = { .vbus_pin = AT91_PIN_PC5, - .pullup_pin = 0, /* pull-up driven by UDC */ + .pullup_pin = -EINVAL, /* pull-up driven by UDC */ }; @@ -109,7 +111,7 @@ static struct spi_board_info ek_spi_devices[] = { /* * MACB Ethernet device */ -static struct at91_eth_data __initdata ek_macb_data = { +static struct macb_platform_data __initdata ek_macb_data = { .phy_irq_pin = AT91_PIN_PA7, .is_rmii = 0, }; @@ -134,7 +136,7 @@ static struct mtd_partition __initdata ek_nand_partition[] = { static struct atmel_nand_data __initdata ek_nand_data = { .ale = 21, .cle = 22, -// .det_pin = ... not connected + .det_pin = -EINVAL, .rdy_pin = AT91_PIN_PC13, .enable_pin = AT91_PIN_PC14, .parts = ek_nand_partition, @@ -162,7 +164,7 @@ static struct sam9_smc_config __initdata ek_nand_smc_config = { static void __init ek_add_device_nand(void) { /* configure chip-select 3 (NAND) */ - sam9_smc_configure(3, &ek_nand_smc_config); + sam9_smc_configure(0, 3, &ek_nand_smc_config); at91_add_device_nand(&ek_nand_data); } @@ -176,7 +178,7 @@ static struct at91_mmc_data __initdata ek_mmc_data = { .wire4 = 1, .det_pin = AT91_PIN_PC8, .wp_pin = AT91_PIN_PC4, -// .vcc_pin = ... not connected + .vcc_pin = -EINVAL, }; static void __init ek_board_init(void) diff --git a/arch/arm/mach-at91/board-sam9260ek.c b/arch/arm/mach-at91/board-sam9260ek.c index 4f10181a078..be8233bcabd 100644 --- a/arch/arm/mach-at91/board-sam9260ek.c +++ b/arch/arm/mach-at91/board-sam9260ek.c @@ -75,6 +75,8 @@ static void __init ek_init_early(void) */ static struct at91_usbh_data __initdata ek_usbh_data = { .ports = 2, + .vbus_pin = {-EINVAL, -EINVAL}, + .overcurrent_pin= {-EINVAL, -EINVAL}, }; /* @@ -82,7 +84,7 @@ static struct at91_usbh_data __initdata ek_usbh_data = { */ static struct at91_udc_data __initdata ek_udc_data = { .vbus_pin = AT91_PIN_PC5, - .pullup_pin = 0, /* pull-up driven by UDC */ + .pullup_pin = -EINVAL, /* pull-up driven by UDC */ }; @@ -151,7 +153,7 @@ static struct spi_board_info ek_spi_devices[] = { /* * MACB Ethernet device */ -static struct at91_eth_data __initdata ek_macb_data = { +static struct macb_platform_data __initdata ek_macb_data = { .phy_irq_pin = AT91_PIN_PA7, .is_rmii = 1, }; @@ -176,7 +178,7 @@ static struct mtd_partition __initdata ek_nand_partition[] = { static struct atmel_nand_data __initdata ek_nand_data = { .ale = 21, .cle = 22, -// .det_pin = ... not connected + .det_pin = -EINVAL, .rdy_pin = AT91_PIN_PC13, .enable_pin = AT91_PIN_PC14, .parts = ek_nand_partition, @@ -211,7 +213,7 @@ static void __init ek_add_device_nand(void) ek_nand_smc_config.mode |= AT91_SMC_DBW_8; /* configure chip-select 3 (NAND) */ - sam9_smc_configure(3, &ek_nand_smc_config); + sam9_smc_configure(0, 3, &ek_nand_smc_config); at91_add_device_nand(&ek_nand_data); } @@ -223,9 +225,9 @@ static void __init ek_add_device_nand(void) static struct at91_mmc_data __initdata ek_mmc_data = { .slot_b = 1, .wire4 = 1, -// .det_pin = ... not connected -// .wp_pin = ... not connected -// .vcc_pin = ... not connected + .det_pin = -EINVAL, + .wp_pin = -EINVAL, + .vcc_pin = -EINVAL, }; diff --git a/arch/arm/mach-at91/board-sam9261ek.c b/arch/arm/mach-at91/board-sam9261ek.c index b005b738e8f..40895072a1a 100644 --- a/arch/arm/mach-at91/board-sam9261ek.c +++ b/arch/arm/mach-at91/board-sam9261ek.c @@ -131,7 +131,7 @@ static struct sam9_smc_config __initdata dm9000_smc_config = { static void __init ek_add_device_dm9000(void) { /* Configure chip-select 2 (DM9000) */ - sam9_smc_configure(2, &dm9000_smc_config); + sam9_smc_configure(0, 2, &dm9000_smc_config); /* Configure Reset signal as output */ at91_set_gpio_output(AT91_PIN_PC10, 0); @@ -151,6 +151,8 @@ static void __init ek_add_device_dm9000(void) {} */ static struct at91_usbh_data __initdata ek_usbh_data = { .ports = 2, + .vbus_pin = {-EINVAL, -EINVAL}, + .overcurrent_pin= {-EINVAL, -EINVAL}, }; @@ -159,7 +161,7 @@ static struct at91_usbh_data __initdata ek_usbh_data = { */ static struct at91_udc_data __initdata ek_udc_data = { .vbus_pin = AT91_PIN_PB29, - .pullup_pin = 0, /* pull-up driven by UDC */ + .pullup_pin = -EINVAL, /* pull-up driven by UDC */ }; @@ -182,7 +184,7 @@ static struct mtd_partition __initdata ek_nand_partition[] = { static struct atmel_nand_data __initdata ek_nand_data = { .ale = 22, .cle = 21, -// .det_pin = ... not connected + .det_pin = -EINVAL, .rdy_pin = AT91_PIN_PC15, .enable_pin = AT91_PIN_PC14, .parts = ek_nand_partition, @@ -217,7 +219,7 @@ static void __init ek_add_device_nand(void) ek_nand_smc_config.mode |= AT91_SMC_DBW_8; /* configure chip-select 3 (NAND) */ - sam9_smc_configure(3, &ek_nand_smc_config); + sam9_smc_configure(0, 3, &ek_nand_smc_config); at91_add_device_nand(&ek_nand_data); } @@ -345,6 +347,9 @@ static struct spi_board_info ek_spi_devices[] = { */ static struct at91_mmc_data __initdata ek_mmc_data = { .wire4 = 1, + .det_pin = -EINVAL, + .wp_pin = -EINVAL, + .vcc_pin = -EINVAL, }; #endif /* CONFIG_SPI_ATMEL_* */ diff --git a/arch/arm/mach-at91/board-sam9263ek.c b/arch/arm/mach-at91/board-sam9263ek.c index bccdcf23caa..29f66052fe6 100644 --- a/arch/arm/mach-at91/board-sam9263ek.c +++ b/arch/arm/mach-at91/board-sam9263ek.c @@ -74,6 +74,7 @@ static void __init ek_init_early(void) static struct at91_usbh_data __initdata ek_usbh_data = { .ports = 2, .vbus_pin = { AT91_PIN_PA24, AT91_PIN_PA21 }, + .overcurrent_pin= {-EINVAL, -EINVAL}, }; /* @@ -81,7 +82,7 @@ static struct at91_usbh_data __initdata ek_usbh_data = { */ static struct at91_udc_data __initdata ek_udc_data = { .vbus_pin = AT91_PIN_PA25, - .pullup_pin = 0, /* pull-up driven by UDC */ + .pullup_pin = -EINVAL, /* pull-up driven by UDC */ }; @@ -151,14 +152,14 @@ static struct at91_mmc_data __initdata ek_mmc_data = { .wire4 = 1, .det_pin = AT91_PIN_PE18, .wp_pin = AT91_PIN_PE19, -// .vcc_pin = ... not connected + .vcc_pin = -EINVAL, }; /* * MACB Ethernet device */ -static struct at91_eth_data __initdata ek_macb_data = { +static struct macb_platform_data __initdata ek_macb_data = { .phy_irq_pin = AT91_PIN_PE31, .is_rmii = 1, }; @@ -183,7 +184,7 @@ static struct mtd_partition __initdata ek_nand_partition[] = { static struct atmel_nand_data __initdata ek_nand_data = { .ale = 21, .cle = 22, -// .det_pin = ... not connected + .det_pin = -EINVAL, .rdy_pin = AT91_PIN_PA22, .enable_pin = AT91_PIN_PD15, .parts = ek_nand_partition, @@ -218,7 +219,7 @@ static void __init ek_add_device_nand(void) ek_nand_smc_config.mode |= AT91_SMC_DBW_8; /* configure chip-select 3 (NAND) */ - sam9_smc_configure(3, &ek_nand_smc_config); + sam9_smc_configure(0, 3, &ek_nand_smc_config); at91_add_device_nand(&ek_nand_data); } @@ -353,6 +354,7 @@ static void __init ek_add_device_buttons(void) {} * reset_pin is not connected: NRST */ static struct ac97c_platform_data ek_ac97_data = { + .reset_pin = -EINVAL, }; diff --git a/arch/arm/mach-at91/board-sam9g20ek.c b/arch/arm/mach-at91/board-sam9g20ek.c index 64fc75c9d0a..843d6286c6f 100644 --- a/arch/arm/mach-at91/board-sam9g20ek.c +++ b/arch/arm/mach-at91/board-sam9g20ek.c @@ -86,6 +86,8 @@ static void __init ek_init_early(void) */ static struct at91_usbh_data __initdata ek_usbh_data = { .ports = 2, + .vbus_pin = {-EINVAL, -EINVAL}, + .overcurrent_pin= {-EINVAL, -EINVAL}, }; /* @@ -93,7 +95,7 @@ static struct at91_usbh_data __initdata ek_usbh_data = { */ static struct at91_udc_data __initdata ek_udc_data = { .vbus_pin = AT91_PIN_PC5, - .pullup_pin = 0, /* pull-up driven by UDC */ + .pullup_pin = -EINVAL, /* pull-up driven by UDC */ }; @@ -123,7 +125,7 @@ static struct spi_board_info ek_spi_devices[] = { /* * MACB Ethernet device */ -static struct at91_eth_data __initdata ek_macb_data = { +static struct macb_platform_data __initdata ek_macb_data = { .phy_irq_pin = AT91_PIN_PA7, .is_rmii = 1, }; @@ -163,6 +165,7 @@ static struct atmel_nand_data __initdata ek_nand_data = { .cle = 22, .rdy_pin = AT91_PIN_PC13, .enable_pin = AT91_PIN_PC14, + .det_pin = -EINVAL, .parts = ek_nand_partition, .num_parts = ARRAY_SIZE(ek_nand_partition), }; @@ -195,7 +198,7 @@ static void __init ek_add_device_nand(void) ek_nand_smc_config.mode |= AT91_SMC_DBW_8; /* configure chip-select 3 (NAND) */ - sam9_smc_configure(3, &ek_nand_smc_config); + sam9_smc_configure(0, 3, &ek_nand_smc_config); at91_add_device_nand(&ek_nand_data); } @@ -210,6 +213,7 @@ static struct mci_platform_data __initdata ek_mmc_data = { .slot[1] = { .bus_width = 4, .detect_pin = AT91_PIN_PC9, + .wp_pin = -EINVAL, }, }; @@ -218,6 +222,8 @@ static struct at91_mmc_data __initdata ek_mmc_data = { .slot_b = 1, /* Only one slot so use slot B */ .wire4 = 1, .det_pin = AT91_PIN_PC9, + .wp_pin = -EINVAL, + .vcc_pin = -EINVAL, }; #endif @@ -227,6 +233,7 @@ static void __init ek_add_device_mmc(void) if (ek_have_2mmc()) { ek_mmc_data.slot[0].bus_width = 4; ek_mmc_data.slot[0].detect_pin = AT91_PIN_PC2; + ek_mmc_data.slot[0].wp_pin = -1; } at91_add_device_mci(0, &ek_mmc_data); #else diff --git a/arch/arm/mach-at91/board-sam9m10g45ek.c b/arch/arm/mach-at91/board-sam9m10g45ek.c index 92de9127923..ea0d1b9c2b7 100644 --- a/arch/arm/mach-at91/board-sam9m10g45ek.c +++ b/arch/arm/mach-at91/board-sam9m10g45ek.c @@ -69,6 +69,7 @@ static void __init ek_init_early(void) static struct at91_usbh_data __initdata ek_usbh_hs_data = { .ports = 2, .vbus_pin = {AT91_PIN_PD1, AT91_PIN_PD3}, + .overcurrent_pin= {-EINVAL, -EINVAL}, }; @@ -100,6 +101,7 @@ static struct mci_platform_data __initdata mci0_data = { .slot[0] = { .bus_width = 4, .detect_pin = AT91_PIN_PD10, + .wp_pin = -EINVAL, }, }; @@ -115,7 +117,7 @@ static struct mci_platform_data __initdata mci1_data = { /* * MACB Ethernet device */ -static struct at91_eth_data __initdata ek_macb_data = { +static struct macb_platform_data __initdata ek_macb_data = { .phy_irq_pin = AT91_PIN_PD5, .is_rmii = 1, }; @@ -143,6 +145,7 @@ static struct atmel_nand_data __initdata ek_nand_data = { .cle = 22, .rdy_pin = AT91_PIN_PC8, .enable_pin = AT91_PIN_PC14, + .det_pin = -EINVAL, .parts = ek_nand_partition, .num_parts = ARRAY_SIZE(ek_nand_partition), }; @@ -175,7 +178,7 @@ static void __init ek_add_device_nand(void) ek_nand_smc_config.mode |= AT91_SMC_DBW_8; /* configure chip-select 3 (NAND) */ - sam9_smc_configure(3, &ek_nand_smc_config); + sam9_smc_configure(0, 3, &ek_nand_smc_config); at91_add_device_nand(&ek_nand_data); } @@ -330,6 +333,7 @@ static void __init ek_add_device_buttons(void) {} * reset_pin is not connected: NRST */ static struct ac97c_platform_data ek_ac97_data = { + .reset_pin = -EINVAL, }; diff --git a/arch/arm/mach-at91/board-sam9rlek.c b/arch/arm/mach-at91/board-sam9rlek.c index b2b748239f3..c1366d0032b 100644 --- a/arch/arm/mach-at91/board-sam9rlek.c +++ b/arch/arm/mach-at91/board-sam9rlek.c @@ -67,8 +67,8 @@ static struct usba_platform_data __initdata ek_usba_udc_data = { static struct at91_mmc_data __initdata ek_mmc_data = { .wire4 = 1, .det_pin = AT91_PIN_PA15, -// .wp_pin = ... not connected -// .vcc_pin = ... not connected + .wp_pin = -EINVAL, + .vcc_pin = -EINVAL, }; @@ -91,7 +91,7 @@ static struct mtd_partition __initdata ek_nand_partition[] = { static struct atmel_nand_data __initdata ek_nand_data = { .ale = 21, .cle = 22, -// .det_pin = ... not connected + .det_pin = -EINVAL, .rdy_pin = AT91_PIN_PD17, .enable_pin = AT91_PIN_PB6, .parts = ek_nand_partition, @@ -119,7 +119,7 @@ static struct sam9_smc_config __initdata ek_nand_smc_config = { static void __init ek_add_device_nand(void) { /* configure chip-select 3 (NAND) */ - sam9_smc_configure(3, &ek_nand_smc_config); + sam9_smc_configure(0, 3, &ek_nand_smc_config); at91_add_device_nand(&ek_nand_data); } @@ -204,6 +204,7 @@ static struct atmel_lcdfb_info __initdata ek_lcdc_data; * reset_pin is not connected: NRST */ static struct ac97c_platform_data ek_ac97_data = { + .reset_pin = -EINVAL, }; diff --git a/arch/arm/mach-at91/board-snapper9260.c b/arch/arm/mach-at91/board-snapper9260.c index 0df01c6e2d0..4770db08e5a 100644 --- a/arch/arm/mach-at91/board-snapper9260.c +++ b/arch/arm/mach-at91/board-snapper9260.c @@ -57,15 +57,19 @@ static void __init snapper9260_init_early(void) static struct at91_usbh_data __initdata snapper9260_usbh_data = { .ports = 2, + .vbus_pin = {-EINVAL, -EINVAL}, + .overcurrent_pin= {-EINVAL, -EINVAL}, }; static struct at91_udc_data __initdata snapper9260_udc_data = { .vbus_pin = SNAPPER9260_IO_EXP_GPIO(5), .vbus_active_low = 1, .vbus_polled = 1, + .pullup_pin = -EINVAL, }; -static struct at91_eth_data snapper9260_macb_data = { +static struct macb_platform_data snapper9260_macb_data = { + .phy_irq_pin = -EINVAL, .is_rmii = 1, }; @@ -104,6 +108,8 @@ static struct atmel_nand_data __initdata snapper9260_nand_data = { .parts = snapper9260_nand_partitions, .num_parts = ARRAY_SIZE(snapper9260_nand_partitions), .bus_width_16 = 0, + .enable_pin = -EINVAL, + .det_pin = -EINVAL, }; static struct sam9_smc_config __initdata snapper9260_nand_smc_config = { @@ -149,7 +155,7 @@ static struct i2c_board_info __initdata snapper9260_i2c_devices[] = { static void __init snapper9260_add_device_nand(void) { at91_set_A_periph(AT91_PIN_PC14, 0); - sam9_smc_configure(3, &snapper9260_nand_smc_config); + sam9_smc_configure(0, 3, &snapper9260_nand_smc_config); at91_add_device_nand(&snapper9260_nand_data); } diff --git a/arch/arm/mach-at91/board-stamp9g20.c b/arch/arm/mach-at91/board-stamp9g20.c index 936e5fd7f40..72eb3b4d9ab 100644 --- a/arch/arm/mach-at91/board-stamp9g20.c +++ b/arch/arm/mach-at91/board-stamp9g20.c @@ -85,6 +85,7 @@ static struct atmel_nand_data __initdata nand_data = { .rdy_pin = AT91_PIN_PC13, .enable_pin = AT91_PIN_PC14, .bus_width_16 = 0, + .det_pin = -EINVAL, }; static struct sam9_smc_config __initdata nand_smc_config = { @@ -108,7 +109,7 @@ static struct sam9_smc_config __initdata nand_smc_config = { static void __init add_device_nand(void) { /* configure chip-select 3 (NAND) */ - sam9_smc_configure(3, &nand_smc_config); + sam9_smc_configure(0, 3, &nand_smc_config); at91_add_device_nand(&nand_data); } @@ -122,12 +123,17 @@ static void __init add_device_nand(void) static struct mci_platform_data __initdata mmc_data = { .slot[0] = { .bus_width = 4, + .detect_pin = -1, + .wp_pin = -1, }, }; #else static struct at91_mmc_data __initdata mmc_data = { .slot_b = 0, .wire4 = 1, + .det_pin = -EINVAL, + .wp_pin = -EINVAL, + .vcc_pin = -EINVAL, }; #endif @@ -137,6 +143,8 @@ static struct at91_mmc_data __initdata mmc_data = { */ static struct at91_usbh_data __initdata usbh_data = { .ports = 2, + .vbus_pin = {-EINVAL, -EINVAL}, + .overcurrent_pin= {-EINVAL, -EINVAL}, }; @@ -145,19 +153,19 @@ static struct at91_usbh_data __initdata usbh_data = { */ static struct at91_udc_data __initdata portuxg20_udc_data = { .vbus_pin = AT91_PIN_PC7, - .pullup_pin = 0, /* pull-up driven by UDC */ + .pullup_pin = -EINVAL, /* pull-up driven by UDC */ }; static struct at91_udc_data __initdata stamp9g20evb_udc_data = { .vbus_pin = AT91_PIN_PA22, - .pullup_pin = 0, /* pull-up driven by UDC */ + .pullup_pin = -EINVAL, /* pull-up driven by UDC */ }; /* * MACB Ethernet device */ -static struct at91_eth_data __initdata macb_data = { +static struct macb_platform_data __initdata macb_data = { .phy_irq_pin = AT91_PIN_PA28, .is_rmii = 1, }; diff --git a/arch/arm/mach-at91/board-usb-a926x.c b/arch/arm/mach-at91/board-usb-a926x.c index 0a20bab21f9..26c36fc2d1e 100644 --- a/arch/arm/mach-at91/board-usb-a926x.c +++ b/arch/arm/mach-at91/board-usb-a926x.c @@ -66,6 +66,8 @@ static void __init ek_init_early(void) */ static struct at91_usbh_data __initdata ek_usbh_data = { .ports = 2, + .vbus_pin = {-EINVAL, -EINVAL}, + .overcurrent_pin= {-EINVAL, -EINVAL}, }; /* @@ -73,7 +75,7 @@ static struct at91_usbh_data __initdata ek_usbh_data = { */ static struct at91_udc_data __initdata ek_udc_data = { .vbus_pin = AT91_PIN_PB11, - .pullup_pin = 0, /* pull-up driven by UDC */ + .pullup_pin = -EINVAL, /* pull-up driven by UDC */ }; static void __init ek_add_device_udc(void) @@ -146,7 +148,7 @@ static void __init ek_add_device_spi(void) /* * MACB Ethernet device */ -static struct at91_eth_data __initdata ek_macb_data = { +static struct macb_platform_data __initdata ek_macb_data = { .phy_irq_pin = AT91_PIN_PE31, .is_rmii = 1, }; @@ -193,7 +195,7 @@ static struct mtd_partition __initdata ek_nand_partition[] = { static struct atmel_nand_data __initdata ek_nand_data = { .ale = 21, .cle = 22, -// .det_pin = ... not connected + .det_pin = -EINVAL, .rdy_pin = AT91_PIN_PA22, .enable_pin = AT91_PIN_PD15, .parts = ek_nand_partition, @@ -245,9 +247,9 @@ static void __init ek_add_device_nand(void) /* configure chip-select 3 (NAND) */ if (machine_is_usb_a9g20()) - sam9_smc_configure(3, &usb_a9g20_nand_smc_config); + sam9_smc_configure(0, 3, &usb_a9g20_nand_smc_config); else - sam9_smc_configure(3, &usb_a9260_nand_smc_config); + sam9_smc_configure(0, 3, &usb_a9260_nand_smc_config); at91_add_device_nand(&ek_nand_data); } @@ -344,7 +346,7 @@ static void __init ek_board_init(void) /* I2C */ at91_add_device_i2c(NULL, 0); /* shutdown controller, wakeup button (5 msec low) */ - at91_sys_write(AT91_SHDW_MR, AT91_SHDW_CPTWK0_(10) + at91_shdwc_write(AT91_SHDW_MR, AT91_SHDW_CPTWK0_(10) | AT91_SHDW_WKMODE0_LOW | AT91_SHDW_RTTWKEN); } diff --git a/arch/arm/mach-at91/board-yl-9200.c b/arch/arm/mach-at91/board-yl-9200.c index 12a3f955162..bbd553e1cd9 100644 --- a/arch/arm/mach-at91/board-yl-9200.c +++ b/arch/arm/mach-at91/board-yl-9200.c @@ -110,7 +110,7 @@ static struct gpio_led yl9200_leds[] = { /* * Ethernet */ -static struct at91_eth_data __initdata yl9200_eth_data = { +static struct macb_platform_data __initdata yl9200_eth_data = { .phy_irq_pin = AT91_PIN_PB28, .is_rmii = 1, }; @@ -120,6 +120,8 @@ static struct at91_eth_data __initdata yl9200_eth_data = { */ static struct at91_usbh_data __initdata yl9200_usbh_data = { .ports = 1, /* PQFP version of AT91RM9200 */ + .vbus_pin = {-EINVAL, -EINVAL}, + .overcurrent_pin= {-EINVAL, -EINVAL}, }; /* @@ -137,8 +139,9 @@ static struct at91_udc_data __initdata yl9200_udc_data = { */ static struct at91_mmc_data __initdata yl9200_mmc_data = { .det_pin = AT91_PIN_PB9, - // .wp_pin = ... not connected .wire4 = 1, + .wp_pin = -EINVAL, + .vcc_pin = -EINVAL, }; /* @@ -175,7 +178,7 @@ static struct mtd_partition __initdata yl9200_nand_partition[] = { static struct atmel_nand_data __initdata yl9200_nand_data = { .ale = 6, .cle = 7, - // .det_pin = ... not connected + .det_pin = -EINVAL, .rdy_pin = AT91_PIN_PC14, /* R/!B (Sheet10) */ .enable_pin = AT91_PIN_PC15, /* !CE (Sheet10) */ .parts = yl9200_nand_partition, diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h index 7f4503bc4cb..4866b8180d6 100644 --- a/arch/arm/mach-at91/generic.h +++ b/arch/arm/mach-at91/generic.h @@ -29,6 +29,7 @@ extern void __init at91_aic_init(unsigned int priority[]); /* Timer */ struct sys_timer; extern struct sys_timer at91rm9200_timer; +extern void at91sam926x_ioremap_pit(u32 addr); extern struct sys_timer at91sam926x_timer; extern struct sys_timer at91x40_timer; @@ -59,14 +60,16 @@ extern void at91_irq_resume(void); /* reset */ extern void at91sam9_alt_restart(char, const char *); +/* shutdown */ +extern void at91_ioremap_shdwc(u32 base_addr); + /* GPIO */ #define AT91RM9200_PQFP 3 /* AT91RM9200 PQFP package has 3 banks */ #define AT91RM9200_BGA 4 /* AT91RM9200 BGA package has 4 banks */ struct at91_gpio_bank { unsigned short id; /* peripheral ID */ - unsigned long offset; /* offset from system peripheral base */ - struct clk *clock; /* associated clock */ + unsigned long regbase; /* offset from system peripheral base */ }; extern void __init at91_gpio_init(struct at91_gpio_bank *, int nr_banks); extern void __init at91_gpio_irq_setup(void); diff --git a/arch/arm/mach-at91/gpio.c b/arch/arm/mach-at91/gpio.c index 224e9e2f867..74d6783eeab 100644 --- a/arch/arm/mach-at91/gpio.c +++ b/arch/arm/mach-at91/gpio.c @@ -29,8 +29,9 @@ struct at91_gpio_chip { struct gpio_chip chip; struct at91_gpio_chip *next; /* Bank sharing same clock */ - struct at91_gpio_bank *bank; /* Bank definition */ + int id; /* ID of register bank */ void __iomem *regbase; /* Base of register bank */ + struct clk *clock; /* associated clock */ }; #define to_at91_gpio_chip(c) container_of(c, struct at91_gpio_chip, chip) @@ -58,18 +59,17 @@ static int at91_gpiolib_direction_input(struct gpio_chip *chip, } static struct at91_gpio_chip gpio_chip[] = { - AT91_GPIO_CHIP("A", 0x00 + PIN_BASE, 32), - AT91_GPIO_CHIP("B", 0x20 + PIN_BASE, 32), - AT91_GPIO_CHIP("C", 0x40 + PIN_BASE, 32), - AT91_GPIO_CHIP("D", 0x60 + PIN_BASE, 32), - AT91_GPIO_CHIP("E", 0x80 + PIN_BASE, 32), + AT91_GPIO_CHIP("pioA", 0x00, 32), + AT91_GPIO_CHIP("pioB", 0x20, 32), + AT91_GPIO_CHIP("pioC", 0x40, 32), + AT91_GPIO_CHIP("pioD", 0x60, 32), + AT91_GPIO_CHIP("pioE", 0x80, 32), }; static int gpio_banks; static inline void __iomem *pin_to_controller(unsigned pin) { - pin -= PIN_BASE; pin /= 32; if (likely(pin < gpio_banks)) return gpio_chip[pin].regbase; @@ -79,7 +79,6 @@ static inline void __iomem *pin_to_controller(unsigned pin) static inline unsigned pin_to_mask(unsigned pin) { - pin -= PIN_BASE; return 1 << (pin % 32); } @@ -274,8 +273,9 @@ static u32 backups[MAX_GPIO_BANKS]; static int gpio_irq_set_wake(struct irq_data *d, unsigned state) { - unsigned mask = pin_to_mask(d->irq); - unsigned bank = (d->irq - PIN_BASE) / 32; + unsigned pin = irq_to_gpio(d->irq); + unsigned mask = pin_to_mask(pin); + unsigned bank = pin / 32; if (unlikely(bank >= MAX_GPIO_BANKS)) return -EINVAL; @@ -285,7 +285,7 @@ static int gpio_irq_set_wake(struct irq_data *d, unsigned state) else wakeups[bank] &= ~mask; - irq_set_irq_wake(gpio_chip[bank].bank->id, state); + irq_set_irq_wake(gpio_chip[bank].id, state); return 0; } @@ -302,7 +302,7 @@ void at91_gpio_suspend(void) __raw_writel(wakeups[i], pio + PIO_IER); if (!wakeups[i]) - clk_disable(gpio_chip[i].bank->clock); + clk_disable(gpio_chip[i].clock); else { #ifdef CONFIG_PM_DEBUG printk(KERN_DEBUG "GPIO-%c may wake for %08x\n", 'A'+i, wakeups[i]); @@ -319,7 +319,7 @@ void at91_gpio_resume(void) void __iomem *pio = gpio_chip[i].regbase; if (!wakeups[i]) - clk_enable(gpio_chip[i].bank->clock); + clk_enable(gpio_chip[i].clock); __raw_writel(wakeups[i], pio + PIO_IDR); __raw_writel(backups[i], pio + PIO_IER); @@ -344,8 +344,9 @@ void at91_gpio_resume(void) static void gpio_irq_mask(struct irq_data *d) { - void __iomem *pio = pin_to_controller(d->irq); - unsigned mask = pin_to_mask(d->irq); + unsigned pin = irq_to_gpio(d->irq); + void __iomem *pio = pin_to_controller(pin); + unsigned mask = pin_to_mask(pin); if (pio) __raw_writel(mask, pio + PIO_IDR); @@ -353,8 +354,9 @@ static void gpio_irq_mask(struct irq_data *d) static void gpio_irq_unmask(struct irq_data *d) { - void __iomem *pio = pin_to_controller(d->irq); - unsigned mask = pin_to_mask(d->irq); + unsigned pin = irq_to_gpio(d->irq); + void __iomem *pio = pin_to_controller(pin); + unsigned mask = pin_to_mask(pin); if (pio) __raw_writel(mask, pio + PIO_IER); @@ -382,7 +384,7 @@ static struct irq_chip gpio_irqchip = { static void gpio_irq_handler(unsigned irq, struct irq_desc *desc) { - unsigned pin; + unsigned irq_pin; struct irq_data *idata = irq_desc_get_irq_data(desc); struct irq_chip *chip = irq_data_get_irq_chip(idata); struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(idata); @@ -405,12 +407,12 @@ static void gpio_irq_handler(unsigned irq, struct irq_desc *desc) continue; } - pin = at91_gpio->chip.base; + irq_pin = gpio_to_irq(at91_gpio->chip.base); while (isr) { if (isr & 1) - generic_handle_irq(pin); - pin++; + generic_handle_irq(irq_pin); + irq_pin++; isr >>= 1; } } @@ -438,7 +440,7 @@ static int at91_gpio_show(struct seq_file *s, void *unused) seq_printf(s, "%i:\t", j); for (bank = 0; bank < gpio_banks; bank++) { - unsigned pin = PIN_BASE + (32 * bank) + j; + unsigned pin = (32 * bank) + j; void __iomem *pio = pin_to_controller(pin); unsigned mask = pin_to_mask(pin); @@ -491,27 +493,28 @@ static struct lock_class_key gpio_lock_class; */ void __init at91_gpio_irq_setup(void) { - unsigned pioc, pin; + unsigned pioc, irq = gpio_to_irq(0); struct at91_gpio_chip *this, *prev; - for (pioc = 0, pin = PIN_BASE, this = gpio_chip, prev = NULL; + for (pioc = 0, this = gpio_chip, prev = NULL; pioc++ < gpio_banks; prev = this, this++) { - unsigned id = this->bank->id; + unsigned id = this->id; unsigned i; __raw_writel(~0, this->regbase + PIO_IDR); - for (i = 0, pin = this->chip.base; i < 32; i++, pin++) { - irq_set_lockdep_class(pin, &gpio_lock_class); + for (i = 0, irq = gpio_to_irq(this->chip.base); i < 32; + i++, irq++) { + irq_set_lockdep_class(irq, &gpio_lock_class); /* * Can use the "simple" and not "edge" handler since it's * shorter, and the AIC handles interrupts sanely. */ - irq_set_chip_and_handler(pin, &gpio_irqchip, + irq_set_chip_and_handler(irq, &gpio_irqchip, handle_simple_irq); - set_irq_flags(pin, IRQF_VALID); + set_irq_flags(irq, IRQF_VALID); } /* The toplevel handler handles one bank of GPIOs, except @@ -524,7 +527,7 @@ void __init at91_gpio_irq_setup(void) irq_set_chip_data(id, this); irq_set_chained_handler(id, gpio_irq_handler); } - pr_info("AT91: %d gpio irqs in %d banks\n", pin - PIN_BASE, gpio_banks); + pr_info("AT91: %d gpio irqs in %d banks\n", irq - gpio_to_irq(0), gpio_banks); } /* gpiolib support */ @@ -612,16 +615,26 @@ void __init at91_gpio_init(struct at91_gpio_bank *data, int nr_banks) for (i = 0; i < nr_banks; i++) { at91_gpio = &gpio_chip[i]; - at91_gpio->bank = &data[i]; - at91_gpio->chip.base = PIN_BASE + i * 32; - at91_gpio->regbase = at91_gpio->bank->offset + - (void __iomem *)AT91_VA_BASE_SYS; + at91_gpio->id = data[i].id; + at91_gpio->chip.base = i * 32; + + at91_gpio->regbase = ioremap(data[i].regbase, 512); + if (!at91_gpio->regbase) { + pr_err("at91_gpio.%d, failed to map registers, ignoring.\n", i); + continue; + } + + at91_gpio->clock = clk_get_sys(NULL, at91_gpio->chip.label); + if (!at91_gpio->clock) { + pr_err("at91_gpio.%d, failed to get clock, ignoring.\n", i); + continue; + } /* enable PIO controller's clock */ - clk_enable(at91_gpio->bank->clock); + clk_enable(at91_gpio->clock); /* AT91SAM9263_ID_PIOCDE groups PIOC, PIOD, PIOE */ - if (last && last->bank->id == at91_gpio->bank->id) + if (last && last->id == at91_gpio->id) last->next = at91_gpio; last = at91_gpio; diff --git a/arch/arm/mach-at91/include/mach/at91_aic.h b/arch/arm/mach-at91/include/mach/at91_aic.h index 03566799d3b..3045781c473 100644 --- a/arch/arm/mach-at91/include/mach/at91_aic.h +++ b/arch/arm/mach-at91/include/mach/at91_aic.h @@ -16,7 +16,19 @@ #ifndef AT91_AIC_H #define AT91_AIC_H -#define AT91_AIC_SMR(n) (AT91_AIC + ((n) * 4)) /* Source Mode Registers 0-31 */ +#ifndef __ASSEMBLY__ +extern void __iomem *at91_aic_base; + +#define at91_aic_read(field) \ + __raw_readl(at91_aic_base + field) + +#define at91_aic_write(field, value) \ + __raw_writel(value, at91_aic_base + field); +#else +.extern at91_aic_base +#endif + +#define AT91_AIC_SMR(n) ((n) * 4) /* Source Mode Registers 0-31 */ #define AT91_AIC_PRIOR (7 << 0) /* Priority Level */ #define AT91_AIC_SRCTYPE (3 << 5) /* Interrupt Source Type */ #define AT91_AIC_SRCTYPE_LOW (0 << 5) @@ -24,30 +36,30 @@ #define AT91_AIC_SRCTYPE_HIGH (2 << 5) #define AT91_AIC_SRCTYPE_RISING (3 << 5) -#define AT91_AIC_SVR(n) (AT91_AIC + 0x80 + ((n) * 4)) /* Source Vector Registers 0-31 */ -#define AT91_AIC_IVR (AT91_AIC + 0x100) /* Interrupt Vector Register */ -#define AT91_AIC_FVR (AT91_AIC + 0x104) /* Fast Interrupt Vector Register */ -#define AT91_AIC_ISR (AT91_AIC + 0x108) /* Interrupt Status Register */ +#define AT91_AIC_SVR(n) (0x80 + ((n) * 4)) /* Source Vector Registers 0-31 */ +#define AT91_AIC_IVR 0x100 /* Interrupt Vector Register */ +#define AT91_AIC_FVR 0x104 /* Fast Interrupt Vector Register */ +#define AT91_AIC_ISR 0x108 /* Interrupt Status Register */ #define AT91_AIC_IRQID (0x1f << 0) /* Current Interrupt Identifier */ -#define AT91_AIC_IPR (AT91_AIC + 0x10c) /* Interrupt Pending Register */ -#define AT91_AIC_IMR (AT91_AIC + 0x110) /* Interrupt Mask Register */ -#define AT91_AIC_CISR (AT91_AIC + 0x114) /* Core Interrupt Status Register */ +#define AT91_AIC_IPR 0x10c /* Interrupt Pending Register */ +#define AT91_AIC_IMR 0x110 /* Interrupt Mask Register */ +#define AT91_AIC_CISR 0x114 /* Core Interrupt Status Register */ #define AT91_AIC_NFIQ (1 << 0) /* nFIQ Status */ #define AT91_AIC_NIRQ (1 << 1) /* nIRQ Status */ -#define AT91_AIC_IECR (AT91_AIC + 0x120) /* Interrupt Enable Command Register */ -#define AT91_AIC_IDCR (AT91_AIC + 0x124) /* Interrupt Disable Command Register */ -#define AT91_AIC_ICCR (AT91_AIC + 0x128) /* Interrupt Clear Command Register */ -#define AT91_AIC_ISCR (AT91_AIC + 0x12c) /* Interrupt Set Command Register */ -#define AT91_AIC_EOICR (AT91_AIC + 0x130) /* End of Interrupt Command Register */ -#define AT91_AIC_SPU (AT91_AIC + 0x134) /* Spurious Interrupt Vector Register */ -#define AT91_AIC_DCR (AT91_AIC + 0x138) /* Debug Control Register */ +#define AT91_AIC_IECR 0x120 /* Interrupt Enable Command Register */ +#define AT91_AIC_IDCR 0x124 /* Interrupt Disable Command Register */ +#define AT91_AIC_ICCR 0x128 /* Interrupt Clear Command Register */ +#define AT91_AIC_ISCR 0x12c /* Interrupt Set Command Register */ +#define AT91_AIC_EOICR 0x130 /* End of Interrupt Command Register */ +#define AT91_AIC_SPU 0x134 /* Spurious Interrupt Vector Register */ +#define AT91_AIC_DCR 0x138 /* Debug Control Register */ #define AT91_AIC_DCR_PROT (1 << 0) /* Protection Mode */ #define AT91_AIC_DCR_GMSK (1 << 1) /* General Mask */ -#define AT91_AIC_FFER (AT91_AIC + 0x140) /* Fast Forcing Enable Register [SAM9 only] */ -#define AT91_AIC_FFDR (AT91_AIC + 0x144) /* Fast Forcing Disable Register [SAM9 only] */ -#define AT91_AIC_FFSR (AT91_AIC + 0x148) /* Fast Forcing Status Register [SAM9 only] */ +#define AT91_AIC_FFER 0x140 /* Fast Forcing Enable Register [SAM9 only] */ +#define AT91_AIC_FFDR 0x144 /* Fast Forcing Disable Register [SAM9 only] */ +#define AT91_AIC_FFSR 0x148 /* Fast Forcing Status Register [SAM9 only] */ #endif diff --git a/arch/arm/mach-at91/include/mach/at91_dbgu.h b/arch/arm/mach-at91/include/mach/at91_dbgu.h index dbfe455a4c4..2aa0c5e1349 100644 --- a/arch/arm/mach-at91/include/mach/at91_dbgu.h +++ b/arch/arm/mach-at91/include/mach/at91_dbgu.h @@ -19,7 +19,7 @@ #define dbgu_readl(dbgu, field) \ __raw_readl(AT91_VA_BASE_SYS + dbgu + AT91_DBGU_ ## field) -#ifdef AT91_DBGU +#if !defined(CONFIG_ARCH_AT91X40) #define AT91_DBGU_CR (0x00) /* Control Register */ #define AT91_DBGU_MR (0x04) /* Mode Register */ #define AT91_DBGU_IER (0x08) /* Interrupt Enable Register */ diff --git a/arch/arm/mach-at91/include/mach/at91_pit.h b/arch/arm/mach-at91/include/mach/at91_pit.h index 974d0bd05b5..d1f80ad7f4d 100644 --- a/arch/arm/mach-at91/include/mach/at91_pit.h +++ b/arch/arm/mach-at91/include/mach/at91_pit.h @@ -16,16 +16,16 @@ #ifndef AT91_PIT_H #define AT91_PIT_H -#define AT91_PIT_MR (AT91_PIT + 0x00) /* Mode Register */ +#define AT91_PIT_MR 0x00 /* Mode Register */ #define AT91_PIT_PITIEN (1 << 25) /* Timer Interrupt Enable */ #define AT91_PIT_PITEN (1 << 24) /* Timer Enabled */ #define AT91_PIT_PIV (0xfffff) /* Periodic Interval Value */ -#define AT91_PIT_SR (AT91_PIT + 0x04) /* Status Register */ +#define AT91_PIT_SR 0x04 /* Status Register */ #define AT91_PIT_PITS (1 << 0) /* Timer Status */ -#define AT91_PIT_PIVR (AT91_PIT + 0x08) /* Periodic Interval Value Register */ -#define AT91_PIT_PIIR (AT91_PIT + 0x0c) /* Periodic Interval Image Register */ +#define AT91_PIT_PIVR 0x08 /* Periodic Interval Value Register */ +#define AT91_PIT_PIIR 0x0c /* Periodic Interval Image Register */ #define AT91_PIT_PICNT (0xfff << 20) /* Interval Counter */ #define AT91_PIT_CPIV (0xfffff) /* Inverval Value */ diff --git a/arch/arm/mach-at91/include/mach/at91_rtc.h b/arch/arm/mach-at91/include/mach/at91_rtc.h index e56f4701a3e..da1945e5f71 100644 --- a/arch/arm/mach-at91/include/mach/at91_rtc.h +++ b/arch/arm/mach-at91/include/mach/at91_rtc.h @@ -16,7 +16,7 @@ #ifndef AT91_RTC_H #define AT91_RTC_H -#define AT91_RTC_CR (AT91_RTC + 0x00) /* Control Register */ +#define AT91_RTC_CR 0x00 /* Control Register */ #define AT91_RTC_UPDTIM (1 << 0) /* Update Request Time Register */ #define AT91_RTC_UPDCAL (1 << 1) /* Update Request Calendar Register */ #define AT91_RTC_TIMEVSEL (3 << 8) /* Time Event Selection */ @@ -29,44 +29,44 @@ #define AT91_RTC_CALEVSEL_MONTH (1 << 16) #define AT91_RTC_CALEVSEL_YEAR (2 << 16) -#define AT91_RTC_MR (AT91_RTC + 0x04) /* Mode Register */ +#define AT91_RTC_MR 0x04 /* Mode Register */ #define AT91_RTC_HRMOD (1 << 0) /* 12/24 Hour Mode */ -#define AT91_RTC_TIMR (AT91_RTC + 0x08) /* Time Register */ +#define AT91_RTC_TIMR 0x08 /* Time Register */ #define AT91_RTC_SEC (0x7f << 0) /* Current Second */ #define AT91_RTC_MIN (0x7f << 8) /* Current Minute */ #define AT91_RTC_HOUR (0x3f << 16) /* Current Hour */ #define AT91_RTC_AMPM (1 << 22) /* Ante Meridiem Post Meridiem Indicator */ -#define AT91_RTC_CALR (AT91_RTC + 0x0c) /* Calendar Register */ +#define AT91_RTC_CALR 0x0c /* Calendar Register */ #define AT91_RTC_CENT (0x7f << 0) /* Current Century */ #define AT91_RTC_YEAR (0xff << 8) /* Current Year */ #define AT91_RTC_MONTH (0x1f << 16) /* Current Month */ #define AT91_RTC_DAY (7 << 21) /* Current Day */ #define AT91_RTC_DATE (0x3f << 24) /* Current Date */ -#define AT91_RTC_TIMALR (AT91_RTC + 0x10) /* Time Alarm Register */ +#define AT91_RTC_TIMALR 0x10 /* Time Alarm Register */ #define AT91_RTC_SECEN (1 << 7) /* Second Alarm Enable */ #define AT91_RTC_MINEN (1 << 15) /* Minute Alarm Enable */ #define AT91_RTC_HOUREN (1 << 23) /* Hour Alarm Enable */ -#define AT91_RTC_CALALR (AT91_RTC + 0x14) /* Calendar Alarm Register */ +#define AT91_RTC_CALALR 0x14 /* Calendar Alarm Register */ #define AT91_RTC_MTHEN (1 << 23) /* Month Alarm Enable */ #define AT91_RTC_DATEEN (1 << 31) /* Date Alarm Enable */ -#define AT91_RTC_SR (AT91_RTC + 0x18) /* Status Register */ +#define AT91_RTC_SR 0x18 /* Status Register */ #define AT91_RTC_ACKUPD (1 << 0) /* Acknowledge for Update */ #define AT91_RTC_ALARM (1 << 1) /* Alarm Flag */ #define AT91_RTC_SECEV (1 << 2) /* Second Event */ #define AT91_RTC_TIMEV (1 << 3) /* Time Event */ #define AT91_RTC_CALEV (1 << 4) /* Calendar Event */ -#define AT91_RTC_SCCR (AT91_RTC + 0x1c) /* Status Clear Command Register */ -#define AT91_RTC_IER (AT91_RTC + 0x20) /* Interrupt Enable Register */ -#define AT91_RTC_IDR (AT91_RTC + 0x24) /* Interrupt Disable Register */ -#define AT91_RTC_IMR (AT91_RTC + 0x28) /* Interrupt Mask Register */ +#define AT91_RTC_SCCR 0x1c /* Status Clear Command Register */ +#define AT91_RTC_IER 0x20 /* Interrupt Enable Register */ +#define AT91_RTC_IDR 0x24 /* Interrupt Disable Register */ +#define AT91_RTC_IMR 0x28 /* Interrupt Mask Register */ -#define AT91_RTC_VER (AT91_RTC + 0x2c) /* Valid Entry Register */ +#define AT91_RTC_VER 0x2c /* Valid Entry Register */ #define AT91_RTC_NVTIM (1 << 0) /* Non valid Time */ #define AT91_RTC_NVCAL (1 << 1) /* Non valid Calendar */ #define AT91_RTC_NVTIMALR (1 << 2) /* Non valid Time Alarm */ diff --git a/arch/arm/mach-at91/include/mach/at91_shdwc.h b/arch/arm/mach-at91/include/mach/at91_shdwc.h index c4ce07e8a8f..1d4fe822c77 100644 --- a/arch/arm/mach-at91/include/mach/at91_shdwc.h +++ b/arch/arm/mach-at91/include/mach/at91_shdwc.h @@ -16,11 +16,21 @@ #ifndef AT91_SHDWC_H #define AT91_SHDWC_H -#define AT91_SHDW_CR (AT91_SHDWC + 0x00) /* Shut Down Control Register */ +#ifndef __ASSEMBLY__ +extern void __iomem *at91_shdwc_base; + +#define at91_shdwc_read(field) \ + __raw_readl(at91_shdwc_base + field) + +#define at91_shdwc_write(field, value) \ + __raw_writel(value, at91_shdwc_base + field); +#endif + +#define AT91_SHDW_CR 0x00 /* Shut Down Control Register */ #define AT91_SHDW_SHDW (1 << 0) /* Shut Down command */ #define AT91_SHDW_KEY (0xa5 << 24) /* KEY Password */ -#define AT91_SHDW_MR (AT91_SHDWC + 0x04) /* Shut Down Mode Register */ +#define AT91_SHDW_MR 0x04 /* Shut Down Mode Register */ #define AT91_SHDW_WKMODE0 (3 << 0) /* Wake-up 0 Mode Selection */ #define AT91_SHDW_WKMODE0_NONE 0 #define AT91_SHDW_WKMODE0_HIGH 1 @@ -30,7 +40,7 @@ #define AT91_SHDW_CPTWK0_(x) ((x) << 4) #define AT91_SHDW_RTTWKEN (1 << 16) /* Real Time Timer Wake-up Enable */ -#define AT91_SHDW_SR (AT91_SHDWC + 0x08) /* Shut Down Status Register */ +#define AT91_SHDW_SR 0x08 /* Shut Down Status Register */ #define AT91_SHDW_WAKEUP0 (1 << 0) /* Wake-up 0 Status */ #define AT91_SHDW_RTTWK (1 << 16) /* Real-time Timer Wake-up */ #define AT91_SHDW_RTCWK (1 << 17) /* Real-time Clock Wake-up [SAM9RL] */ diff --git a/arch/arm/mach-at91/include/mach/at91cap9.h b/arch/arm/mach-at91/include/mach/at91cap9.h index c5df1e8f195..4c0e2f6011d 100644 --- a/arch/arm/mach-at91/include/mach/at91cap9.h +++ b/arch/arm/mach-at91/include/mach/at91cap9.h @@ -79,29 +79,28 @@ /* * System Peripherals (offset from AT91_BASE_SYS) */ -#define AT91_ECC (0xffffe200 - AT91_BASE_SYS) #define AT91_BCRAMC (0xffffe400 - AT91_BASE_SYS) #define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS) -#define AT91_SMC (0xffffe800 - AT91_BASE_SYS) #define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS) -#define AT91_CCFG (0xffffeb10 - AT91_BASE_SYS) -#define AT91_DMA (0xffffec00 - AT91_BASE_SYS) -#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS) -#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) -#define AT91_PIOA (0xfffff200 - AT91_BASE_SYS) -#define AT91_PIOB (0xfffff400 - AT91_BASE_SYS) -#define AT91_PIOC (0xfffff600 - AT91_BASE_SYS) -#define AT91_PIOD (0xfffff800 - AT91_BASE_SYS) #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) #define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) -#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) -#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS) -#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) -#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) #define AT91_GPBR (cpu_is_at91cap9_revB() ? \ (0xfffffd50 - AT91_BASE_SYS) : \ (0xfffffd60 - AT91_BASE_SYS)) +#define AT91CAP9_BASE_ECC 0xffffe200 +#define AT91CAP9_BASE_DMA 0xffffec00 +#define AT91CAP9_BASE_SMC 0xffffe800 +#define AT91CAP9_BASE_DBGU AT91_BASE_DBGU1 +#define AT91CAP9_BASE_PIOA 0xfffff200 +#define AT91CAP9_BASE_PIOB 0xfffff400 +#define AT91CAP9_BASE_PIOC 0xfffff600 +#define AT91CAP9_BASE_PIOD 0xfffff800 +#define AT91CAP9_BASE_SHDWC 0xfffffd10 +#define AT91CAP9_BASE_RTT 0xfffffd20 +#define AT91CAP9_BASE_PIT 0xfffffd30 +#define AT91CAP9_BASE_WDT 0xfffffd40 + #define AT91_USART0 AT91CAP9_BASE_US0 #define AT91_USART1 AT91CAP9_BASE_US1 #define AT91_USART2 AT91CAP9_BASE_US2 diff --git a/arch/arm/mach-at91/include/mach/at91rm9200.h b/arch/arm/mach-at91/include/mach/at91rm9200.h index e4037b50030..bacb5114181 100644 --- a/arch/arm/mach-at91/include/mach/at91rm9200.h +++ b/arch/arm/mach-at91/include/mach/at91rm9200.h @@ -79,17 +79,17 @@ /* * System Peripherals (offset from AT91_BASE_SYS) */ -#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) /* Advanced Interrupt Controller */ -#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) /* Debug Unit */ -#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS) /* PIO Controller A */ -#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS) /* PIO Controller B */ -#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS) /* PIO Controller C */ -#define AT91_PIOD (0xfffffa00 - AT91_BASE_SYS) /* PIO Controller D */ #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) /* Power Management Controller */ #define AT91_ST (0xfffffd00 - AT91_BASE_SYS) /* System Timer */ -#define AT91_RTC (0xfffffe00 - AT91_BASE_SYS) /* Real-Time Clock */ #define AT91_MC (0xffffff00 - AT91_BASE_SYS) /* Memory Controllers */ +#define AT91RM9200_BASE_DBGU AT91_BASE_DBGU0 /* Debug Unit */ +#define AT91RM9200_BASE_PIOA 0xfffff400 /* PIO Controller A */ +#define AT91RM9200_BASE_PIOB 0xfffff600 /* PIO Controller B */ +#define AT91RM9200_BASE_PIOC 0xfffff800 /* PIO Controller C */ +#define AT91RM9200_BASE_PIOD 0xfffffa00 /* PIO Controller D */ +#define AT91RM9200_BASE_RTC 0xfffffe00 /* Real-Time Clock */ + #define AT91_USART0 AT91RM9200_BASE_US0 #define AT91_USART1 AT91RM9200_BASE_US1 #define AT91_USART2 AT91RM9200_BASE_US2 diff --git a/arch/arm/mach-at91/include/mach/at91sam9260.h b/arch/arm/mach-at91/include/mach/at91sam9260.h index 9a791165913..f937c476bb6 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9260.h +++ b/arch/arm/mach-at91/include/mach/at91sam9260.h @@ -80,24 +80,23 @@ /* * System Peripherals (offset from AT91_BASE_SYS) */ -#define AT91_ECC (0xffffe800 - AT91_BASE_SYS) #define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS) -#define AT91_SMC (0xffffec00 - AT91_BASE_SYS) #define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) -#define AT91_CCFG (0xffffef10 - AT91_BASE_SYS) -#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) -#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) -#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS) -#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS) -#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS) #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) #define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) -#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) -#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS) -#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) -#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) #define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) +#define AT91SAM9260_BASE_ECC 0xffffe800 +#define AT91SAM9260_BASE_SMC 0xffffec00 +#define AT91SAM9260_BASE_DBGU AT91_BASE_DBGU0 +#define AT91SAM9260_BASE_PIOA 0xfffff400 +#define AT91SAM9260_BASE_PIOB 0xfffff600 +#define AT91SAM9260_BASE_PIOC 0xfffff800 +#define AT91SAM9260_BASE_SHDWC 0xfffffd10 +#define AT91SAM9260_BASE_RTT 0xfffffd20 +#define AT91SAM9260_BASE_PIT 0xfffffd30 +#define AT91SAM9260_BASE_WDT 0xfffffd40 + #define AT91_USART0 AT91SAM9260_BASE_US0 #define AT91_USART1 AT91SAM9260_BASE_US1 #define AT91_USART2 AT91SAM9260_BASE_US2 diff --git a/arch/arm/mach-at91/include/mach/at91sam9261.h b/arch/arm/mach-at91/include/mach/at91sam9261.h index ce596204cef..175604e261b 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9261.h +++ b/arch/arm/mach-at91/include/mach/at91sam9261.h @@ -66,21 +66,21 @@ * System Peripherals (offset from AT91_BASE_SYS) */ #define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS) -#define AT91_SMC (0xffffec00 - AT91_BASE_SYS) #define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) -#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) -#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) -#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS) -#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS) -#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS) #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) #define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) -#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) -#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS) -#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) -#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) #define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) +#define AT91SAM9261_BASE_SMC 0xffffec00 +#define AT91SAM9261_BASE_DBGU AT91_BASE_DBGU0 +#define AT91SAM9261_BASE_PIOA 0xfffff400 +#define AT91SAM9261_BASE_PIOB 0xfffff600 +#define AT91SAM9261_BASE_PIOC 0xfffff800 +#define AT91SAM9261_BASE_SHDWC 0xfffffd10 +#define AT91SAM9261_BASE_RTT 0xfffffd20 +#define AT91SAM9261_BASE_PIT 0xfffffd30 +#define AT91SAM9261_BASE_WDT 0xfffffd40 + #define AT91_USART0 AT91SAM9261_BASE_US0 #define AT91_USART1 AT91SAM9261_BASE_US1 #define AT91_USART2 AT91SAM9261_BASE_US2 diff --git a/arch/arm/mach-at91/include/mach/at91sam9263.h b/arch/arm/mach-at91/include/mach/at91sam9263.h index f1b92961a2b..80c915002d8 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9263.h +++ b/arch/arm/mach-at91/include/mach/at91sam9263.h @@ -74,30 +74,29 @@ /* * System Peripherals (offset from AT91_BASE_SYS) */ -#define AT91_ECC0 (0xffffe000 - AT91_BASE_SYS) #define AT91_SDRAMC0 (0xffffe200 - AT91_BASE_SYS) -#define AT91_SMC0 (0xffffe400 - AT91_BASE_SYS) -#define AT91_ECC1 (0xffffe600 - AT91_BASE_SYS) #define AT91_SDRAMC1 (0xffffe800 - AT91_BASE_SYS) -#define AT91_SMC1 (0xffffea00 - AT91_BASE_SYS) #define AT91_MATRIX (0xffffec00 - AT91_BASE_SYS) -#define AT91_CCFG (0xffffed10 - AT91_BASE_SYS) -#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS) -#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) -#define AT91_PIOA (0xfffff200 - AT91_BASE_SYS) -#define AT91_PIOB (0xfffff400 - AT91_BASE_SYS) -#define AT91_PIOC (0xfffff600 - AT91_BASE_SYS) -#define AT91_PIOD (0xfffff800 - AT91_BASE_SYS) -#define AT91_PIOE (0xfffffa00 - AT91_BASE_SYS) #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) #define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) -#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) -#define AT91_RTT0 (0xfffffd20 - AT91_BASE_SYS) -#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) -#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) -#define AT91_RTT1 (0xfffffd50 - AT91_BASE_SYS) #define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) +#define AT91SAM9263_BASE_ECC0 0xffffe000 +#define AT91SAM9263_BASE_SMC0 0xffffe400 +#define AT91SAM9263_BASE_ECC1 0xffffe600 +#define AT91SAM9263_BASE_SMC1 0xffffea00 +#define AT91SAM9263_BASE_DBGU AT91_BASE_DBGU1 +#define AT91SAM9263_BASE_PIOA 0xfffff200 +#define AT91SAM9263_BASE_PIOB 0xfffff400 +#define AT91SAM9263_BASE_PIOC 0xfffff600 +#define AT91SAM9263_BASE_PIOD 0xfffff800 +#define AT91SAM9263_BASE_PIOE 0xfffffa00 +#define AT91SAM9263_BASE_SHDWC 0xfffffd10 +#define AT91SAM9263_BASE_RTT0 0xfffffd20 +#define AT91SAM9263_BASE_PIT 0xfffffd30 +#define AT91SAM9263_BASE_WDT 0xfffffd40 +#define AT91SAM9263_BASE_RTT1 0xfffffd50 + #define AT91_USART0 AT91SAM9263_BASE_US0 #define AT91_USART1 AT91SAM9263_BASE_US1 #define AT91_USART2 AT91SAM9263_BASE_US2 diff --git a/arch/arm/mach-at91/include/mach/at91sam9_smc.h b/arch/arm/mach-at91/include/mach/at91sam9_smc.h index 57de6207e57..eb18a70fa64 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9_smc.h +++ b/arch/arm/mach-at91/include/mach/at91sam9_smc.h @@ -16,7 +16,9 @@ #ifndef AT91SAM9_SMC_H #define AT91SAM9_SMC_H -#define AT91_SMC_SETUP(n) (AT91_SMC + 0x00 + ((n)*0x10)) /* Setup Register for CS n */ +#include <mach/cpu.h> + +#define AT91_SMC_SETUP 0x00 /* Setup Register for CS n */ #define AT91_SMC_NWESETUP (0x3f << 0) /* NWE Setup Length */ #define AT91_SMC_NWESETUP_(x) ((x) << 0) #define AT91_SMC_NCS_WRSETUP (0x3f << 8) /* NCS Setup Length in Write Access */ @@ -26,7 +28,7 @@ #define AT91_SMC_NCS_RDSETUP (0x3f << 24) /* NCS Setup Length in Read Access */ #define AT91_SMC_NCS_RDSETUP_(x) ((x) << 24) -#define AT91_SMC_PULSE(n) (AT91_SMC + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */ +#define AT91_SMC_PULSE 0x04 /* Pulse Register for CS n */ #define AT91_SMC_NWEPULSE (0x7f << 0) /* NWE Pulse Length */ #define AT91_SMC_NWEPULSE_(x) ((x) << 0) #define AT91_SMC_NCS_WRPULSE (0x7f << 8) /* NCS Pulse Length in Write Access */ @@ -36,13 +38,13 @@ #define AT91_SMC_NCS_RDPULSE (0x7f << 24) /* NCS Pulse Length in Read Access */ #define AT91_SMC_NCS_RDPULSE_(x)((x) << 24) -#define AT91_SMC_CYCLE(n) (AT91_SMC + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */ +#define AT91_SMC_CYCLE 0x08 /* Cycle Register for CS n */ #define AT91_SMC_NWECYCLE (0x1ff << 0 ) /* Total Write Cycle Length */ #define AT91_SMC_NWECYCLE_(x) ((x) << 0) #define AT91_SMC_NRDCYCLE (0x1ff << 16) /* Total Read Cycle Length */ #define AT91_SMC_NRDCYCLE_(x) ((x) << 16) -#define AT91_SMC_MODE(n) (AT91_SMC + 0x0c + ((n)*0x10)) /* Mode Register for CS n */ +#define AT91_SMC_MODE 0x0c /* Mode Register for CS n */ #define AT91_SMC_READMODE (1 << 0) /* Read Mode */ #define AT91_SMC_WRITEMODE (1 << 1) /* Write Mode */ #define AT91_SMC_EXNWMODE (3 << 4) /* NWAIT Mode */ @@ -66,11 +68,4 @@ #define AT91_SMC_PS_16 (2 << 28) #define AT91_SMC_PS_32 (3 << 28) -#if defined(AT91_SMC1) /* The AT91SAM9263 has 2 Static Memory contollers */ -#define AT91_SMC1_SETUP(n) (AT91_SMC1 + 0x00 + ((n)*0x10)) /* Setup Register for CS n */ -#define AT91_SMC1_PULSE(n) (AT91_SMC1 + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */ -#define AT91_SMC1_CYCLE(n) (AT91_SMC1 + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */ -#define AT91_SMC1_MODE(n) (AT91_SMC1 + 0x0c + ((n)*0x10)) /* Mode Register for CS n */ -#endif - #endif diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45.h b/arch/arm/mach-at91/include/mach/at91sam9g45.h index 406bb649680..f0c23c960de 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9g45.h +++ b/arch/arm/mach-at91/include/mach/at91sam9g45.h @@ -86,27 +86,27 @@ /* * System Peripherals (offset from AT91_BASE_SYS) */ -#define AT91_ECC (0xffffe200 - AT91_BASE_SYS) #define AT91_DDRSDRC1 (0xffffe400 - AT91_BASE_SYS) #define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS) -#define AT91_SMC (0xffffe800 - AT91_BASE_SYS) #define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS) -#define AT91_DMA (0xffffec00 - AT91_BASE_SYS) -#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS) -#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) -#define AT91_PIOA (0xfffff200 - AT91_BASE_SYS) -#define AT91_PIOB (0xfffff400 - AT91_BASE_SYS) -#define AT91_PIOC (0xfffff600 - AT91_BASE_SYS) -#define AT91_PIOD (0xfffff800 - AT91_BASE_SYS) -#define AT91_PIOE (0xfffffa00 - AT91_BASE_SYS) #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) #define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) -#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) -#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS) -#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) -#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) #define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) -#define AT91_RTC (0xfffffdb0 - AT91_BASE_SYS) + +#define AT91SAM9G45_BASE_ECC 0xffffe200 +#define AT91SAM9G45_BASE_DMA 0xffffec00 +#define AT91SAM9G45_BASE_SMC 0xffffe800 +#define AT91SAM9G45_BASE_DBGU AT91_BASE_DBGU1 +#define AT91SAM9G45_BASE_PIOA 0xfffff200 +#define AT91SAM9G45_BASE_PIOB 0xfffff400 +#define AT91SAM9G45_BASE_PIOC 0xfffff600 +#define AT91SAM9G45_BASE_PIOD 0xfffff800 +#define AT91SAM9G45_BASE_PIOE 0xfffffa00 +#define AT91SAM9G45_BASE_SHDWC 0xfffffd10 +#define AT91SAM9G45_BASE_RTT 0xfffffd20 +#define AT91SAM9G45_BASE_PIT 0xfffffd30 +#define AT91SAM9G45_BASE_WDT 0xfffffd40 +#define AT91SAM9G45_BASE_RTC 0xfffffdb0 #define AT91_USART0 AT91SAM9G45_BASE_US0 #define AT91_USART1 AT91SAM9G45_BASE_US1 diff --git a/arch/arm/mach-at91/include/mach/at91sam9rl.h b/arch/arm/mach-at91/include/mach/at91sam9rl.h index 1aabacd315d..2bb359e60b9 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9rl.h +++ b/arch/arm/mach-at91/include/mach/at91sam9rl.h @@ -69,27 +69,26 @@ /* * System Peripherals (offset from AT91_BASE_SYS) */ -#define AT91_DMA (0xffffe600 - AT91_BASE_SYS) -#define AT91_ECC (0xffffe800 - AT91_BASE_SYS) #define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS) -#define AT91_SMC (0xffffec00 - AT91_BASE_SYS) #define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) -#define AT91_CCFG (0xffffef10 - AT91_BASE_SYS) -#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) -#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) -#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS) -#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS) -#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS) -#define AT91_PIOD (0xfffffa00 - AT91_BASE_SYS) #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) #define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) -#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) -#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS) -#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) -#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) #define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS) #define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) -#define AT91_RTC (0xfffffe00 - AT91_BASE_SYS) + +#define AT91SAM9RL_BASE_DMA 0xffffe600 +#define AT91SAM9RL_BASE_ECC 0xffffe800 +#define AT91SAM9RL_BASE_SMC 0xffffec00 +#define AT91SAM9RL_BASE_DBGU AT91_BASE_DBGU0 +#define AT91SAM9RL_BASE_PIOA 0xfffff400 +#define AT91SAM9RL_BASE_PIOB 0xfffff600 +#define AT91SAM9RL_BASE_PIOC 0xfffff800 +#define AT91SAM9RL_BASE_PIOD 0xfffffa00 +#define AT91SAM9RL_BASE_SHDWC 0xfffffd10 +#define AT91SAM9RL_BASE_RTT 0xfffffd20 +#define AT91SAM9RL_BASE_PIT 0xfffffd30 +#define AT91SAM9RL_BASE_WDT 0xfffffd40 +#define AT91SAM9RL_BASE_RTC 0xfffffe00 #define AT91_USART0 AT91SAM9RL_BASE_US0 #define AT91_USART1 AT91SAM9RL_BASE_US1 diff --git a/arch/arm/mach-at91/include/mach/at91x40.h b/arch/arm/mach-at91/include/mach/at91x40.h index a152ff87e68..a57829f4fd1 100644 --- a/arch/arm/mach-at91/include/mach/at91x40.h +++ b/arch/arm/mach-at91/include/mach/at91x40.h @@ -40,7 +40,6 @@ #define AT91_PIOA (0xffff0000 - AT91_BASE_SYS) /* PIO Controller A */ #define AT91_PS (0xffff4000 - AT91_BASE_SYS) /* Power Save */ #define AT91_WD (0xffff8000 - AT91_BASE_SYS) /* Watchdog Timer */ -#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) /* Advanced Interrupt Controller */ /* * The AT91x40 series doesn't have a debug unit like the other AT91 parts. diff --git a/arch/arm/mach-at91/include/mach/board.h b/arch/arm/mach-at91/include/mach/board.h index eac92e995bb..d0b377b21bd 100644 --- a/arch/arm/mach-at91/include/mach/board.h +++ b/arch/arm/mach-at91/include/mach/board.h @@ -40,13 +40,14 @@ #include <linux/atmel-mci.h> #include <sound/atmel-ac97c.h> #include <linux/serial.h> +#include <linux/platform_data/macb.h> /* USB Device */ struct at91_udc_data { - u8 vbus_pin; /* high == host powering us */ + int vbus_pin; /* high == host powering us */ u8 vbus_active_low; /* vbus polarity */ u8 vbus_polled; /* Use polling, not interrupt */ - u8 pullup_pin; /* active == D+ pulled up */ + int pullup_pin; /* active == D+ pulled up */ u8 pullup_active_low; /* true == pullup_pin is active low */ }; extern void __init at91_add_device_udc(struct at91_udc_data *data); @@ -56,10 +57,10 @@ extern void __init at91_add_device_usba(struct usba_platform_data *data); /* Compact Flash */ struct at91_cf_data { - u8 irq_pin; /* I/O IRQ */ - u8 det_pin; /* Card detect */ - u8 vcc_pin; /* power switching */ - u8 rst_pin; /* card reset */ + int irq_pin; /* I/O IRQ */ + int det_pin; /* Card detect */ + int vcc_pin; /* power switching */ + int rst_pin; /* card reset */ u8 chipselect; /* EBI Chip Select number */ u8 flags; #define AT91_CF_TRUE_IDE 0x01 @@ -70,37 +71,26 @@ extern void __init at91_add_device_cf(struct at91_cf_data *data); /* MMC / SD */ /* at91_mci platform config */ struct at91_mmc_data { - u8 det_pin; /* card detect IRQ */ + int det_pin; /* card detect IRQ */ unsigned slot_b:1; /* uses Slot B */ unsigned wire4:1; /* (SD) supports DAT0..DAT3 */ - u8 wp_pin; /* (SD) writeprotect detect */ - u8 vcc_pin; /* power switching (high == on) */ + int wp_pin; /* (SD) writeprotect detect */ + int vcc_pin; /* power switching (high == on) */ }; extern void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data); /* atmel-mci platform config */ extern void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data); - /* Ethernet (EMAC & MACB) */ -struct at91_eth_data { - u32 phy_mask; - u8 phy_irq_pin; /* PHY IRQ */ - u8 is_rmii; /* using RMII interface? */ -}; -extern void __init at91_add_device_eth(struct at91_eth_data *data); - -#if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9263) || defined(CONFIG_ARCH_AT91SAM9G20) || defined(CONFIG_ARCH_AT91CAP9) \ - || defined(CONFIG_ARCH_AT91SAM9G45) -#define eth_platform_data at91_eth_data -#endif +extern void __init at91_add_device_eth(struct macb_platform_data *data); /* USB Host */ struct at91_usbh_data { u8 ports; /* number of ports on root hub */ - u8 vbus_pin[2]; /* port power-control pin */ + int vbus_pin[2]; /* port power-control pin */ u8 vbus_pin_inverted; u8 overcurrent_supported; - u8 overcurrent_pin[2]; + int overcurrent_pin[2]; u8 overcurrent_status[2]; u8 overcurrent_changed[2]; }; @@ -110,9 +100,9 @@ extern void __init at91_add_device_usbh_ehci(struct at91_usbh_data *data); /* NAND / SmartMedia */ struct atmel_nand_data { - u8 enable_pin; /* chip enable */ - u8 det_pin; /* card detect */ - u8 rdy_pin; /* ready/busy */ + int enable_pin; /* chip enable */ + int det_pin; /* card detect */ + int rdy_pin; /* ready/busy */ u8 rdy_pin_active_low; /* rdy_pin value is inverted */ u8 ale; /* address line number connected to ALE */ u8 cle; /* address line number connected to CLE */ diff --git a/arch/arm/mach-at91/include/mach/debug-macro.S b/arch/arm/mach-at91/include/mach/debug-macro.S index 0ed8648c645..c6bb9e2d9ba 100644 --- a/arch/arm/mach-at91/include/mach/debug-macro.S +++ b/arch/arm/mach-at91/include/mach/debug-macro.S @@ -14,9 +14,15 @@ #include <mach/hardware.h> #include <mach/at91_dbgu.h> +#if defined(CONFIG_AT91_DEBUG_LL_DBGU0) +#define AT91_DBGU AT91_BASE_DBGU0 +#else +#define AT91_DBGU AT91_BASE_DBGU1 +#endif + .macro addruart, rp, rv, tmp - ldr \rp, =(AT91_BASE_SYS + AT91_DBGU) @ System peripherals (phys address) - ldr \rv, =(AT91_VA_BASE_SYS + AT91_DBGU) @ System peripherals (virt address) + ldr \rp, =AT91_DBGU @ System peripherals (phys address) + ldr \rv, =AT91_IO_P2V(AT91_DBGU) @ System peripherals (virt address) .endm .macro senduart,rd,rx diff --git a/arch/arm/mach-at91/include/mach/entry-macro.S b/arch/arm/mach-at91/include/mach/entry-macro.S index 7ab68f97222..423eea0ed74 100644 --- a/arch/arm/mach-at91/include/mach/entry-macro.S +++ b/arch/arm/mach-at91/include/mach/entry-macro.S @@ -17,16 +17,17 @@ .endm .macro get_irqnr_preamble, base, tmp - ldr \base, =(AT91_VA_BASE_SYS + AT91_AIC) @ base virtual address of AIC peripheral + ldr \base, =at91_aic_base @ base virtual address of AIC peripheral + ldr \base, [\base] .endm .macro arch_ret_to_user, tmp1, tmp2 .endm .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - ldr \irqnr, [\base, #(AT91_AIC_IVR - AT91_AIC)] @ read IRQ vector register: de-asserts nIRQ to processor (and clears interrupt) - ldr \irqstat, [\base, #(AT91_AIC_ISR - AT91_AIC)] @ read interrupt source number - teq \irqstat, #0 @ ISR is 0 when no current interrupt, or spurious interrupt - streq \tmp, [\base, #(AT91_AIC_EOICR - AT91_AIC)] @ not going to be handled further, then ACK it now. + ldr \irqnr, [\base, #AT91_AIC_IVR] @ read IRQ vector register: de-asserts nIRQ to processor (and clears interrupt) + ldr \irqstat, [\base, #AT91_AIC_ISR] @ read interrupt source number + teq \irqstat, #0 @ ISR is 0 when no current interrupt, or spurious interrupt + streq \tmp, [\base, #AT91_AIC_EOICR] @ not going to be handled further, then ACK it now. .endm diff --git a/arch/arm/mach-at91/include/mach/gpio.h b/arch/arm/mach-at91/include/mach/gpio.h index 2b9a1f51210..e3fd225121c 100644 --- a/arch/arm/mach-at91/include/mach/gpio.h +++ b/arch/arm/mach-at91/include/mach/gpio.h @@ -16,177 +16,175 @@ #include <linux/kernel.h> #include <asm/irq.h> -#define PIN_BASE NR_AIC_IRQS - #define MAX_GPIO_BANKS 5 -#define NR_BUILTIN_GPIO (PIN_BASE + (MAX_GPIO_BANKS * 32)) +#define NR_BUILTIN_GPIO (MAX_GPIO_BANKS * 32) /* these pin numbers double as IRQ numbers, like AT91xxx_ID_* values */ -#define AT91_PIN_PA0 (PIN_BASE + 0x00 + 0) -#define AT91_PIN_PA1 (PIN_BASE + 0x00 + 1) -#define AT91_PIN_PA2 (PIN_BASE + 0x00 + 2) -#define AT91_PIN_PA3 (PIN_BASE + 0x00 + 3) -#define AT91_PIN_PA4 (PIN_BASE + 0x00 + 4) -#define AT91_PIN_PA5 (PIN_BASE + 0x00 + 5) -#define AT91_PIN_PA6 (PIN_BASE + 0x00 + 6) -#define AT91_PIN_PA7 (PIN_BASE + 0x00 + 7) -#define AT91_PIN_PA8 (PIN_BASE + 0x00 + 8) -#define AT91_PIN_PA9 (PIN_BASE + 0x00 + 9) -#define AT91_PIN_PA10 (PIN_BASE + 0x00 + 10) -#define AT91_PIN_PA11 (PIN_BASE + 0x00 + 11) -#define AT91_PIN_PA12 (PIN_BASE + 0x00 + 12) -#define AT91_PIN_PA13 (PIN_BASE + 0x00 + 13) -#define AT91_PIN_PA14 (PIN_BASE + 0x00 + 14) -#define AT91_PIN_PA15 (PIN_BASE + 0x00 + 15) -#define AT91_PIN_PA16 (PIN_BASE + 0x00 + 16) -#define AT91_PIN_PA17 (PIN_BASE + 0x00 + 17) -#define AT91_PIN_PA18 (PIN_BASE + 0x00 + 18) -#define AT91_PIN_PA19 (PIN_BASE + 0x00 + 19) -#define AT91_PIN_PA20 (PIN_BASE + 0x00 + 20) -#define AT91_PIN_PA21 (PIN_BASE + 0x00 + 21) -#define AT91_PIN_PA22 (PIN_BASE + 0x00 + 22) -#define AT91_PIN_PA23 (PIN_BASE + 0x00 + 23) -#define AT91_PIN_PA24 (PIN_BASE + 0x00 + 24) -#define AT91_PIN_PA25 (PIN_BASE + 0x00 + 25) -#define AT91_PIN_PA26 (PIN_BASE + 0x00 + 26) -#define AT91_PIN_PA27 (PIN_BASE + 0x00 + 27) -#define AT91_PIN_PA28 (PIN_BASE + 0x00 + 28) -#define AT91_PIN_PA29 (PIN_BASE + 0x00 + 29) -#define AT91_PIN_PA30 (PIN_BASE + 0x00 + 30) -#define AT91_PIN_PA31 (PIN_BASE + 0x00 + 31) - -#define AT91_PIN_PB0 (PIN_BASE + 0x20 + 0) -#define AT91_PIN_PB1 (PIN_BASE + 0x20 + 1) -#define AT91_PIN_PB2 (PIN_BASE + 0x20 + 2) -#define AT91_PIN_PB3 (PIN_BASE + 0x20 + 3) -#define AT91_PIN_PB4 (PIN_BASE + 0x20 + 4) -#define AT91_PIN_PB5 (PIN_BASE + 0x20 + 5) -#define AT91_PIN_PB6 (PIN_BASE + 0x20 + 6) -#define AT91_PIN_PB7 (PIN_BASE + 0x20 + 7) -#define AT91_PIN_PB8 (PIN_BASE + 0x20 + 8) -#define AT91_PIN_PB9 (PIN_BASE + 0x20 + 9) -#define AT91_PIN_PB10 (PIN_BASE + 0x20 + 10) -#define AT91_PIN_PB11 (PIN_BASE + 0x20 + 11) -#define AT91_PIN_PB12 (PIN_BASE + 0x20 + 12) -#define AT91_PIN_PB13 (PIN_BASE + 0x20 + 13) -#define AT91_PIN_PB14 (PIN_BASE + 0x20 + 14) -#define AT91_PIN_PB15 (PIN_BASE + 0x20 + 15) -#define AT91_PIN_PB16 (PIN_BASE + 0x20 + 16) -#define AT91_PIN_PB17 (PIN_BASE + 0x20 + 17) -#define AT91_PIN_PB18 (PIN_BASE + 0x20 + 18) -#define AT91_PIN_PB19 (PIN_BASE + 0x20 + 19) -#define AT91_PIN_PB20 (PIN_BASE + 0x20 + 20) -#define AT91_PIN_PB21 (PIN_BASE + 0x20 + 21) -#define AT91_PIN_PB22 (PIN_BASE + 0x20 + 22) -#define AT91_PIN_PB23 (PIN_BASE + 0x20 + 23) -#define AT91_PIN_PB24 (PIN_BASE + 0x20 + 24) -#define AT91_PIN_PB25 (PIN_BASE + 0x20 + 25) -#define AT91_PIN_PB26 (PIN_BASE + 0x20 + 26) -#define AT91_PIN_PB27 (PIN_BASE + 0x20 + 27) -#define AT91_PIN_PB28 (PIN_BASE + 0x20 + 28) -#define AT91_PIN_PB29 (PIN_BASE + 0x20 + 29) -#define AT91_PIN_PB30 (PIN_BASE + 0x20 + 30) -#define AT91_PIN_PB31 (PIN_BASE + 0x20 + 31) - -#define AT91_PIN_PC0 (PIN_BASE + 0x40 + 0) -#define AT91_PIN_PC1 (PIN_BASE + 0x40 + 1) -#define AT91_PIN_PC2 (PIN_BASE + 0x40 + 2) -#define AT91_PIN_PC3 (PIN_BASE + 0x40 + 3) -#define AT91_PIN_PC4 (PIN_BASE + 0x40 + 4) -#define AT91_PIN_PC5 (PIN_BASE + 0x40 + 5) -#define AT91_PIN_PC6 (PIN_BASE + 0x40 + 6) -#define AT91_PIN_PC7 (PIN_BASE + 0x40 + 7) -#define AT91_PIN_PC8 (PIN_BASE + 0x40 + 8) -#define AT91_PIN_PC9 (PIN_BASE + 0x40 + 9) -#define AT91_PIN_PC10 (PIN_BASE + 0x40 + 10) -#define AT91_PIN_PC11 (PIN_BASE + 0x40 + 11) -#define AT91_PIN_PC12 (PIN_BASE + 0x40 + 12) -#define AT91_PIN_PC13 (PIN_BASE + 0x40 + 13) -#define AT91_PIN_PC14 (PIN_BASE + 0x40 + 14) -#define AT91_PIN_PC15 (PIN_BASE + 0x40 + 15) -#define AT91_PIN_PC16 (PIN_BASE + 0x40 + 16) -#define AT91_PIN_PC17 (PIN_BASE + 0x40 + 17) -#define AT91_PIN_PC18 (PIN_BASE + 0x40 + 18) -#define AT91_PIN_PC19 (PIN_BASE + 0x40 + 19) -#define AT91_PIN_PC20 (PIN_BASE + 0x40 + 20) -#define AT91_PIN_PC21 (PIN_BASE + 0x40 + 21) -#define AT91_PIN_PC22 (PIN_BASE + 0x40 + 22) -#define AT91_PIN_PC23 (PIN_BASE + 0x40 + 23) -#define AT91_PIN_PC24 (PIN_BASE + 0x40 + 24) -#define AT91_PIN_PC25 (PIN_BASE + 0x40 + 25) -#define AT91_PIN_PC26 (PIN_BASE + 0x40 + 26) -#define AT91_PIN_PC27 (PIN_BASE + 0x40 + 27) -#define AT91_PIN_PC28 (PIN_BASE + 0x40 + 28) -#define AT91_PIN_PC29 (PIN_BASE + 0x40 + 29) -#define AT91_PIN_PC30 (PIN_BASE + 0x40 + 30) -#define AT91_PIN_PC31 (PIN_BASE + 0x40 + 31) - -#define AT91_PIN_PD0 (PIN_BASE + 0x60 + 0) -#define AT91_PIN_PD1 (PIN_BASE + 0x60 + 1) -#define AT91_PIN_PD2 (PIN_BASE + 0x60 + 2) -#define AT91_PIN_PD3 (PIN_BASE + 0x60 + 3) -#define AT91_PIN_PD4 (PIN_BASE + 0x60 + 4) -#define AT91_PIN_PD5 (PIN_BASE + 0x60 + 5) -#define AT91_PIN_PD6 (PIN_BASE + 0x60 + 6) -#define AT91_PIN_PD7 (PIN_BASE + 0x60 + 7) -#define AT91_PIN_PD8 (PIN_BASE + 0x60 + 8) -#define AT91_PIN_PD9 (PIN_BASE + 0x60 + 9) -#define AT91_PIN_PD10 (PIN_BASE + 0x60 + 10) -#define AT91_PIN_PD11 (PIN_BASE + 0x60 + 11) -#define AT91_PIN_PD12 (PIN_BASE + 0x60 + 12) -#define AT91_PIN_PD13 (PIN_BASE + 0x60 + 13) -#define AT91_PIN_PD14 (PIN_BASE + 0x60 + 14) -#define AT91_PIN_PD15 (PIN_BASE + 0x60 + 15) -#define AT91_PIN_PD16 (PIN_BASE + 0x60 + 16) -#define AT91_PIN_PD17 (PIN_BASE + 0x60 + 17) -#define AT91_PIN_PD18 (PIN_BASE + 0x60 + 18) -#define AT91_PIN_PD19 (PIN_BASE + 0x60 + 19) -#define AT91_PIN_PD20 (PIN_BASE + 0x60 + 20) -#define AT91_PIN_PD21 (PIN_BASE + 0x60 + 21) -#define AT91_PIN_PD22 (PIN_BASE + 0x60 + 22) -#define AT91_PIN_PD23 (PIN_BASE + 0x60 + 23) -#define AT91_PIN_PD24 (PIN_BASE + 0x60 + 24) -#define AT91_PIN_PD25 (PIN_BASE + 0x60 + 25) -#define AT91_PIN_PD26 (PIN_BASE + 0x60 + 26) -#define AT91_PIN_PD27 (PIN_BASE + 0x60 + 27) -#define AT91_PIN_PD28 (PIN_BASE + 0x60 + 28) -#define AT91_PIN_PD29 (PIN_BASE + 0x60 + 29) -#define AT91_PIN_PD30 (PIN_BASE + 0x60 + 30) -#define AT91_PIN_PD31 (PIN_BASE + 0x60 + 31) - -#define AT91_PIN_PE0 (PIN_BASE + 0x80 + 0) -#define AT91_PIN_PE1 (PIN_BASE + 0x80 + 1) -#define AT91_PIN_PE2 (PIN_BASE + 0x80 + 2) -#define AT91_PIN_PE3 (PIN_BASE + 0x80 + 3) -#define AT91_PIN_PE4 (PIN_BASE + 0x80 + 4) -#define AT91_PIN_PE5 (PIN_BASE + 0x80 + 5) -#define AT91_PIN_PE6 (PIN_BASE + 0x80 + 6) -#define AT91_PIN_PE7 (PIN_BASE + 0x80 + 7) -#define AT91_PIN_PE8 (PIN_BASE + 0x80 + 8) -#define AT91_PIN_PE9 (PIN_BASE + 0x80 + 9) -#define AT91_PIN_PE10 (PIN_BASE + 0x80 + 10) -#define AT91_PIN_PE11 (PIN_BASE + 0x80 + 11) -#define AT91_PIN_PE12 (PIN_BASE + 0x80 + 12) -#define AT91_PIN_PE13 (PIN_BASE + 0x80 + 13) -#define AT91_PIN_PE14 (PIN_BASE + 0x80 + 14) -#define AT91_PIN_PE15 (PIN_BASE + 0x80 + 15) -#define AT91_PIN_PE16 (PIN_BASE + 0x80 + 16) -#define AT91_PIN_PE17 (PIN_BASE + 0x80 + 17) -#define AT91_PIN_PE18 (PIN_BASE + 0x80 + 18) -#define AT91_PIN_PE19 (PIN_BASE + 0x80 + 19) -#define AT91_PIN_PE20 (PIN_BASE + 0x80 + 20) -#define AT91_PIN_PE21 (PIN_BASE + 0x80 + 21) -#define AT91_PIN_PE22 (PIN_BASE + 0x80 + 22) -#define AT91_PIN_PE23 (PIN_BASE + 0x80 + 23) -#define AT91_PIN_PE24 (PIN_BASE + 0x80 + 24) -#define AT91_PIN_PE25 (PIN_BASE + 0x80 + 25) -#define AT91_PIN_PE26 (PIN_BASE + 0x80 + 26) -#define AT91_PIN_PE27 (PIN_BASE + 0x80 + 27) -#define AT91_PIN_PE28 (PIN_BASE + 0x80 + 28) -#define AT91_PIN_PE29 (PIN_BASE + 0x80 + 29) -#define AT91_PIN_PE30 (PIN_BASE + 0x80 + 30) -#define AT91_PIN_PE31 (PIN_BASE + 0x80 + 31) +#define AT91_PIN_PA0 (0x00 + 0) +#define AT91_PIN_PA1 (0x00 + 1) +#define AT91_PIN_PA2 (0x00 + 2) +#define AT91_PIN_PA3 (0x00 + 3) +#define AT91_PIN_PA4 (0x00 + 4) +#define AT91_PIN_PA5 (0x00 + 5) +#define AT91_PIN_PA6 (0x00 + 6) +#define AT91_PIN_PA7 (0x00 + 7) +#define AT91_PIN_PA8 (0x00 + 8) +#define AT91_PIN_PA9 (0x00 + 9) +#define AT91_PIN_PA10 (0x00 + 10) +#define AT91_PIN_PA11 (0x00 + 11) +#define AT91_PIN_PA12 (0x00 + 12) +#define AT91_PIN_PA13 (0x00 + 13) +#define AT91_PIN_PA14 (0x00 + 14) +#define AT91_PIN_PA15 (0x00 + 15) +#define AT91_PIN_PA16 (0x00 + 16) +#define AT91_PIN_PA17 (0x00 + 17) +#define AT91_PIN_PA18 (0x00 + 18) +#define AT91_PIN_PA19 (0x00 + 19) +#define AT91_PIN_PA20 (0x00 + 20) +#define AT91_PIN_PA21 (0x00 + 21) +#define AT91_PIN_PA22 (0x00 + 22) +#define AT91_PIN_PA23 (0x00 + 23) +#define AT91_PIN_PA24 (0x00 + 24) +#define AT91_PIN_PA25 (0x00 + 25) +#define AT91_PIN_PA26 (0x00 + 26) +#define AT91_PIN_PA27 (0x00 + 27) +#define AT91_PIN_PA28 (0x00 + 28) +#define AT91_PIN_PA29 (0x00 + 29) +#define AT91_PIN_PA30 (0x00 + 30) +#define AT91_PIN_PA31 (0x00 + 31) + +#define AT91_PIN_PB0 (0x20 + 0) +#define AT91_PIN_PB1 (0x20 + 1) +#define AT91_PIN_PB2 (0x20 + 2) +#define AT91_PIN_PB3 (0x20 + 3) +#define AT91_PIN_PB4 (0x20 + 4) +#define AT91_PIN_PB5 (0x20 + 5) +#define AT91_PIN_PB6 (0x20 + 6) +#define AT91_PIN_PB7 (0x20 + 7) +#define AT91_PIN_PB8 (0x20 + 8) +#define AT91_PIN_PB9 (0x20 + 9) +#define AT91_PIN_PB10 (0x20 + 10) +#define AT91_PIN_PB11 (0x20 + 11) +#define AT91_PIN_PB12 (0x20 + 12) +#define AT91_PIN_PB13 (0x20 + 13) +#define AT91_PIN_PB14 (0x20 + 14) +#define AT91_PIN_PB15 (0x20 + 15) +#define AT91_PIN_PB16 (0x20 + 16) +#define AT91_PIN_PB17 (0x20 + 17) +#define AT91_PIN_PB18 (0x20 + 18) +#define AT91_PIN_PB19 (0x20 + 19) +#define AT91_PIN_PB20 (0x20 + 20) +#define AT91_PIN_PB21 (0x20 + 21) +#define AT91_PIN_PB22 (0x20 + 22) +#define AT91_PIN_PB23 (0x20 + 23) +#define AT91_PIN_PB24 (0x20 + 24) +#define AT91_PIN_PB25 (0x20 + 25) +#define AT91_PIN_PB26 (0x20 + 26) +#define AT91_PIN_PB27 (0x20 + 27) +#define AT91_PIN_PB28 (0x20 + 28) +#define AT91_PIN_PB29 (0x20 + 29) +#define AT91_PIN_PB30 (0x20 + 30) +#define AT91_PIN_PB31 (0x20 + 31) + +#define AT91_PIN_PC0 (0x40 + 0) +#define AT91_PIN_PC1 (0x40 + 1) +#define AT91_PIN_PC2 (0x40 + 2) +#define AT91_PIN_PC3 (0x40 + 3) +#define AT91_PIN_PC4 (0x40 + 4) +#define AT91_PIN_PC5 (0x40 + 5) +#define AT91_PIN_PC6 (0x40 + 6) +#define AT91_PIN_PC7 (0x40 + 7) +#define AT91_PIN_PC8 (0x40 + 8) +#define AT91_PIN_PC9 (0x40 + 9) +#define AT91_PIN_PC10 (0x40 + 10) +#define AT91_PIN_PC11 (0x40 + 11) +#define AT91_PIN_PC12 (0x40 + 12) +#define AT91_PIN_PC13 (0x40 + 13) +#define AT91_PIN_PC14 (0x40 + 14) +#define AT91_PIN_PC15 (0x40 + 15) +#define AT91_PIN_PC16 (0x40 + 16) +#define AT91_PIN_PC17 (0x40 + 17) +#define AT91_PIN_PC18 (0x40 + 18) +#define AT91_PIN_PC19 (0x40 + 19) +#define AT91_PIN_PC20 (0x40 + 20) +#define AT91_PIN_PC21 (0x40 + 21) +#define AT91_PIN_PC22 (0x40 + 22) +#define AT91_PIN_PC23 (0x40 + 23) +#define AT91_PIN_PC24 (0x40 + 24) +#define AT91_PIN_PC25 (0x40 + 25) +#define AT91_PIN_PC26 (0x40 + 26) +#define AT91_PIN_PC27 (0x40 + 27) +#define AT91_PIN_PC28 (0x40 + 28) +#define AT91_PIN_PC29 (0x40 + 29) +#define AT91_PIN_PC30 (0x40 + 30) +#define AT91_PIN_PC31 (0x40 + 31) + +#define AT91_PIN_PD0 (0x60 + 0) +#define AT91_PIN_PD1 (0x60 + 1) +#define AT91_PIN_PD2 (0x60 + 2) +#define AT91_PIN_PD3 (0x60 + 3) +#define AT91_PIN_PD4 (0x60 + 4) +#define AT91_PIN_PD5 (0x60 + 5) +#define AT91_PIN_PD6 (0x60 + 6) +#define AT91_PIN_PD7 (0x60 + 7) +#define AT91_PIN_PD8 (0x60 + 8) +#define AT91_PIN_PD9 (0x60 + 9) +#define AT91_PIN_PD10 (0x60 + 10) +#define AT91_PIN_PD11 (0x60 + 11) +#define AT91_PIN_PD12 (0x60 + 12) +#define AT91_PIN_PD13 (0x60 + 13) +#define AT91_PIN_PD14 (0x60 + 14) +#define AT91_PIN_PD15 (0x60 + 15) +#define AT91_PIN_PD16 (0x60 + 16) +#define AT91_PIN_PD17 (0x60 + 17) +#define AT91_PIN_PD18 (0x60 + 18) +#define AT91_PIN_PD19 (0x60 + 19) +#define AT91_PIN_PD20 (0x60 + 20) +#define AT91_PIN_PD21 (0x60 + 21) +#define AT91_PIN_PD22 (0x60 + 22) +#define AT91_PIN_PD23 (0x60 + 23) +#define AT91_PIN_PD24 (0x60 + 24) +#define AT91_PIN_PD25 (0x60 + 25) +#define AT91_PIN_PD26 (0x60 + 26) +#define AT91_PIN_PD27 (0x60 + 27) +#define AT91_PIN_PD28 (0x60 + 28) +#define AT91_PIN_PD29 (0x60 + 29) +#define AT91_PIN_PD30 (0x60 + 30) +#define AT91_PIN_PD31 (0x60 + 31) + +#define AT91_PIN_PE0 (0x80 + 0) +#define AT91_PIN_PE1 (0x80 + 1) +#define AT91_PIN_PE2 (0x80 + 2) +#define AT91_PIN_PE3 (0x80 + 3) +#define AT91_PIN_PE4 (0x80 + 4) +#define AT91_PIN_PE5 (0x80 + 5) +#define AT91_PIN_PE6 (0x80 + 6) +#define AT91_PIN_PE7 (0x80 + 7) +#define AT91_PIN_PE8 (0x80 + 8) +#define AT91_PIN_PE9 (0x80 + 9) +#define AT91_PIN_PE10 (0x80 + 10) +#define AT91_PIN_PE11 (0x80 + 11) +#define AT91_PIN_PE12 (0x80 + 12) +#define AT91_PIN_PE13 (0x80 + 13) +#define AT91_PIN_PE14 (0x80 + 14) +#define AT91_PIN_PE15 (0x80 + 15) +#define AT91_PIN_PE16 (0x80 + 16) +#define AT91_PIN_PE17 (0x80 + 17) +#define AT91_PIN_PE18 (0x80 + 18) +#define AT91_PIN_PE19 (0x80 + 19) +#define AT91_PIN_PE20 (0x80 + 20) +#define AT91_PIN_PE21 (0x80 + 21) +#define AT91_PIN_PE22 (0x80 + 22) +#define AT91_PIN_PE23 (0x80 + 23) +#define AT91_PIN_PE24 (0x80 + 24) +#define AT91_PIN_PE25 (0x80 + 25) +#define AT91_PIN_PE26 (0x80 + 26) +#define AT91_PIN_PE27 (0x80 + 27) +#define AT91_PIN_PE28 (0x80 + 28) +#define AT91_PIN_PE29 (0x80 + 29) +#define AT91_PIN_PE30 (0x80 + 30) +#define AT91_PIN_PE31 (0x80 + 31) #ifndef __ASSEMBLY__ /* setup setup routines, called from board init or driver probe() */ @@ -215,8 +213,8 @@ extern void at91_gpio_resume(void); #include <asm/errno.h> -#define gpio_to_irq(gpio) (gpio) -#define irq_to_gpio(irq) (irq) +#define gpio_to_irq(gpio) (gpio + NR_AIC_IRQS) +#define irq_to_gpio(irq) (irq - NR_AIC_IRQS) #endif /* __ASSEMBLY__ */ diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h index 483478d8be6..2d0e4e99856 100644 --- a/arch/arm/mach-at91/include/mach/hardware.h +++ b/arch/arm/mach-at91/include/mach/hardware.h @@ -16,6 +16,12 @@ #include <asm/sizes.h> +/* DBGU base */ +/* rm9200, 9260/9g20, 9261/9g10, 9rl */ +#define AT91_BASE_DBGU0 0xfffff200 +/* 9263, 9g45, cap9 */ +#define AT91_BASE_DBGU1 0xffffee00 + #if defined(CONFIG_ARCH_AT91RM9200) #include <mach/at91rm9200.h> #elif defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9G20) @@ -52,6 +58,12 @@ #endif /* + * On all at91 have the Advanced Interrupt Controller starts at address + * 0xfffff000 + */ +#define AT91_AIC 0xfffff000 + +/* * Peripheral identifiers/interrupts. */ #define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ diff --git a/arch/arm/mach-at91/include/mach/irqs.h b/arch/arm/mach-at91/include/mach/irqs.h index 36bd55f3fc6..ac8b7dfc85e 100644 --- a/arch/arm/mach-at91/include/mach/irqs.h +++ b/arch/arm/mach-at91/include/mach/irqs.h @@ -31,7 +31,7 @@ * Acknowledge interrupt with AIC after interrupt has been handled. * (by kernel/irq.c) */ -#define irq_finish(irq) do { at91_sys_write(AT91_AIC_EOICR, 0); } while (0) +#define irq_finish(irq) do { at91_aic_write(AT91_AIC_EOICR, 0); } while (0) /* diff --git a/arch/arm/mach-at91/include/mach/timex.h b/arch/arm/mach-at91/include/mach/timex.h index 85820ad801c..5e917a66edd 100644 --- a/arch/arm/mach-at91/include/mach/timex.h +++ b/arch/arm/mach-at91/include/mach/timex.h @@ -23,70 +23,15 @@ #include <mach/hardware.h> -#if defined(CONFIG_ARCH_AT91RM9200) +#ifdef CONFIG_ARCH_AT91X40 -#define CLOCK_TICK_RATE (AT91_SLOW_CLOCK) - -#elif defined(CONFIG_ARCH_AT91SAM9260) - -#if defined(CONFIG_MACH_USB_A9260) || defined(CONFIG_MACH_QIL_A9260) -#define AT91SAM9_MASTER_CLOCK 90000000 -#else -#define AT91SAM9_MASTER_CLOCK 99300000 -#endif - -#define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16) - -#elif defined(CONFIG_ARCH_AT91SAM9261) - -#define AT91SAM9_MASTER_CLOCK 99300000 -#define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16) - -#elif defined(CONFIG_ARCH_AT91SAM9G10) - -#define AT91SAM9_MASTER_CLOCK 133000000 -#define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16) - -#elif defined(CONFIG_ARCH_AT91SAM9263) - -#if defined(CONFIG_MACH_USB_A9263) -#define AT91SAM9_MASTER_CLOCK 90000000 -#else -#define AT91SAM9_MASTER_CLOCK 99959500 -#endif - -#define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16) - -#elif defined(CONFIG_ARCH_AT91SAM9RL) - -#define AT91SAM9_MASTER_CLOCK 100000000 -#define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16) - -#elif defined(CONFIG_ARCH_AT91SAM9G20) +#define AT91X40_MASTER_CLOCK 40000000 +#define CLOCK_TICK_RATE (AT91X40_MASTER_CLOCK) -#if defined(CONFIG_MACH_USB_A9G20) -#define AT91SAM9_MASTER_CLOCK 133000000 #else -#define AT91SAM9_MASTER_CLOCK 132096000 -#endif - -#define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16) - -#elif defined(CONFIG_ARCH_AT91SAM9G45) -#define AT91SAM9_MASTER_CLOCK 133333333 -#define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16) - -#elif defined(CONFIG_ARCH_AT91CAP9) - -#define AT91CAP9_MASTER_CLOCK 100000000 -#define CLOCK_TICK_RATE (AT91CAP9_MASTER_CLOCK/16) - -#elif defined(CONFIG_ARCH_AT91X40) - -#define AT91X40_MASTER_CLOCK 40000000 -#define CLOCK_TICK_RATE (AT91X40_MASTER_CLOCK) +#define CLOCK_TICK_RATE 12345678 #endif -#endif +#endif /* __ASM_ARCH_TIMEX_H */ diff --git a/arch/arm/mach-at91/include/mach/uncompress.h b/arch/arm/mach-at91/include/mach/uncompress.h index 18bdcdeb474..0234fd9d20d 100644 --- a/arch/arm/mach-at91/include/mach/uncompress.h +++ b/arch/arm/mach-at91/include/mach/uncompress.h @@ -24,8 +24,10 @@ #include <linux/io.h> #include <linux/atmel_serial.h> -#if defined(CONFIG_AT91_EARLY_DBGU) -#define UART_OFFSET (AT91_DBGU + AT91_BASE_SYS) +#if defined(CONFIG_AT91_EARLY_DBGU0) +#define UART_OFFSET AT91_BASE_DBGU0 +#elif defined(CONFIG_AT91_EARLY_DBGU1) +#define UART_OFFSET AT91_BASE_DBGU1 #elif defined(CONFIG_AT91_EARLY_USART0) #define UART_OFFSET AT91_USART0 #elif defined(CONFIG_AT91_EARLY_USART1) diff --git a/arch/arm/mach-at91/irq.c b/arch/arm/mach-at91/irq.c index 9665265ec75..be6b639ecd7 100644 --- a/arch/arm/mach-at91/irq.c +++ b/arch/arm/mach-at91/irq.c @@ -33,17 +33,18 @@ #include <asm/mach/irq.h> #include <asm/mach/map.h> +void __iomem *at91_aic_base; static void at91_aic_mask_irq(struct irq_data *d) { /* Disable interrupt on AIC */ - at91_sys_write(AT91_AIC_IDCR, 1 << d->irq); + at91_aic_write(AT91_AIC_IDCR, 1 << d->irq); } static void at91_aic_unmask_irq(struct irq_data *d) { /* Enable interrupt on AIC */ - at91_sys_write(AT91_AIC_IECR, 1 << d->irq); + at91_aic_write(AT91_AIC_IECR, 1 << d->irq); } unsigned int at91_extern_irq; @@ -77,8 +78,8 @@ static int at91_aic_set_type(struct irq_data *d, unsigned type) return -EINVAL; } - smr = at91_sys_read(AT91_AIC_SMR(d->irq)) & ~AT91_AIC_SRCTYPE; - at91_sys_write(AT91_AIC_SMR(d->irq), smr | srctype); + smr = at91_aic_read(AT91_AIC_SMR(d->irq)) & ~AT91_AIC_SRCTYPE; + at91_aic_write(AT91_AIC_SMR(d->irq), smr | srctype); return 0; } @@ -102,15 +103,15 @@ static int at91_aic_set_wake(struct irq_data *d, unsigned value) void at91_irq_suspend(void) { - backups = at91_sys_read(AT91_AIC_IMR); - at91_sys_write(AT91_AIC_IDCR, backups); - at91_sys_write(AT91_AIC_IECR, wakeups); + backups = at91_aic_read(AT91_AIC_IMR); + at91_aic_write(AT91_AIC_IDCR, backups); + at91_aic_write(AT91_AIC_IECR, wakeups); } void at91_irq_resume(void) { - at91_sys_write(AT91_AIC_IDCR, wakeups); - at91_sys_write(AT91_AIC_IECR, backups); + at91_aic_write(AT91_AIC_IDCR, wakeups); + at91_aic_write(AT91_AIC_IECR, backups); } #else @@ -133,34 +134,39 @@ void __init at91_aic_init(unsigned int priority[NR_AIC_IRQS]) { unsigned int i; + at91_aic_base = ioremap(AT91_AIC, 512); + + if (!at91_aic_base) + panic("Impossible to ioremap AT91_AIC\n"); + /* * The IVR is used by macro get_irqnr_and_base to read and verify. * The irq number is NR_AIC_IRQS when a spurious interrupt has occurred. */ for (i = 0; i < NR_AIC_IRQS; i++) { /* Put irq number in Source Vector Register: */ - at91_sys_write(AT91_AIC_SVR(i), i); + at91_aic_write(AT91_AIC_SVR(i), i); /* Active Low interrupt, with the specified priority */ - at91_sys_write(AT91_AIC_SMR(i), AT91_AIC_SRCTYPE_LOW | priority[i]); + at91_aic_write(AT91_AIC_SMR(i), AT91_AIC_SRCTYPE_LOW | priority[i]); irq_set_chip_and_handler(i, &at91_aic_chip, handle_level_irq); set_irq_flags(i, IRQF_VALID | IRQF_PROBE); /* Perform 8 End Of Interrupt Command to make sure AIC will not Lock out nIRQ */ if (i < 8) - at91_sys_write(AT91_AIC_EOICR, 0); + at91_aic_write(AT91_AIC_EOICR, 0); } /* * Spurious Interrupt ID in Spurious Vector Register is NR_AIC_IRQS * When there is no current interrupt, the IRQ Vector Register reads the value stored in AIC_SPU */ - at91_sys_write(AT91_AIC_SPU, NR_AIC_IRQS); + at91_aic_write(AT91_AIC_SPU, NR_AIC_IRQS); /* No debugging in AIC: Debug (Protect) Control Register */ - at91_sys_write(AT91_AIC_DCR, 0); + at91_aic_write(AT91_AIC_DCR, 0); /* Disable and clear all interrupts initially */ - at91_sys_write(AT91_AIC_IDCR, 0xFFFFFFFF); - at91_sys_write(AT91_AIC_ICCR, 0xFFFFFFFF); + at91_aic_write(AT91_AIC_IDCR, 0xFFFFFFFF); + at91_aic_write(AT91_AIC_ICCR, 0xFFFFFFFF); } diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c index 7046158109d..62ad95556c3 100644 --- a/arch/arm/mach-at91/pm.c +++ b/arch/arm/mach-at91/pm.c @@ -34,7 +34,7 @@ /* * Show the reason for the previous system reset. */ -#if defined(AT91_SHDWC) +#if defined(AT91_RSTC) #include <mach/at91_rstc.h> #include <mach/at91_shdwc.h> @@ -58,8 +58,11 @@ static void __init show_reset_status(void) char *reason, *r2 = reset; u32 reset_type, wake_type; + if (!at91_shdwc_base) + return; + reset_type = at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_RSTTYP; - wake_type = at91_sys_read(AT91_SHDW_SR); + wake_type = at91_shdwc_read(AT91_SHDW_SR); switch (reset_type) { case AT91_RSTC_RSTTYP_GENERAL: @@ -215,7 +218,7 @@ static int at91_pm_enter(suspend_state_t state) | (1 << AT91_ID_FIQ) | (1 << AT91_ID_SYS) | (at91_extern_irq)) - & at91_sys_read(AT91_AIC_IMR), + & at91_aic_read(AT91_AIC_IMR), state); switch (state) { @@ -283,7 +286,7 @@ static int at91_pm_enter(suspend_state_t state) } pr_debug("AT91: PM - wakeup %08x\n", - at91_sys_read(AT91_AIC_IPR) & at91_sys_read(AT91_AIC_IMR)); + at91_aic_read(AT91_AIC_IPR) & at91_aic_read(AT91_AIC_IMR)); error: target_state = PM_SUSPEND_ON; diff --git a/arch/arm/mach-at91/sam9_smc.c b/arch/arm/mach-at91/sam9_smc.c index 5eab6aa621d..8294783b679 100644 --- a/arch/arm/mach-at91/sam9_smc.c +++ b/arch/arm/mach-at91/sam9_smc.c @@ -10,38 +10,58 @@ #include <linux/module.h> #include <linux/io.h> +#include <linux/of.h> +#include <linux/of_address.h> #include <mach/at91sam9_smc.h> #include "sam9_smc.h" -void __init sam9_smc_configure(int cs, struct sam9_smc_config* config) + +#define AT91_SMC_CS(id, n) (smc_base_addr[id] + ((n) * 0x10)) + +static void __iomem *smc_base_addr[2]; + +static void __init sam9_smc_cs_configure(void __iomem *base, struct sam9_smc_config* config) { + /* Setup register */ - at91_sys_write(AT91_SMC_SETUP(cs), - AT91_SMC_NWESETUP_(config->nwe_setup) - | AT91_SMC_NCS_WRSETUP_(config->ncs_write_setup) - | AT91_SMC_NRDSETUP_(config->nrd_setup) - | AT91_SMC_NCS_RDSETUP_(config->ncs_read_setup) - ); + __raw_writel(AT91_SMC_NWESETUP_(config->nwe_setup) + | AT91_SMC_NCS_WRSETUP_(config->ncs_write_setup) + | AT91_SMC_NRDSETUP_(config->nrd_setup) + | AT91_SMC_NCS_RDSETUP_(config->ncs_read_setup), + base + AT91_SMC_SETUP); /* Pulse register */ - at91_sys_write(AT91_SMC_PULSE(cs), - AT91_SMC_NWEPULSE_(config->nwe_pulse) - | AT91_SMC_NCS_WRPULSE_(config->ncs_write_pulse) - | AT91_SMC_NRDPULSE_(config->nrd_pulse) - | AT91_SMC_NCS_RDPULSE_(config->ncs_read_pulse) - ); + __raw_writel(AT91_SMC_NWEPULSE_(config->nwe_pulse) + | AT91_SMC_NCS_WRPULSE_(config->ncs_write_pulse) + | AT91_SMC_NRDPULSE_(config->nrd_pulse) + | AT91_SMC_NCS_RDPULSE_(config->ncs_read_pulse), + base + AT91_SMC_PULSE); /* Cycle register */ - at91_sys_write(AT91_SMC_CYCLE(cs), - AT91_SMC_NWECYCLE_(config->write_cycle) - | AT91_SMC_NRDCYCLE_(config->read_cycle) - ); + __raw_writel(AT91_SMC_NWECYCLE_(config->write_cycle) + | AT91_SMC_NRDCYCLE_(config->read_cycle), + base + AT91_SMC_CYCLE); /* Mode register */ - at91_sys_write(AT91_SMC_MODE(cs), - config->mode - | AT91_SMC_TDF_(config->tdf_cycles) - ); + __raw_writel(config->mode + | AT91_SMC_TDF_(config->tdf_cycles), + base + AT91_SMC_MODE); +} + +void __init sam9_smc_configure(int id, int cs, struct sam9_smc_config* config) +{ + sam9_smc_cs_configure(AT91_SMC_CS(id, cs), config); +} + +void __init at91sam9_ioremap_smc(int id, u32 addr) +{ + if (id > 1) { + pr_warn("%s: id > 2\n", __func__); + return; + } + smc_base_addr[id] = ioremap(addr, 512); + if (!smc_base_addr[id]) + pr_warn("Impossible to ioremap smc.%d 0x%x\n", id, addr); } diff --git a/arch/arm/mach-at91/sam9_smc.h b/arch/arm/mach-at91/sam9_smc.h index bf72cfb3455..039c5ce17ae 100644 --- a/arch/arm/mach-at91/sam9_smc.h +++ b/arch/arm/mach-at91/sam9_smc.h @@ -30,4 +30,5 @@ struct sam9_smc_config { u8 tdf_cycles:4; }; -extern void __init sam9_smc_configure(int cs, struct sam9_smc_config* config); +extern void __init sam9_smc_configure(int id, int cs, struct sam9_smc_config* config); +extern void __init at91sam9_ioremap_smc(int id, u32 addr); diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c index cf98a8f94dc..8bdcc3cb601 100644 --- a/arch/arm/mach-at91/setup.c +++ b/arch/arm/mach-at91/setup.c @@ -8,6 +8,7 @@ #include <linux/module.h> #include <linux/io.h> #include <linux/mm.h> +#include <linux/pm.h> #include <asm/mach/map.h> @@ -15,6 +16,7 @@ #include <mach/cpu.h> #include <mach/at91_dbgu.h> #include <mach/at91_pmc.h> +#include <mach/at91_shdwc.h> #include "soc.h" #include "generic.h" @@ -73,9 +75,6 @@ static struct map_desc at91_io_desc __initdata = { .type = MT_DEVICE, }; -#define AT91_DBGU0 0xfffff200 -#define AT91_DBGU1 0xffffee00 - static void __init soc_detect(u32 dbgu_base) { u32 cidr, socid; @@ -248,9 +247,9 @@ void __init at91_map_io(void) at91_soc_initdata.type = AT91_SOC_NONE; at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE; - soc_detect(AT91_DBGU0); + soc_detect(AT91_BASE_DBGU0); if (!at91_soc_is_detected()) - soc_detect(AT91_DBGU1); + soc_detect(AT91_BASE_DBGU1); if (!at91_soc_is_detected()) panic("AT91: Impossible to detect the SOC type"); @@ -267,8 +266,25 @@ void __init at91_map_io(void) at91_boot_soc.map_io(); } +void __iomem *at91_shdwc_base = NULL; + +static void at91sam9_poweroff(void) +{ + at91_shdwc_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW); +} + +void __init at91_ioremap_shdwc(u32 base_addr) +{ + at91_shdwc_base = ioremap(base_addr, 16); + if (!at91_shdwc_base) + panic("Impossible to ioremap at91_shdwc_base\n"); + pm_power_off = at91sam9_poweroff; +} + void __init at91_initialize(unsigned long main_clock) { + at91_boot_soc.ioremap_registers(); + /* Init clock subsystem */ at91_clock_init(main_clock); diff --git a/arch/arm/mach-at91/soc.h b/arch/arm/mach-at91/soc.h index 21ed8816e6f..4588ae6f7ac 100644 --- a/arch/arm/mach-at91/soc.h +++ b/arch/arm/mach-at91/soc.h @@ -7,6 +7,7 @@ struct at91_init_soc { unsigned int *default_irq_priority; void (*map_io)(void); + void (*ioremap_registers)(void); void (*register_clocks)(void); void (*init)(void); }; diff --git a/arch/arm/mach-bcmring/core.c b/arch/arm/mach-bcmring/core.c index 430da120a29..6b67b7e8426 100644 --- a/arch/arm/mach-bcmring/core.c +++ b/arch/arm/mach-bcmring/core.c @@ -25,7 +25,6 @@ #include <linux/device.h> #include <linux/dma-mapping.h> #include <linux/platform_device.h> -#include <linux/sysdev.h> #include <linux/interrupt.h> #include <linux/amba/bus.h> #include <linux/clkdev.h> diff --git a/arch/arm/mach-cns3xxx/pcie.c b/arch/arm/mach-cns3xxx/pcie.c index 0f8fca48a5e..e159d69967c 100644 --- a/arch/arm/mach-cns3xxx/pcie.c +++ b/arch/arm/mach-cns3xxx/pcie.c @@ -151,13 +151,12 @@ static int cns3xxx_pci_setup(int nr, struct pci_sys_data *sys) struct cns3xxx_pcie *cnspci = sysdata_to_cnspci(sys); struct resource *res_io = &cnspci->res_io; struct resource *res_mem = &cnspci->res_mem; - struct resource **sysres = sys->resource; BUG_ON(request_resource(&iomem_resource, res_io) || request_resource(&iomem_resource, res_mem)); - sysres[0] = res_io; - sysres[1] = res_mem; + pci_add_resource(&sys->resources, res_io); + pci_add_resource(&sys->resources, res_mem); return 1; } @@ -169,7 +168,8 @@ static struct pci_ops cns3xxx_pcie_ops = { static struct pci_bus *cns3xxx_pci_scan_bus(int nr, struct pci_sys_data *sys) { - return pci_scan_bus(sys->busnr, &cns3xxx_pcie_ops, sys); + return pci_scan_root_bus(NULL, sys->busnr, &cns3xxx_pcie_ops, sys, + &sys->resources); } static int cns3xxx_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c index f8a682f60a4..6b22b543a83 100644 --- a/arch/arm/mach-davinci/board-da850-evm.c +++ b/arch/arm/mach-davinci/board-da850-evm.c @@ -127,7 +127,7 @@ static void da850_evm_m25p80_notify_add(struct mtd_info *mtd) size_t retlen; if (!strcmp(mtd->name, "MAC-Address")) { - mtd->read(mtd, 0, ETH_ALEN, &retlen, mac_addr); + mtd_read(mtd, 0, ETH_ALEN, &retlen, mac_addr); if (retlen == ETH_ALEN) pr_info("Read MAC addr from SPI Flash: %pM\n", mac_addr); diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c index 00861139101..008772e3b84 100644 --- a/arch/arm/mach-davinci/clock.c +++ b/arch/arm/mach-davinci/clock.c @@ -31,19 +31,12 @@ static LIST_HEAD(clocks); static DEFINE_MUTEX(clocks_mutex); static DEFINE_SPINLOCK(clockfw_lock); -static unsigned psc_domain(struct clk *clk) -{ - return (clk->flags & PSC_DSP) - ? DAVINCI_GPSC_DSPDOMAIN - : DAVINCI_GPSC_ARMDOMAIN; -} - static void __clk_enable(struct clk *clk) { if (clk->parent) __clk_enable(clk->parent); if (clk->usecount++ == 0 && (clk->flags & CLK_PSC)) - davinci_psc_config(psc_domain(clk), clk->gpsc, clk->lpsc, + davinci_psc_config(clk->domain, clk->gpsc, clk->lpsc, true, clk->flags); } @@ -53,7 +46,7 @@ static void __clk_disable(struct clk *clk) return; if (--clk->usecount == 0 && !(clk->flags & CLK_PLL) && (clk->flags & CLK_PSC)) - davinci_psc_config(psc_domain(clk), clk->gpsc, clk->lpsc, + davinci_psc_config(clk->domain, clk->gpsc, clk->lpsc, false, clk->flags); if (clk->parent) __clk_disable(clk->parent); @@ -237,7 +230,7 @@ static int __init clk_disable_unused(void) pr_debug("Clocks: disable unused %s\n", ck->name); - davinci_psc_config(psc_domain(ck), ck->gpsc, ck->lpsc, + davinci_psc_config(ck->domain, ck->gpsc, ck->lpsc, false, ck->flags); } spin_unlock_irq(&clockfw_lock); diff --git a/arch/arm/mach-davinci/clock.h b/arch/arm/mach-davinci/clock.h index a705f367a84..46f0f1bf1a4 100644 --- a/arch/arm/mach-davinci/clock.h +++ b/arch/arm/mach-davinci/clock.h @@ -93,6 +93,7 @@ struct clk { u8 usecount; u8 lpsc; u8 gpsc; + u8 domain; u32 flags; struct clk *parent; struct list_head children; /* list of children */ @@ -107,11 +108,10 @@ struct clk { /* Clock flags: SoC-specific flags start at BIT(16) */ #define ALWAYS_ENABLED BIT(1) #define CLK_PSC BIT(2) -#define PSC_DSP BIT(3) /* PSC uses DSP domain, not ARM */ -#define CLK_PLL BIT(4) /* PLL-derived clock */ -#define PRE_PLL BIT(5) /* source is before PLL mult/div */ -#define PSC_SWRSTDISABLE BIT(6) /* Disable state is SwRstDisable */ -#define PSC_FORCE BIT(7) /* Force module state transtition */ +#define CLK_PLL BIT(3) /* PLL-derived clock */ +#define PRE_PLL BIT(4) /* source is before PLL mult/div */ +#define PSC_SWRSTDISABLE BIT(5) /* Disable state is SwRstDisable */ +#define PSC_FORCE BIT(6) /* Force module state transtition */ #define CLK(dev, con, ck) \ { \ diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c index 0800f9cf33b..43a48ee1917 100644 --- a/arch/arm/mach-davinci/dm644x.c +++ b/arch/arm/mach-davinci/dm644x.c @@ -130,7 +130,7 @@ static struct clk dsp_clk = { .name = "dsp", .parent = &pll1_sysclk1, .lpsc = DAVINCI_LPSC_GEM, - .flags = PSC_DSP, + .domain = DAVINCI_GPSC_DSPDOMAIN, .usecount = 1, /* REVISIT how to disable? */ }; @@ -145,7 +145,7 @@ static struct clk vicp_clk = { .name = "vicp", .parent = &pll1_sysclk2, .lpsc = DAVINCI_LPSC_IMCOP, - .flags = PSC_DSP, + .domain = DAVINCI_GPSC_DSPDOMAIN, .usecount = 1, /* REVISIT how to disable? */ }; diff --git a/arch/arm/mach-davinci/include/mach/dm646x.h b/arch/arm/mach-davinci/include/mach/dm646x.h index 2a00fe5ac25..a8ee6c9f0bb 100644 --- a/arch/arm/mach-davinci/include/mach/dm646x.h +++ b/arch/arm/mach-davinci/include/mach/dm646x.h @@ -16,6 +16,7 @@ #include <linux/i2c.h> #include <linux/videodev2.h> #include <linux/davinci_emac.h> +#include <media/davinci/vpif_types.h> #define DM646X_EMAC_BASE (0x01C80000) #define DM646X_EMAC_MDIO_BASE (DM646X_EMAC_BASE + 0x4000) @@ -34,58 +35,6 @@ int __init dm646x_init_edma(struct edma_rsv_info *rsv); void dm646x_video_init(void); -enum vpif_if_type { - VPIF_IF_BT656, - VPIF_IF_BT1120, - VPIF_IF_RAW_BAYER -}; - -struct vpif_interface { - enum vpif_if_type if_type; - unsigned hd_pol:1; - unsigned vd_pol:1; - unsigned fid_pol:1; -}; - -struct vpif_subdev_info { - const char *name; - struct i2c_board_info board_info; - u32 input; - u32 output; - unsigned can_route:1; - struct vpif_interface vpif_if; -}; - -struct vpif_display_config { - int (*set_clock)(int, int); - struct vpif_subdev_info *subdevinfo; - int subdev_count; - const char **output; - int output_count; - const char *card_name; -}; - -struct vpif_input { - struct v4l2_input input; - const char *subdev_name; -}; - -#define VPIF_CAPTURE_MAX_CHANNELS 2 - -struct vpif_capture_chan_config { - const struct vpif_input *inputs; - int input_count; -}; - -struct vpif_capture_config { - int (*setup_input_channel_mode)(int); - int (*setup_input_path)(int, const char *); - struct vpif_capture_chan_config chan_config[VPIF_CAPTURE_MAX_CHANNELS]; - struct vpif_subdev_info *subdev_info; - int subdev_count; - const char *card_name; -}; - void dm646x_setup_vpif(struct vpif_display_config *, struct vpif_capture_config *); diff --git a/arch/arm/mach-dove/addr-map.c b/arch/arm/mach-dove/addr-map.c index 00be4fc26dd..98b8c83b09a 100644 --- a/arch/arm/mach-dove/addr-map.c +++ b/arch/arm/mach-dove/addr-map.c @@ -14,6 +14,7 @@ #include <linux/io.h> #include <asm/mach/arch.h> #include <asm/setup.h> +#include <plat/addr-map.h> #include "common.h" /* @@ -34,98 +35,72 @@ #define ATTR_PCIE_MEM 0xe8 #define ATTR_SCRATCHPAD 0x0 -/* - * CPU Address Decode Windows registers - */ -#define WIN_CTRL(n) (BRIDGE_VIRT_BASE + ((n) << 4) + 0x0) -#define WIN_BASE(n) (BRIDGE_VIRT_BASE + ((n) << 4) + 0x4) -#define WIN_REMAP_LO(n) (BRIDGE_VIRT_BASE + ((n) << 4) + 0x8) -#define WIN_REMAP_HI(n) (BRIDGE_VIRT_BASE + ((n) << 4) + 0xc) - -struct mbus_dram_target_info dove_mbus_dram_info; - static inline void __iomem *ddr_map_sc(int i) { return (void __iomem *)(DOVE_MC_VIRT_BASE + 0x100 + ((i) << 4)); } -static int cpu_win_can_remap(int win) -{ - if (win < 4) - return 1; - - return 0; -} - -static void __init setup_cpu_win(int win, u32 base, u32 size, - u8 target, u8 attr, int remap) -{ - u32 ctrl; - - base &= 0xffff0000; - ctrl = ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1; - - writel(base, WIN_BASE(win)); - writel(ctrl, WIN_CTRL(win)); - if (cpu_win_can_remap(win)) { - if (remap < 0) - remap = base; - writel(remap & 0xffff0000, WIN_REMAP_LO(win)); - writel(0, WIN_REMAP_HI(win)); - } -} - -void __init dove_setup_cpu_mbus(void) -{ - int i; - int cs; +/* + * Description of the windows needed by the platform code + */ +static struct __initdata orion_addr_map_cfg addr_map_cfg = { + .num_wins = 8, + .remappable_wins = 4, + .bridge_virt_base = BRIDGE_VIRT_BASE, +}; +static const struct __initdata orion_addr_map_info addr_map_info[] = { /* - * First, disable and clear windows. + * Windows for PCIe IO+MEM space. */ - for (i = 0; i < 8; i++) { - writel(0, WIN_BASE(i)); - writel(0, WIN_CTRL(i)); - if (cpu_win_can_remap(i)) { - writel(0, WIN_REMAP_LO(i)); - writel(0, WIN_REMAP_HI(i)); - } - } - + { 0, DOVE_PCIE0_IO_PHYS_BASE, DOVE_PCIE0_IO_SIZE, + TARGET_PCIE0, ATTR_PCIE_IO, DOVE_PCIE0_IO_BUS_BASE + }, + { 1, DOVE_PCIE1_IO_PHYS_BASE, DOVE_PCIE1_IO_SIZE, + TARGET_PCIE1, ATTR_PCIE_IO, DOVE_PCIE1_IO_BUS_BASE + }, + { 2, DOVE_PCIE0_MEM_PHYS_BASE, DOVE_PCIE0_MEM_SIZE, + TARGET_PCIE0, ATTR_PCIE_MEM, -1 + }, + { 3, DOVE_PCIE1_MEM_PHYS_BASE, DOVE_PCIE1_MEM_SIZE, + TARGET_PCIE1, ATTR_PCIE_MEM, -1 + }, /* - * Setup windows for PCIe IO+MEM space. + * Window for CESA engine. */ - setup_cpu_win(0, DOVE_PCIE0_IO_PHYS_BASE, DOVE_PCIE0_IO_SIZE, - TARGET_PCIE0, ATTR_PCIE_IO, DOVE_PCIE0_IO_BUS_BASE); - setup_cpu_win(1, DOVE_PCIE1_IO_PHYS_BASE, DOVE_PCIE1_IO_SIZE, - TARGET_PCIE1, ATTR_PCIE_IO, DOVE_PCIE1_IO_BUS_BASE); - setup_cpu_win(2, DOVE_PCIE0_MEM_PHYS_BASE, DOVE_PCIE0_MEM_SIZE, - TARGET_PCIE0, ATTR_PCIE_MEM, -1); - setup_cpu_win(3, DOVE_PCIE1_MEM_PHYS_BASE, DOVE_PCIE1_MEM_SIZE, - TARGET_PCIE1, ATTR_PCIE_MEM, -1); - + { 4, DOVE_CESA_PHYS_BASE, DOVE_CESA_SIZE, + TARGET_CESA, ATTR_CESA, -1 + }, /* - * Setup window for CESA engine. + * Window to the BootROM for Standby and Sleep Resume */ - setup_cpu_win(4, DOVE_CESA_PHYS_BASE, DOVE_CESA_SIZE, - TARGET_CESA, ATTR_CESA, -1); - + { 5, DOVE_BOOTROM_PHYS_BASE, DOVE_BOOTROM_SIZE, + TARGET_BOOTROM, ATTR_BOOTROM, -1 + }, /* - * Setup the Window to the BootROM for Standby and Sleep Resume + * Window to the PMU Scratch Pad space */ - setup_cpu_win(5, DOVE_BOOTROM_PHYS_BASE, DOVE_BOOTROM_SIZE, - TARGET_BOOTROM, ATTR_BOOTROM, -1); + { 6, DOVE_SCRATCHPAD_PHYS_BASE, DOVE_SCRATCHPAD_SIZE, + TARGET_SCRATCHPAD, ATTR_SCRATCHPAD, -1 + }, + /* End marker */ + { -1, 0, 0, 0, 0, 0 } +}; + +void __init dove_setup_cpu_mbus(void) +{ + int i; + int cs; /* - * Setup the Window to the PMU Scratch Pad space + * Disable, clear and configure windows. */ - setup_cpu_win(6, DOVE_SCRATCHPAD_PHYS_BASE, DOVE_SCRATCHPAD_SIZE, - TARGET_SCRATCHPAD, ATTR_SCRATCHPAD, -1); + orion_config_wins(&addr_map_cfg, addr_map_info); /* * Setup MBUS dram target info. */ - dove_mbus_dram_info.mbus_dram_target_id = TARGET_DDR; + orion_mbus_dram_info.mbus_dram_target_id = TARGET_DDR; for (i = 0, cs = 0; i < 2; i++) { u32 map = readl(ddr_map_sc(i)); @@ -136,7 +111,7 @@ void __init dove_setup_cpu_mbus(void) if (map & 1) { struct mbus_dram_window *w; - w = &dove_mbus_dram_info.cs[cs++]; + w = &orion_mbus_dram_info.cs[cs++]; w->cs_index = i; w->mbus_attr = 0; /* CS address decoding done inside */ /* the DDR controller, no need to */ @@ -145,5 +120,5 @@ void __init dove_setup_cpu_mbus(void) w->size = 0x100000 << (((map & 0x000f0000) >> 16) - 4); } } - dove_mbus_dram_info.num_cs = cs; + orion_mbus_dram_info.num_cs = cs; } diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c index 13bb236cd0c..dd1429ae640 100644 --- a/arch/arm/mach-dove/common.c +++ b/arch/arm/mach-dove/common.c @@ -14,7 +14,6 @@ #include <linux/platform_device.h> #include <linux/pci.h> #include <linux/clk.h> -#include <linux/mbus.h> #include <linux/ata_platform.h> #include <linux/gpio.h> #include <asm/page.h> @@ -30,6 +29,7 @@ #include <linux/irq.h> #include <plat/time.h> #include <plat/common.h> +#include <plat/addr-map.h> #include "common.h" static int get_tclk(void); @@ -71,8 +71,7 @@ void __init dove_map_io(void) ****************************************************************************/ void __init dove_ehci0_init(void) { - orion_ehci_init(&dove_mbus_dram_info, - DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0); + orion_ehci_init(DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0); } /***************************************************************************** @@ -80,8 +79,7 @@ void __init dove_ehci0_init(void) ****************************************************************************/ void __init dove_ehci1_init(void) { - orion_ehci_1_init(&dove_mbus_dram_info, - DOVE_USB1_PHYS_BASE, IRQ_DOVE_USB1); + orion_ehci_1_init(DOVE_USB1_PHYS_BASE, IRQ_DOVE_USB1); } /***************************************************************************** @@ -89,7 +87,7 @@ void __init dove_ehci1_init(void) ****************************************************************************/ void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data) { - orion_ge00_init(eth_data, &dove_mbus_dram_info, + orion_ge00_init(eth_data, DOVE_GE00_PHYS_BASE, IRQ_DOVE_GE00_SUM, 0, get_tclk()); } @@ -107,8 +105,7 @@ void __init dove_rtc_init(void) ****************************************************************************/ void __init dove_sata_init(struct mv_sata_platform_data *sata_data) { - orion_sata_init(sata_data, &dove_mbus_dram_info, - DOVE_SATA_PHYS_BASE, IRQ_DOVE_SATA); + orion_sata_init(sata_data, DOVE_SATA_PHYS_BASE, IRQ_DOVE_SATA); } @@ -198,8 +195,7 @@ struct sys_timer dove_timer = { ****************************************************************************/ void __init dove_xor0_init(void) { - orion_xor0_init(&dove_mbus_dram_info, - DOVE_XOR0_PHYS_BASE, DOVE_XOR0_HIGH_PHYS_BASE, + orion_xor0_init(DOVE_XOR0_PHYS_BASE, DOVE_XOR0_HIGH_PHYS_BASE, IRQ_DOVE_XOR_00, IRQ_DOVE_XOR_01); } diff --git a/arch/arm/mach-dove/common.h b/arch/arm/mach-dove/common.h index 42027305c10..6432a3ba864 100644 --- a/arch/arm/mach-dove/common.h +++ b/arch/arm/mach-dove/common.h @@ -15,7 +15,6 @@ struct mv643xx_eth_platform_data; struct mv_sata_platform_data; extern struct sys_timer dove_timer; -extern struct mbus_dram_target_info dove_mbus_dram_info; /* * Basic Dove init functions used early by machine-setup. diff --git a/arch/arm/mach-dove/pcie.c b/arch/arm/mach-dove/pcie.c index aa2b3a09a51..52e96d397ba 100644 --- a/arch/arm/mach-dove/pcie.c +++ b/arch/arm/mach-dove/pcie.c @@ -10,7 +10,6 @@ #include <linux/kernel.h> #include <linux/pci.h> -#include <linux/mbus.h> #include <video/vga.h> #include <asm/mach/pci.h> #include <asm/mach/arch.h> @@ -19,6 +18,7 @@ #include <plat/pcie.h> #include <mach/irqs.h> #include <mach/bridge-regs.h> +#include <plat/addr-map.h> #include "common.h" struct pcie_port { @@ -50,7 +50,7 @@ static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys) */ orion_pcie_set_local_bus_nr(pp->base, sys->busnr); - orion_pcie_setup(pp->base, &dove_mbus_dram_info); + orion_pcie_setup(pp->base); /* * IORESOURCE_IO @@ -69,7 +69,7 @@ static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys) pp->res[0].flags = IORESOURCE_IO; if (request_resource(&ioport_resource, &pp->res[0])) panic("Request PCIe IO resource failed\n"); - sys->resource[0] = &pp->res[0]; + pci_add_resource(&sys->resources, &pp->res[0]); /* * IORESOURCE_MEM @@ -88,9 +88,7 @@ static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys) pp->res[1].flags = IORESOURCE_MEM; if (request_resource(&iomem_resource, &pp->res[1])) panic("Request PCIe Memory resource failed\n"); - sys->resource[1] = &pp->res[1]; - - sys->resource[2] = NULL; + pci_add_resource(&sys->resources, &pp->res[1]); return 1; } @@ -184,7 +182,8 @@ dove_pcie_scan_bus(int nr, struct pci_sys_data *sys) struct pci_bus *bus; if (nr < num_pcie_ports) { - bus = pci_scan_bus(sys->busnr, &pcie_ops, sys); + bus = pci_scan_root_bus(NULL, sys->busnr, &pcie_ops, sys, + &sys->resources); } else { bus = NULL; BUG(); diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index e1efbca2a53..5d602f68a0e 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -59,6 +59,11 @@ config EXYNOS4_MCT help Use MCT (Multi Core Timer) as kernel timers +config EXYNOS4_DEV_DMA + bool + help + Compile in amba device definitions for DMA controller + config EXYNOS4_DEV_AHCI bool help @@ -84,6 +89,11 @@ config EXYNOS4_DEV_DWMCI help Compile in platform device definitions for DWMCI +config EXYNOS4_DEV_USB_OHCI + bool + help + Compile in platform device definition for USB OHCI + config EXYNOS4_SETUP_I2C1 bool help @@ -145,6 +155,11 @@ config EXYNOS4_SETUP_USB_PHY help Common setup code for USB PHY controller +config EXYNOS4_SETUP_SPI + bool + help + Common setup code for SPI GPIO configurations. + # machine support if ARCH_EXYNOS4 @@ -179,8 +194,10 @@ config MACH_SMDKV310 select SAMSUNG_DEV_BACKLIGHT select EXYNOS4_DEV_AHCI select SAMSUNG_DEV_KEYPAD + select EXYNOS4_DEV_DMA select EXYNOS4_DEV_PD select SAMSUNG_DEV_PWM + select EXYNOS4_DEV_USB_OHCI select EXYNOS4_DEV_SYSMMU select EXYNOS4_SETUP_FIMD0 select EXYNOS4_SETUP_I2C1 @@ -199,6 +216,7 @@ config MACH_ARMLEX4210 select S3C_DEV_HSMMC2 select S3C_DEV_HSMMC3 select EXYNOS4_DEV_AHCI + select EXYNOS4_DEV_DMA select EXYNOS4_DEV_SYSMMU select EXYNOS4_SETUP_SDHCI help @@ -224,6 +242,7 @@ config MACH_UNIVERSAL_C210 select S5P_DEV_MFC select S5P_DEV_ONENAND select S5P_DEV_TV + select EXYNOS4_DEV_DMA select EXYNOS4_DEV_PD select EXYNOS4_SETUP_FIMD0 select EXYNOS4_SETUP_I2C1 @@ -257,6 +276,7 @@ config MACH_NURI select S5P_DEV_MFC select S5P_DEV_USB_EHCI select S5P_SETUP_MIPIPHY + select EXYNOS4_DEV_DMA select EXYNOS4_DEV_PD select EXYNOS4_SETUP_FIMC select EXYNOS4_SETUP_FIMD0 @@ -289,7 +309,9 @@ config MACH_ORIGEN select S5P_DEV_USB_EHCI select SAMSUNG_DEV_BACKLIGHT select SAMSUNG_DEV_PWM + select EXYNOS4_DEV_DMA select EXYNOS4_DEV_PD + select EXYNOS4_DEV_USB_OHCI select EXYNOS4_SETUP_FIMD0 select EXYNOS4_SETUP_SDHCI select EXYNOS4_SETUP_USB_PHY @@ -329,6 +351,20 @@ config MACH_SMDK4412 Machine support for Samsung SMDK4412 endif +comment "Flattened Device Tree based board for Exynos4 based SoC" + +config MACH_EXYNOS4_DT + bool "Samsung Exynos4 Machine using device tree" + select CPU_EXYNOS4210 + select USE_OF + select ARM_AMBA + select HAVE_SAMSUNG_KEYPAD if INPUT_KEYBOARD + help + Machine support for Samsung Exynos4 machine with device tree enabled. + Select this if a fdt blob is available for the Exynos4 SoC based board. + Note: This is under development and not all peripherals can be supported + with this machine file. + if ARCH_EXYNOS4 comment "Configuration for HSMMC 8-bit bus width" diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile index bcb9efc576e..5fc202cdfdb 100644 --- a/arch/arm/mach-exynos/Makefile +++ b/arch/arm/mach-exynos/Makefile @@ -19,7 +19,7 @@ obj-$(CONFIG_SOC_EXYNOS4212) += clock-exynos4212.o obj-$(CONFIG_PM) += pm.o obj-$(CONFIG_CPU_IDLE) += cpuidle.o -obj-$(CONFIG_ARCH_EXYNOS4) += dma.o pmu.o +obj-$(CONFIG_ARCH_EXYNOS4) += pmu.o obj-$(CONFIG_SMP) += platsmp.o headsmp.o @@ -39,6 +39,8 @@ obj-$(CONFIG_MACH_ORIGEN) += mach-origen.o obj-$(CONFIG_MACH_SMDK4212) += mach-smdk4x12.o obj-$(CONFIG_MACH_SMDK4412) += mach-smdk4x12.o +obj-$(CONFIG_MACH_EXYNOS4_DT) += mach-exynos4-dt.o + # device support obj-$(CONFIG_ARCH_EXYNOS4) += dev-audio.o @@ -46,6 +48,8 @@ obj-$(CONFIG_EXYNOS4_DEV_AHCI) += dev-ahci.o obj-$(CONFIG_EXYNOS4_DEV_PD) += dev-pd.o obj-$(CONFIG_EXYNOS4_DEV_SYSMMU) += dev-sysmmu.o obj-$(CONFIG_EXYNOS4_DEV_DWMCI) += dev-dwmci.o +obj-$(CONFIG_EXYNOS4_DEV_DMA) += dma.o +obj-$(CONFIG_EXYNOS4_DEV_USB_OHCI) += dev-ohci.o obj-$(CONFIG_ARCH_EXYNOS4) += setup-i2c0.o obj-$(CONFIG_EXYNOS4_SETUP_FIMC) += setup-fimc.o @@ -58,6 +62,6 @@ obj-$(CONFIG_EXYNOS4_SETUP_I2C5) += setup-i2c5.o obj-$(CONFIG_EXYNOS4_SETUP_I2C6) += setup-i2c6.o obj-$(CONFIG_EXYNOS4_SETUP_I2C7) += setup-i2c7.o obj-$(CONFIG_EXYNOS4_SETUP_KEYPAD) += setup-keypad.o -obj-$(CONFIG_EXYNOS4_SETUP_SDHCI) += setup-sdhci.o obj-$(CONFIG_EXYNOS4_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o obj-$(CONFIG_EXYNOS4_SETUP_USB_PHY) += setup-usb-phy.o +obj-$(CONFIG_EXYNOS4_SETUP_SPI) += setup-spi.o diff --git a/arch/arm/mach-exynos/clock.c b/arch/arm/mach-exynos/clock.c index 83616a039b1..5a8c42e9000 100644 --- a/arch/arm/mach-exynos/clock.c +++ b/arch/arm/mach-exynos/clock.c @@ -554,16 +554,6 @@ static struct clk init_clocks_off[] = { .enable = exynos4_clk_dac_ctrl, .ctrlbit = (1 << 0), }, { - .name = "dma", - .devname = "dma-pl330.0", - .enable = exynos4_clk_ip_fsys_ctrl, - .ctrlbit = (1 << 0), - }, { - .name = "dma", - .devname = "dma-pl330.1", - .enable = exynos4_clk_ip_fsys_ctrl, - .ctrlbit = (1 << 1), - }, { .name = "adc", .enable = exynos4_clk_ip_peril_ctrl, .ctrlbit = (1 << 15), @@ -779,6 +769,20 @@ static struct clk init_clocks[] = { } }; +static struct clk clk_pdma0 = { + .name = "dma", + .devname = "dma-pl330.0", + .enable = exynos4_clk_ip_fsys_ctrl, + .ctrlbit = (1 << 0), +}; + +static struct clk clk_pdma1 = { + .name = "dma", + .devname = "dma-pl330.1", + .enable = exynos4_clk_ip_fsys_ctrl, + .ctrlbit = (1 << 1), +}; + struct clk *clkset_group_list[] = { [0] = &clk_ext_xtal_mux, [1] = &clk_xusbxti, @@ -1010,46 +1014,6 @@ static struct clksrc_clk clk_dout_mmc4 = { static struct clksrc_clk clksrcs[] = { { - .clk = { - .name = "uclk1", - .devname = "s5pv210-uart.0", - .enable = exynos4_clksrc_mask_peril0_ctrl, - .ctrlbit = (1 << 0), - }, - .sources = &clkset_group, - .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 0, .size = 4 }, - .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 0, .size = 4 }, - }, { - .clk = { - .name = "uclk1", - .devname = "s5pv210-uart.1", - .enable = exynos4_clksrc_mask_peril0_ctrl, - .ctrlbit = (1 << 4), - }, - .sources = &clkset_group, - .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 4, .size = 4 }, - .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 4, .size = 4 }, - }, { - .clk = { - .name = "uclk1", - .devname = "s5pv210-uart.2", - .enable = exynos4_clksrc_mask_peril0_ctrl, - .ctrlbit = (1 << 8), - }, - .sources = &clkset_group, - .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 8, .size = 4 }, - .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 8, .size = 4 }, - }, { - .clk = { - .name = "uclk1", - .devname = "s5pv210-uart.3", - .enable = exynos4_clksrc_mask_peril0_ctrl, - .ctrlbit = (1 << 12), - }, - .sources = &clkset_group, - .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 12, .size = 4 }, - .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 12, .size = 4 }, - }, { .clk = { .name = "sclk_pwm", .enable = exynos4_clksrc_mask_peril0_ctrl, @@ -1148,36 +1112,6 @@ static struct clksrc_clk clksrcs[] = { .reg_div = { .reg = S5P_CLKDIV_LCD0, .shift = 0, .size = 4 }, }, { .clk = { - .name = "sclk_spi", - .devname = "s3c64xx-spi.0", - .enable = exynos4_clksrc_mask_peril1_ctrl, - .ctrlbit = (1 << 16), - }, - .sources = &clkset_group, - .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 16, .size = 4 }, - .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 0, .size = 4 }, - }, { - .clk = { - .name = "sclk_spi", - .devname = "s3c64xx-spi.1", - .enable = exynos4_clksrc_mask_peril1_ctrl, - .ctrlbit = (1 << 20), - }, - .sources = &clkset_group, - .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 20, .size = 4 }, - .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 16, .size = 4 }, - }, { - .clk = { - .name = "sclk_spi", - .devname = "s3c64xx-spi.2", - .enable = exynos4_clksrc_mask_peril1_ctrl, - .ctrlbit = (1 << 24), - }, - .sources = &clkset_group, - .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 24, .size = 4 }, - .reg_div = { .reg = S5P_CLKDIV_PERIL2, .shift = 0, .size = 4 }, - }, { - .clk = { .name = "sclk_fimg2d", }, .sources = &clkset_mout_g2d, @@ -1193,42 +1127,6 @@ static struct clksrc_clk clksrcs[] = { .reg_div = { .reg = S5P_CLKDIV_MFC, .shift = 0, .size = 4 }, }, { .clk = { - .name = "sclk_mmc", - .devname = "s3c-sdhci.0", - .parent = &clk_dout_mmc0.clk, - .enable = exynos4_clksrc_mask_fsys_ctrl, - .ctrlbit = (1 << 0), - }, - .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 }, - }, { - .clk = { - .name = "sclk_mmc", - .devname = "s3c-sdhci.1", - .parent = &clk_dout_mmc1.clk, - .enable = exynos4_clksrc_mask_fsys_ctrl, - .ctrlbit = (1 << 4), - }, - .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 }, - }, { - .clk = { - .name = "sclk_mmc", - .devname = "s3c-sdhci.2", - .parent = &clk_dout_mmc2.clk, - .enable = exynos4_clksrc_mask_fsys_ctrl, - .ctrlbit = (1 << 8), - }, - .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 }, - }, { - .clk = { - .name = "sclk_mmc", - .devname = "s3c-sdhci.3", - .parent = &clk_dout_mmc3.clk, - .enable = exynos4_clksrc_mask_fsys_ctrl, - .ctrlbit = (1 << 12), - }, - .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 }, - }, { - .clk = { .name = "sclk_dwmmc", .parent = &clk_dout_mmc4.clk, .enable = exynos4_clksrc_mask_fsys_ctrl, @@ -1238,6 +1136,134 @@ static struct clksrc_clk clksrcs[] = { } }; +static struct clksrc_clk clk_sclk_uart0 = { + .clk = { + .name = "uclk1", + .devname = "exynos4210-uart.0", + .enable = exynos4_clksrc_mask_peril0_ctrl, + .ctrlbit = (1 << 0), + }, + .sources = &clkset_group, + .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 0, .size = 4 }, + .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 0, .size = 4 }, +}; + +static struct clksrc_clk clk_sclk_uart1 = { + .clk = { + .name = "uclk1", + .devname = "exynos4210-uart.1", + .enable = exynos4_clksrc_mask_peril0_ctrl, + .ctrlbit = (1 << 4), + }, + .sources = &clkset_group, + .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 4, .size = 4 }, + .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 4, .size = 4 }, +}; + +static struct clksrc_clk clk_sclk_uart2 = { + .clk = { + .name = "uclk1", + .devname = "exynos4210-uart.2", + .enable = exynos4_clksrc_mask_peril0_ctrl, + .ctrlbit = (1 << 8), + }, + .sources = &clkset_group, + .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 8, .size = 4 }, + .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 8, .size = 4 }, +}; + +static struct clksrc_clk clk_sclk_uart3 = { + .clk = { + .name = "uclk1", + .devname = "exynos4210-uart.3", + .enable = exynos4_clksrc_mask_peril0_ctrl, + .ctrlbit = (1 << 12), + }, + .sources = &clkset_group, + .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 12, .size = 4 }, + .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 12, .size = 4 }, +}; + +static struct clksrc_clk clk_sclk_mmc0 = { + .clk = { + .name = "sclk_mmc", + .devname = "s3c-sdhci.0", + .parent = &clk_dout_mmc0.clk, + .enable = exynos4_clksrc_mask_fsys_ctrl, + .ctrlbit = (1 << 0), + }, + .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 }, +}; + +static struct clksrc_clk clk_sclk_mmc1 = { + .clk = { + .name = "sclk_mmc", + .devname = "s3c-sdhci.1", + .parent = &clk_dout_mmc1.clk, + .enable = exynos4_clksrc_mask_fsys_ctrl, + .ctrlbit = (1 << 4), + }, + .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 }, +}; + +static struct clksrc_clk clk_sclk_mmc2 = { + .clk = { + .name = "sclk_mmc", + .devname = "s3c-sdhci.2", + .parent = &clk_dout_mmc2.clk, + .enable = exynos4_clksrc_mask_fsys_ctrl, + .ctrlbit = (1 << 8), + }, + .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 }, +}; + +static struct clksrc_clk clk_sclk_mmc3 = { + .clk = { + .name = "sclk_mmc", + .devname = "s3c-sdhci.3", + .parent = &clk_dout_mmc3.clk, + .enable = exynos4_clksrc_mask_fsys_ctrl, + .ctrlbit = (1 << 12), + }, + .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 }, +}; + +static struct clksrc_clk clk_sclk_spi0 = { + .clk = { + .name = "sclk_spi", + .devname = "s3c64xx-spi.0", + .enable = exynos4_clksrc_mask_peril1_ctrl, + .ctrlbit = (1 << 16), + }, + .sources = &clkset_group, + .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 16, .size = 4 }, + .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 0, .size = 4 }, +}; + +static struct clksrc_clk clk_sclk_spi1 = { + .clk = { + .name = "sclk_spi", + .devname = "s3c64xx-spi.1", + .enable = exynos4_clksrc_mask_peril1_ctrl, + .ctrlbit = (1 << 20), + }, + .sources = &clkset_group, + .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 20, .size = 4 }, + .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 16, .size = 4 }, +}; + +static struct clksrc_clk clk_sclk_spi2 = { + .clk = { + .name = "sclk_spi", + .devname = "s3c64xx-spi.2", + .enable = exynos4_clksrc_mask_peril1_ctrl, + .ctrlbit = (1 << 24), + }, + .sources = &clkset_group, + .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 24, .size = 4 }, + .reg_div = { .reg = S5P_CLKDIV_PERIL2, .shift = 0, .size = 4 }, +}; + /* Clock initialization code */ static struct clksrc_clk *sysclks[] = { &clk_mout_apll, @@ -1272,6 +1298,42 @@ static struct clksrc_clk *sysclks[] = { &clk_mout_mfc1, }; +static struct clk *clk_cdev[] = { + &clk_pdma0, + &clk_pdma1, +}; + +static struct clksrc_clk *clksrc_cdev[] = { + &clk_sclk_uart0, + &clk_sclk_uart1, + &clk_sclk_uart2, + &clk_sclk_uart3, + &clk_sclk_mmc0, + &clk_sclk_mmc1, + &clk_sclk_mmc2, + &clk_sclk_mmc3, + &clk_sclk_spi0, + &clk_sclk_spi1, + &clk_sclk_spi2, + +}; + +static struct clk_lookup exynos4_clk_lookup[] = { + CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &clk_sclk_uart0.clk), + CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &clk_sclk_uart1.clk), + CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &clk_sclk_uart2.clk), + CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &clk_sclk_uart3.clk), + CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk), + CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk), + CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk), + CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &clk_sclk_mmc3.clk), + CLKDEV_INIT("dma-pl330.0", "apb_pclk", &clk_pdma0), + CLKDEV_INIT("dma-pl330.1", "apb_pclk", &clk_pdma1), + CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk0", &clk_sclk_spi0.clk), + CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk0", &clk_sclk_spi1.clk), + CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk0", &clk_sclk_spi2.clk), +}; + static int xtal_rate; static unsigned long exynos4_fout_apll_get_rate(struct clk *clk) @@ -1479,11 +1541,19 @@ void __init exynos4_register_clocks(void) for (ptr = 0; ptr < ARRAY_SIZE(sclk_tv); ptr++) s3c_register_clksrc(sclk_tv[ptr], 1); + for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++) + s3c_register_clksrc(clksrc_cdev[ptr], 1); + s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); + s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev)); + for (ptr = 0; ptr < ARRAY_SIZE(clk_cdev); ptr++) + s3c_disable_clocks(clk_cdev[ptr], 1); + s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); + clkdev_add_table(exynos4_clk_lookup, ARRAY_SIZE(exynos4_clk_lookup)); register_syscore_ops(&exynos4_clock_syscore_ops); s3c24xx_register_clock(&dummy_apb_pclk); diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c index d2acb0f948c..c59e1887100 100644 --- a/arch/arm/mach-exynos/common.c +++ b/arch/arm/mach-exynos/common.c @@ -13,12 +13,15 @@ #include <linux/interrupt.h> #include <linux/irq.h> #include <linux/io.h> -#include <linux/sysdev.h> +#include <linux/device.h> #include <linux/gpio.h> #include <linux/sched.h> #include <linux/serial_core.h> +#include <linux/of.h> +#include <linux/of_irq.h> #include <asm/proc-fns.h> +#include <asm/exception.h> #include <asm/hardware/cache-l2x0.h> #include <asm/hardware/gic.h> #include <asm/mach/map.h> @@ -43,8 +46,6 @@ #include "common.h" -unsigned int gic_bank_offset __read_mostly; - static const char name_exynos4210[] = "EXYNOS4210"; static const char name_exynos4212[] = "EXYNOS4212"; static const char name_exynos4412[] = "EXYNOS4412"; @@ -386,27 +387,26 @@ static void __init combiner_init(unsigned int combiner_nr, void __iomem *base, } } -static void exynos4_gic_irq_fix_base(struct irq_data *d) -{ - struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d); - - gic_data->cpu_base = S5P_VA_GIC_CPU + - (gic_bank_offset * smp_processor_id()); - - gic_data->dist_base = S5P_VA_GIC_DIST + - (gic_bank_offset * smp_processor_id()); -} +#ifdef CONFIG_OF +static const struct of_device_id exynos4_dt_irq_match[] = { + { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, }, + {}, +}; +#endif void __init exynos4_init_irq(void) { int irq; + unsigned int gic_bank_offset; gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000; - gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU); - gic_arch_extn.irq_eoi = exynos4_gic_irq_fix_base; - gic_arch_extn.irq_unmask = exynos4_gic_irq_fix_base; - gic_arch_extn.irq_mask = exynos4_gic_irq_fix_base; + if (!of_have_populated_dt()) + gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset); +#ifdef CONFIG_OF + else + of_irq_init(exynos4_dt_irq_match); +#endif for (irq = 0; irq < MAX_COMBINER_NR; irq++) { @@ -423,17 +423,18 @@ void __init exynos4_init_irq(void) s5p_init_irq(NULL, 0); } -struct sysdev_class exynos4_sysclass = { - .name = "exynos4-core", +struct bus_type exynos4_subsys = { + .name = "exynos4-core", + .dev_name = "exynos4-core", }; -static struct sys_device exynos4_sysdev = { - .cls = &exynos4_sysclass, +static struct device exynos4_dev = { + .bus = &exynos4_subsys, }; static int __init exynos4_core_init(void) { - return sysdev_class_register(&exynos4_sysclass); + return subsys_system_register(&exynos4_subsys, NULL); } core_initcall(exynos4_core_init); @@ -470,18 +471,9 @@ int __init exynos_init(void) /* set idle function */ pm_idle = exynos_idle; - return sysdev_register(&exynos4_sysdev); + return device_register(&exynos4_dev); } -static struct s3c24xx_uart_clksrc exynos4_serial_clocks[] = { - [0] = { - .name = "uclk1", - .divisor = 1, - .min_baud = 0, - .max_baud = 0, - }, -}; - /* uart registration process */ void __init exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no) @@ -489,16 +481,10 @@ void __init exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no) struct s3c2410_uartcfg *tcfg = cfg; u32 ucnt; - for (ucnt = 0; ucnt < no; ucnt++, tcfg++) { - if (!tcfg->clocks) { - tcfg->has_fracval = 1; - tcfg->clocks = exynos4_serial_clocks; - tcfg->clocks_size = ARRAY_SIZE(exynos4_serial_clocks); - } - tcfg->flags |= NO_NEED_CHECK_CLKSRC; - } + for (ucnt = 0; ucnt < no; ucnt++, tcfg++) + tcfg->has_fracval = 1; - s3c24xx_init_uartdevs("s5pv210-uart", s5p_uart_resources, cfg, no); + s3c24xx_init_uartdevs("exynos4210-uart", s5p_uart_resources, cfg, no); } static DEFINE_SPINLOCK(eint_lock); diff --git a/arch/arm/mach-exynos/dev-ohci.c b/arch/arm/mach-exynos/dev-ohci.c new file mode 100644 index 00000000000..b8e75300c77 --- /dev/null +++ b/arch/arm/mach-exynos/dev-ohci.c @@ -0,0 +1,52 @@ +/* linux/arch/arm/mach-exynos/dev-ohci.c + * + * Copyright (c) 2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * EXYNOS - OHCI support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/dma-mapping.h> +#include <linux/platform_device.h> + +#include <mach/irqs.h> +#include <mach/map.h> +#include <mach/ohci.h> + +#include <plat/devs.h> +#include <plat/usb-phy.h> + +static struct resource exynos4_ohci_resource[] = { + [0] = DEFINE_RES_MEM(EXYNOS4_PA_OHCI, SZ_256), + [1] = DEFINE_RES_IRQ(IRQ_USB_HOST), +}; + +static u64 exynos4_ohci_dma_mask = DMA_BIT_MASK(32); + +struct platform_device exynos4_device_ohci = { + .name = "exynos-ohci", + .id = -1, + .num_resources = ARRAY_SIZE(exynos4_ohci_resource), + .resource = exynos4_ohci_resource, + .dev = { + .dma_mask = &exynos4_ohci_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + } +}; + +void __init exynos4_ohci_set_platdata(struct exynos4_ohci_platdata *pd) +{ + struct exynos4_ohci_platdata *npd; + + npd = s3c_set_platdata(pd, sizeof(struct exynos4_ohci_platdata), + &exynos4_device_ohci); + + if (!npd->phy_init) + npd->phy_init = s5p_usb_phy_init; + if (!npd->phy_exit) + npd->phy_exit = s5p_usb_phy_exit; +} diff --git a/arch/arm/mach-exynos/dma.c b/arch/arm/mach-exynos/dma.c index 9667c61e64f..b10fcd270f0 100644 --- a/arch/arm/mach-exynos/dma.c +++ b/arch/arm/mach-exynos/dma.c @@ -24,6 +24,7 @@ #include <linux/dma-mapping.h> #include <linux/amba/bus.h> #include <linux/amba/pl330.h> +#include <linux/of.h> #include <asm/irq.h> #include <plat/devs.h> @@ -35,95 +36,42 @@ static u64 dma_dmamask = DMA_BIT_MASK(32); -struct dma_pl330_peri pdma0_peri[28] = { - { - .peri_id = (u8)DMACH_PCM0_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_PCM0_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_PCM2_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_PCM2_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_MSM_REQ0, - }, { - .peri_id = (u8)DMACH_MSM_REQ2, - }, { - .peri_id = (u8)DMACH_SPI0_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_SPI0_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_SPI2_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_SPI2_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_I2S0S_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_I2S0_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_I2S0_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_UART0_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_UART0_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_UART2_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_UART2_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_UART4_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_UART4_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_SLIMBUS0_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_SLIMBUS0_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_SLIMBUS2_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_SLIMBUS2_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_SLIMBUS4_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_SLIMBUS4_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_AC97_MICIN, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_AC97_PCMIN, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_AC97_PCMOUT, - .rqtype = MEMTODEV, - }, +u8 pdma0_peri[] = { + DMACH_PCM0_RX, + DMACH_PCM0_TX, + DMACH_PCM2_RX, + DMACH_PCM2_TX, + DMACH_MSM_REQ0, + DMACH_MSM_REQ2, + DMACH_SPI0_RX, + DMACH_SPI0_TX, + DMACH_SPI2_RX, + DMACH_SPI2_TX, + DMACH_I2S0S_TX, + DMACH_I2S0_RX, + DMACH_I2S0_TX, + DMACH_I2S2_RX, + DMACH_I2S2_TX, + DMACH_UART0_RX, + DMACH_UART0_TX, + DMACH_UART2_RX, + DMACH_UART2_TX, + DMACH_UART4_RX, + DMACH_UART4_TX, + DMACH_SLIMBUS0_RX, + DMACH_SLIMBUS0_TX, + DMACH_SLIMBUS2_RX, + DMACH_SLIMBUS2_TX, + DMACH_SLIMBUS4_RX, + DMACH_SLIMBUS4_TX, + DMACH_AC97_MICIN, + DMACH_AC97_PCMIN, + DMACH_AC97_PCMOUT, }; struct dma_pl330_platdata exynos4_pdma0_pdata = { .nr_valid_peri = ARRAY_SIZE(pdma0_peri), - .peri = pdma0_peri, + .peri_id = pdma0_peri, }; struct amba_device exynos4_device_pdma0 = { @@ -142,86 +90,37 @@ struct amba_device exynos4_device_pdma0 = { .periphid = 0x00041330, }; -struct dma_pl330_peri pdma1_peri[25] = { - { - .peri_id = (u8)DMACH_PCM0_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_PCM0_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_PCM1_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_PCM1_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_MSM_REQ1, - }, { - .peri_id = (u8)DMACH_MSM_REQ3, - }, { - .peri_id = (u8)DMACH_SPI1_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_SPI1_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_I2S0S_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_I2S0_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_I2S0_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_I2S1_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_I2S1_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_UART0_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_UART0_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_UART1_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_UART1_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_UART3_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_UART3_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_SLIMBUS1_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_SLIMBUS1_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_SLIMBUS3_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_SLIMBUS3_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_SLIMBUS5_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_SLIMBUS5_TX, - .rqtype = MEMTODEV, - }, +u8 pdma1_peri[] = { + DMACH_PCM0_RX, + DMACH_PCM0_TX, + DMACH_PCM1_RX, + DMACH_PCM1_TX, + DMACH_MSM_REQ1, + DMACH_MSM_REQ3, + DMACH_SPI1_RX, + DMACH_SPI1_TX, + DMACH_I2S0S_TX, + DMACH_I2S0_RX, + DMACH_I2S0_TX, + DMACH_I2S1_RX, + DMACH_I2S1_TX, + DMACH_UART0_RX, + DMACH_UART0_TX, + DMACH_UART1_RX, + DMACH_UART1_TX, + DMACH_UART3_RX, + DMACH_UART3_TX, + DMACH_SLIMBUS1_RX, + DMACH_SLIMBUS1_TX, + DMACH_SLIMBUS3_RX, + DMACH_SLIMBUS3_TX, + DMACH_SLIMBUS5_RX, + DMACH_SLIMBUS5_TX, }; struct dma_pl330_platdata exynos4_pdma1_pdata = { .nr_valid_peri = ARRAY_SIZE(pdma1_peri), - .peri = pdma1_peri, + .peri_id = pdma1_peri, }; struct amba_device exynos4_device_pdma1 = { @@ -242,7 +141,15 @@ struct amba_device exynos4_device_pdma1 = { static int __init exynos4_dma_init(void) { + if (of_have_populated_dt()) + return 0; + + dma_cap_set(DMA_SLAVE, exynos4_pdma0_pdata.cap_mask); + dma_cap_set(DMA_CYCLIC, exynos4_pdma0_pdata.cap_mask); amba_device_register(&exynos4_device_pdma0, &iomem_resource); + + dma_cap_set(DMA_SLAVE, exynos4_pdma1_pdata.cap_mask); + dma_cap_set(DMA_CYCLIC, exynos4_pdma1_pdata.cap_mask); amba_device_register(&exynos4_device_pdma1, &iomem_resource); return 0; diff --git a/arch/arm/mach-exynos/include/mach/cpufreq.h b/arch/arm/mach-exynos/include/mach/cpufreq.h new file mode 100644 index 00000000000..3df27f2d503 --- /dev/null +++ b/arch/arm/mach-exynos/include/mach/cpufreq.h @@ -0,0 +1,34 @@ +/* linux/arch/arm/mach-exynos/include/mach/cpufreq.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * EXYNOS - CPUFreq support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +enum cpufreq_level_index { + L0, L1, L2, L3, L4, + L5, L6, L7, L8, L9, + L10, L11, L12, L13, L14, + L15, L16, L17, L18, L19, + L20, +}; + +struct exynos_dvfs_info { + unsigned long mpll_freq_khz; + unsigned int pll_safe_idx; + unsigned int pm_lock_idx; + unsigned int max_support_idx; + unsigned int min_support_idx; + struct clk *cpu_clk; + unsigned int *volt_table; + struct cpufreq_frequency_table *freq_table; + void (*set_freq)(unsigned int, unsigned int); + bool (*need_apll_change)(unsigned int, unsigned int); +}; + +extern int exynos4210_cpufreq_init(struct exynos_dvfs_info *); diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h index dfd4b7eecb9..f77bce04789 100644 --- a/arch/arm/mach-exynos/include/mach/irqs.h +++ b/arch/arm/mach-exynos/include/mach/irqs.h @@ -17,13 +17,13 @@ /* PPI: Private Peripheral Interrupt */ -#define IRQ_PPI(x) S5P_IRQ(x+16) +#define IRQ_PPI(x) (x+16) #define IRQ_MCT_LOCALTIMER IRQ_PPI(12) /* SPI: Shared Peripheral Interrupt */ -#define IRQ_SPI(x) S5P_IRQ(x+32) +#define IRQ_SPI(x) (x+32) #define IRQ_EINT0 IRQ_SPI(16) #define IRQ_EINT1 IRQ_SPI(17) @@ -72,6 +72,9 @@ #define IRQ_IIC5 IRQ_SPI(63) #define IRQ_IIC6 IRQ_SPI(64) #define IRQ_IIC7 IRQ_SPI(65) +#define IRQ_SPI0 IRQ_SPI(66) +#define IRQ_SPI1 IRQ_SPI(67) +#define IRQ_SPI2 IRQ_SPI(68) #define IRQ_USB_HOST IRQ_SPI(70) #define IRQ_USB_HSOTG IRQ_SPI(71) @@ -163,7 +166,9 @@ #define IRQ_GPIO2_NR_GROUPS 9 #define IRQ_GPIO_END (S5P_GPIOINT_BASE + S5P_GPIOINT_COUNT) +#define IRQ_TIMER_BASE (IRQ_GPIO_END + 64) + /* Set the default NR_IRQS */ -#define NR_IRQS (IRQ_GPIO_END + 64) +#define NR_IRQS (IRQ_TIMER_BASE + IRQ_TIMER_COUNT) #endif /* __ASM_ARCH_IRQS_H */ diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h index d1829860a0e..c754a22a2bb 100644 --- a/arch/arm/mach-exynos/include/mach/map.h +++ b/arch/arm/mach-exynos/include/mach/map.h @@ -87,6 +87,10 @@ #define EXYNOS4_PA_SYSMMU_TV 0x12E20000 #define EXYNOS4_PA_SYSMMU_MFC_L 0x13620000 #define EXYNOS4_PA_SYSMMU_MFC_R 0x13630000 +#define EXYNOS4_PA_SPI0 0x13920000 +#define EXYNOS4_PA_SPI1 0x13930000 +#define EXYNOS4_PA_SPI2 0x13940000 + #define EXYNOS4_PA_GPIO1 0x11400000 #define EXYNOS4_PA_GPIO2 0x11000000 @@ -107,6 +111,7 @@ #define EXYNOS4_PA_SROMC 0x12570000 #define EXYNOS4_PA_EHCI 0x12580000 +#define EXYNOS4_PA_OHCI 0x12590000 #define EXYNOS4_PA_HSPHY 0x125B0000 #define EXYNOS4_PA_MFC 0x13400000 @@ -148,6 +153,9 @@ #define S3C_PA_RTC EXYNOS4_PA_RTC #define S3C_PA_WDT EXYNOS4_PA_WATCHDOG #define S3C_PA_UART EXYNOS4_PA_UART +#define S3C_PA_SPI0 EXYNOS4_PA_SPI0 +#define S3C_PA_SPI1 EXYNOS4_PA_SPI1 +#define S3C_PA_SPI2 EXYNOS4_PA_SPI2 #define S5P_PA_EHCI EXYNOS4_PA_EHCI #define S5P_PA_FIMC0 EXYNOS4_PA_FIMC0 diff --git a/arch/arm/mach-exynos/include/mach/ohci.h b/arch/arm/mach-exynos/include/mach/ohci.h new file mode 100644 index 00000000000..c256c595be5 --- /dev/null +++ b/arch/arm/mach-exynos/include/mach/ohci.h @@ -0,0 +1,21 @@ +/* + * Copyright (C) 2011 Samsung Electronics Co.Ltd + * http://www.samsung.com/ + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#ifndef __MACH_EXYNOS_OHCI_H +#define __MACH_EXYNOS_OHCI_H + +struct exynos4_ohci_platdata { + int (*phy_init)(struct platform_device *pdev, int type); + int (*phy_exit)(struct platform_device *pdev, int type); +}; + +extern void exynos4_ohci_set_platdata(struct exynos4_ohci_platdata *pd); + +#endif /* __MACH_EXYNOS_OHCI_H */ diff --git a/arch/arm/mach-exynos/include/mach/spi-clocks.h b/arch/arm/mach-exynos/include/mach/spi-clocks.h new file mode 100644 index 00000000000..576efdf6d09 --- /dev/null +++ b/arch/arm/mach-exynos/include/mach/spi-clocks.h @@ -0,0 +1,16 @@ +/* linux/arch/arm/mach-exynos4/include/mach/spi-clocks.h + * + * Copyright (C) 2011 Samsung Electronics Co. Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_SPI_CLKS_H +#define __ASM_ARCH_SPI_CLKS_H __FILE__ + +/* Must source from SCLK_SPI */ +#define EXYNOS4_SPI_SRCCLK_SCLK 0 + +#endif /* __ASM_ARCH_SPI_CLKS_H */ diff --git a/arch/arm/mach-exynos/mach-exynos4-dt.c b/arch/arm/mach-exynos/mach-exynos4-dt.c new file mode 100644 index 00000000000..85fa02767d6 --- /dev/null +++ b/arch/arm/mach-exynos/mach-exynos4-dt.c @@ -0,0 +1,85 @@ +/* + * Samsung's Exynos4210 flattened device tree enabled machine + * + * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * Copyright (c) 2010-2011 Linaro Ltd. + * www.linaro.org + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/of_platform.h> +#include <linux/serial_core.h> + +#include <asm/mach/arch.h> +#include <mach/map.h> + +#include <plat/cpu.h> +#include <plat/regs-serial.h> +#include <plat/exynos4.h> + +/* + * The following lookup table is used to override device names when devices + * are registered from device tree. This is temporarily added to enable + * device tree support addition for the Exynos4 architecture. + * + * For drivers that require platform data to be provided from the machine + * file, a platform data pointer can also be supplied along with the + * devices names. Usually, the platform data elements that cannot be parsed + * from the device tree by the drivers (example: function pointers) are + * supplied. But it should be noted that this is a temporary mechanism and + * at some point, the drivers should be capable of parsing all the platform + * data from the device tree. + */ +static const struct of_dev_auxdata exynos4210_auxdata_lookup[] __initconst = { + OF_DEV_AUXDATA("samsung,exynos4210-uart", S5P_PA_UART0, + "exynos4210-uart.0", NULL), + OF_DEV_AUXDATA("samsung,exynos4210-uart", S5P_PA_UART1, + "exynos4210-uart.1", NULL), + OF_DEV_AUXDATA("samsung,exynos4210-uart", S5P_PA_UART2, + "exynos4210-uart.2", NULL), + OF_DEV_AUXDATA("samsung,exynos4210-uart", S5P_PA_UART3, + "exynos4210-uart.3", NULL), + OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(0), + "exynos4-sdhci.0", NULL), + OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(1), + "exynos4-sdhci.1", NULL), + OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(2), + "exynos4-sdhci.2", NULL), + OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(3), + "exynos4-sdhci.3", NULL), + OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(0), + "s3c2440-i2c.0", NULL), + OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA0, "dma-pl330.0", NULL), + OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA1, "dma-pl330.1", NULL), + {}, +}; + +static void __init exynos4210_dt_map_io(void) +{ + s5p_init_io(NULL, 0, S5P_VA_CHIPID); + s3c24xx_init_clocks(24000000); +} + +static void __init exynos4210_dt_machine_init(void) +{ + of_platform_populate(NULL, of_default_bus_match_table, + exynos4210_auxdata_lookup, NULL); +} + +static char const *exynos4210_dt_compat[] __initdata = { + "samsung,exynos4210", + NULL +}; + +DT_MACHINE_START(EXYNOS4210_DT, "Samsung Exynos4 (Flattened Device Tree)") + /* Maintainer: Thomas Abraham <thomas.abraham@linaro.org> */ + .init_irq = exynos4_init_irq, + .map_io = exynos4210_dt_map_io, + .init_machine = exynos4210_dt_machine_init, + .timer = &exynos4_timer, + .dt_compat = exynos4210_dt_compat, +MACHINE_END diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c index 635fb97e31a..b895ec03110 100644 --- a/arch/arm/mach-exynos/mach-nuri.c +++ b/arch/arm/mach-exynos/mach-nuri.c @@ -249,13 +249,8 @@ static void nuri_lcd_power_on(struct plat_lcd_data *pd, unsigned int power) static int nuri_bl_init(struct device *dev) { - int ret, gpio = EXYNOS4_GPE2(3); - - ret = gpio_request(gpio, "LCD_LDO_EN"); - if (!ret) - gpio_direction_output(gpio, 0); - - return ret; + return gpio_request_one(EXYNOS4_GPE2(3), GPIOF_OUT_INIT_LOW, + "LCD_LD0_EN"); } static int nuri_bl_notify(struct device *dev, int brightness) diff --git a/arch/arm/mach-exynos/mach-origen.c b/arch/arm/mach-exynos/mach-origen.c index 586eb995aa9..2b11e046d39 100644 --- a/arch/arm/mach-exynos/mach-origen.c +++ b/arch/arm/mach-exynos/mach-origen.c @@ -41,6 +41,7 @@ #include <plat/fb.h> #include <plat/mfc.h> +#include <mach/ohci.h> #include <mach/map.h> #include "common.h" @@ -485,6 +486,16 @@ static void __init origen_ehci_init(void) s5p_ehci_set_platdata(pdata); } +/* USB OHCI */ +static struct exynos4_ohci_platdata origen_ohci_pdata; + +static void __init origen_ohci_init(void) +{ + struct exynos4_ohci_platdata *pdata = &origen_ohci_pdata; + + exynos4_ohci_set_platdata(pdata); +} + static struct gpio_keys_button origen_gpio_keys_table[] = { { .code = KEY_MENU, @@ -608,6 +619,7 @@ static struct platform_device *origen_devices[] __initdata = { &s5p_device_mfc_l, &s5p_device_mfc_r, &s5p_device_mixer, + &exynos4_device_ohci, &exynos4_device_pd[PD_LCD0], &exynos4_device_pd[PD_TV], &exynos4_device_pd[PD_G3D], @@ -672,6 +684,7 @@ static void __init origen_machine_init(void) s3c_sdhci0_set_platdata(&origen_hsmmc0_pdata); origen_ehci_init(); + origen_ohci_init(); clk_xusbxti.rate = 24000000; s5p_tv_setup(); diff --git a/arch/arm/mach-exynos/mach-smdkv310.c b/arch/arm/mach-exynos/mach-smdkv310.c index 5b365613b47..b2c5557f50e 100644 --- a/arch/arm/mach-exynos/mach-smdkv310.c +++ b/arch/arm/mach-exynos/mach-smdkv310.c @@ -42,6 +42,7 @@ #include <plat/clock.h> #include <mach/map.h> +#include <mach/ohci.h> #include "common.h" @@ -131,9 +132,7 @@ static void lcd_lte480wv_set_power(struct plat_lcd_data *pd, gpio_free(EXYNOS4_GPD0(1)); #endif /* fire nRESET on power up */ - gpio_request(EXYNOS4_GPX0(6), "GPX0"); - - gpio_direction_output(EXYNOS4_GPX0(6), 1); + gpio_request_one(EXYNOS4_GPX0(6), GPIOF_OUT_INIT_HIGH, "GPX0"); mdelay(100); gpio_set_value(EXYNOS4_GPX0(6), 0); @@ -247,6 +246,16 @@ static void __init smdkv310_ehci_init(void) s5p_ehci_set_platdata(pdata); } +/* USB OHCI */ +static struct exynos4_ohci_platdata smdkv310_ohci_pdata; + +static void __init smdkv310_ohci_init(void) +{ + struct exynos4_ohci_platdata *pdata = &smdkv310_ohci_pdata; + + exynos4_ohci_set_platdata(pdata); +} + static struct platform_device *smdkv310_devices[] __initdata = { &s3c_device_hsmmc0, &s3c_device_hsmmc1, @@ -263,6 +272,7 @@ static struct platform_device *smdkv310_devices[] __initdata = { &s5p_device_fimc3, &exynos4_device_ac97, &exynos4_device_i2s0, + &exynos4_device_ohci, &samsung_device_keypad, &s5p_device_mfc, &s5p_device_mfc_l, @@ -365,6 +375,7 @@ static void __init smdkv310_machine_init(void) s5p_fimd0_set_platdata(&smdkv310_lcd0_pdata); smdkv310_ehci_init(); + smdkv310_ohci_init(); clk_xusbxti.rate = 24000000; platform_add_devices(smdkv310_devices, ARRAY_SIZE(smdkv310_devices)); diff --git a/arch/arm/mach-exynos/mach-universal_c210.c b/arch/arm/mach-exynos/mach-universal_c210.c index 52aea972746..37ac93e8d6d 100644 --- a/arch/arm/mach-exynos/mach-universal_c210.c +++ b/arch/arm/mach-exynos/mach-universal_c210.c @@ -610,8 +610,7 @@ static void __init universal_tsp_init(void) /* TSP_LDO_ON: XMDMADDR_11 */ gpio = EXYNOS4_GPE2(3); - gpio_request(gpio, "TSP_LDO_ON"); - gpio_direction_output(gpio, 1); + gpio_request_one(gpio, GPIOF_OUT_INIT_HIGH, "TSP_LDO_ON"); gpio_export(gpio, 0); /* TSP_INT: XMDMADDR_7 */ @@ -671,8 +670,7 @@ static void __init universal_touchkey_init(void) i2c_gpio12_devs[0].irq = gpio_to_irq(gpio); gpio = EXYNOS4_GPE3(3); /* XMDMDATA_3 */ - gpio_request(gpio, "3_TOUCH_EN"); - gpio_direction_output(gpio, 1); + gpio_request_one(gpio, GPIOF_OUT_INIT_HIGH, "3_TOUCH_EN"); } static struct s3c2410_platform_i2c universal_i2c0_platdata __initdata = { @@ -1002,9 +1000,7 @@ static void __init universal_map_io(void) void s5p_tv_setup(void) { /* direct HPD to HDMI chip */ - gpio_request(EXYNOS4_GPX3(7), "hpd-plug"); - - gpio_direction_input(EXYNOS4_GPX3(7)); + gpio_request_one(EXYNOS4_GPX3(7), GPIOF_IN, "hpd-plug"); s3c_gpio_cfgpin(EXYNOS4_GPX3(7), S3C_GPIO_SFN(0x3)); s3c_gpio_setpull(EXYNOS4_GPX3(7), S3C_GPIO_PULL_NONE); diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c index 509a435afd4..a4f61a43c7b 100644 --- a/arch/arm/mach-exynos/pm.c +++ b/arch/arm/mach-exynos/pm.c @@ -23,6 +23,7 @@ #include <asm/cacheflush.h> #include <asm/hardware/cache-l2x0.h> +#include <asm/smp_scu.h> #include <plat/cpu.h> #include <plat/pm.h> @@ -205,7 +206,7 @@ static void exynos4_pm_prepare(void) } -static int exynos4_pm_add(struct sys_device *sysdev) +static int exynos4_pm_add(struct device *dev) { pm_cpu_prep = exynos4_pm_prepare; pm_cpu_sleep = exynos4_cpu_suspend; @@ -213,27 +214,6 @@ static int exynos4_pm_add(struct sys_device *sysdev) return 0; } -/* This function copy from linux/arch/arm/kernel/smp_scu.c */ - -void exynos4_scu_enable(void __iomem *scu_base) -{ - u32 scu_ctrl; - - scu_ctrl = __raw_readl(scu_base); - /* already enabled? */ - if (scu_ctrl & 1) - return; - - scu_ctrl |= 1; - __raw_writel(scu_ctrl, scu_base); - - /* - * Ensure that the data accessed by CPU0 before the SCU was - * initialised is visible to the other CPUs. - */ - flush_cache_all(); -} - static unsigned long pll_base_rate; static void exynos4_restore_pll(void) @@ -301,8 +281,10 @@ static void exynos4_restore_pll(void) } while (epll_wait || vpll_wait); } -static struct sysdev_driver exynos4_pm_driver = { - .add = exynos4_pm_add, +static struct subsys_interface exynos4_pm_interface = { + .name = "exynos4_pm", + .subsys = &exynos4_subsys, + .add_dev = exynos4_pm_add, }; static __init int exynos4_pm_drvinit(void) @@ -325,7 +307,7 @@ static __init int exynos4_pm_drvinit(void) clk_put(pll_base); } - return sysdev_driver_register(&exynos4_sysclass, &exynos4_pm_driver); + return subsys_interface_register(&exynos4_pm_interface); } arch_initcall(exynos4_pm_drvinit); @@ -402,7 +384,7 @@ static void exynos4_pm_resume(void) exynos4_restore_pll(); - exynos4_scu_enable(S5P_VA_SCU); + scu_enable(S5P_VA_SCU); #ifdef CONFIG_CACHE_L2X0 s3c_pm_do_restore_core(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save)); diff --git a/arch/arm/mach-exynos/setup-sdhci.c b/arch/arm/mach-exynos/setup-sdhci.c deleted file mode 100644 index 92937b41090..00000000000 --- a/arch/arm/mach-exynos/setup-sdhci.c +++ /dev/null @@ -1,22 +0,0 @@ -/* linux/arch/arm/mach-exynos4/setup-sdhci.c - * - * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * EXYNOS4 - Helper functions for settign up SDHCI device(s) (HSMMC) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/types.h> - -/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */ - -char *exynos4_hsmmc_clksrcs[4] = { - [0] = NULL, - [1] = NULL, - [2] = "sclk_mmc", /* mmc_bus */ - [3] = NULL, -}; diff --git a/arch/arm/mach-exynos/setup-spi.c b/arch/arm/mach-exynos/setup-spi.c new file mode 100644 index 00000000000..833ff40ee0e --- /dev/null +++ b/arch/arm/mach-exynos/setup-spi.c @@ -0,0 +1,72 @@ +/* linux/arch/arm/mach-exynos4/setup-spi.c + * + * Copyright (C) 2011 Samsung Electronics Ltd. + * http://www.samsung.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/gpio.h> +#include <linux/platform_device.h> + +#include <plat/gpio-cfg.h> +#include <plat/s3c64xx-spi.h> + +#ifdef CONFIG_S3C64XX_DEV_SPI0 +struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = { + .fifo_lvl_mask = 0x1ff, + .rx_lvl_offset = 15, + .high_speed = 1, + .clk_from_cmu = true, + .tx_st_done = 25, +}; + +int s3c64xx_spi0_cfg_gpio(struct platform_device *dev) +{ + s3c_gpio_cfgpin(EXYNOS4_GPB(0), S3C_GPIO_SFN(2)); + s3c_gpio_setpull(EXYNOS4_GPB(0), S3C_GPIO_PULL_UP); + s3c_gpio_cfgall_range(EXYNOS4_GPB(2), 2, + S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); + return 0; +} +#endif + +#ifdef CONFIG_S3C64XX_DEV_SPI1 +struct s3c64xx_spi_info s3c64xx_spi1_pdata __initdata = { + .fifo_lvl_mask = 0x7f, + .rx_lvl_offset = 15, + .high_speed = 1, + .clk_from_cmu = true, + .tx_st_done = 25, +}; + +int s3c64xx_spi1_cfg_gpio(struct platform_device *dev) +{ + s3c_gpio_cfgpin(EXYNOS4_GPB(4), S3C_GPIO_SFN(2)); + s3c_gpio_setpull(EXYNOS4_GPB(4), S3C_GPIO_PULL_UP); + s3c_gpio_cfgall_range(EXYNOS4_GPB(6), 2, + S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); + return 0; +} +#endif + +#ifdef CONFIG_S3C64XX_DEV_SPI2 +struct s3c64xx_spi_info s3c64xx_spi2_pdata __initdata = { + .fifo_lvl_mask = 0x7f, + .rx_lvl_offset = 15, + .high_speed = 1, + .clk_from_cmu = true, + .tx_st_done = 25, +}; + +int s3c64xx_spi2_cfg_gpio(struct platform_device *dev) +{ + s3c_gpio_cfgpin(EXYNOS4_GPC1(1), S3C_GPIO_SFN(5)); + s3c_gpio_setpull(EXYNOS4_GPC1(1), S3C_GPIO_PULL_UP); + s3c_gpio_cfgall_range(EXYNOS4_GPC1(3), 2, + S3C_GPIO_SFN(5), S3C_GPIO_PULL_UP); + return 0; +} +#endif diff --git a/arch/arm/mach-exynos/setup-usb-phy.c b/arch/arm/mach-exynos/setup-usb-phy.c index 39aca045f66..41743d21e8c 100644 --- a/arch/arm/mach-exynos/setup-usb-phy.c +++ b/arch/arm/mach-exynos/setup-usb-phy.c @@ -19,6 +19,13 @@ #include <plat/cpu.h> #include <plat/usb-phy.h> +static atomic_t host_usage; + +static int exynos4_usb_host_phy_is_on(void) +{ + return (readl(EXYNOS4_PHYPWR) & PHY1_STD_ANALOG_POWERDOWN) ? 0 : 1; +} + static int exynos4_usb_phy1_init(struct platform_device *pdev) { struct clk *otg_clk; @@ -27,6 +34,8 @@ static int exynos4_usb_phy1_init(struct platform_device *pdev) u32 rstcon; int err; + atomic_inc(&host_usage); + otg_clk = clk_get(&pdev->dev, "otg"); if (IS_ERR(otg_clk)) { dev_err(&pdev->dev, "Failed to get otg clock\n"); @@ -39,6 +48,9 @@ static int exynos4_usb_phy1_init(struct platform_device *pdev) return err; } + if (exynos4_usb_host_phy_is_on()) + return 0; + writel(readl(S5P_USBHOST_PHY_CONTROL) | S5P_USBHOST_PHY_ENABLE, S5P_USBHOST_PHY_CONTROL); @@ -95,6 +107,9 @@ static int exynos4_usb_phy1_exit(struct platform_device *pdev) struct clk *otg_clk; int err; + if (atomic_dec_return(&host_usage) > 0) + return 0; + otg_clk = clk_get(&pdev->dev, "otg"); if (IS_ERR(otg_clk)) { dev_err(&pdev->dev, "Failed to get otg clock\n"); diff --git a/arch/arm/mach-footbridge/dc21285.c b/arch/arm/mach-footbridge/dc21285.c index 18c32a5541d..f685650c25d 100644 --- a/arch/arm/mach-footbridge/dc21285.c +++ b/arch/arm/mach-footbridge/dc21285.c @@ -275,9 +275,9 @@ int __init dc21285_setup(int nr, struct pci_sys_data *sys) allocate_resource(&iomem_resource, &res[0], 0x40000000, 0x80000000, 0xffffffff, 0x40000000, NULL, NULL); - sys->resource[0] = &ioport_resource; - sys->resource[1] = &res[0]; - sys->resource[2] = &res[1]; + pci_add_resource(&sys->resources, &ioport_resource); + pci_add_resource(&sys->resources, &res[0]); + pci_add_resource(&sys->resources, &res[1]); sys->mem_offset = DC21285_PCI_MEM; return 1; @@ -285,7 +285,7 @@ int __init dc21285_setup(int nr, struct pci_sys_data *sys) struct pci_bus * __init dc21285_scan_bus(int nr, struct pci_sys_data *sys) { - return pci_scan_bus(0, &dc21285_ops, sys); + return pci_scan_root_bus(NULL, 0, &dc21285_ops, sys, &sys->resources); } #define dc21285_request_irq(_a, _b, _c, _d, _e) \ diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 35a218cb5c7..0e6de366c64 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -98,6 +98,7 @@ config MACH_SCB9328 config MACH_APF9328 bool "APF9328" select SOC_IMX1 + select IMX_HAVE_PLATFORM_IMX_I2C select IMX_HAVE_PLATFORM_IMX_UART help Say Yes here if you are using the Armadeus APF9328 development board @@ -595,6 +596,7 @@ comment "i.MX6 family:" config SOC_IMX6Q bool "i.MX6 Quad support" + select ARM_CPU_SUSPEND if PM select ARM_GIC select CPU_V7 select HAVE_ARM_SCU diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index d97f409ce98..f5920c24f7d 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -70,4 +70,8 @@ AFLAGS_head-v7.o :=-Wa,-march=armv7-a obj-$(CONFIG_SMP) += platsmp.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o -obj-$(CONFIG_SOC_IMX6Q) += clock-imx6q.o mach-imx6q.o pm-imx6q.o +obj-$(CONFIG_SOC_IMX6Q) += clock-imx6q.o mach-imx6q.o + +ifeq ($(CONFIG_PM),y) +obj-$(CONFIG_SOC_IMX6Q) += pm-imx6q.o +endif diff --git a/arch/arm/mach-imx/Makefile.boot b/arch/arm/mach-imx/Makefile.boot index cfede5768aa..5f4d06af491 100644 --- a/arch/arm/mach-imx/Makefile.boot +++ b/arch/arm/mach-imx/Makefile.boot @@ -25,3 +25,6 @@ initrd_phys-$(CONFIG_SOC_IMX35) := 0x80800000 zreladdr-$(CONFIG_SOC_IMX6Q) += 0x10008000 params_phys-$(CONFIG_SOC_IMX6Q) := 0x10000100 initrd_phys-$(CONFIG_SOC_IMX6Q) := 0x10800000 + +dtb-$(CONFIG_SOC_IMX6Q) += imx6q-arm2.dtb \ + imx6q-sabrelite.dtb diff --git a/arch/arm/mach-imx/head-v7.S b/arch/arm/mach-imx/head-v7.S index 6229efbc70c..7e49deb128a 100644 --- a/arch/arm/mach-imx/head-v7.S +++ b/arch/arm/mach-imx/head-v7.S @@ -16,7 +16,6 @@ #include <asm/hardware/cache-l2x0.h> .section ".text.head", "ax" - __CPUINIT /* * The secondary kernel init calls v7_flush_dcache_all before it enables @@ -33,6 +32,7 @@ */ ENTRY(v7_invalidate_l1) mov r0, #0 + mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache mcr p15, 2, r0, c0, c0, 0 mrc p15, 1, r0, c0, c0, 0 @@ -71,6 +71,7 @@ ENTRY(v7_secondary_startup) ENDPROC(v7_secondary_startup) #endif +#ifdef CONFIG_PM /* * The following code is located into the .data section. This is to * allow phys_l2x0_saved_regs to be accessed with a relative load @@ -79,6 +80,7 @@ ENDPROC(v7_secondary_startup) .data .align +#ifdef CONFIG_CACHE_L2X0 .macro pl310_resume ldr r2, phys_l2x0_saved_regs ldr r0, [r2, #L2X0_R_PHY_BASE] @ get physical base of l2x0 @@ -88,12 +90,17 @@ ENDPROC(v7_secondary_startup) str r1, [r0, #L2X0_CTRL] @ re-enable L2 .endm + .globl phys_l2x0_saved_regs +phys_l2x0_saved_regs: + .long 0 +#else + .macro pl310_resume + .endm +#endif + ENTRY(v7_cpu_resume) bl v7_invalidate_l1 pl310_resume b cpu_resume ENDPROC(v7_cpu_resume) - - .globl phys_l2x0_saved_regs -phys_l2x0_saved_regs: - .long 0 +#endif diff --git a/arch/arm/mach-imx/mach-apf9328.c b/arch/arm/mach-imx/mach-apf9328.c index 146a4f07346..f4a63ee9e21 100644 --- a/arch/arm/mach-imx/mach-apf9328.c +++ b/arch/arm/mach-imx/mach-apf9328.c @@ -18,6 +18,7 @@ #include <linux/platform_device.h> #include <linux/mtd/physmap.h> #include <linux/dm9000.h> +#include <linux/i2c.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> @@ -41,6 +42,9 @@ static const int apf9328_pins[] __initconst = { PB29_PF_UART2_RTS, PB30_PF_UART2_TXD, PB31_PF_UART2_RXD, + /* I2C */ + PA15_PF_I2C_SDA, + PA16_PF_I2C_SCL, }; /* @@ -103,6 +107,10 @@ static const struct imxuart_platform_data uart1_pdata __initconst = { .flags = IMXUART_HAVE_RTSCTS, }; +static const struct imxi2c_platform_data apf9328_i2c_data __initconst = { + .bitrate = 100000, +}; + static struct platform_device *devices[] __initdata = { &apf9328_flash_device, &dm9000x_device, @@ -119,6 +127,8 @@ static void __init apf9328_init(void) imx1_add_imx_uart0(NULL); imx1_add_imx_uart1(&uart1_pdata); + imx1_add_imx_i2c(&apf9328_i2c_data); + platform_add_devices(devices, ARRAY_SIZE(devices)); } diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c index 05b49bb5d67..c2572810691 100644 --- a/arch/arm/mach-imx/mach-imx6q.c +++ b/arch/arm/mach-imx/mach-imx6q.c @@ -19,6 +19,8 @@ #include <linux/of_address.h> #include <linux/of_irq.h> #include <linux/of_platform.h> +#include <linux/phy.h> +#include <linux/micrel_phy.h> #include <asm/hardware/cache-l2x0.h> #include <asm/hardware/gic.h> #include <asm/mach/arch.h> @@ -56,8 +58,27 @@ soft: soft_restart(0); } +/* For imx6q sabrelite board: set KSZ9021RN RGMII pad skew */ +static int ksz9021rn_phy_fixup(struct phy_device *phydev) +{ + /* min rx data delay */ + phy_write(phydev, 0x0b, 0x8105); + phy_write(phydev, 0x0c, 0x0000); + + /* max rx/tx clock delay, min rx/tx control delay */ + phy_write(phydev, 0x0b, 0x8104); + phy_write(phydev, 0x0c, 0xf0f0); + phy_write(phydev, 0x0b, 0x104); + + return 0; +} + static void __init imx6q_init_machine(void) { + if (of_machine_is_compatible("fsl,imx6q-sabrelite")) + phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK, + ksz9021rn_phy_fixup); + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); imx6q_pm_init(); @@ -105,7 +126,8 @@ static struct sys_timer imx6q_timer = { }; static const char *imx6q_dt_compat[] __initdata = { - "fsl,imx6q-sabreauto", + "fsl,imx6q-arm2", + "fsl,imx6q-sabrelite", NULL, }; diff --git a/arch/arm/mach-imx/mach-mx31_3ds.c b/arch/arm/mach-imx/mach-mx31_3ds.c index 2b565c38134..89c33258639 100644 --- a/arch/arm/mach-imx/mach-mx31_3ds.c +++ b/arch/arm/mach-imx/mach-mx31_3ds.c @@ -492,7 +492,7 @@ static struct mc13xxx_platform_data mc13783_pdata = { .regulators = mx31_3ds_regulators, .num_regulators = ARRAY_SIZE(mx31_3ds_regulators), }, - .flags = MC13XXX_USE_TOUCHSCREEN, + .flags = MC13XXX_USE_TOUCHSCREEN | MC13XXX_USE_RTC, }; /* SPI */ diff --git a/arch/arm/mach-imx/pm-imx6q.c b/arch/arm/mach-imx/pm-imx6q.c index f20f191d7cc..f7b0c2b1b90 100644 --- a/arch/arm/mach-imx/pm-imx6q.c +++ b/arch/arm/mach-imx/pm-imx6q.c @@ -64,7 +64,9 @@ void __init imx6q_pm_init(void) * address of the data structure used by l2x0 core to save registers, * and later restore the necessary ones in imx6q resume entry. */ +#ifdef CONFIG_CACHE_L2X0 phys_l2x0_saved_regs = __pa(&l2x0_saved_regs); +#endif suspend_set_ops(&imx6q_pm_ops); } diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c index 3a730d447c9..a8b6aa6003f 100644 --- a/arch/arm/mach-integrator/integrator_cp.c +++ b/arch/arm/mach-integrator/integrator_cp.c @@ -14,7 +14,7 @@ #include <linux/platform_device.h> #include <linux/dma-mapping.h> #include <linux/string.h> -#include <linux/sysdev.h> +#include <linux/device.h> #include <linux/amba/bus.h> #include <linux/amba/kmi.h> #include <linux/amba/clcd.h> diff --git a/arch/arm/mach-integrator/pci_v3.c b/arch/arm/mach-integrator/pci_v3.c index b4d8f8b8a08..3c82566acec 100644 --- a/arch/arm/mach-integrator/pci_v3.c +++ b/arch/arm/mach-integrator/pci_v3.c @@ -359,7 +359,7 @@ static struct resource pre_mem = { .flags = IORESOURCE_MEM | IORESOURCE_PREFETCH, }; -static int __init pci_v3_setup_resources(struct resource **resource) +static int __init pci_v3_setup_resources(struct pci_sys_data *sys) { if (request_resource(&iomem_resource, &non_mem)) { printk(KERN_ERR "PCI: unable to allocate non-prefetchable " @@ -374,13 +374,13 @@ static int __init pci_v3_setup_resources(struct resource **resource) } /* - * bus->resource[0] is the IO resource for this bus - * bus->resource[1] is the mem resource for this bus - * bus->resource[2] is the prefetch mem resource for this bus + * the IO resource for this bus + * the mem resource for this bus + * the prefetch mem resource for this bus */ - resource[0] = &ioport_resource; - resource[1] = &non_mem; - resource[2] = &pre_mem; + pci_add_resource(&sys->resources, &ioport_resource); + pci_add_resource(&sys->resources, &non_mem); + pci_add_resource(&sys->resources, &pre_mem); return 1; } @@ -481,7 +481,7 @@ int __init pci_v3_setup(int nr, struct pci_sys_data *sys) if (nr == 0) { sys->mem_offset = PHYS_PCI_MEM_BASE; - ret = pci_v3_setup_resources(sys->resource); + ret = pci_v3_setup_resources(sys); } return ret; @@ -489,7 +489,8 @@ int __init pci_v3_setup(int nr, struct pci_sys_data *sys) struct pci_bus * __init pci_v3_scan_bus(int nr, struct pci_sys_data *sys) { - return pci_scan_bus(sys->busnr, &pci_v3_ops, sys); + return pci_scan_root_bus(NULL, sys->busnr, &pci_v3_ops, sys, + &sys->resources); } /* diff --git a/arch/arm/mach-iop13xx/pci.c b/arch/arm/mach-iop13xx/pci.c index db012fadf88..b8f5a873651 100644 --- a/arch/arm/mach-iop13xx/pci.c +++ b/arch/arm/mach-iop13xx/pci.c @@ -537,14 +537,14 @@ struct pci_bus *iop13xx_scan_bus(int nr, struct pci_sys_data *sys) while(time_before(jiffies, atux_trhfa_timeout)) udelay(100); - bus = pci_bus_atux = pci_scan_bus(sys->busnr, - &iop13xx_atux_ops, - sys); + bus = pci_bus_atux = pci_scan_root_bus(NULL, sys->busnr, + &iop13xx_atux_ops, + sys, &sys->resources); break; case IOP13XX_INIT_ATU_ATUE: - bus = pci_bus_atue = pci_scan_bus(sys->busnr, - &iop13xx_atue_ops, - sys); + bus = pci_bus_atue = pci_scan_root_bus(NULL, sys->busnr, + &iop13xx_atue_ops, + sys, &sys->resources); break; } @@ -1084,9 +1084,8 @@ int iop13xx_pci_setup(int nr, struct pci_sys_data *sys) request_resource(&ioport_resource, &res[0]); request_resource(&iomem_resource, &res[1]); - sys->resource[0] = &res[0]; - sys->resource[1] = &res[1]; - sys->resource[2] = NULL; + pci_add_resource(&sys->resources, &res[0]); + pci_add_resource(&sys->resources, &res[1]); return 1; } diff --git a/arch/arm/mach-ixp2000/enp2611.c b/arch/arm/mach-ixp2000/enp2611.c index ee525416f0d..e872d238cd0 100644 --- a/arch/arm/mach-ixp2000/enp2611.c +++ b/arch/arm/mach-ixp2000/enp2611.c @@ -145,7 +145,8 @@ static struct pci_ops enp2611_pci_ops = { static struct pci_bus * __init enp2611_pci_scan_bus(int nr, struct pci_sys_data *sys) { - return pci_scan_bus(sys->busnr, &enp2611_pci_ops, sys); + return pci_scan_root_bus(NULL, sys->busnr, &enp2611_pci_ops, sys, + &sys->resources); } static int __init enp2611_pci_map_irq(const struct pci_dev *dev, u8 slot, diff --git a/arch/arm/mach-ixp2000/pci.c b/arch/arm/mach-ixp2000/pci.c index f5098b306fd..626fda435aa 100644 --- a/arch/arm/mach-ixp2000/pci.c +++ b/arch/arm/mach-ixp2000/pci.c @@ -132,7 +132,8 @@ static struct pci_ops ixp2000_pci_ops = { struct pci_bus *ixp2000_pci_scan_bus(int nr, struct pci_sys_data *sysdata) { - return pci_scan_bus(sysdata->busnr, &ixp2000_pci_ops, sysdata); + return pci_scan_root_bus(NULL, sysdata->busnr, &ixp2000_pci_ops, + sysdata, &sysdata->resources); } @@ -242,9 +243,8 @@ int ixp2000_pci_setup(int nr, struct pci_sys_data *sys) if (nr >= 1) return 0; - sys->resource[0] = &ixp2000_pci_io_space; - sys->resource[1] = &ixp2000_pci_mem_space; - sys->resource[2] = NULL; + pci_add_resource(&sys->resources, &ixp2000_pci_io_space); + pci_add_resource(&sys->resources, &ixp2000_pci_mem_space); return 1; } diff --git a/arch/arm/mach-ixp23xx/pci.c b/arch/arm/mach-ixp23xx/pci.c index e6be5711c70..25b5c462cea 100644 --- a/arch/arm/mach-ixp23xx/pci.c +++ b/arch/arm/mach-ixp23xx/pci.c @@ -143,7 +143,8 @@ struct pci_ops ixp23xx_pci_ops = { struct pci_bus *ixp23xx_pci_scan_bus(int nr, struct pci_sys_data *sysdata) { - return pci_scan_bus(sysdata->busnr, &ixp23xx_pci_ops, sysdata); + return pci_scan_root_bus(NULL, sysdata->busnr, &ixp23xx_pci_ops, + sysdata, &sysdata->resources); } int ixp23xx_pci_abort_handler(unsigned long addr, unsigned int fsr, struct pt_regs *regs) @@ -280,9 +281,8 @@ int ixp23xx_pci_setup(int nr, struct pci_sys_data *sys) if (nr >= 1) return 0; - sys->resource[0] = &ixp23xx_pci_io_space; - sys->resource[1] = &ixp23xx_pci_mem_space; - sys->resource[2] = NULL; + pci_add_resource(&sys->resources, &ixp23xx_pci_io_space); + pci_add_resource(&sys->resources, &ixp23xx_pci_mem_space); return 1; } diff --git a/arch/arm/mach-ixp4xx/common-pci.c b/arch/arm/mach-ixp4xx/common-pci.c index 8325058ef87..5eff15f24bc 100644 --- a/arch/arm/mach-ixp4xx/common-pci.c +++ b/arch/arm/mach-ixp4xx/common-pci.c @@ -472,9 +472,8 @@ int ixp4xx_setup(int nr, struct pci_sys_data *sys) request_resource(&ioport_resource, &res[0]); request_resource(&iomem_resource, &res[1]); - sys->resource[0] = &res[0]; - sys->resource[1] = &res[1]; - sys->resource[2] = NULL; + pci_add_resource(&sys->resources, &res[0]); + pci_add_resource(&sys->resources, &res[1]); platform_notify = ixp4xx_pci_platform_notify; platform_notify_remove = ixp4xx_pci_platform_notify_remove; @@ -484,7 +483,8 @@ int ixp4xx_setup(int nr, struct pci_sys_data *sys) struct pci_bus * __devinit ixp4xx_scan_bus(int nr, struct pci_sys_data *sys) { - return pci_scan_bus(sys->busnr, &ixp4xx_ops, sys); + return pci_scan_root_bus(NULL, sys->busnr, &ixp4xx_ops, sys, + &sys->resources); } int dma_set_coherent_mask(struct device *dev, u64 mask) diff --git a/arch/arm/mach-kirkwood/addr-map.c b/arch/arm/mach-kirkwood/addr-map.c index 8d03bcef518..e9a7180863d 100644 --- a/arch/arm/mach-kirkwood/addr-map.c +++ b/arch/arm/mach-kirkwood/addr-map.c @@ -13,12 +13,12 @@ #include <linux/mbus.h> #include <linux/io.h> #include <mach/hardware.h> +#include <plat/addr-map.h> #include "common.h" /* * Generic Address Decode Windows bit settings */ -#define TARGET_DDR 0 #define TARGET_DEV_BUS 1 #define TARGET_SRAM 3 #define TARGET_PCIE 4 @@ -36,118 +36,55 @@ #define ATTR_SRAM 0x01 /* - * Helpers to get DDR bank info + * Description of the windows needed by the platform code */ -#define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3)) -#define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3)) - -/* - * CPU Address Decode Windows registers - */ -#define WIN_OFF(n) (BRIDGE_VIRT_BASE + 0x0000 + ((n) << 4)) -#define WIN_CTRL_OFF 0x0000 -#define WIN_BASE_OFF 0x0004 -#define WIN_REMAP_LO_OFF 0x0008 -#define WIN_REMAP_HI_OFF 0x000c - - -struct mbus_dram_target_info kirkwood_mbus_dram_info; - -static int __init cpu_win_can_remap(int win) -{ - if (win < 4) - return 1; - - return 0; -} - -static void __init setup_cpu_win(int win, u32 base, u32 size, - u8 target, u8 attr, int remap) -{ - void __iomem *addr = (void __iomem *)WIN_OFF(win); - u32 ctrl; - - base &= 0xffff0000; - ctrl = ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1; - - writel(base, addr + WIN_BASE_OFF); - writel(ctrl, addr + WIN_CTRL_OFF); - if (cpu_win_can_remap(win)) { - if (remap < 0) - remap = base; - - writel(remap & 0xffff0000, addr + WIN_REMAP_LO_OFF); - writel(0, addr + WIN_REMAP_HI_OFF); - } -} - -void __init kirkwood_setup_cpu_mbus(void) -{ - void __iomem *addr; - int i; - int cs; +static struct __initdata orion_addr_map_cfg addr_map_cfg = { + .num_wins = 8, + .remappable_wins = 4, + .bridge_virt_base = BRIDGE_VIRT_BASE, +}; +static const struct __initdata orion_addr_map_info addr_map_info[] = { /* - * First, disable and clear windows. + * Windows for PCIe IO+MEM space. */ - for (i = 0; i < 8; i++) { - addr = (void __iomem *)WIN_OFF(i); - - writel(0, addr + WIN_BASE_OFF); - writel(0, addr + WIN_CTRL_OFF); - if (cpu_win_can_remap(i)) { - writel(0, addr + WIN_REMAP_LO_OFF); - writel(0, addr + WIN_REMAP_HI_OFF); - } - } - + { 0, KIRKWOOD_PCIE_IO_PHYS_BASE, KIRKWOOD_PCIE_IO_SIZE, + TARGET_PCIE, ATTR_PCIE_IO, KIRKWOOD_PCIE_IO_BUS_BASE + }, + { 1, KIRKWOOD_PCIE_MEM_PHYS_BASE, KIRKWOOD_PCIE_MEM_SIZE, + TARGET_PCIE, ATTR_PCIE_MEM, KIRKWOOD_PCIE_MEM_BUS_BASE + }, + { 2, KIRKWOOD_PCIE1_IO_PHYS_BASE, KIRKWOOD_PCIE1_IO_SIZE, + TARGET_PCIE, ATTR_PCIE1_IO, KIRKWOOD_PCIE1_IO_BUS_BASE + }, + { 3, KIRKWOOD_PCIE1_MEM_PHYS_BASE, KIRKWOOD_PCIE1_MEM_SIZE, + TARGET_PCIE, ATTR_PCIE1_MEM, KIRKWOOD_PCIE1_MEM_BUS_BASE + }, /* - * Setup windows for PCIe IO+MEM space. + * Window for NAND controller. */ - setup_cpu_win(0, KIRKWOOD_PCIE_IO_PHYS_BASE, KIRKWOOD_PCIE_IO_SIZE, - TARGET_PCIE, ATTR_PCIE_IO, KIRKWOOD_PCIE_IO_BUS_BASE); - setup_cpu_win(1, KIRKWOOD_PCIE_MEM_PHYS_BASE, KIRKWOOD_PCIE_MEM_SIZE, - TARGET_PCIE, ATTR_PCIE_MEM, KIRKWOOD_PCIE_MEM_BUS_BASE); - setup_cpu_win(2, KIRKWOOD_PCIE1_IO_PHYS_BASE, KIRKWOOD_PCIE1_IO_SIZE, - TARGET_PCIE, ATTR_PCIE1_IO, KIRKWOOD_PCIE1_IO_BUS_BASE); - setup_cpu_win(3, KIRKWOOD_PCIE1_MEM_PHYS_BASE, KIRKWOOD_PCIE1_MEM_SIZE, - TARGET_PCIE, ATTR_PCIE1_MEM, KIRKWOOD_PCIE1_MEM_BUS_BASE); - + { 4, KIRKWOOD_NAND_MEM_PHYS_BASE, KIRKWOOD_NAND_MEM_SIZE, + TARGET_DEV_BUS, ATTR_DEV_NAND, -1 + }, /* - * Setup window for NAND controller. + * Window for SRAM. */ - setup_cpu_win(4, KIRKWOOD_NAND_MEM_PHYS_BASE, KIRKWOOD_NAND_MEM_SIZE, - TARGET_DEV_BUS, ATTR_DEV_NAND, -1); + { 5, KIRKWOOD_SRAM_PHYS_BASE, KIRKWOOD_SRAM_SIZE, + TARGET_SRAM, ATTR_SRAM, -1 + }, + /* End marker */ + { -1, 0, 0, 0, 0, 0 } +}; +void __init kirkwood_setup_cpu_mbus(void) +{ /* - * Setup window for SRAM. + * Disable, clear and configure windows. */ - setup_cpu_win(5, KIRKWOOD_SRAM_PHYS_BASE, KIRKWOOD_SRAM_SIZE, - TARGET_SRAM, ATTR_SRAM, -1); + orion_config_wins(&addr_map_cfg, addr_map_info); /* * Setup MBUS dram target info. */ - kirkwood_mbus_dram_info.mbus_dram_target_id = TARGET_DDR; - - addr = (void __iomem *)DDR_WINDOW_CPU_BASE; - - for (i = 0, cs = 0; i < 4; i++) { - u32 base = readl(addr + DDR_BASE_CS_OFF(i)); - u32 size = readl(addr + DDR_SIZE_CS_OFF(i)); - - /* - * Chip select enabled? - */ - if (size & 1) { - struct mbus_dram_window *w; - - w = &kirkwood_mbus_dram_info.cs[cs++]; - w->cs_index = i; - w->mbus_attr = 0xf & ~(1 << i); - w->base = base & 0xffff0000; - w->size = (size | 0x0000ffff) + 1; - } - } - kirkwood_mbus_dram_info.num_cs = cs; + orion_setup_cpu_mbus_target(&addr_map_cfg, DDR_WINDOW_CPU_BASE); } diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c index 0bff4a91623..cc15426787b 100644 --- a/arch/arm/mach-kirkwood/common.c +++ b/arch/arm/mach-kirkwood/common.c @@ -12,7 +12,6 @@ #include <linux/init.h> #include <linux/platform_device.h> #include <linux/serial_8250.h> -#include <linux/mbus.h> #include <linux/ata_platform.h> #include <linux/mtd/nand.h> #include <linux/dma-mapping.h> @@ -30,6 +29,7 @@ #include <plat/orion_nand.h> #include <plat/common.h> #include <plat/time.h> +#include <plat/addr-map.h> #include "common.h" /***************************************************************************** @@ -73,8 +73,7 @@ unsigned int kirkwood_clk_ctrl = CGC_DUNIT | CGC_RESERVED; void __init kirkwood_ehci_init(void) { kirkwood_clk_ctrl |= CGC_USB0; - orion_ehci_init(&kirkwood_mbus_dram_info, - USB_PHYS_BASE, IRQ_KIRKWOOD_USB); + orion_ehci_init(USB_PHYS_BASE, IRQ_KIRKWOOD_USB); } @@ -85,7 +84,7 @@ void __init kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data) { kirkwood_clk_ctrl |= CGC_GE0; - orion_ge00_init(eth_data, &kirkwood_mbus_dram_info, + orion_ge00_init(eth_data, GE00_PHYS_BASE, IRQ_KIRKWOOD_GE00_SUM, IRQ_KIRKWOOD_GE00_ERR, kirkwood_tclk); } @@ -99,7 +98,7 @@ void __init kirkwood_ge01_init(struct mv643xx_eth_platform_data *eth_data) kirkwood_clk_ctrl |= CGC_GE1; - orion_ge01_init(eth_data, &kirkwood_mbus_dram_info, + orion_ge01_init(eth_data, GE01_PHYS_BASE, IRQ_KIRKWOOD_GE01_SUM, IRQ_KIRKWOOD_GE01_ERR, kirkwood_tclk); } @@ -178,8 +177,7 @@ void __init kirkwood_sata_init(struct mv_sata_platform_data *sata_data) if (sata_data->n_ports > 1) kirkwood_clk_ctrl |= CGC_SATA1; - orion_sata_init(sata_data, &kirkwood_mbus_dram_info, - SATA_PHYS_BASE, IRQ_KIRKWOOD_SATA); + orion_sata_init(sata_data, SATA_PHYS_BASE, IRQ_KIRKWOOD_SATA); } @@ -221,7 +219,6 @@ void __init kirkwood_sdio_init(struct mvsdio_platform_data *mvsdio_data) mvsdio_data->clock = 100000000; else mvsdio_data->clock = 200000000; - mvsdio_data->dram = &kirkwood_mbus_dram_info; kirkwood_clk_ctrl |= CGC_SDIO; kirkwood_sdio.dev.platform_data = mvsdio_data; platform_device_register(&kirkwood_sdio); @@ -285,8 +282,7 @@ static void __init kirkwood_xor0_init(void) { kirkwood_clk_ctrl |= CGC_XOR0; - orion_xor0_init(&kirkwood_mbus_dram_info, - XOR0_PHYS_BASE, XOR0_HIGH_PHYS_BASE, + orion_xor0_init(XOR0_PHYS_BASE, XOR0_HIGH_PHYS_BASE, IRQ_KIRKWOOD_XOR_00, IRQ_KIRKWOOD_XOR_01); } @@ -364,7 +360,6 @@ static struct resource kirkwood_i2s_resources[] = { }; static struct kirkwood_asoc_platform_data kirkwood_i2s_data = { - .dram = &kirkwood_mbus_dram_info, .burst = 128, }; @@ -430,6 +425,8 @@ static char * __init kirkwood_id(void) } else if (dev == MV88F6282_DEV_ID) { if (rev == MV88F6282_REV_A0) return "MV88F6282-Rev-A0"; + else if (rev == MV88F6282_REV_A1) + return "MV88F6282-Rev-A1"; else return "MV88F6282-Rev-Unsupported"; } else { diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h index 1529280246d..9071a397136 100644 --- a/arch/arm/mach-kirkwood/common.h +++ b/arch/arm/mach-kirkwood/common.h @@ -30,7 +30,6 @@ void kirkwood_init(void); void kirkwood_init_early(void); void kirkwood_init_irq(void); -extern struct mbus_dram_target_info kirkwood_mbus_dram_info; void kirkwood_setup_cpu_mbus(void); void kirkwood_enable_pcie(void); diff --git a/arch/arm/mach-kirkwood/include/mach/kirkwood.h b/arch/arm/mach-kirkwood/include/mach/kirkwood.h index 010bdeb4ac5..fede3d503ef 100644 --- a/arch/arm/mach-kirkwood/include/mach/kirkwood.h +++ b/arch/arm/mach-kirkwood/include/mach/kirkwood.h @@ -135,4 +135,5 @@ #define MV88F6282_DEV_ID 0x6282 #define MV88F6282_REV_A0 0 +#define MV88F6282_REV_A1 1 #endif diff --git a/arch/arm/mach-kirkwood/mpp.c b/arch/arm/mach-kirkwood/mpp.c index cc431fa22cc..0c6ad63f10c 100644 --- a/arch/arm/mach-kirkwood/mpp.c +++ b/arch/arm/mach-kirkwood/mpp.c @@ -10,7 +10,6 @@ #include <linux/gpio.h> #include <linux/kernel.h> #include <linux/init.h> -#include <linux/mbus.h> #include <linux/io.h> #include <mach/hardware.h> #include <plat/mpp.h> diff --git a/arch/arm/mach-kirkwood/mpp.h b/arch/arm/mach-kirkwood/mpp.h index ac787957e2d..e8fda45c073 100644 --- a/arch/arm/mach-kirkwood/mpp.h +++ b/arch/arm/mach-kirkwood/mpp.h @@ -102,6 +102,7 @@ #define MPP11_SATA0_ACTn MPP( 11, 0x5, 0, 1, 0, 1, 1, 1, 1 ) #define MPP12_GPO MPP( 12, 0x0, 0, 1, 1, 1, 1, 1, 1 ) +#define MPP12_GPIO MPP( 12, 0x0, 1, 1, 0, 0, 0, 1, 0 ) #define MPP12_SD_CLK MPP( 12, 0x1, 0, 1, 1, 1, 1, 1, 1 ) #define MPP12_AU_SPDIF0 MPP( 12, 0xa, 0, 1, 0, 0, 0, 0, 1 ) #define MPP12_SPI_MOSI MPP( 12, 0xb, 0, 1, 0, 0, 0, 0, 1 ) diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c index 74b992d810e..a066a6d8d9d 100644 --- a/arch/arm/mach-kirkwood/pcie.c +++ b/arch/arm/mach-kirkwood/pcie.c @@ -11,12 +11,12 @@ #include <linux/kernel.h> #include <linux/pci.h> #include <linux/slab.h> -#include <linux/mbus.h> #include <video/vga.h> #include <asm/irq.h> #include <asm/mach/pci.h> #include <plat/pcie.h> #include <mach/bridge-regs.h> +#include <plat/addr-map.h> #include "common.h" void kirkwood_enable_pcie(void) @@ -198,9 +198,8 @@ static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys) if (request_resource(&iomem_resource, &pp->res[1])) panic("Request PCIe%d Memory resource failed\n", index); - sys->resource[0] = &pp->res[0]; - sys->resource[1] = &pp->res[1]; - sys->resource[2] = NULL; + pci_add_resource(&sys->resources, &pp->res[0]); + pci_add_resource(&sys->resources, &pp->res[1]); sys->io_offset = 0; /* @@ -208,7 +207,7 @@ static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys) */ orion_pcie_set_local_bus_nr(pp->base, sys->busnr); - orion_pcie_setup(pp->base, &kirkwood_mbus_dram_info); + orion_pcie_setup(pp->base); return 1; } @@ -236,7 +235,8 @@ kirkwood_pcie_scan_bus(int nr, struct pci_sys_data *sys) struct pci_bus *bus; if (nr < num_pcie_ports) { - bus = pci_scan_bus(sys->busnr, &pcie_ops, sys); + bus = pci_scan_root_bus(NULL, sys->busnr, &pcie_ops, sys, + &sys->resources); } else { bus = NULL; BUG(); diff --git a/arch/arm/mach-ks8695/irq.c b/arch/arm/mach-ks8695/irq.c index a78092dcd6f..76802aac0f4 100644 --- a/arch/arm/mach-ks8695/irq.c +++ b/arch/arm/mach-ks8695/irq.c @@ -23,7 +23,7 @@ #include <linux/module.h> #include <linux/interrupt.h> #include <linux/ioport.h> -#include <linux/sysdev.h> +#include <linux/device.h> #include <linux/io.h> #include <mach/hardware.h> diff --git a/arch/arm/mach-ks8695/pci.c b/arch/arm/mach-ks8695/pci.c index c7c9a188d10..b26f992071d 100644 --- a/arch/arm/mach-ks8695/pci.c +++ b/arch/arm/mach-ks8695/pci.c @@ -143,7 +143,8 @@ static struct pci_ops ks8695_pci_ops = { static struct pci_bus* __init ks8695_pci_scan_bus(int nr, struct pci_sys_data *sys) { - return pci_scan_bus(sys->busnr, &ks8695_pci_ops, sys); + return pci_scan_root_bus(NULL, sys->busnr, &ks8695_pci_ops, sys, + &sys->resources); } static struct resource pci_mem = { @@ -168,9 +169,8 @@ static int __init ks8695_pci_setup(int nr, struct pci_sys_data *sys) request_resource(&iomem_resource, &pci_mem); request_resource(&ioport_resource, &pci_io); - sys->resource[0] = &pci_io; - sys->resource[1] = &pci_mem; - sys->resource[2] = NULL; + pci_add_resource(&sys->resources, &pci_io); + pci_add_resource(&sys->resources, &pci_mem); /* Assign and enable processor bridge */ ks8695_local_writeconfig(PCI_BASE_ADDRESS_0, KS8695_PCIMEM_PA); diff --git a/arch/arm/mach-lpc32xx/phy3250.c b/arch/arm/mach-lpc32xx/phy3250.c index ecb94114c81..bfee5b45510 100644 --- a/arch/arm/mach-lpc32xx/phy3250.c +++ b/arch/arm/mach-lpc32xx/phy3250.c @@ -18,7 +18,7 @@ #include <linux/init.h> #include <linux/platform_device.h> -#include <linux/sysdev.h> +#include <linux/device.h> #include <linux/interrupt.h> #include <linux/irq.h> #include <linux/dma-mapping.h> diff --git a/arch/arm/mach-mmp/aspenite.c b/arch/arm/mach-mmp/aspenite.c index 3e6dfab59ef..17cb7606012 100644 --- a/arch/arm/mach-mmp/aspenite.c +++ b/arch/arm/mach-mmp/aspenite.c @@ -120,8 +120,8 @@ static struct resource smc91x_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = gpio_to_irq(27), - .end = gpio_to_irq(27), + .start = MMP_GPIO_TO_IRQ(27), + .end = MMP_GPIO_TO_IRQ(27), .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, } }; @@ -232,6 +232,7 @@ static void __init common_init(void) pxa168_add_nand(&aspenite_nand_info); pxa168_add_fb(&aspenite_lcd_info); pxa168_add_keypad(&aspenite_keypad_info); + platform_device_register(&pxa168_device_gpio); /* off-chip devices */ platform_device_register(&smc91x_device); diff --git a/arch/arm/mach-mmp/avengers_lite.c b/arch/arm/mach-mmp/avengers_lite.c index 8de3dc6131a..b148a9dc5a4 100644 --- a/arch/arm/mach-mmp/avengers_lite.c +++ b/arch/arm/mach-mmp/avengers_lite.c @@ -38,6 +38,7 @@ static void __init avengers_lite_init(void) /* on-chip devices */ pxa168_add_uart(2); + platform_device_register(&pxa168_device_gpio); } MACHINE_START(AVENGERS_LITE, "PXA168 Avengers lite Development Platform") diff --git a/arch/arm/mach-mmp/brownstone.c b/arch/arm/mach-mmp/brownstone.c index e16f04b39b1..d839fe6421e 100644 --- a/arch/arm/mach-mmp/brownstone.c +++ b/arch/arm/mach-mmp/brownstone.c @@ -202,6 +202,7 @@ static void __init brownstone_init(void) /* on-chip devices */ mmp2_add_uart(1); mmp2_add_uart(3); + platform_device_register(&mmp2_device_gpio); mmp2_add_twsi(1, NULL, ARRAY_AND_SIZE(brownstone_twsi1_info)); mmp2_add_sdhost(0, &mmp2_sdh_platdata_mmc0); /* SD/MMC */ mmp2_add_sdhost(2, &mmp2_sdh_platdata_mmc2); /* eMMC */ diff --git a/arch/arm/mach-mmp/flint.c b/arch/arm/mach-mmp/flint.c index 5a6a27a6cfd..2ee8cd7829d 100644 --- a/arch/arm/mach-mmp/flint.c +++ b/arch/arm/mach-mmp/flint.c @@ -87,8 +87,8 @@ static struct resource smc91x_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = gpio_to_irq(155), - .end = gpio_to_irq(155), + .start = MMP_GPIO_TO_IRQ(155), + .end = MMP_GPIO_TO_IRQ(155), .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, } }; @@ -110,6 +110,7 @@ static void __init flint_init(void) /* on-chip devices */ mmp2_add_uart(1); mmp2_add_uart(2); + platform_device_register(&mmp2_device_gpio); /* off-chip devices */ platform_device_register(&smc91x_device); diff --git a/arch/arm/mach-mmp/gplugd.c b/arch/arm/mach-mmp/gplugd.c index 1e3abbe37ca..87765467de6 100644 --- a/arch/arm/mach-mmp/gplugd.c +++ b/arch/arm/mach-mmp/gplugd.c @@ -184,6 +184,7 @@ static void __init gplugd_init(void) pxa168_add_uart(3); pxa168_add_ssp(1); pxa168_add_twsi(0, NULL, ARRAY_AND_SIZE(gplugd_i2c_board_info)); + platform_device_register(&pxa168_device_gpio); pxa168_add_eth(&gplugd_eth_platform_data); } diff --git a/arch/arm/mach-mmp/include/mach/gpio-pxa.h b/arch/arm/mach-mmp/include/mach/gpio-pxa.h index 99b4ce1b656..0e135a599f3 100644 --- a/arch/arm/mach-mmp/include/mach/gpio-pxa.h +++ b/arch/arm/mach-mmp/include/mach/gpio-pxa.h @@ -2,6 +2,7 @@ #define __ASM_MACH_GPIO_PXA_H #include <mach/addr-map.h> +#include <mach/cputype.h> #include <mach/irqs.h> #define GPIO_REGS_VIRT (APB_VIRT_BASE + 0x19000) @@ -9,8 +10,6 @@ #define BANK_OFF(n) (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2)) #define GPIO_REG(x) (*(volatile u32 *)(GPIO_REGS_VIRT + (x))) -#define NR_BUILTIN_GPIO IRQ_GPIO_NUM - #define gpio_to_bank(gpio) ((gpio) >> 5) /* NOTE: these macros are defined here to make optimization of diff --git a/arch/arm/mach-mmp/include/mach/gpio.h b/arch/arm/mach-mmp/include/mach/gpio.h index 681262359d1..13219ebf512 100644 --- a/arch/arm/mach-mmp/include/mach/gpio.h +++ b/arch/arm/mach-mmp/include/mach/gpio.h @@ -3,11 +3,6 @@ #include <asm-generic/gpio.h> -#define gpio_to_irq(gpio) (IRQ_GPIO_START + (gpio)) -#define irq_to_gpio(irq) ((irq) - IRQ_GPIO_START) +#include <mach/cputype.h> -#define __gpio_is_inverted(gpio) (0) -#define __gpio_is_occupied(gpio) (0) - -#include <plat/gpio.h> #endif /* __ASM_MACH_GPIO_H */ diff --git a/arch/arm/mach-mmp/include/mach/irqs.h b/arch/arm/mach-mmp/include/mach/irqs.h index a09d328e2dd..34635a0bbb5 100644 --- a/arch/arm/mach-mmp/include/mach/irqs.h +++ b/arch/arm/mach-mmp/include/mach/irqs.h @@ -219,10 +219,10 @@ #define IRQ_MMP2_MUX_END (IRQ_MMP2_SSP_BASE + 2) #define IRQ_GPIO_START 128 -#define IRQ_GPIO_NUM 192 -#define IRQ_GPIO(x) (IRQ_GPIO_START + (x)) +#define MMP_NR_BUILTIN_GPIO 192 +#define MMP_GPIO_TO_IRQ(gpio) (IRQ_GPIO_START + (gpio)) -#define IRQ_BOARD_START (IRQ_GPIO_START + IRQ_GPIO_NUM) +#define IRQ_BOARD_START (IRQ_GPIO_START + MMP_NR_BUILTIN_GPIO) #define NR_IRQS (IRQ_BOARD_START) diff --git a/arch/arm/mach-mmp/include/mach/mmp2.h b/arch/arm/mach-mmp/include/mach/mmp2.h index 2f7b2d3c2b1..cba22fed226 100644 --- a/arch/arm/mach-mmp/include/mach/mmp2.h +++ b/arch/arm/mach-mmp/include/mach/mmp2.h @@ -32,6 +32,8 @@ extern struct pxa_device_desc mmp2_device_sdh3; extern struct pxa_device_desc mmp2_device_asram; extern struct pxa_device_desc mmp2_device_isram; +extern struct platform_device mmp2_device_gpio; + static inline int mmp2_add_uart(int id) { struct pxa_device_desc *d = NULL; diff --git a/arch/arm/mach-mmp/include/mach/pxa168.h b/arch/arm/mach-mmp/include/mach/pxa168.h index a677aa732c2..dc03d580a06 100644 --- a/arch/arm/mach-mmp/include/mach/pxa168.h +++ b/arch/arm/mach-mmp/include/mach/pxa168.h @@ -43,6 +43,8 @@ struct pxa168_usb_pdata { /* pdata can be NULL */ int __init pxa168_add_usb_host(struct pxa168_usb_pdata *pdata); +extern struct platform_device pxa168_device_gpio; + static inline int pxa168_add_uart(int id) { struct pxa_device_desc *d = NULL; diff --git a/arch/arm/mach-mmp/include/mach/pxa910.h b/arch/arm/mach-mmp/include/mach/pxa910.h index 91be7559139..4de13abef7b 100644 --- a/arch/arm/mach-mmp/include/mach/pxa910.h +++ b/arch/arm/mach-mmp/include/mach/pxa910.h @@ -21,6 +21,8 @@ extern struct pxa_device_desc pxa910_device_pwm3; extern struct pxa_device_desc pxa910_device_pwm4; extern struct pxa_device_desc pxa910_device_nand; +extern struct platform_device pxa910_device_gpio; + static inline int pxa910_add_uart(int id) { struct pxa_device_desc *d = NULL; diff --git a/arch/arm/mach-mmp/mmp2.c b/arch/arm/mach-mmp/mmp2.c index 5dd1d4a6aeb..617c60a170a 100644 --- a/arch/arm/mach-mmp/mmp2.c +++ b/arch/arm/mach-mmp/mmp2.c @@ -13,6 +13,7 @@ #include <linux/kernel.h> #include <linux/init.h> #include <linux/io.h> +#include <linux/platform_device.h> #include <asm/hardware/cache-tauros2.h> @@ -24,7 +25,6 @@ #include <mach/irqs.h> #include <mach/dma.h> #include <mach/mfp.h> -#include <mach/gpio-pxa.h> #include <mach/devices.h> #include <mach/mmp2.h> @@ -33,8 +33,6 @@ #define MFPR_VIRT_BASE (APB_VIRT_BASE + 0x1e000) -#define APMASK(i) (GPIO_REGS_VIRT + BANK_OFF(i) + 0x9c) - static struct mfp_addr_map mmp2_addr_map[] __initdata = { MFP_ADDR_X(GPIO0, GPIO58, 0x54), @@ -95,24 +93,9 @@ void mmp2_clear_pmic_int(void) __raw_writel(data, mfpr_pmic); } -static void __init mmp2_init_gpio(void) -{ - int i; - - /* enable GPIO clock */ - __raw_writel(APBC_APBCLK | APBC_FNCLK, APBC_MMP2_GPIO); - - /* unmask GPIO edge detection for all 6 banks -- APMASKx */ - for (i = 0; i < 6; i++) - __raw_writel(0xffffffff, APMASK(i)); - - pxa_init_gpio(IRQ_MMP2_GPIO, 0, 167, NULL); -} - void __init mmp2_init_irq(void) { mmp2_init_icu(); - mmp2_init_gpio(); } static void sdhc_clk_enable(struct clk *clk) @@ -149,6 +132,7 @@ static APBC_CLK(twsi3, MMP2_TWSI3, 0, 26000000); static APBC_CLK(twsi4, MMP2_TWSI4, 0, 26000000); static APBC_CLK(twsi5, MMP2_TWSI5, 0, 26000000); static APBC_CLK(twsi6, MMP2_TWSI6, 0, 26000000); +static APBC_CLK(gpio, MMP2_GPIO, 0, 26000000); static APMU_CLK(nand, NAND, 0xbf, 100000000); static APMU_CLK_OPS(sdh0, SDH0, 0x1b, 200000000, &sdhc_clk_ops); @@ -168,6 +152,7 @@ static struct clk_lookup mmp2_clkregs[] = { INIT_CLKREG(&clk_twsi5, "pxa2xx-i2c.4", NULL), INIT_CLKREG(&clk_twsi6, "pxa2xx-i2c.5", NULL), INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL), + INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL), INIT_CLKREG(&clk_sdh0, "sdhci-pxav3.0", "PXA-SDHCLK"), INIT_CLKREG(&clk_sdh1, "sdhci-pxav3.1", "PXA-SDHCLK"), INIT_CLKREG(&clk_sdh2, "sdhci-pxav3.2", "PXA-SDHCLK"), @@ -230,3 +215,21 @@ MMP2_DEVICE(asram, "asram", -1, NONE, 0xe0000000, 0x4000); /* 0xd1000000 ~ 0xd101ffff is reserved for secure processor */ MMP2_DEVICE(isram, "isram", -1, NONE, 0xd1020000, 0x18000); +struct resource mmp2_resource_gpio[] = { + { + .start = 0xd4019000, + .end = 0xd4019fff, + .flags = IORESOURCE_MEM, + }, { + .start = IRQ_MMP2_GPIO, + .end = IRQ_MMP2_GPIO, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device mmp2_device_gpio = { + .name = "pxa-gpio", + .id = -1, + .num_resources = ARRAY_SIZE(mmp2_resource_gpio), + .resource = mmp2_resource_gpio, +}; diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c index 13f23867a86..7bc17eaa12e 100644 --- a/arch/arm/mach-mmp/pxa168.c +++ b/arch/arm/mach-mmp/pxa168.c @@ -13,6 +13,7 @@ #include <linux/list.h> #include <linux/io.h> #include <linux/clk.h> +#include <linux/platform_device.h> #include <asm/mach/time.h> #include <mach/addr-map.h> @@ -20,7 +21,6 @@ #include <mach/regs-apbc.h> #include <mach/regs-apmu.h> #include <mach/irqs.h> -#include <mach/gpio-pxa.h> #include <mach/dma.h> #include <mach/devices.h> #include <mach/mfp.h> @@ -43,26 +43,9 @@ static struct mfp_addr_map pxa168_mfp_addr_map[] __initdata = MFP_ADDR_END, }; -#define APMASK(i) (GPIO_REGS_VIRT + BANK_OFF(i) + 0x09c) - -static void __init pxa168_init_gpio(void) -{ - int i; - - /* enable GPIO clock */ - __raw_writel(APBC_APBCLK | APBC_FNCLK, APBC_PXA168_GPIO); - - /* unmask GPIO edge detection for all 4 banks - APMASKx */ - for (i = 0; i < 4; i++) - __raw_writel(0xffffffff, APMASK(i)); - - pxa_init_gpio(IRQ_PXA168_GPIOX, 0, 127, NULL); -} - void __init pxa168_init_irq(void) { icu_init_irq(); - pxa168_init_gpio(); } /* APB peripheral clocks */ @@ -80,6 +63,7 @@ static APBC_CLK(ssp2, PXA168_SSP2, 4, 0); static APBC_CLK(ssp3, PXA168_SSP3, 4, 0); static APBC_CLK(ssp4, PXA168_SSP4, 4, 0); static APBC_CLK(ssp5, PXA168_SSP5, 4, 0); +static APBC_CLK(gpio, PXA168_GPIO, 0, 13000000); static APBC_CLK(keypad, PXA168_KPC, 0, 32000); static APMU_CLK(nand, NAND, 0x19b, 156000000); @@ -105,6 +89,7 @@ static struct clk_lookup pxa168_clkregs[] = { INIT_CLKREG(&clk_ssp5, "pxa168-ssp.4", NULL), INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL), INIT_CLKREG(&clk_lcd, "pxa168-fb", NULL), + INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL), INIT_CLKREG(&clk_keypad, "pxa27x-keypad", NULL), INIT_CLKREG(&clk_eth, "pxa168-eth", "MFUCLK"), INIT_CLKREG(&clk_usb, "pxa168-ehci", "PXA168-USBCLK"), @@ -174,6 +159,25 @@ PXA168_DEVICE(fb, "pxa168-fb", -1, LCD, 0xd420b000, 0x1c8); PXA168_DEVICE(keypad, "pxa27x-keypad", -1, KEYPAD, 0xd4012000, 0x4c); PXA168_DEVICE(eth, "pxa168-eth", -1, MFU, 0xc0800000, 0x0fff); +struct resource pxa168_resource_gpio[] = { + { + .start = 0xd4019000, + .end = 0xd4019fff, + .flags = IORESOURCE_MEM, + }, { + .start = IRQ_PXA168_GPIOX, + .end = IRQ_PXA168_GPIOX, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device pxa168_device_gpio = { + .name = "pxa-gpio", + .id = -1, + .num_resources = ARRAY_SIZE(pxa168_resource_gpio), + .resource = pxa168_resource_gpio, +}; + struct resource pxa168_usb_host_resources[] = { /* USB Host conroller register base */ [0] = { diff --git a/arch/arm/mach-mmp/pxa910.c b/arch/arm/mach-mmp/pxa910.c index 4ebbfbba39f..3241a25784d 100644 --- a/arch/arm/mach-mmp/pxa910.c +++ b/arch/arm/mach-mmp/pxa910.c @@ -12,6 +12,7 @@ #include <linux/init.h> #include <linux/list.h> #include <linux/io.h> +#include <linux/platform_device.h> #include <asm/mach/time.h> #include <mach/addr-map.h> @@ -19,7 +20,6 @@ #include <mach/regs-apmu.h> #include <mach/cputype.h> #include <mach/irqs.h> -#include <mach/gpio-pxa.h> #include <mach/dma.h> #include <mach/mfp.h> #include <mach/devices.h> @@ -77,26 +77,9 @@ static struct mfp_addr_map pxa910_mfp_addr_map[] __initdata = MFP_ADDR_END, }; -#define APMASK(i) (GPIO_REGS_VIRT + BANK_OFF(i) + 0x09c) - -static void __init pxa910_init_gpio(void) -{ - int i; - - /* enable GPIO clock */ - __raw_writel(APBC_APBCLK | APBC_FNCLK, APBC_PXA910_GPIO); - - /* unmask GPIO edge detection for all 4 banks - APMASKx */ - for (i = 0; i < 4; i++) - __raw_writel(0xffffffff, APMASK(i)); - - pxa_init_gpio(IRQ_PXA910_AP_GPIO, 0, 127, NULL); -} - void __init pxa910_init_irq(void) { icu_init_irq(); - pxa910_init_gpio(); } /* APB peripheral clocks */ @@ -108,6 +91,7 @@ static APBC_CLK(pwm1, PXA910_PWM1, 1, 13000000); static APBC_CLK(pwm2, PXA910_PWM2, 1, 13000000); static APBC_CLK(pwm3, PXA910_PWM3, 1, 13000000); static APBC_CLK(pwm4, PXA910_PWM4, 1, 13000000); +static APBC_CLK(gpio, PXA910_GPIO, 0, 13000000); static APMU_CLK(nand, NAND, 0x19b, 156000000); static APMU_CLK(u2o, USB, 0x1b, 480000000); @@ -123,6 +107,7 @@ static struct clk_lookup pxa910_clkregs[] = { INIT_CLKREG(&clk_pwm3, "pxa910-pwm.2", NULL), INIT_CLKREG(&clk_pwm4, "pxa910-pwm.3", NULL), INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL), + INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL), INIT_CLKREG(&clk_u2o, "pxa-u2o", "U2OCLK"), }; @@ -179,3 +164,22 @@ PXA910_DEVICE(pwm2, "pxa910-pwm", 1, NONE, 0xd401a400, 0x10); PXA910_DEVICE(pwm3, "pxa910-pwm", 2, NONE, 0xd401a800, 0x10); PXA910_DEVICE(pwm4, "pxa910-pwm", 3, NONE, 0xd401ac00, 0x10); PXA910_DEVICE(nand, "pxa3xx-nand", -1, NAND, 0xd4283000, 0x80, 97, 99); + +struct resource pxa910_resource_gpio[] = { + { + .start = 0xd4019000, + .end = 0xd4019fff, + .flags = IORESOURCE_MEM, + }, { + .start = IRQ_PXA910_AP_GPIO, + .end = IRQ_PXA910_AP_GPIO, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device pxa910_device_gpio = { + .name = "pxa-gpio", + .id = -1, + .num_resources = ARRAY_SIZE(pxa910_resource_gpio), + .resource = pxa910_resource_gpio, +}; diff --git a/arch/arm/mach-mmp/tavorevb.c b/arch/arm/mach-mmp/tavorevb.c index 257a21283ec..8e3b5af04a5 100644 --- a/arch/arm/mach-mmp/tavorevb.c +++ b/arch/arm/mach-mmp/tavorevb.c @@ -19,6 +19,7 @@ #include <mach/addr-map.h> #include <mach/mfp-pxa910.h> #include <mach/pxa910.h> +#include <mach/irqs.h> #include "common.h" @@ -71,8 +72,8 @@ static struct resource smc91x_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = gpio_to_irq(80), - .end = gpio_to_irq(80), + .start = MMP_GPIO_TO_IRQ(80), + .end = MMP_GPIO_TO_IRQ(80), .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, } }; @@ -93,6 +94,7 @@ static void __init tavorevb_init(void) /* on-chip devices */ pxa910_add_uart(1); + platform_device_register(&pxa910_device_gpio); /* off-chip devices */ platform_device_register(&smc91x_device); diff --git a/arch/arm/mach-mmp/teton_bga.c b/arch/arm/mach-mmp/teton_bga.c index 8ac22a62bf1..0523e422990 100644 --- a/arch/arm/mach-mmp/teton_bga.c +++ b/arch/arm/mach-mmp/teton_bga.c @@ -66,7 +66,7 @@ static struct pxa27x_keypad_platform_data teton_bga_keypad_info __initdata = { static struct i2c_board_info teton_bga_i2c_info[] __initdata = { { I2C_BOARD_INFO("ds1337", 0x68), - .irq = gpio_to_irq(RTC_INT_GPIO) + .irq = MMP_GPIO_TO_IRQ(RTC_INT_GPIO) }, }; @@ -78,6 +78,7 @@ static void __init teton_bga_init(void) pxa168_add_uart(1); pxa168_add_keypad(&teton_bga_keypad_info); pxa168_add_twsi(0, NULL, ARRAY_AND_SIZE(teton_bga_i2c_info)); + platform_device_register(&pxa168_device_gpio); } MACHINE_START(TETON_BGA, "PXA168-based Teton BGA Development Platform") diff --git a/arch/arm/mach-mmp/ttc_dkb.c b/arch/arm/mach-mmp/ttc_dkb.c index f0265882557..5ac5d5832e4 100644 --- a/arch/arm/mach-mmp/ttc_dkb.c +++ b/arch/arm/mach-mmp/ttc_dkb.c @@ -24,12 +24,13 @@ #include <mach/addr-map.h> #include <mach/mfp-pxa910.h> #include <mach/pxa910.h> +#include <mach/irqs.h> #include "common.h" -#define TTCDKB_GPIO_EXT0(x) (NR_BUILTIN_GPIO + ((x < 0) ? 0 : \ +#define TTCDKB_GPIO_EXT0(x) (MMP_NR_BUILTIN_GPIO + ((x < 0) ? 0 : \ ((x < 16) ? x : 15))) -#define TTCDKB_GPIO_EXT1(x) (NR_BUILTIN_GPIO + 16 + ((x < 0) ? 0 : \ +#define TTCDKB_GPIO_EXT1(x) (MMP_NR_BUILTIN_GPIO + 16 + ((x < 0) ? 0 : \ ((x < 16) ? x : 15))) /* @@ -122,6 +123,7 @@ static struct platform_device ttc_dkb_device_onenand = { }; static struct platform_device *ttc_dkb_devices[] = { + &pxa910_device_gpio, &ttc_dkb_device_onenand, }; @@ -136,7 +138,7 @@ static struct i2c_board_info ttc_dkb_i2c_info[] = { { .type = "max7312", .addr = 0x23, - .irq = IRQ_GPIO(80), + .irq = MMP_GPIO_TO_IRQ(80), .platform_data = &max7312_data, }, }; diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig index e6beaff7621..1cd40ad301d 100644 --- a/arch/arm/mach-msm/Kconfig +++ b/arch/arm/mach-msm/Kconfig @@ -13,7 +13,6 @@ config ARCH_MSM7X00A select CPU_V6 select GPIO_MSM_V1 select MSM_PROC_COMM - select HAS_MSM_DEBUG_UART_PHYS config ARCH_MSM7X30 bool "MSM7x30" @@ -25,7 +24,6 @@ config ARCH_MSM7X30 select MSM_GPIOMUX select GPIO_MSM_V1 select MSM_PROC_COMM - select HAS_MSM_DEBUG_UART_PHYS config ARCH_QSD8X50 bool "QSD8X50" @@ -37,7 +35,6 @@ config ARCH_QSD8X50 select MSM_GPIOMUX select GPIO_MSM_V1 select MSM_PROC_COMM - select HAS_MSM_DEBUG_UART_PHYS config ARCH_MSM8X60 bool "MSM8X60" @@ -63,6 +60,9 @@ config ARCH_MSM8960 endchoice +config MSM_HAS_DEBUG_UART_HS + bool + config MSM_SOC_REV_A bool config ARCH_MSM_SCORPIONMP @@ -74,9 +74,6 @@ config ARCH_MSM_ARM11 config ARCH_MSM_SCORPION bool -config HAS_MSM_DEBUG_UART_PHYS - bool - config MSM_VIC bool @@ -153,32 +150,6 @@ config MACH_MSM8960_RUMI3 endmenu -config MSM_DEBUG_UART - int - default 1 if MSM_DEBUG_UART1 - default 2 if MSM_DEBUG_UART2 - default 3 if MSM_DEBUG_UART3 - -if HAS_MSM_DEBUG_UART_PHYS -choice - prompt "Debug UART" - - default MSM_DEBUG_UART_NONE - - config MSM_DEBUG_UART_NONE - bool "None" - - config MSM_DEBUG_UART1 - bool "UART1" - - config MSM_DEBUG_UART2 - bool "UART2" - - config MSM_DEBUG_UART3 - bool "UART3" -endchoice -endif - config MSM_SMD_PKG3 bool diff --git a/arch/arm/mach-msm/board-sapphire.c b/arch/arm/mach-msm/board-sapphire.c index 32b465763db..97b8191d9d3 100644 --- a/arch/arm/mach-msm/board-sapphire.c +++ b/arch/arm/mach-msm/board-sapphire.c @@ -18,7 +18,7 @@ #include <linux/input.h> #include <linux/interrupt.h> #include <linux/irq.h> -#include <linux/sysdev.h> +#include <linux/device.h> #include <linux/delay.h> diff --git a/arch/arm/mach-msm/include/mach/debug-macro.S b/arch/arm/mach-msm/include/mach/debug-macro.S index 2dc73ccddb1..3ffd8668c9a 100644 --- a/arch/arm/mach-msm/include/mach/debug-macro.S +++ b/arch/arm/mach-msm/include/mach/debug-macro.S @@ -1,6 +1,7 @@ -/* arch/arm/mach-msm7200/include/mach/debug-macro.S +/* * * Copyright (C) 2007 Google, Inc. + * Copyright (c) 2011, Code Aurora Forum. All rights reserved. * Author: Brian Swetland <swetland@google.com> * * This software is licensed under the terms of the GNU General Public @@ -14,40 +15,52 @@ * */ - - #include <mach/hardware.h> #include <mach/msm_iomap.h> -#if defined(CONFIG_HAS_MSM_DEBUG_UART_PHYS) && !defined(CONFIG_MSM_DEBUG_UART_NONE) .macro addruart, rp, rv, tmp +#ifdef MSM_DEBUG_UART_PHYS ldr \rp, =MSM_DEBUG_UART_PHYS ldr \rv, =MSM_DEBUG_UART_BASE +#endif .endm - .macro senduart,rd,rx + .macro senduart, rd, rx +#ifdef CONFIG_MSM_HAS_DEBUG_UART_HS + @ Write the 1 character to UARTDM_TF + str \rd, [\rx, #0x70] +#else teq \rx, #0 strne \rd, [\rx, #0x0C] +#endif .endm - .macro waituart,rd,rx + .macro waituart, rd, rx +#ifdef CONFIG_MSM_HAS_DEBUG_UART_HS + @ check for TX_EMT in UARTDM_SR + ldr \rd, [\rx, #0x08] + tst \rd, #0x08 + bne 1002f + @ wait for TXREADY in UARTDM_ISR +1001: ldr \rd, [\rx, #0x14] + tst \rd, #0x80 + beq 1001b +1002: + @ Clear TX_READY by writing to the UARTDM_CR register + mov \rd, #0x300 + str \rd, [\rx, #0x10] + @ Write 0x1 to NCF register + mov \rd, #0x1 + str \rd, [\rx, #0x40] + @ UARTDM reg. Read to induce delay + ldr \rd, [\rx, #0x08] +#else @ wait for TX_READY 1001: ldr \rd, [\rx, #0x08] tst \rd, #0x04 beq 1001b - .endm -#else - .macro addruart, rp, rv, tmp - mov \rv, #0xff000000 - orr \rv, \rv, #0x00f00000 - .endm - - .macro senduart,rd,rx - .endm - - .macro waituart,rd,rx - .endm #endif + .endm - .macro busyuart,rd,rx + .macro busyuart, rd, rx .endm diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h b/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h index 94fe9fe6feb..8af46123dab 100644 --- a/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h +++ b/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h @@ -78,18 +78,6 @@ #define MSM_UART3_PHYS 0xA9C00000 #define MSM_UART3_SIZE SZ_4K -#ifdef CONFIG_MSM_DEBUG_UART -#define MSM_DEBUG_UART_BASE 0xE1000000 -#if CONFIG_MSM_DEBUG_UART == 1 -#define MSM_DEBUG_UART_PHYS MSM_UART1_PHYS -#elif CONFIG_MSM_DEBUG_UART == 2 -#define MSM_DEBUG_UART_PHYS MSM_UART2_PHYS -#elif CONFIG_MSM_DEBUG_UART == 3 -#define MSM_DEBUG_UART_PHYS MSM_UART3_PHYS -#endif -#define MSM_DEBUG_UART_SIZE SZ_4K -#endif - #define MSM_SDC1_PHYS 0xA0400000 #define MSM_SDC1_SIZE SZ_4K diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h b/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h index 37694442d1b..198202c267c 100644 --- a/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h +++ b/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h @@ -89,18 +89,6 @@ #define MSM_UART3_PHYS 0xACC00000 #define MSM_UART3_SIZE SZ_4K -#ifdef CONFIG_MSM_DEBUG_UART -#define MSM_DEBUG_UART_BASE 0xE1000000 -#if CONFIG_MSM_DEBUG_UART == 1 -#define MSM_DEBUG_UART_PHYS MSM_UART1_PHYS -#elif CONFIG_MSM_DEBUG_UART == 2 -#define MSM_DEBUG_UART_PHYS MSM_UART2_PHYS -#elif CONFIG_MSM_DEBUG_UART == 3 -#define MSM_DEBUG_UART_PHYS MSM_UART3_PHYS -#endif -#define MSM_DEBUG_UART_SIZE SZ_4K -#endif - #define MSM_MDC_BASE IOMEM(0xE0200000) #define MSM_MDC_PHYS 0xAA500000 #define MSM_MDC_SIZE SZ_1M diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8960.h b/arch/arm/mach-msm/include/mach/msm_iomap-8960.h index 3c9d9602a31..800b55767e6 100644 --- a/arch/arm/mach-msm/include/mach/msm_iomap-8960.h +++ b/arch/arm/mach-msm/include/mach/msm_iomap-8960.h @@ -45,4 +45,9 @@ #define MSM8960_TMR0_PHYS 0x0208A000 #define MSM8960_TMR0_SIZE SZ_4K +#ifdef CONFIG_DEBUG_MSM8960_UART +#define MSM_DEBUG_UART_BASE 0xE1040000 +#define MSM_DEBUG_UART_PHYS 0x16440000 +#endif + #endif diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h index d67cd73316f..0faa894729b 100644 --- a/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h +++ b/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h @@ -83,18 +83,6 @@ #define MSM_UART3_PHYS 0xA9C00000 #define MSM_UART3_SIZE SZ_4K -#ifdef CONFIG_MSM_DEBUG_UART -#define MSM_DEBUG_UART_BASE 0xE1000000 -#if CONFIG_MSM_DEBUG_UART == 1 -#define MSM_DEBUG_UART_PHYS MSM_UART1_PHYS -#elif CONFIG_MSM_DEBUG_UART == 2 -#define MSM_DEBUG_UART_PHYS MSM_UART2_PHYS -#elif CONFIG_MSM_DEBUG_UART == 3 -#define MSM_DEBUG_UART_PHYS MSM_UART3_PHYS -#endif -#define MSM_DEBUG_UART_SIZE SZ_4K -#endif - #define MSM_MDC_BASE IOMEM(0xE0200000) #define MSM_MDC_PHYS 0xAA500000 #define MSM_MDC_SIZE SZ_1M diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h index 3b19b8f244b..54e12caa8d8 100644 --- a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h +++ b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h @@ -62,4 +62,9 @@ #define MSM8X60_TMR0_PHYS 0x02040000 #define MSM8X60_TMR0_SIZE SZ_4K +#ifdef CONFIG_DEBUG_MSM8660_UART +#define MSM_DEBUG_UART_BASE 0xE1040000 +#define MSM_DEBUG_UART_PHYS 0x19C40000 +#endif + #endif diff --git a/arch/arm/mach-msm/include/mach/msm_iomap.h b/arch/arm/mach-msm/include/mach/msm_iomap.h index 4ded15238b6..90682f4599d 100644 --- a/arch/arm/mach-msm/include/mach/msm_iomap.h +++ b/arch/arm/mach-msm/include/mach/msm_iomap.h @@ -55,6 +55,18 @@ #include "msm_iomap-8960.h" +#define MSM_DEBUG_UART_SIZE SZ_4K +#if defined(CONFIG_DEBUG_MSM_UART1) +#define MSM_DEBUG_UART_BASE 0xE1000000 +#define MSM_DEBUG_UART_PHYS MSM_UART1_PHYS +#elif defined(CONFIG_DEBUG_MSM_UART2) +#define MSM_DEBUG_UART_BASE 0xE1000000 +#define MSM_DEBUG_UART_PHYS MSM_UART2_PHYS +#elif defined(CONFIG_DEBUG_MSM_UART3) +#define MSM_DEBUG_UART_BASE 0xE1000000 +#define MSM_DEBUG_UART_PHYS MSM_UART3_PHYS +#endif + /* Virtual addresses shared across all MSM targets. */ #define MSM_CSR_BASE IOMEM(0xE0001000) #define MSM_QGIC_DIST_BASE IOMEM(0xF0000000) diff --git a/arch/arm/mach-msm/include/mach/uncompress.h b/arch/arm/mach-msm/include/mach/uncompress.h index d94292c29d8..169a8400745 100644 --- a/arch/arm/mach-msm/include/mach/uncompress.h +++ b/arch/arm/mach-msm/include/mach/uncompress.h @@ -1,6 +1,6 @@ -/* arch/arm/mach-msm/include/mach/uncompress.h - * +/* * Copyright (C) 2007 Google, Inc. + * Copyright (c) 2011, Code Aurora Forum. All rights reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -14,17 +14,40 @@ */ #ifndef __ASM_ARCH_MSM_UNCOMPRESS_H +#define __ASM_ARCH_MSM_UNCOMPRESS_H + +#include <asm/processor.h> +#include <mach/msm_iomap.h> + +#define UART_CSR (*(volatile uint32_t *)(MSM_DEBUG_UART_PHYS + 0x08)) +#define UART_TF (*(volatile uint32_t *)(MSM_DEBUG_UART_PHYS + 0x0c)) -#include "hardware.h" -#include "linux/io.h" -#include "mach/msm_iomap.h" +#define UART_DM_SR (*((volatile uint32_t *)(MSM_DEBUG_UART_PHYS + 0x08))) +#define UART_DM_CR (*((volatile uint32_t *)(MSM_DEBUG_UART_PHYS + 0x10))) +#define UART_DM_ISR (*((volatile uint32_t *)(MSM_DEBUG_UART_PHYS + 0x14))) +#define UART_DM_NCHAR (*((volatile uint32_t *)(MSM_DEBUG_UART_PHYS + 0x40))) +#define UART_DM_TF (*((volatile uint32_t *)(MSM_DEBUG_UART_PHYS + 0x70))) static void putc(int c) { #if defined(MSM_DEBUG_UART_PHYS) - unsigned base = MSM_DEBUG_UART_PHYS; - while (!(readl(base + 0x08) & 0x04)) ; - writel(c, base + 0x0c); +#ifdef CONFIG_MSM_HAS_DEBUG_UART_HS + /* + * Wait for TX_READY to be set; but skip it if we have a + * TX underrun. + */ + if (UART_DM_SR & 0x08) + while (!(UART_DM_ISR & 0x80)) + cpu_relax(); + + UART_DM_CR = 0x300; + UART_DM_NCHAR = 0x1; + UART_DM_TF = c; +#else + while (!(UART_CSR & 0x04)) + cpu_relax(); + UART_TF = c; +#endif #endif } diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c index 8759ecf7454..578b04e42de 100644 --- a/arch/arm/mach-msm/io.c +++ b/arch/arm/mach-msm/io.c @@ -47,7 +47,8 @@ static struct map_desc msm_io_desc[] __initdata = { MSM_CHIP_DEVICE(GPIO1, MSM7X00), MSM_CHIP_DEVICE(GPIO2, MSM7X00), MSM_DEVICE(CLK_CTL), -#ifdef CONFIG_MSM_DEBUG_UART +#if defined(CONFIG_DEBUG_MSM_UART1) || defined(CONFIG_DEBUG_MSM_UART2) || \ + defined(CONFIG_DEBUG_MSM_UART3) MSM_DEVICE(DEBUG_UART), #endif #ifdef CONFIG_ARCH_MSM7X30 @@ -84,7 +85,8 @@ static struct map_desc qsd8x50_io_desc[] __initdata = { MSM_DEVICE(SCPLL), MSM_DEVICE(AD5), MSM_DEVICE(MDC), -#ifdef CONFIG_MSM_DEBUG_UART +#if defined(CONFIG_DEBUG_MSM_UART1) || defined(CONFIG_DEBUG_MSM_UART2) || \ + defined(CONFIG_DEBUG_MSM_UART3) MSM_DEVICE(DEBUG_UART), #endif { @@ -109,6 +111,9 @@ static struct map_desc msm8x60_io_desc[] __initdata = { MSM_CHIP_DEVICE(TMR0, MSM8X60), MSM_DEVICE(ACC), MSM_DEVICE(GCC), +#ifdef CONFIG_DEBUG_MSM8660_UART + MSM_DEVICE(DEBUG_UART), +#endif }; void __init msm_map_msm8x60_io(void) @@ -123,6 +128,9 @@ static struct map_desc msm8960_io_desc[] __initdata = { MSM_CHIP_DEVICE(QGIC_CPU, MSM8960), MSM_CHIP_DEVICE(TMR, MSM8960), MSM_CHIP_DEVICE(TMR0, MSM8960), +#ifdef CONFIG_DEBUG_MSM8960_UART + MSM_DEVICE(DEBUG_UART), +#endif }; void __init msm_map_msm8960_io(void) @@ -146,7 +154,8 @@ static struct map_desc msm7x30_io_desc[] __initdata = { MSM_DEVICE(SAW), MSM_DEVICE(GCC), MSM_DEVICE(TCSR), -#ifdef CONFIG_MSM_DEBUG_UART +#if defined(CONFIG_DEBUG_MSM_UART1) || defined(CONFIG_DEBUG_MSM_UART2) || \ + defined(CONFIG_DEBUG_MSM_UART3) MSM_DEVICE(DEBUG_UART), #endif { diff --git a/arch/arm/mach-msm/platsmp.c b/arch/arm/mach-msm/platsmp.c index fdec58aaa35..0b3e357c4c8 100644 --- a/arch/arm/mach-msm/platsmp.c +++ b/arch/arm/mach-msm/platsmp.c @@ -79,7 +79,7 @@ static __cpuinit void prepare_cold_cpu(unsigned int cpu) ret = scm_set_boot_addr(virt_to_phys(msm_secondary_startup), SCM_FLAG_COLDBOOT_CPU1); if (ret == 0) { - void *sc1_base_ptr; + void __iomem *sc1_base_ptr; sc1_base_ptr = ioremap_nocache(0x00902000, SZ_4K*2); if (sc1_base_ptr) { writel(0, sc1_base_ptr + VDD_SC1_ARRAY_CLAMP_GFS_CTL); diff --git a/arch/arm/mach-msm/smd_debug.c b/arch/arm/mach-msm/smd_debug.c index 8736afff82f..0c56a5aaf58 100644 --- a/arch/arm/mach-msm/smd_debug.c +++ b/arch/arm/mach-msm/smd_debug.c @@ -215,7 +215,7 @@ static const struct file_operations debug_ops = { .llseek = default_llseek, }; -static void debug_create(const char *name, mode_t mode, +static void debug_create(const char *name, umode_t mode, struct dentry *dent, int (*fill)(char *buf, int max)) { diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c index afeeca52fc6..11d0d8f2656 100644 --- a/arch/arm/mach-msm/timer.c +++ b/arch/arm/mach-msm/timer.c @@ -1,6 +1,7 @@ -/* linux/arch/arm/mach-msm/timer.c +/* * * Copyright (C) 2007 Google, Inc. + * Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -13,306 +14,207 @@ * */ +#include <linux/clocksource.h> +#include <linux/clockchips.h> #include <linux/init.h> -#include <linux/time.h> #include <linux/interrupt.h> #include <linux/irq.h> -#include <linux/clk.h> -#include <linux/clockchips.h> -#include <linux/delay.h> #include <linux/io.h> #include <asm/mach/time.h> #include <asm/hardware/gic.h> +#include <asm/localtimer.h> #include <mach/msm_iomap.h> #include <mach/cpu.h> +#include <mach/board.h> #define TIMER_MATCH_VAL 0x0000 #define TIMER_COUNT_VAL 0x0004 #define TIMER_ENABLE 0x0008 -#define TIMER_ENABLE_CLR_ON_MATCH_EN 2 -#define TIMER_ENABLE_EN 1 +#define TIMER_ENABLE_CLR_ON_MATCH_EN BIT(1) +#define TIMER_ENABLE_EN BIT(0) #define TIMER_CLEAR 0x000C #define DGT_CLK_CTL 0x0034 -enum { - DGT_CLK_CTL_DIV_1 = 0, - DGT_CLK_CTL_DIV_2 = 1, - DGT_CLK_CTL_DIV_3 = 2, - DGT_CLK_CTL_DIV_4 = 3, -}; -#define CSR_PROTECTION 0x0020 -#define CSR_PROTECTION_EN 1 +#define DGT_CLK_CTL_DIV_4 0x3 #define GPT_HZ 32768 -enum timer_location { - LOCAL_TIMER = 0, - GLOBAL_TIMER = 1, -}; - -#define MSM_GLOBAL_TIMER MSM_CLOCK_DGT - -/* TODO: Remove these ifdefs */ -#if defined(CONFIG_ARCH_QSD8X50) -#define DGT_HZ (19200000 / 4) /* 19.2 MHz / 4 by default */ -#define MSM_DGT_SHIFT (0) -#elif defined(CONFIG_ARCH_MSM7X30) -#define DGT_HZ (24576000 / 4) /* 24.576 MHz (LPXO) / 4 by default */ -#define MSM_DGT_SHIFT (0) -#elif defined(CONFIG_ARCH_MSM8X60) || defined(CONFIG_ARCH_MSM8960) -#define DGT_HZ (27000000 / 4) /* 27 MHz (PXO) / 4 by default */ -#define MSM_DGT_SHIFT (0) -#else -#define DGT_HZ 19200000 /* 19.2 MHz or 600 KHz after shift */ -#define MSM_DGT_SHIFT (5) -#endif +#define MSM_DGT_SHIFT 5 -struct msm_clock { - struct clock_event_device clockevent; - struct clocksource clocksource; - unsigned int irq; - void __iomem *regbase; - uint32_t freq; - uint32_t shift; - void __iomem *global_counter; - void __iomem *local_counter; - union { - struct clock_event_device *evt; - struct clock_event_device __percpu **percpu_evt; - }; -}; - -enum { - MSM_CLOCK_GPT, - MSM_CLOCK_DGT, - NR_TIMERS, -}; - - -static struct msm_clock msm_clocks[]; +static void __iomem *event_base; static irqreturn_t msm_timer_interrupt(int irq, void *dev_id) { struct clock_event_device *evt = *(struct clock_event_device **)dev_id; - if (evt->event_handler == NULL) - return IRQ_HANDLED; + /* Stop the timer tick */ + if (evt->mode == CLOCK_EVT_MODE_ONESHOT) { + u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE); + ctrl &= ~TIMER_ENABLE_EN; + writel_relaxed(ctrl, event_base + TIMER_ENABLE); + } evt->event_handler(evt); return IRQ_HANDLED; } -static cycle_t msm_read_timer_count(struct clocksource *cs) -{ - struct msm_clock *clk = container_of(cs, struct msm_clock, clocksource); - - /* - * Shift timer count down by a constant due to unreliable lower bits - * on some targets. - */ - return readl(clk->global_counter) >> clk->shift; -} - -static struct msm_clock *clockevent_to_clock(struct clock_event_device *evt) -{ -#ifdef CONFIG_SMP - int i; - for (i = 0; i < NR_TIMERS; i++) - if (evt == &(msm_clocks[i].clockevent)) - return &msm_clocks[i]; - return &msm_clocks[MSM_GLOBAL_TIMER]; -#else - return container_of(evt, struct msm_clock, clockevent); -#endif -} - static int msm_timer_set_next_event(unsigned long cycles, struct clock_event_device *evt) { - struct msm_clock *clock = clockevent_to_clock(evt); - uint32_t now = readl(clock->local_counter); - uint32_t alarm = now + (cycles << clock->shift); + u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE); - writel(alarm, clock->regbase + TIMER_MATCH_VAL); + writel_relaxed(0, event_base + TIMER_CLEAR); + writel_relaxed(cycles, event_base + TIMER_MATCH_VAL); + writel_relaxed(ctrl | TIMER_ENABLE_EN, event_base + TIMER_ENABLE); return 0; } static void msm_timer_set_mode(enum clock_event_mode mode, struct clock_event_device *evt) { - struct msm_clock *clock = clockevent_to_clock(evt); + u32 ctrl; + + ctrl = readl_relaxed(event_base + TIMER_ENABLE); + ctrl &= ~(TIMER_ENABLE_EN | TIMER_ENABLE_CLR_ON_MATCH_EN); switch (mode) { case CLOCK_EVT_MODE_RESUME: case CLOCK_EVT_MODE_PERIODIC: break; case CLOCK_EVT_MODE_ONESHOT: - writel(TIMER_ENABLE_EN, clock->regbase + TIMER_ENABLE); + /* Timer is enabled in set_next_event */ break; case CLOCK_EVT_MODE_UNUSED: case CLOCK_EVT_MODE_SHUTDOWN: - writel(0, clock->regbase + TIMER_ENABLE); break; } + writel_relaxed(ctrl, event_base + TIMER_ENABLE); } -static struct msm_clock msm_clocks[] = { - [MSM_CLOCK_GPT] = { - .clockevent = { - .name = "gp_timer", - .features = CLOCK_EVT_FEAT_ONESHOT, - .shift = 32, - .rating = 200, - .set_next_event = msm_timer_set_next_event, - .set_mode = msm_timer_set_mode, - }, - .clocksource = { - .name = "gp_timer", - .rating = 200, - .read = msm_read_timer_count, - .mask = CLOCKSOURCE_MASK(32), - .flags = CLOCK_SOURCE_IS_CONTINUOUS, - }, - .irq = INT_GP_TIMER_EXP, - .freq = GPT_HZ, - }, - [MSM_CLOCK_DGT] = { - .clockevent = { - .name = "dg_timer", - .features = CLOCK_EVT_FEAT_ONESHOT, - .shift = 32 + MSM_DGT_SHIFT, - .rating = 300, - .set_next_event = msm_timer_set_next_event, - .set_mode = msm_timer_set_mode, - }, - .clocksource = { - .name = "dg_timer", - .rating = 300, - .read = msm_read_timer_count, - .mask = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT)), - .flags = CLOCK_SOURCE_IS_CONTINUOUS, - }, - .irq = INT_DEBUG_TIMER_EXP, - .freq = DGT_HZ >> MSM_DGT_SHIFT, - .shift = MSM_DGT_SHIFT, - } +static struct clock_event_device msm_clockevent = { + .name = "gp_timer", + .features = CLOCK_EVT_FEAT_ONESHOT, + .rating = 200, + .set_next_event = msm_timer_set_next_event, + .set_mode = msm_timer_set_mode, +}; + +static union { + struct clock_event_device *evt; + struct clock_event_device __percpu **percpu_evt; +} msm_evt; + +static void __iomem *source_base; + +static cycle_t msm_read_timer_count(struct clocksource *cs) +{ + return readl_relaxed(source_base + TIMER_COUNT_VAL); +} + +static cycle_t msm_read_timer_count_shift(struct clocksource *cs) +{ + /* + * Shift timer count down by a constant due to unreliable lower bits + * on some targets. + */ + return msm_read_timer_count(cs) >> MSM_DGT_SHIFT; +} + +static struct clocksource msm_clocksource = { + .name = "dg_timer", + .rating = 300, + .read = msm_read_timer_count, + .mask = CLOCKSOURCE_MASK(32), + .flags = CLOCK_SOURCE_IS_CONTINUOUS, }; static void __init msm_timer_init(void) { - int i; + struct clock_event_device *ce = &msm_clockevent; + struct clocksource *cs = &msm_clocksource; int res; - int global_offset = 0; + u32 dgt_hz; if (cpu_is_msm7x01()) { - msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE; - msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x10; + event_base = MSM_CSR_BASE; + source_base = MSM_CSR_BASE + 0x10; + dgt_hz = 19200000 >> MSM_DGT_SHIFT; /* 600 KHz */ + cs->read = msm_read_timer_count_shift; + cs->mask = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT)); } else if (cpu_is_msm7x30()) { - msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE + 0x04; - msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x24; + event_base = MSM_CSR_BASE + 0x04; + source_base = MSM_CSR_BASE + 0x24; + dgt_hz = 24576000 / 4; } else if (cpu_is_qsd8x50()) { - msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE; - msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x10; + event_base = MSM_CSR_BASE; + source_base = MSM_CSR_BASE + 0x10; + dgt_hz = 19200000 / 4; } else if (cpu_is_msm8x60() || cpu_is_msm8960()) { - msm_clocks[MSM_CLOCK_GPT].regbase = MSM_TMR_BASE + 0x04; - msm_clocks[MSM_CLOCK_DGT].regbase = MSM_TMR_BASE + 0x24; - - /* Use CPU0's timer as the global timer. */ - global_offset = MSM_TMR0_BASE - MSM_TMR_BASE; + event_base = MSM_TMR_BASE + 0x04; + /* Use CPU0's timer as the global clock source. */ + source_base = MSM_TMR0_BASE + 0x24; + dgt_hz = 27000000 / 4; + writel_relaxed(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL); } else BUG(); -#ifdef CONFIG_ARCH_MSM_SCORPIONMP - writel(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL); -#endif - - for (i = 0; i < ARRAY_SIZE(msm_clocks); i++) { - struct msm_clock *clock = &msm_clocks[i]; - struct clock_event_device *ce = &clock->clockevent; - struct clocksource *cs = &clock->clocksource; - - clock->local_counter = clock->regbase + TIMER_COUNT_VAL; - clock->global_counter = clock->local_counter + global_offset; - - writel(0, clock->regbase + TIMER_ENABLE); - writel(0, clock->regbase + TIMER_CLEAR); - writel(~0, clock->regbase + TIMER_MATCH_VAL); - - ce->mult = div_sc(clock->freq, NSEC_PER_SEC, ce->shift); - /* allow at least 10 seconds to notice that the timer wrapped */ - ce->max_delta_ns = - clockevent_delta2ns(0xf0000000 >> clock->shift, ce); - /* 4 gets rounded down to 3 */ - ce->min_delta_ns = clockevent_delta2ns(4, ce); - ce->cpumask = cpumask_of(0); - - res = clocksource_register_hz(cs, clock->freq); - if (res) - printk(KERN_ERR "msm_timer_init: clocksource_register " - "failed for %s\n", cs->name); - - ce->irq = clock->irq; - if (cpu_is_msm8x60() || cpu_is_msm8960()) { - clock->percpu_evt = alloc_percpu(struct clock_event_device *); - if (!clock->percpu_evt) { - pr_err("msm_timer_init: memory allocation " - "failed for %s\n", ce->name); - continue; - } - - *__this_cpu_ptr(clock->percpu_evt) = ce; - res = request_percpu_irq(ce->irq, msm_timer_interrupt, - ce->name, clock->percpu_evt); - if (!res) - enable_percpu_irq(ce->irq, 0); - } else { - clock->evt = ce; - res = request_irq(ce->irq, msm_timer_interrupt, - IRQF_TIMER | IRQF_NOBALANCING | IRQF_TRIGGER_RISING, - ce->name, &clock->evt); + writel_relaxed(0, event_base + TIMER_ENABLE); + writel_relaxed(0, event_base + TIMER_CLEAR); + writel_relaxed(~0, event_base + TIMER_MATCH_VAL); + ce->cpumask = cpumask_of(0); + + ce->irq = INT_GP_TIMER_EXP; + clockevents_config_and_register(ce, GPT_HZ, 4, 0xffffffff); + if (cpu_is_msm8x60() || cpu_is_msm8960()) { + msm_evt.percpu_evt = alloc_percpu(struct clock_event_device *); + if (!msm_evt.percpu_evt) { + pr_err("memory allocation failed for %s\n", ce->name); + goto err; } - - if (res) - pr_err("msm_timer_init: request_irq failed for %s\n", - ce->name); - - clockevents_register_device(ce); + *__this_cpu_ptr(msm_evt.percpu_evt) = ce; + res = request_percpu_irq(ce->irq, msm_timer_interrupt, + ce->name, msm_evt.percpu_evt); + if (!res) + enable_percpu_irq(ce->irq, 0); + } else { + msm_evt.evt = ce; + res = request_irq(ce->irq, msm_timer_interrupt, + IRQF_TIMER | IRQF_NOBALANCING | + IRQF_TRIGGER_RISING, ce->name, &msm_evt.evt); } + + if (res) + pr_err("request_irq failed for %s\n", ce->name); +err: + writel_relaxed(TIMER_ENABLE_EN, source_base + TIMER_ENABLE); + res = clocksource_register_hz(cs, dgt_hz); + if (res) + pr_err("clocksource_register failed\n"); } -#ifdef CONFIG_SMP +#ifdef CONFIG_LOCAL_TIMERS int __cpuinit local_timer_setup(struct clock_event_device *evt) { - static bool local_timer_inited; - struct msm_clock *clock = &msm_clocks[MSM_GLOBAL_TIMER]; - /* Use existing clock_event for cpu 0 */ if (!smp_processor_id()) return 0; - writel(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL); - - if (!local_timer_inited) { - writel(0, clock->regbase + TIMER_ENABLE); - writel(0, clock->regbase + TIMER_CLEAR); - writel(~0, clock->regbase + TIMER_MATCH_VAL); - local_timer_inited = true; - } - evt->irq = clock->irq; + writel_relaxed(0, event_base + TIMER_ENABLE); + writel_relaxed(0, event_base + TIMER_CLEAR); + writel_relaxed(~0, event_base + TIMER_MATCH_VAL); + evt->irq = msm_clockevent.irq; evt->name = "local_timer"; - evt->features = CLOCK_EVT_FEAT_ONESHOT; - evt->rating = clock->clockevent.rating; + evt->features = msm_clockevent.features; + evt->rating = msm_clockevent.rating; evt->set_mode = msm_timer_set_mode; evt->set_next_event = msm_timer_set_next_event; - evt->shift = clock->clockevent.shift; - evt->mult = div_sc(clock->freq, NSEC_PER_SEC, evt->shift); - evt->max_delta_ns = - clockevent_delta2ns(0xf0000000 >> clock->shift, evt); + evt->shift = msm_clockevent.shift; + evt->mult = div_sc(GPT_HZ, NSEC_PER_SEC, evt->shift); + evt->max_delta_ns = clockevent_delta2ns(0xf0000000, evt); evt->min_delta_ns = clockevent_delta2ns(4, evt); - *__this_cpu_ptr(clock->percpu_evt) = evt; - enable_percpu_irq(evt->irq, 0); - + *__this_cpu_ptr(msm_evt.percpu_evt) = evt; clockevents_register_device(evt); + enable_percpu_irq(evt->irq, 0); return 0; } @@ -321,8 +223,7 @@ void local_timer_stop(struct clock_event_device *evt) evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt); disable_percpu_irq(evt->irq); } - -#endif +#endif /* CONFIG_LOCAL_TIMERS */ struct sys_timer msm_timer = { .init = msm_timer_init diff --git a/arch/arm/mach-mv78xx0/addr-map.c b/arch/arm/mach-mv78xx0/addr-map.c index 311d5b0e9bc..62b53d710ef 100644 --- a/arch/arm/mach-mv78xx0/addr-map.c +++ b/arch/arm/mach-mv78xx0/addr-map.c @@ -12,12 +12,12 @@ #include <linux/init.h> #include <linux/mbus.h> #include <linux/io.h> +#include <plat/addr-map.h> #include "common.h" /* * Generic Address Decode Windows bit settings */ -#define TARGET_DDR 0 #define TARGET_DEV_BUS 1 #define TARGET_PCIE0 4 #define TARGET_PCIE1 8 @@ -32,23 +32,10 @@ #define ATTR_PCIE_MEM(l) (0xf8 & ~(0x10 << (l))) /* - * Helpers to get DDR bank info - */ -#define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3)) -#define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3)) - -/* * CPU Address Decode Windows registers */ #define WIN0_OFF(n) (BRIDGE_VIRT_BASE + 0x0000 + ((n) << 4)) #define WIN8_OFF(n) (BRIDGE_VIRT_BASE + 0x0900 + (((n) - 8) << 4)) -#define WIN_CTRL_OFF 0x0000 -#define WIN_BASE_OFF 0x0004 -#define WIN_REMAP_LO_OFF 0x0008 -#define WIN_REMAP_HI_OFF 0x000c - - -struct mbus_dram_target_info mv78xx0_mbus_dram_info; static void __init __iomem *win_cfg_base(int win) { @@ -63,94 +50,43 @@ static void __init __iomem *win_cfg_base(int win) return (void __iomem *)((win < 8) ? WIN0_OFF(win) : WIN8_OFF(win)); } -static int __init cpu_win_can_remap(int win) -{ - if (win < 8) - return 1; - - return 0; -} - -static void __init setup_cpu_win(int win, u32 base, u32 size, - u8 target, u8 attr, int remap) -{ - void __iomem *addr = win_cfg_base(win); - u32 ctrl; - - base &= 0xffff0000; - ctrl = ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1; - - writel(base, addr + WIN_BASE_OFF); - writel(ctrl, addr + WIN_CTRL_OFF); - if (cpu_win_can_remap(win)) { - if (remap < 0) - remap = base; - - writel(remap & 0xffff0000, addr + WIN_REMAP_LO_OFF); - writel(0, addr + WIN_REMAP_HI_OFF); - } -} +/* + * Description of the windows needed by the platform code + */ +static struct __initdata orion_addr_map_cfg addr_map_cfg = { + .num_wins = 14, + .remappable_wins = 8, + .win_cfg_base = win_cfg_base, +}; void __init mv78xx0_setup_cpu_mbus(void) { - void __iomem *addr; - int i; - int cs; - /* - * First, disable and clear windows. + * Disable, clear and configure windows. */ - for (i = 0; i < 14; i++) { - addr = win_cfg_base(i); - - writel(0, addr + WIN_BASE_OFF); - writel(0, addr + WIN_CTRL_OFF); - if (cpu_win_can_remap(i)) { - writel(0, addr + WIN_REMAP_LO_OFF); - writel(0, addr + WIN_REMAP_HI_OFF); - } - } + orion_config_wins(&addr_map_cfg, NULL); /* * Setup MBUS dram target info. */ - mv78xx0_mbus_dram_info.mbus_dram_target_id = TARGET_DDR; - if (mv78xx0_core_index() == 0) - addr = (void __iomem *)DDR_WINDOW_CPU0_BASE; + orion_setup_cpu_mbus_target(&addr_map_cfg, + DDR_WINDOW_CPU0_BASE); else - addr = (void __iomem *)DDR_WINDOW_CPU1_BASE; - - for (i = 0, cs = 0; i < 4; i++) { - u32 base = readl(addr + DDR_BASE_CS_OFF(i)); - u32 size = readl(addr + DDR_SIZE_CS_OFF(i)); - - /* - * Chip select enabled? - */ - if (size & 1) { - struct mbus_dram_window *w; - - w = &mv78xx0_mbus_dram_info.cs[cs++]; - w->cs_index = i; - w->mbus_attr = 0xf & ~(1 << i); - w->base = base & 0xffff0000; - w->size = (size | 0x0000ffff) + 1; - } - } - mv78xx0_mbus_dram_info.num_cs = cs; + orion_setup_cpu_mbus_target(&addr_map_cfg, + DDR_WINDOW_CPU1_BASE); } void __init mv78xx0_setup_pcie_io_win(int window, u32 base, u32 size, int maj, int min) { - setup_cpu_win(window, base, size, TARGET_PCIE(maj), - ATTR_PCIE_IO(min), -1); + orion_setup_cpu_win(&addr_map_cfg, window, base, size, + TARGET_PCIE(maj), ATTR_PCIE_IO(min), -1); } void __init mv78xx0_setup_pcie_mem_win(int window, u32 base, u32 size, int maj, int min) { - setup_cpu_win(window, base, size, TARGET_PCIE(maj), - ATTR_PCIE_MEM(min), -1); + orion_setup_cpu_win(&addr_map_cfg, window, base, size, + TARGET_PCIE(maj), ATTR_PCIE_MEM(min), -1); } diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c index 5b9632b0116..0cdd41004ad 100644 --- a/arch/arm/mach-mv78xx0/common.c +++ b/arch/arm/mach-mv78xx0/common.c @@ -12,7 +12,6 @@ #include <linux/init.h> #include <linux/platform_device.h> #include <linux/serial_8250.h> -#include <linux/mbus.h> #include <linux/ata_platform.h> #include <linux/ethtool.h> #include <asm/mach/map.h> @@ -23,6 +22,7 @@ #include <plat/orion_nand.h> #include <plat/time.h> #include <plat/common.h> +#include <plat/addr-map.h> #include "common.h" static int get_tclk(void); @@ -169,8 +169,7 @@ void __init mv78xx0_map_io(void) ****************************************************************************/ void __init mv78xx0_ehci0_init(void) { - orion_ehci_init(&mv78xx0_mbus_dram_info, - USB0_PHYS_BASE, IRQ_MV78XX0_USB_0); + orion_ehci_init(USB0_PHYS_BASE, IRQ_MV78XX0_USB_0); } @@ -179,8 +178,7 @@ void __init mv78xx0_ehci0_init(void) ****************************************************************************/ void __init mv78xx0_ehci1_init(void) { - orion_ehci_1_init(&mv78xx0_mbus_dram_info, - USB1_PHYS_BASE, IRQ_MV78XX0_USB_1); + orion_ehci_1_init(USB1_PHYS_BASE, IRQ_MV78XX0_USB_1); } @@ -189,8 +187,7 @@ void __init mv78xx0_ehci1_init(void) ****************************************************************************/ void __init mv78xx0_ehci2_init(void) { - orion_ehci_2_init(&mv78xx0_mbus_dram_info, - USB2_PHYS_BASE, IRQ_MV78XX0_USB_2); + orion_ehci_2_init(USB2_PHYS_BASE, IRQ_MV78XX0_USB_2); } @@ -199,7 +196,7 @@ void __init mv78xx0_ehci2_init(void) ****************************************************************************/ void __init mv78xx0_ge00_init(struct mv643xx_eth_platform_data *eth_data) { - orion_ge00_init(eth_data, &mv78xx0_mbus_dram_info, + orion_ge00_init(eth_data, GE00_PHYS_BASE, IRQ_MV78XX0_GE00_SUM, IRQ_MV78XX0_GE_ERR, get_tclk()); } @@ -210,7 +207,7 @@ void __init mv78xx0_ge00_init(struct mv643xx_eth_platform_data *eth_data) ****************************************************************************/ void __init mv78xx0_ge01_init(struct mv643xx_eth_platform_data *eth_data) { - orion_ge01_init(eth_data, &mv78xx0_mbus_dram_info, + orion_ge01_init(eth_data, GE01_PHYS_BASE, IRQ_MV78XX0_GE01_SUM, NO_IRQ, get_tclk()); } @@ -234,7 +231,7 @@ void __init mv78xx0_ge10_init(struct mv643xx_eth_platform_data *eth_data) eth_data->duplex = DUPLEX_FULL; } - orion_ge10_init(eth_data, &mv78xx0_mbus_dram_info, + orion_ge10_init(eth_data, GE10_PHYS_BASE, IRQ_MV78XX0_GE10_SUM, NO_IRQ, get_tclk()); } @@ -258,7 +255,7 @@ void __init mv78xx0_ge11_init(struct mv643xx_eth_platform_data *eth_data) eth_data->duplex = DUPLEX_FULL; } - orion_ge11_init(eth_data, &mv78xx0_mbus_dram_info, + orion_ge11_init(eth_data, GE11_PHYS_BASE, IRQ_MV78XX0_GE11_SUM, NO_IRQ, get_tclk()); } @@ -277,8 +274,7 @@ void __init mv78xx0_i2c_init(void) ****************************************************************************/ void __init mv78xx0_sata_init(struct mv_sata_platform_data *sata_data) { - orion_sata_init(sata_data, &mv78xx0_mbus_dram_info, - SATA_PHYS_BASE, IRQ_MV78XX0_SATA); + orion_sata_init(sata_data, SATA_PHYS_BASE, IRQ_MV78XX0_SATA); } diff --git a/arch/arm/mach-mv78xx0/common.h b/arch/arm/mach-mv78xx0/common.h index 07d5f8f6be7..507c767d49e 100644 --- a/arch/arm/mach-mv78xx0/common.h +++ b/arch/arm/mach-mv78xx0/common.h @@ -23,7 +23,6 @@ void mv78xx0_init(void); void mv78xx0_init_early(void); void mv78xx0_init_irq(void); -extern struct mbus_dram_target_info mv78xx0_mbus_dram_info; void mv78xx0_setup_cpu_mbus(void); void mv78xx0_setup_pcie_io_win(int window, u32 base, u32 size, int maj, int min); diff --git a/arch/arm/mach-mv78xx0/mpp.c b/arch/arm/mach-mv78xx0/mpp.c index cf4e494d44b..df50342179e 100644 --- a/arch/arm/mach-mv78xx0/mpp.c +++ b/arch/arm/mach-mv78xx0/mpp.c @@ -10,7 +10,6 @@ #include <linux/gpio.h> #include <linux/kernel.h> #include <linux/init.h> -#include <linux/mbus.h> #include <linux/io.h> #include <plat/mpp.h> #include <mach/hardware.h> diff --git a/arch/arm/mach-mv78xx0/pcie.c b/arch/arm/mach-mv78xx0/pcie.c index c51af1cac30..8459f6d7d8c 100644 --- a/arch/arm/mach-mv78xx0/pcie.c +++ b/arch/arm/mach-mv78xx0/pcie.c @@ -10,11 +10,11 @@ #include <linux/kernel.h> #include <linux/pci.h> -#include <linux/mbus.h> #include <video/vga.h> #include <asm/irq.h> #include <asm/mach/pci.h> #include <plat/pcie.h> +#include <plat/addr-map.h> #include "common.h" struct pcie_port { @@ -153,11 +153,10 @@ static int __init mv78xx0_pcie_setup(int nr, struct pci_sys_data *sys) * Generic PCIe unit setup. */ orion_pcie_set_local_bus_nr(pp->base, sys->busnr); - orion_pcie_setup(pp->base, &mv78xx0_mbus_dram_info); + orion_pcie_setup(pp->base); - sys->resource[0] = &pp->res[0]; - sys->resource[1] = &pp->res[1]; - sys->resource[2] = NULL; + pci_add_resource(&sys->resources, &pp->res[0]); + pci_add_resource(&sys->resources, &pp->res[1]); return 1; } @@ -251,7 +250,8 @@ mv78xx0_pcie_scan_bus(int nr, struct pci_sys_data *sys) struct pci_bus *bus; if (nr < num_pcie_ports) { - bus = pci_scan_bus(sys->busnr, &pcie_ops, sys); + bus = pci_scan_root_bus(NULL, sys->busnr, &pcie_ops, sys, + &sys->resources); } else { bus = NULL; BUG(); diff --git a/arch/arm/mach-mx5/mm.c b/arch/arm/mach-mx5/mm.c index df4a508f240..bc17dfea381 100644 --- a/arch/arm/mach-mx5/mm.c +++ b/arch/arm/mach-mx5/mm.c @@ -13,6 +13,7 @@ #include <linux/mm.h> #include <linux/init.h> +#include <linux/clk.h> #include <asm/mach/map.h> @@ -21,10 +22,26 @@ #include <mach/devices-common.h> #include <mach/iomux-v3.h> +static struct clk *gpc_dvfs_clk; + static void imx5_idle(void) { - if (!need_resched()) + if (!need_resched()) { + /* gpc clock is needed for SRPG */ + if (gpc_dvfs_clk == NULL) { + gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs"); + if (IS_ERR(gpc_dvfs_clk)) + goto err0; + } + clk_enable(gpc_dvfs_clk); mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF); + if (tzic_enable_wake()) + goto err1; + cpu_do_idle(); +err1: + clk_disable(gpc_dvfs_clk); + } +err0: local_irq_enable(); } diff --git a/arch/arm/mach-mx5/system.c b/arch/arm/mach-mx5/system.c index 144ebebc4a6..5eebfaad122 100644 --- a/arch/arm/mach-mx5/system.c +++ b/arch/arm/mach-mx5/system.c @@ -55,9 +55,6 @@ void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode) stop_mode = 1; } arm_srpgcr |= MXC_SRPGCR_PCR; - - if (tzic_enable_wake(1) != 0) - return; break; case STOP_POWER_ON: ccm_clpcr |= 0x2 << MXC_CCM_CLPCR_LPM_OFFSET; diff --git a/arch/arm/mach-mxs/clock-mx23.c b/arch/arm/mach-mxs/clock-mx23.c index 0163b6d8377..e12e11231dc 100644 --- a/arch/arm/mach-mxs/clock-mx23.c +++ b/arch/arm/mach-mxs/clock-mx23.c @@ -545,11 +545,11 @@ int __init mx23_clocks_init(void) */ clk_set_parent(&ssp_clk, &ref_io_clk); - clk_enable(&cpu_clk); - clk_enable(&hbus_clk); - clk_enable(&xbus_clk); - clk_enable(&emi_clk); - clk_enable(&uart_clk); + clk_prepare_enable(&cpu_clk); + clk_prepare_enable(&hbus_clk); + clk_prepare_enable(&xbus_clk); + clk_prepare_enable(&emi_clk); + clk_prepare_enable(&uart_clk); clkdev_add_table(lookups, ARRAY_SIZE(lookups)); diff --git a/arch/arm/mach-mxs/clock-mx28.c b/arch/arm/mach-mxs/clock-mx28.c index da6e4aad177..5d68e415222 100644 --- a/arch/arm/mach-mxs/clock-mx28.c +++ b/arch/arm/mach-mxs/clock-mx28.c @@ -22,6 +22,7 @@ #include <linux/io.h> #include <linux/jiffies.h> #include <linux/clkdev.h> +#include <linux/spinlock.h> #include <asm/clkdev.h> #include <asm/div64.h> @@ -29,6 +30,7 @@ #include <mach/mx28.h> #include <mach/common.h> #include <mach/clock.h> +#include <mach/digctl.h> #include "regs-clkctrl-mx28.h" @@ -43,6 +45,33 @@ static struct clk emi_clk; static struct clk saif0_clk; static struct clk saif1_clk; static struct clk clk32k_clk; +static DEFINE_SPINLOCK(clkmux_lock); + +/* + * HW_SAIF_CLKMUX_SEL: + * DIRECT(0x0): SAIF0 clock pins selected for SAIF0 input clocks, and SAIF1 + * clock pins selected for SAIF1 input clocks. + * CROSSINPUT(0x1): SAIF1 clock inputs selected for SAIF0 input clocks, and + * SAIF0 clock inputs selected for SAIF1 input clocks. + * EXTMSTR0(0x2): SAIF0 clock pin selected for both SAIF0 and SAIF1 input + * clocks. + * EXTMSTR1(0x3): SAIF1 clock pin selected for both SAIF0 and SAIF1 input + * clocks. + */ +int mxs_saif_clkmux_select(unsigned int clkmux) +{ + if (clkmux > 0x3) + return -EINVAL; + + spin_lock(&clkmux_lock); + __raw_writel(BM_DIGCTL_CTRL_SAIF_CLKMUX, + DIGCTRL_BASE_ADDR + HW_DIGCTL_CTRL + MXS_CLR_ADDR); + __raw_writel(clkmux << BP_DIGCTL_CTRL_SAIF_CLKMUX, + DIGCTRL_BASE_ADDR + HW_DIGCTL_CTRL + MXS_SET_ADDR); + spin_unlock(&clkmux_lock); + + return 0; +} static int _raw_clk_enable(struct clk *clk) { @@ -775,16 +804,25 @@ int __init mx28_clocks_init(void) clk_set_parent(&ssp0_clk, &ref_io0_clk); clk_set_parent(&ssp1_clk, &ref_io0_clk); - clk_enable(&cpu_clk); - clk_enable(&hbus_clk); - clk_enable(&xbus_clk); - clk_enable(&emi_clk); - clk_enable(&uart_clk); + clk_prepare_enable(&cpu_clk); + clk_prepare_enable(&hbus_clk); + clk_prepare_enable(&xbus_clk); + clk_prepare_enable(&emi_clk); + clk_prepare_enable(&uart_clk); clk_set_parent(&lcdif_clk, &ref_pix_clk); clk_set_parent(&saif0_clk, &pll0_clk); clk_set_parent(&saif1_clk, &pll0_clk); + /* + * Set an initial clock rate for the saif internal logic to work + * properly. This is important when working in EXTMASTER mode that + * uses the other saif's BITCLK&LRCLK but it still needs a basic + * clock which should be fast enough for the internal logic. + */ + clk_set_rate(&saif0_clk, 24000000); + clk_set_rate(&saif1_clk, 24000000); + clkdev_add_table(lookups, ARRAY_SIZE(lookups)); mxs_timer_init(&clk32k_clk, MX28_INT_TIMER0); diff --git a/arch/arm/mach-mxs/clock.c b/arch/arm/mach-mxs/clock.c index a7093c88e6a..97a6f4acc6c 100644 --- a/arch/arm/mach-mxs/clock.c +++ b/arch/arm/mach-mxs/clock.c @@ -74,10 +74,15 @@ static int __clk_enable(struct clk *clk) return 0; } -/* This function increments the reference count on the clock and enables the - * clock if not already enabled. The parent clock tree is recursively enabled +/* + * The clk_enable/clk_disable could be called by drivers in atomic context, + * so they should not really hold mutex. Instead, clk_prepare/clk_unprepare + * can hold a mutex, as the pair will only be called in non-atomic context. + * Before migrating to common clk framework, we can have __clk_enable and + * __clk_disable called in clk_prepare/clk_unprepare with mutex held and + * leave clk_enable/clk_disable as the dummy functions. */ -int clk_enable(struct clk *clk) +int clk_prepare(struct clk *clk) { int ret = 0; @@ -90,13 +95,9 @@ int clk_enable(struct clk *clk) return ret; } -EXPORT_SYMBOL(clk_enable); +EXPORT_SYMBOL(clk_prepare); -/* This function decrements the reference count on the clock and disables - * the clock when reference count is 0. The parent clock tree is - * recursively disabled - */ -void clk_disable(struct clk *clk) +void clk_unprepare(struct clk *clk) { if (clk == NULL || IS_ERR(clk)) return; @@ -105,6 +106,18 @@ void clk_disable(struct clk *clk) __clk_disable(clk); mutex_unlock(&clocks_mutex); } +EXPORT_SYMBOL(clk_unprepare); + +int clk_enable(struct clk *clk) +{ + return 0; +} +EXPORT_SYMBOL(clk_enable); + +void clk_disable(struct clk *clk) +{ + /* nothing to do */ +} EXPORT_SYMBOL(clk_disable); /* Retrieve the *current* clock rate. If the clock itself @@ -166,7 +179,7 @@ int clk_set_parent(struct clk *clk, struct clk *parent) return ret; if (clk->usecount) - clk_enable(parent); + clk_prepare_enable(parent); mutex_lock(&clocks_mutex); ret = clk->set_parent(clk, parent); diff --git a/arch/arm/mach-mxs/devices-mx28.h b/arch/arm/mach-mxs/devices-mx28.h index c8887103f0e..4f50094e293 100644 --- a/arch/arm/mach-mxs/devices-mx28.h +++ b/arch/arm/mach-mxs/devices-mx28.h @@ -47,6 +47,7 @@ struct platform_device *__init mx28_add_mxsfb( const struct mxsfb_platform_data *pdata); extern const struct mxs_saif_data mx28_saif_data[] __initconst; -#define mx28_add_saif(id) mxs_add_saif(&mx28_saif_data[id]) +#define mx28_add_saif(id, pdata) \ + mxs_add_saif(&mx28_saif_data[id], pdata) struct platform_device *__init mx28_add_rtc_stmp3xxx(void); diff --git a/arch/arm/mach-mxs/devices/platform-mxs-saif.c b/arch/arm/mach-mxs/devices/platform-mxs-saif.c index 1ec965e9fe9..f6e3a60b420 100644 --- a/arch/arm/mach-mxs/devices/platform-mxs-saif.c +++ b/arch/arm/mach-mxs/devices/platform-mxs-saif.c @@ -32,7 +32,8 @@ const struct mxs_saif_data mx28_saif_data[] __initconst = { }; #endif -struct platform_device *__init mxs_add_saif(const struct mxs_saif_data *data) +struct platform_device *__init mxs_add_saif(const struct mxs_saif_data *data, + const struct mxs_saif_platform_data *pdata) { struct resource res[] = { { @@ -56,5 +57,5 @@ struct platform_device *__init mxs_add_saif(const struct mxs_saif_data *data) }; return mxs_add_platform_device("mxs-saif", data->id, res, - ARRAY_SIZE(res), NULL, 0); + ARRAY_SIZE(res), pdata, sizeof(*pdata)); } diff --git a/arch/arm/mach-mxs/include/mach/common.h b/arch/arm/mach-mxs/include/mach/common.h index 1388485414c..e1237ab2586 100644 --- a/arch/arm/mach-mxs/include/mach/common.h +++ b/arch/arm/mach-mxs/include/mach/common.h @@ -17,6 +17,7 @@ extern const u32 *mxs_get_ocotp(void); extern int mxs_reset_block(void __iomem *); extern void mxs_timer_init(struct clk *, int); extern void mxs_restart(char, const char *); +extern int mxs_saif_clkmux_select(unsigned int clkmux); extern int mx23_register_gpios(void); extern int mx23_clocks_init(void); diff --git a/arch/arm/mach-mxs/include/mach/devices-common.h b/arch/arm/mach-mxs/include/mach/devices-common.h index a8080f44c03..dc369c1239f 100644 --- a/arch/arm/mach-mxs/include/mach/devices-common.h +++ b/arch/arm/mach-mxs/include/mach/devices-common.h @@ -94,6 +94,7 @@ struct platform_device *__init mxs_add_mxs_pwm( resource_size_t iobase, int id); /* saif */ +#include <sound/saif.h> struct mxs_saif_data { int id; resource_size_t iobase; @@ -103,4 +104,5 @@ struct mxs_saif_data { }; struct platform_device *__init mxs_add_saif( - const struct mxs_saif_data *data); + const struct mxs_saif_data *data, + const struct mxs_saif_platform_data *pdata); diff --git a/arch/arm/mach-mxs/include/mach/digctl.h b/arch/arm/mach-mxs/include/mach/digctl.h new file mode 100644 index 00000000000..49a888c65d6 --- /dev/null +++ b/arch/arm/mach-mxs/include/mach/digctl.h @@ -0,0 +1,21 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __MACH_DIGCTL_H__ +#define __MACH_DIGCTL_H__ + +/* MXS DIGCTL SAIF CLKMUX */ +#define MXS_DIGCTL_SAIF_CLKMUX_DIRECT 0x0 +#define MXS_DIGCTL_SAIF_CLKMUX_CROSSINPUT 0x1 +#define MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0 0x2 +#define MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR1 0x3 + +#define HW_DIGCTL_CTRL 0x0 +#define BP_DIGCTL_CTRL_SAIF_CLKMUX 10 +#define BM_DIGCTL_CTRL_SAIF_CLKMUX (0x3 << 10) +#endif diff --git a/arch/arm/mach-mxs/mach-mx28evk.c b/arch/arm/mach-mxs/mach-mx28evk.c index d0cc37fd23a..fdb0a5664dd 100644 --- a/arch/arm/mach-mxs/mach-mx28evk.c +++ b/arch/arm/mach-mxs/mach-mx28evk.c @@ -27,6 +27,7 @@ #include <mach/common.h> #include <mach/iomux-mx28.h> +#include <mach/digctl.h> #include "devices-mx28.h" @@ -228,7 +229,7 @@ static void __init mx28evk_fec_reset(void) /* Enable fec phy clock */ clk = clk_get_sys("pll2", NULL); if (!IS_ERR(clk)) - clk_enable(clk); + clk_prepare_enable(clk); /* Power up fec phy */ ret = gpio_request(MX28EVK_FEC_PHY_POWER, "fec-phy-power"); @@ -421,6 +422,18 @@ static struct gpio mx28evk_lcd_gpios[] = { { MX28EVK_BL_ENABLE, GPIOF_OUT_INIT_HIGH, "bl-enable" }, }; +static const struct mxs_saif_platform_data + mx28evk_mxs_saif_pdata[] __initconst = { + /* working on EXTMSTR0 mode (saif0 master, saif1 slave) */ + { + .master_mode = 1, + .master_id = 0, + }, { + .master_mode = 0, + .master_id = 0, + }, +}; + static void __init mx28evk_init(void) { int ret; @@ -454,8 +467,9 @@ static void __init mx28evk_init(void) else mx28_add_mxsfb(&mx28evk_mxsfb_pdata); - mx28_add_saif(0); - mx28_add_saif(1); + mxs_saif_clkmux_select(MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0); + mx28_add_saif(0, &mx28evk_mxs_saif_pdata[0]); + mx28_add_saif(1, &mx28evk_mxs_saif_pdata[1]); mx28_add_mxs_i2c(0); i2c_register_board_info(0, mxs_i2c0_board_info, diff --git a/arch/arm/mach-mxs/system.c b/arch/arm/mach-mxs/system.c index b936633b768..54f91ad1c96 100644 --- a/arch/arm/mach-mxs/system.c +++ b/arch/arm/mach-mxs/system.c @@ -66,7 +66,7 @@ static int __init mxs_arch_reset_init(void) clk = clk_get_sys("rtc", NULL); if (!IS_ERR(clk)) - clk_enable(clk); + clk_prepare_enable(clk); return 0; } diff --git a/arch/arm/mach-mxs/timer.c b/arch/arm/mach-mxs/timer.c index cace0d2e5a5..564a63279f1 100644 --- a/arch/arm/mach-mxs/timer.c +++ b/arch/arm/mach-mxs/timer.c @@ -245,7 +245,7 @@ static int __init mxs_clocksource_init(struct clk *timer_clk) void __init mxs_timer_init(struct clk *timer_clk, int irq) { - clk_enable(timer_clk); + clk_prepare_enable(timer_clk); /* * Initialize timers to a known state diff --git a/arch/arm/mach-omap1/Kconfig b/arch/arm/mach-omap1/Kconfig index 73f287d6429..4f8d66f044e 100644 --- a/arch/arm/mach-omap1/Kconfig +++ b/arch/arm/mach-omap1/Kconfig @@ -168,70 +168,6 @@ config MACH_OMAP_GENERIC custom OMAP boards. Say Y here if you have a custom board. -comment "OMAP CPU Speed" - depends on ARCH_OMAP1 - -config OMAP_ARM_216MHZ - bool "OMAP ARM 216 MHz CPU (1710 only)" - depends on ARCH_OMAP1 && ARCH_OMAP16XX - help - Enable 216 MHz clock for OMAP1710 CPU. If unsure, say N. - -config OMAP_ARM_195MHZ - bool "OMAP ARM 195 MHz CPU" - depends on ARCH_OMAP1 && (ARCH_OMAP730 || ARCH_OMAP850) - help - Enable 195MHz clock for OMAP CPU. If unsure, say N. - -config OMAP_ARM_192MHZ - bool "OMAP ARM 192 MHz CPU" - depends on ARCH_OMAP1 && ARCH_OMAP16XX - help - Enable 192MHz clock for OMAP CPU. If unsure, say N. - -config OMAP_ARM_182MHZ - bool "OMAP ARM 182 MHz CPU" - depends on ARCH_OMAP1 && (ARCH_OMAP730 || ARCH_OMAP850) - help - Enable 182MHz clock for OMAP CPU. If unsure, say N. - -config OMAP_ARM_168MHZ - bool "OMAP ARM 168 MHz CPU" - depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730 || ARCH_OMAP850) - help - Enable 168MHz clock for OMAP CPU. If unsure, say N. - -config OMAP_ARM_150MHZ - bool "OMAP ARM 150 MHz CPU" - depends on ARCH_OMAP1 && ARCH_OMAP15XX - help - Enable 150MHz clock for OMAP CPU. If unsure, say N. - -config OMAP_ARM_120MHZ - bool "OMAP ARM 120 MHz CPU" - depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730 || ARCH_OMAP850) - help - Enable 120MHz clock for OMAP CPU. If unsure, say N. - -config OMAP_ARM_96MHZ - bool "OMAP ARM 96 MHz CPU" - depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730 || ARCH_OMAP850) - help - Enable 96MHz clock for OMAP CPU. If unsure, say N. - -config OMAP_ARM_60MHZ - bool "OMAP ARM 60 MHz CPU" - depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730 || ARCH_OMAP850) - default y - help - Enable 60MHz clock for OMAP CPU. If unsure, say Y. - -config OMAP_ARM_30MHZ - bool "OMAP ARM 30 MHz CPU" - depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730 || ARCH_OMAP850) - help - Enable 30MHz clock for OMAP CPU. If unsure, say N. - endmenu endif diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c index 84ef70476b5..0c50df05d13 100644 --- a/arch/arm/mach-omap1/clock.c +++ b/arch/arm/mach-omap1/clock.c @@ -197,11 +197,10 @@ int omap1_select_table_rate(struct clk *clk, unsigned long rate) ref_rate = ck_ref_p->rate; for (ptr = omap1_rate_table; ptr->rate; ptr++) { - if (ptr->xtal != ref_rate) + if (!(ptr->flags & cpu_mask)) continue; - /* DPLL1 cannot be reprogrammed without risking system crash */ - if (likely(dpll1_rate != 0) && ptr->pll_rate != dpll1_rate) + if (ptr->xtal != ref_rate) continue; /* Can check only after xtal frequency check */ @@ -215,12 +214,8 @@ int omap1_select_table_rate(struct clk *clk, unsigned long rate) /* * In most cases we should not need to reprogram DPLL. * Reprogramming the DPLL is tricky, it must be done from SRAM. - * (on 730, bit 13 must always be 1) */ - if (cpu_is_omap7xx()) - omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val | 0x2000); - else - omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val); + omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val); /* XXX Do we need to recalculate the tree below DPLL1 at this point? */ ck_dpll1_p->rate = ptr->pll_rate; @@ -290,6 +285,9 @@ long omap1_round_to_table_rate(struct clk *clk, unsigned long rate) highest_rate = -EINVAL; for (ptr = omap1_rate_table; ptr->rate; ptr++) { + if (!(ptr->flags & cpu_mask)) + continue; + if (ptr->xtal != ref_rate) continue; diff --git a/arch/arm/mach-omap1/clock.h b/arch/arm/mach-omap1/clock.h index 16b1423b454..3d04f4f6767 100644 --- a/arch/arm/mach-omap1/clock.h +++ b/arch/arm/mach-omap1/clock.h @@ -111,4 +111,7 @@ extern const struct clkops clkops_dummy; extern const struct clkops clkops_uart_16xx; extern const struct clkops clkops_generic; +/* used for passing SoC type to omap1_{select,round_to}_table_rate() */ +extern u32 cpu_mask; + #endif diff --git a/arch/arm/mach-omap1/clock_data.c b/arch/arm/mach-omap1/clock_data.c index 9ff90a744a2..94699a82a73 100644 --- a/arch/arm/mach-omap1/clock_data.c +++ b/arch/arm/mach-omap1/clock_data.c @@ -25,6 +25,7 @@ #include <plat/clock.h> #include <plat/cpu.h> #include <plat/clkdev_omap.h> +#include <plat/sram.h> /* for omap_sram_reprogram_clock() */ #include <plat/usb.h> /* for OTG_BASE */ #include "clock.h" @@ -778,12 +779,14 @@ static void __init omap1_show_rates(void) arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10); } +u32 cpu_mask; + int __init omap1_clk_init(void) { struct omap_clk *c; const struct omap_clock_config *info; int crystal_type = 0; /* Default 12 MHz */ - u32 reg, cpu_mask; + u32 reg; #ifdef CONFIG_DEBUG_LL /* @@ -808,6 +811,8 @@ int __init omap1_clk_init(void) clk_preinit(c->lk.clk); cpu_mask = 0; + if (cpu_is_omap1710()) + cpu_mask |= CK_1710; if (cpu_is_omap16xx()) cpu_mask |= CK_16XX; if (cpu_is_omap1510()) @@ -931,17 +936,13 @@ void __init omap1_clk_late_init(void) { unsigned long rate = ck_dpll1.rate; - if (rate >= OMAP1_DPLL1_SANE_VALUE) - return; - - /* System booting at unusable rate, force reprogramming of DPLL1 */ - ck_dpll1_p->rate = 0; - /* Find the highest supported frequency and enable it */ if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) { pr_err("System frequencies not set, using default. Check your config.\n"); - omap_writew(0x2290, DPLL_CTL); - omap_writew(cpu_is_omap7xx() ? 0x2005 : 0x0005, ARM_CKCTL); + /* + * Reprogramming the DPLL is tricky, it must be done from SRAM. + */ + omap_sram_reprogram_clock(0x2290, 0x0005); ck_dpll1.rate = OMAP1_DPLL1_SANE_VALUE; } propagate_rate(&ck_dpll1); diff --git a/arch/arm/mach-omap1/opp.h b/arch/arm/mach-omap1/opp.h index 07074d79adc..79a683864a5 100644 --- a/arch/arm/mach-omap1/opp.h +++ b/arch/arm/mach-omap1/opp.h @@ -21,6 +21,7 @@ struct mpu_rate { unsigned long pll_rate; __u16 ckctl_val; __u16 dpllctl_val; + u32 flags; }; extern struct mpu_rate omap1_rate_table[]; diff --git a/arch/arm/mach-omap1/opp_data.c b/arch/arm/mach-omap1/opp_data.c index 75a54651499..9cd4ddb5139 100644 --- a/arch/arm/mach-omap1/opp_data.c +++ b/arch/arm/mach-omap1/opp_data.c @@ -10,6 +10,7 @@ * published by the Free Software Foundation. */ +#include <plat/clkdev_omap.h> #include "opp.h" /*------------------------------------------------------------------------- @@ -20,40 +21,34 @@ struct mpu_rate omap1_rate_table[] = { * NOTE: Comment order here is different from bits in CKCTL value: * armdiv, dspdiv, dspmmu, tcdiv, perdiv, lcddiv */ -#if defined(CONFIG_OMAP_ARM_216MHZ) - { 216000000, 12000000, 216000000, 0x050d, 0x2910 }, /* 1/1/2/2/2/8 */ -#endif -#if defined(CONFIG_OMAP_ARM_195MHZ) - { 195000000, 13000000, 195000000, 0x050e, 0x2790 }, /* 1/1/2/2/4/8 */ -#endif -#if defined(CONFIG_OMAP_ARM_192MHZ) - { 192000000, 19200000, 192000000, 0x050f, 0x2510 }, /* 1/1/2/2/8/8 */ - { 192000000, 12000000, 192000000, 0x050f, 0x2810 }, /* 1/1/2/2/8/8 */ - { 96000000, 12000000, 192000000, 0x055f, 0x2810 }, /* 2/2/2/2/8/8 */ - { 48000000, 12000000, 192000000, 0x0baf, 0x2810 }, /* 4/4/4/8/8/8 */ - { 24000000, 12000000, 192000000, 0x0fff, 0x2810 }, /* 8/8/8/8/8/8 */ -#endif -#if defined(CONFIG_OMAP_ARM_182MHZ) - { 182000000, 13000000, 182000000, 0x050e, 0x2710 }, /* 1/1/2/2/4/8 */ -#endif -#if defined(CONFIG_OMAP_ARM_168MHZ) - { 168000000, 12000000, 168000000, 0x010f, 0x2710 }, /* 1/1/1/2/8/8 */ -#endif -#if defined(CONFIG_OMAP_ARM_150MHZ) - { 150000000, 12000000, 150000000, 0x010a, 0x2cb0 }, /* 1/1/1/2/4/4 */ -#endif -#if defined(CONFIG_OMAP_ARM_120MHZ) - { 120000000, 12000000, 120000000, 0x010a, 0x2510 }, /* 1/1/1/2/4/4 */ -#endif -#if defined(CONFIG_OMAP_ARM_96MHZ) - { 96000000, 12000000, 96000000, 0x0005, 0x2410 }, /* 1/1/1/1/2/2 */ -#endif -#if defined(CONFIG_OMAP_ARM_60MHZ) - { 60000000, 12000000, 60000000, 0x0005, 0x2290 }, /* 1/1/1/1/2/2 */ -#endif -#if defined(CONFIG_OMAP_ARM_30MHZ) - { 30000000, 12000000, 60000000, 0x0555, 0x2290 }, /* 2/2/2/2/2/2 */ -#endif + { 216000000, 12000000, 216000000, 0x050d, 0x2910, /* 1/1/2/2/2/8 */ + CK_1710 }, + { 195000000, 13000000, 195000000, 0x050e, 0x2790, /* 1/1/2/2/4/8 */ + CK_7XX }, + { 192000000, 19200000, 192000000, 0x050f, 0x2510, /* 1/1/2/2/8/8 */ + CK_16XX }, + { 192000000, 12000000, 192000000, 0x050f, 0x2810, /* 1/1/2/2/8/8 */ + CK_16XX }, + { 96000000, 12000000, 192000000, 0x055f, 0x2810, /* 2/2/2/2/8/8 */ + CK_16XX }, + { 48000000, 12000000, 192000000, 0x0baf, 0x2810, /* 4/4/4/8/8/8 */ + CK_16XX }, + { 24000000, 12000000, 192000000, 0x0fff, 0x2810, /* 8/8/8/8/8/8 */ + CK_16XX }, + { 182000000, 13000000, 182000000, 0x050e, 0x2710, /* 1/1/2/2/4/8 */ + CK_7XX }, + { 168000000, 12000000, 168000000, 0x010f, 0x2710, /* 1/1/1/2/8/8 */ + CK_16XX|CK_7XX }, + { 150000000, 12000000, 150000000, 0x010a, 0x2cb0, /* 1/1/1/2/4/4 */ + CK_1510 }, + { 120000000, 12000000, 120000000, 0x010a, 0x2510, /* 1/1/1/2/4/4 */ + CK_16XX|CK_1510|CK_310|CK_7XX }, + { 96000000, 12000000, 96000000, 0x0005, 0x2410, /* 1/1/1/1/2/2 */ + CK_16XX|CK_1510|CK_310|CK_7XX }, + { 60000000, 12000000, 60000000, 0x0005, 0x2290, /* 1/1/1/1/2/2 */ + CK_16XX|CK_1510|CK_310|CK_7XX }, + { 30000000, 12000000, 60000000, 0x0555, 0x2290, /* 2/2/2/2/2/2 */ + CK_16XX|CK_1510|CK_310|CK_7XX }, { 0, 0, 0, 0, 0 }, }; diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index 4f01533083c..904bd1dfcd2 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -78,8 +78,13 @@ config SOC_OMAP3430 default y select ARCH_OMAP_OTG -config SOC_OMAPTI816X - bool "TI816X support" +config SOC_OMAPTI81XX + bool "TI81XX support" + depends on ARCH_OMAP3 + default y + +config SOC_OMAPAM33XX + bool "AM33XX support" depends on ARCH_OMAP3 default y @@ -316,7 +321,12 @@ config MACH_OMAP_3630SDP config MACH_TI8168EVM bool "TI8168 Evaluation Module" - depends on SOC_OMAPTI816X + depends on SOC_OMAPTI81XX + default y + +config MACH_TI8148EVM + bool "TI8148 Evaluation Module" + depends on SOC_OMAPTI81XX default y config MACH_OMAP_4430SDP @@ -355,6 +365,27 @@ config OMAP3_SDRC_AC_TIMING wish to say no. Selecting yes without understanding what is going on could result in system crashes; +config OMAP4_ERRATA_I688 + bool "OMAP4 errata: Async Bridge Corruption" + depends on ARCH_OMAP4 + select ARCH_HAS_BARRIERS + help + If a data is stalled inside asynchronous bridge because of back + pressure, it may be accepted multiple times, creating pointer + misalignment that will corrupt next transfers on that data path + until next reset of the system (No recovery procedure once the + issue is hit, the path remains consistently broken). Async bridge + can be found on path between MPU to EMIF and MPU to L3 interconnect. + This situation can happen only when the idle is initiated by a + Master Request Disconnection (which is trigged by software when + executing WFI on CPU). + The work-around for this errata needs all the initiators connected + through async bridge must ensure that data path is properly drained + before issuing WFI. This condition will be met if one Strongly ordered + access is performed to the target right before executing the WFI. + In MPU case, L3 T2ASYNC FIFO and DDR T2ASYNC FIFO needs to be drained. + IO barrier ensure that there is no synchronisation loss on initiators + operating on both interconnect port simultaneously. endmenu endif diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index b009f17dee5..fc9b238cbc1 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -11,10 +11,11 @@ hwmod-common = omap_hwmod.o \ omap_hwmod_common_data.o clock-common = clock.o clock_common_data.o \ clkt_dpll.o clkt_clksel.o +secure-common = omap-smc.o omap-secure.o -obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common) -obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) -obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common) +obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common) $(secure-common) +obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common) +obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common) $(secure-common) obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o @@ -24,11 +25,13 @@ obj-$(CONFIG_TWL4030_CORE) += omap_twl.o obj-$(CONFIG_SMP) += omap-smp.o omap-headsmp.o obj-$(CONFIG_LOCAL_TIMERS) += timer-mpu.o obj-$(CONFIG_HOTPLUG_CPU) += omap-hotplug.o -obj-$(CONFIG_ARCH_OMAP4) += omap44xx-smc.o omap4-common.o +obj-$(CONFIG_ARCH_OMAP4) += omap4-common.o omap-wakeupgen.o \ + sleep44xx.o plus_sec := $(call as-instr,.arch_extension sec,+sec) AFLAGS_omap-headsmp.o :=-Wa,-march=armv7-a$(plus_sec) -AFLAGS_omap44xx-smc.o :=-Wa,-march=armv7-a$(plus_sec) +AFLAGS_omap-smc.o :=-Wa,-march=armv7-a$(plus_sec) +AFLAGS_sleep44xx.o :=-Wa,-march=armv7-a$(plus_sec) # Functions loaded to SRAM obj-$(CONFIG_SOC_OMAP2420) += sram242x.o @@ -62,7 +65,8 @@ obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o obj-$(CONFIG_ARCH_OMAP2) += sleep24xx.o obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o \ cpuidle34xx.o -obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o +obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o omap-mpuss-lowpower.o \ + cpuidle44xx.o obj-$(CONFIG_PM_DEBUG) += pm-debug.o obj-$(CONFIG_OMAP_SMARTREFLEX) += sr_device.o smartreflex.o obj-$(CONFIG_OMAP_SMARTREFLEX_CLASS3) += smartreflex-class3.o @@ -77,6 +81,7 @@ endif endif # PRCM +obj-y += prm_common.o obj-$(CONFIG_ARCH_OMAP2) += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o obj-$(CONFIG_ARCH_OMAP3) += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o \ vc3xxx_data.o vp3xxx_data.o @@ -86,7 +91,7 @@ obj-$(CONFIG_ARCH_OMAP3) += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o \ obj-$(CONFIG_ARCH_OMAP4) += prcm.o cm2xxx_3xxx.o cminst44xx.o \ cm44xx.o prcm_mpu44xx.o \ prminst44xx.o vc44xx_data.o \ - vp44xx_data.o + vp44xx_data.o prm44xx.o # OMAP voltage domains voltagedomain-common := voltage.o vc.o vp.o @@ -232,6 +237,7 @@ obj-$(CONFIG_MACH_CRANEBOARD) += board-am3517crane.o obj-$(CONFIG_MACH_SBC3530) += board-omap3stalker.o obj-$(CONFIG_MACH_TI8168EVM) += board-ti8168evm.o +obj-$(CONFIG_MACH_TI8148EVM) += board-ti8168evm.o # Platform specific device init code diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c index 9996334cb68..383717ba63b 100644 --- a/arch/arm/mach-omap2/board-3430sdp.c +++ b/arch/arm/mach-omap2/board-3430sdp.c @@ -475,106 +475,8 @@ static const struct usbhs_omap_board_data usbhs_bdata __initconst = { static struct omap_board_mux board_mux[] __initdata = { { .reg_offset = OMAP_MUX_TERMINATOR }, }; - -static struct omap_device_pad serial1_pads[] __initdata = { - /* - * Note that off output enable is an active low - * signal. So setting this means pin is a - * input enabled in off mode - */ - OMAP_MUX_STATIC("uart1_cts.uart1_cts", - OMAP_PIN_INPUT | - OMAP_PIN_OFF_INPUT_PULLDOWN | - OMAP_OFFOUT_EN | - OMAP_MUX_MODE0), - OMAP_MUX_STATIC("uart1_rts.uart1_rts", - OMAP_PIN_OUTPUT | - OMAP_OFF_EN | - OMAP_MUX_MODE0), - OMAP_MUX_STATIC("uart1_rx.uart1_rx", - OMAP_PIN_INPUT | - OMAP_PIN_OFF_INPUT_PULLDOWN | - OMAP_OFFOUT_EN | - OMAP_MUX_MODE0), - OMAP_MUX_STATIC("uart1_tx.uart1_tx", - OMAP_PIN_OUTPUT | - OMAP_OFF_EN | - OMAP_MUX_MODE0), -}; - -static struct omap_device_pad serial2_pads[] __initdata = { - OMAP_MUX_STATIC("uart2_cts.uart2_cts", - OMAP_PIN_INPUT_PULLUP | - OMAP_PIN_OFF_INPUT_PULLDOWN | - OMAP_OFFOUT_EN | - OMAP_MUX_MODE0), - OMAP_MUX_STATIC("uart2_rts.uart2_rts", - OMAP_PIN_OUTPUT | - OMAP_OFF_EN | - OMAP_MUX_MODE0), - OMAP_MUX_STATIC("uart2_rx.uart2_rx", - OMAP_PIN_INPUT | - OMAP_PIN_OFF_INPUT_PULLDOWN | - OMAP_OFFOUT_EN | - OMAP_MUX_MODE0), - OMAP_MUX_STATIC("uart2_tx.uart2_tx", - OMAP_PIN_OUTPUT | - OMAP_OFF_EN | - OMAP_MUX_MODE0), -}; - -static struct omap_device_pad serial3_pads[] __initdata = { - OMAP_MUX_STATIC("uart3_cts_rctx.uart3_cts_rctx", - OMAP_PIN_INPUT_PULLDOWN | - OMAP_PIN_OFF_INPUT_PULLDOWN | - OMAP_OFFOUT_EN | - OMAP_MUX_MODE0), - OMAP_MUX_STATIC("uart3_rts_sd.uart3_rts_sd", - OMAP_PIN_OUTPUT | - OMAP_OFF_EN | - OMAP_MUX_MODE0), - OMAP_MUX_STATIC("uart3_rx_irrx.uart3_rx_irrx", - OMAP_PIN_INPUT | - OMAP_PIN_OFF_INPUT_PULLDOWN | - OMAP_OFFOUT_EN | - OMAP_MUX_MODE0), - OMAP_MUX_STATIC("uart3_tx_irtx.uart3_tx_irtx", - OMAP_PIN_OUTPUT | - OMAP_OFF_EN | - OMAP_MUX_MODE0), -}; - -static struct omap_board_data serial1_data __initdata = { - .id = 0, - .pads = serial1_pads, - .pads_cnt = ARRAY_SIZE(serial1_pads), -}; - -static struct omap_board_data serial2_data __initdata = { - .id = 1, - .pads = serial2_pads, - .pads_cnt = ARRAY_SIZE(serial2_pads), -}; - -static struct omap_board_data serial3_data __initdata = { - .id = 2, - .pads = serial3_pads, - .pads_cnt = ARRAY_SIZE(serial3_pads), -}; - -static inline void board_serial_init(void) -{ - omap_serial_init_port(&serial1_data); - omap_serial_init_port(&serial2_data); - omap_serial_init_port(&serial3_data); -} #else #define board_mux NULL - -static inline void board_serial_init(void) -{ - omap_serial_init(); -} #endif /* @@ -711,7 +613,7 @@ static void __init omap_3430sdp_init(void) else gpio_pendown = SDP3430_TS_GPIO_IRQ_SDPV1; omap_ads7846_init(1, gpio_pendown, 310, NULL); - board_serial_init(); + omap_serial_init(); omap_sdrc_init(hyb18m512160af6_sdrc_params, NULL); usb_musb_init(NULL); board_smc91x_init(); diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c index bad5d5a5ef7..2ceb75d21eb 100644 --- a/arch/arm/mach-omap2/board-4430sdp.c +++ b/arch/arm/mach-omap2/board-4430sdp.c @@ -372,11 +372,17 @@ static struct platform_device sdp4430_vbat = { }, }; +static struct platform_device sdp4430_dmic_codec = { + .name = "dmic-codec", + .id = -1, +}; + static struct platform_device *sdp4430_devices[] __initdata = { &sdp4430_gpio_keys_device, &sdp4430_leds_gpio, &sdp4430_leds_pwm, &sdp4430_vbat, + &sdp4430_dmic_codec, }; static struct omap_musb_board_data musb_board_data = { @@ -404,6 +410,7 @@ static struct omap2_hsmmc_info mmc[] = { { .mmc = 5, .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD, + .pm_caps = MMC_PM_KEEP_POWER, .gpio_cd = -EINVAL, .gpio_wp = -EINVAL, .ocr_mask = MMC_VDD_165_195, @@ -837,74 +844,8 @@ static struct omap_board_mux board_mux[] __initdata = { { .reg_offset = OMAP_MUX_TERMINATOR }, }; -static struct omap_device_pad serial2_pads[] __initdata = { - OMAP_MUX_STATIC("uart2_cts.uart2_cts", - OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0), - OMAP_MUX_STATIC("uart2_rts.uart2_rts", - OMAP_PIN_OUTPUT | OMAP_MUX_MODE0), - OMAP_MUX_STATIC("uart2_rx.uart2_rx", - OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0), - OMAP_MUX_STATIC("uart2_tx.uart2_tx", - OMAP_PIN_OUTPUT | OMAP_MUX_MODE0), -}; - -static struct omap_device_pad serial3_pads[] __initdata = { - OMAP_MUX_STATIC("uart3_cts_rctx.uart3_cts_rctx", - OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0), - OMAP_MUX_STATIC("uart3_rts_sd.uart3_rts_sd", - OMAP_PIN_OUTPUT | OMAP_MUX_MODE0), - OMAP_MUX_STATIC("uart3_rx_irrx.uart3_rx_irrx", - OMAP_PIN_INPUT | OMAP_MUX_MODE0), - OMAP_MUX_STATIC("uart3_tx_irtx.uart3_tx_irtx", - OMAP_PIN_OUTPUT | OMAP_MUX_MODE0), -}; - -static struct omap_device_pad serial4_pads[] __initdata = { - OMAP_MUX_STATIC("uart4_rx.uart4_rx", - OMAP_PIN_INPUT | OMAP_MUX_MODE0), - OMAP_MUX_STATIC("uart4_tx.uart4_tx", - OMAP_PIN_OUTPUT | OMAP_MUX_MODE0), -}; - -static struct omap_board_data serial2_data __initdata = { - .id = 1, - .pads = serial2_pads, - .pads_cnt = ARRAY_SIZE(serial2_pads), -}; - -static struct omap_board_data serial3_data __initdata = { - .id = 2, - .pads = serial3_pads, - .pads_cnt = ARRAY_SIZE(serial3_pads), -}; - -static struct omap_board_data serial4_data __initdata = { - .id = 3, - .pads = serial4_pads, - .pads_cnt = ARRAY_SIZE(serial4_pads), -}; - -static inline void board_serial_init(void) -{ - struct omap_board_data bdata; - bdata.flags = 0; - bdata.pads = NULL; - bdata.pads_cnt = 0; - bdata.id = 0; - /* pass dummy data for UART1 */ - omap_serial_init_port(&bdata); - - omap_serial_init_port(&serial2_data); - omap_serial_init_port(&serial3_data); - omap_serial_init_port(&serial4_data); -} #else #define board_mux NULL - -static inline void board_serial_init(void) -{ - omap_serial_init(); -} #endif static void omap4_sdp4430_wifi_mux_init(void) @@ -954,7 +895,7 @@ static void __init omap_4430sdp_init(void) omap4_i2c_init(); omap_sfh7741prox_init(); platform_add_devices(sdp4430_devices, ARRAY_SIZE(sdp4430_devices)); - board_serial_init(); + omap_serial_init(); omap_sdrc_init(NULL, NULL); omap4_sdp4430_wifi_init(); omap4_twl6030_hsmmc_init(mmc); diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c index f5a3a3f1173..4b1cfe32e6b 100644 --- a/arch/arm/mach-omap2/board-am3517evm.c +++ b/arch/arm/mach-omap2/board-am3517evm.c @@ -24,6 +24,7 @@ #include <linux/i2c/pca953x.h> #include <linux/can/platform/ti_hecc.h> #include <linux/davinci_emac.h> +#include <linux/mmc/host.h> #include <mach/hardware.h> #include <mach/am35xx.h> @@ -40,6 +41,7 @@ #include "mux.h" #include "control.h" +#include "hsmmc.h" #define AM35XX_EVM_MDIO_FREQUENCY (1000000) @@ -455,6 +457,23 @@ static void am3517_evm_hecc_init(struct ti_hecc_platform_data *pdata) static struct omap_board_config_kernel am3517_evm_config[] __initdata = { }; +static struct omap2_hsmmc_info mmc[] = { + { + .mmc = 1, + .caps = MMC_CAP_4_BIT_DATA, + .gpio_cd = 127, + .gpio_wp = 126, + }, + { + .mmc = 2, + .caps = MMC_CAP_4_BIT_DATA, + .gpio_cd = 128, + .gpio_wp = 129, + }, + {} /* Terminator */ +}; + + static void __init am3517_evm_init(void) { omap_board_config = am3517_evm_config; @@ -483,6 +502,9 @@ static void __init am3517_evm_init(void) /* MUSB */ am3517_evm_musb_init(); + + /* MMC init function */ + omap2_hsmmc_init(mmc); } MACHINE_START(OMAP3517EVM, "OMAP3517/AM3517 EVM") diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c index 1545102d1f9..e921e3be24a 100644 --- a/arch/arm/mach-omap2/board-cm-t35.c +++ b/arch/arm/mach-omap2/board-cm-t35.c @@ -53,7 +53,8 @@ #include "hsmmc.h" #include "common-board-devices.h" -#define CM_T35_GPIO_PENDOWN 57 +#define CM_T35_GPIO_PENDOWN 57 +#define SB_T35_USB_HUB_RESET_GPIO 167 #define CM_T35_SMSC911X_CS 5 #define CM_T35_SMSC911X_GPIO 163 @@ -339,8 +340,10 @@ static struct regulator_consumer_supply cm_t35_vsim_supply[] = { REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"), }; -static struct regulator_consumer_supply cm_t35_vdvi_supply[] = { - REGULATOR_SUPPLY("vdvi", "omapdss"), +static struct regulator_consumer_supply cm_t35_vio_supplies[] = { + REGULATOR_SUPPLY("vcc", "spi1.0"), + REGULATOR_SUPPLY("vdds_dsi", "omapdss"), + REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"), }; /* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */ @@ -373,6 +376,19 @@ static struct regulator_init_data cm_t35_vsim = { .consumer_supplies = cm_t35_vsim_supply, }; +static struct regulator_init_data cm_t35_vio = { + .constraints = { + .min_uV = 1800000, + .max_uV = 1800000, + .apply_uV = true, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_MODE, + }, + .num_consumer_supplies = ARRAY_SIZE(cm_t35_vio_supplies), + .consumer_supplies = cm_t35_vio_supplies, +}; + static uint32_t cm_t35_keymap[] = { KEY(0, 0, KEY_A), KEY(0, 1, KEY_B), KEY(0, 2, KEY_LEFT), KEY(1, 0, KEY_UP), KEY(1, 1, KEY_ENTER), KEY(1, 2, KEY_DOWN), @@ -421,6 +437,23 @@ static struct usbhs_omap_board_data usbhs_bdata __initdata = { .reset_gpio_port[2] = -EINVAL }; +static void cm_t35_init_usbh(void) +{ + int err; + + err = gpio_request_one(SB_T35_USB_HUB_RESET_GPIO, + GPIOF_OUT_INIT_LOW, "usb hub rst"); + if (err) { + pr_err("SB-T35: usb hub rst gpio request failed: %d\n", err); + } else { + udelay(10); + gpio_set_value(SB_T35_USB_HUB_RESET_GPIO, 1); + msleep(1); + } + + usbhs_init(&usbhs_bdata); +} + static int cm_t35_twl_gpio_setup(struct device *dev, unsigned gpio, unsigned ngpio) { @@ -456,17 +489,14 @@ static struct twl4030_platform_data cm_t35_twldata = { .gpio = &cm_t35_gpio_data, .vmmc1 = &cm_t35_vmmc1, .vsim = &cm_t35_vsim, + .vio = &cm_t35_vio, }; static void __init cm_t35_init_i2c(void) { omap3_pmic_get_config(&cm_t35_twldata, TWL_COMMON_PDATA_USB, - TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2); - - cm_t35_twldata.vpll2->constraints.name = "VDVI"; - cm_t35_twldata.vpll2->num_consumer_supplies = - ARRAY_SIZE(cm_t35_vdvi_supply); - cm_t35_twldata.vpll2->consumer_supplies = cm_t35_vdvi_supply; + TWL_COMMON_REGULATOR_VDAC | + TWL_COMMON_PDATA_AUDIO); omap3_pmic_init("tps65930", &cm_t35_twldata); } @@ -570,24 +600,28 @@ static void __init cm_t3x_common_dss_mux_init(int mux_mode) static void __init cm_t35_init_mux(void) { - omap_mux_init_signal("gpio_70", OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT); - omap_mux_init_signal("gpio_71", OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT); - omap_mux_init_signal("gpio_72", OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT); - omap_mux_init_signal("gpio_73", OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT); - omap_mux_init_signal("gpio_74", OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT); - omap_mux_init_signal("gpio_75", OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT); - cm_t3x_common_dss_mux_init(OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT); + int mux_mode = OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT; + + omap_mux_init_signal("dss_data0.dss_data0", mux_mode); + omap_mux_init_signal("dss_data1.dss_data1", mux_mode); + omap_mux_init_signal("dss_data2.dss_data2", mux_mode); + omap_mux_init_signal("dss_data3.dss_data3", mux_mode); + omap_mux_init_signal("dss_data4.dss_data4", mux_mode); + omap_mux_init_signal("dss_data5.dss_data5", mux_mode); + cm_t3x_common_dss_mux_init(mux_mode); } static void __init cm_t3730_init_mux(void) { - omap_mux_init_signal("sys_boot0", OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT); - omap_mux_init_signal("sys_boot1", OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT); - omap_mux_init_signal("sys_boot3", OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT); - omap_mux_init_signal("sys_boot4", OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT); - omap_mux_init_signal("sys_boot5", OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT); - omap_mux_init_signal("sys_boot6", OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT); - cm_t3x_common_dss_mux_init(OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT); + int mux_mode = OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT; + + omap_mux_init_signal("sys_boot0", mux_mode); + omap_mux_init_signal("sys_boot1", mux_mode); + omap_mux_init_signal("sys_boot3", mux_mode); + omap_mux_init_signal("sys_boot4", mux_mode); + omap_mux_init_signal("sys_boot5", mux_mode); + omap_mux_init_signal("sys_boot6", mux_mode); + cm_t3x_common_dss_mux_init(mux_mode); } #else static inline void cm_t35_init_mux(void) {} @@ -612,7 +646,7 @@ static void __init cm_t3x_common_init(void) cm_t35_init_display(); usb_musb_init(NULL); - usbhs_init(&usbhs_bdata); + cm_t35_init_usbh(); } static void __init cm_t35_init(void) diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c index f8c5b2cc7c9..d5875606048 100644 --- a/arch/arm/mach-omap2/board-generic.c +++ b/arch/arm/mach-omap2/board-generic.c @@ -69,7 +69,6 @@ static void __init omap_generic_init(void) if (node) irq_domain_add_simple(node, 0); - omap_serial_init(); omap_sdrc_init(NULL, NULL); of_platform_populate(NULL, omap_dt_match_table, NULL, NULL); diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c index cef2cf1c0b8..42a4d11fad2 100644 --- a/arch/arm/mach-omap2/board-n8x0.c +++ b/arch/arm/mach-omap2/board-n8x0.c @@ -46,7 +46,7 @@ static struct device *mmc_device; #define TUSB6010_GPIO_ENABLE 0 #define TUSB6010_DMACHAN 0x3f -#ifdef CONFIG_USB_MUSB_TUSB6010 +#if defined(CONFIG_USB_MUSB_TUSB6010) || defined(CONFIG_USB_MUSB_TUSB6010_MODULE) /* * Enable or disable power to TUSB6010. When enabling, turn on 3.3 V and * 1.5 V voltage regulators of PM companion chip. Companion chip will then @@ -644,15 +644,15 @@ static inline void board_serial_init(void) bdata.pads_cnt = 0; bdata.id = 0; - omap_serial_init_port(&bdata); + omap_serial_init_port(&bdata, NULL); bdata.id = 1; - omap_serial_init_port(&bdata); + omap_serial_init_port(&bdata, NULL); bdata.id = 2; bdata.pads = serial2_pads; bdata.pads_cnt = ARRAY_SIZE(serial2_pads); - omap_serial_init_port(&bdata); + omap_serial_init_port(&bdata, NULL); } #else diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c index 8b06c6a60d0..e96a2e7ad36 100644 --- a/arch/arm/mach-omap2/board-omap4panda.c +++ b/arch/arm/mach-omap2/board-omap4panda.c @@ -364,74 +364,8 @@ static struct omap_board_mux board_mux[] __initdata = { { .reg_offset = OMAP_MUX_TERMINATOR }, }; -static struct omap_device_pad serial2_pads[] __initdata = { - OMAP_MUX_STATIC("uart2_cts.uart2_cts", - OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0), - OMAP_MUX_STATIC("uart2_rts.uart2_rts", - OMAP_PIN_OUTPUT | OMAP_MUX_MODE0), - OMAP_MUX_STATIC("uart2_rx.uart2_rx", - OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0), - OMAP_MUX_STATIC("uart2_tx.uart2_tx", - OMAP_PIN_OUTPUT | OMAP_MUX_MODE0), -}; - -static struct omap_device_pad serial3_pads[] __initdata = { - OMAP_MUX_STATIC("uart3_cts_rctx.uart3_cts_rctx", - OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0), - OMAP_MUX_STATIC("uart3_rts_sd.uart3_rts_sd", - OMAP_PIN_OUTPUT | OMAP_MUX_MODE0), - OMAP_MUX_STATIC("uart3_rx_irrx.uart3_rx_irrx", - OMAP_PIN_INPUT | OMAP_MUX_MODE0), - OMAP_MUX_STATIC("uart3_tx_irtx.uart3_tx_irtx", - OMAP_PIN_OUTPUT | OMAP_MUX_MODE0), -}; - -static struct omap_device_pad serial4_pads[] __initdata = { - OMAP_MUX_STATIC("uart4_rx.uart4_rx", - OMAP_PIN_INPUT | OMAP_MUX_MODE0), - OMAP_MUX_STATIC("uart4_tx.uart4_tx", - OMAP_PIN_OUTPUT | OMAP_MUX_MODE0), -}; - -static struct omap_board_data serial2_data __initdata = { - .id = 1, - .pads = serial2_pads, - .pads_cnt = ARRAY_SIZE(serial2_pads), -}; - -static struct omap_board_data serial3_data __initdata = { - .id = 2, - .pads = serial3_pads, - .pads_cnt = ARRAY_SIZE(serial3_pads), -}; - -static struct omap_board_data serial4_data __initdata = { - .id = 3, - .pads = serial4_pads, - .pads_cnt = ARRAY_SIZE(serial4_pads), -}; - -static inline void board_serial_init(void) -{ - struct omap_board_data bdata; - bdata.flags = 0; - bdata.pads = NULL; - bdata.pads_cnt = 0; - bdata.id = 0; - /* pass dummy data for UART1 */ - omap_serial_init_port(&bdata); - - omap_serial_init_port(&serial2_data); - omap_serial_init_port(&serial3_data); - omap_serial_init_port(&serial4_data); -} #else #define board_mux NULL - -static inline void board_serial_init(void) -{ - omap_serial_init(); -} #endif /* Display DVI */ @@ -562,7 +496,7 @@ static void __init omap4_panda_init(void) omap4_panda_i2c_init(); platform_add_devices(panda_devices, ARRAY_SIZE(panda_devices)); platform_device_register(&omap_vwlan_device); - board_serial_init(); + omap_serial_init(); omap_sdrc_init(NULL, NULL); omap4_twl6030_hsmmc_init(mmc); omap4_ehci_init(); diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c index 108fee6146f..acb4e77b39e 100644 --- a/arch/arm/mach-omap2/board-rx51-peripherals.c +++ b/arch/arm/mach-omap2/board-rx51-peripherals.c @@ -15,6 +15,7 @@ #include <linux/input/matrix_keypad.h> #include <linux/spi/spi.h> #include <linux/wl12xx.h> +#include <linux/spi/tsc2005.h> #include <linux/i2c.h> #include <linux/i2c/twl.h> #include <linux/clk.h> @@ -58,6 +59,9 @@ #define RX51_USB_TRANSCEIVER_RST_GPIO 67 +#define RX51_TSC2005_RESET_GPIO 104 +#define RX51_TSC2005_IRQ_GPIO 100 + /* list all spi devices here */ enum { RX51_SPI_WL1251, @@ -66,6 +70,7 @@ enum { }; static struct wl12xx_platform_data wl1251_pdata; +static struct tsc2005_platform_data tsc2005_pdata; #if defined(CONFIG_SENSORS_TSL2563) || defined(CONFIG_SENSORS_TSL2563_MODULE) static struct tsl2563_platform_data rx51_tsl2563_platform_data = { @@ -167,10 +172,10 @@ static struct spi_board_info rx51_peripherals_spi_board_info[] __initdata = { .modalias = "tsc2005", .bus_num = 1, .chip_select = 0, - /* .irq = OMAP_GPIO_IRQ(RX51_TSC2005_IRQ_GPIO),*/ + .irq = OMAP_GPIO_IRQ(RX51_TSC2005_IRQ_GPIO), .max_speed_hz = 6000000, .controller_data = &tsc2005_mcspi_config, - /* .platform_data = &tsc2005_config,*/ + .platform_data = &tsc2005_pdata, }, }; @@ -940,6 +945,9 @@ static struct i2c_board_info __initdata rx51_peripherals_i2c_board_info_2[] = { }, #endif { + I2C_BOARD_INFO("bq27200", 0x55), + }, + { I2C_BOARD_INFO("tpa6130a2", 0x60), .platform_data = &rx51_tpa6130a2_data, } @@ -1086,6 +1094,42 @@ error: */ } +static struct tsc2005_platform_data tsc2005_pdata = { + .ts_pressure_max = 2048, + .ts_pressure_fudge = 2, + .ts_x_max = 4096, + .ts_x_fudge = 4, + .ts_y_max = 4096, + .ts_y_fudge = 7, + .ts_x_plate_ohm = 280, + .esd_timeout_ms = 8000, +}; + +static void rx51_tsc2005_set_reset(bool enable) +{ + gpio_set_value(RX51_TSC2005_RESET_GPIO, enable); +} + +static void __init rx51_init_tsc2005(void) +{ + int r; + + r = gpio_request_one(RX51_TSC2005_IRQ_GPIO, GPIOF_IN, "tsc2005 IRQ"); + if (r < 0) { + printk(KERN_ERR "unable to get %s GPIO\n", "tsc2005 IRQ"); + rx51_peripherals_spi_board_info[RX51_SPI_TSC2005].irq = 0; + } + + r = gpio_request_one(RX51_TSC2005_RESET_GPIO, GPIOF_OUT_INIT_HIGH, + "tsc2005 reset"); + if (r >= 0) { + tsc2005_pdata.set_reset = rx51_tsc2005_set_reset; + } else { + printk(KERN_ERR "unable to get %s GPIO\n", "tsc2005 reset"); + tsc2005_pdata.esd_timeout_ms = 0; + } +} + void __init rx51_peripherals_init(void) { rx51_i2c_init(); @@ -1094,6 +1138,7 @@ void __init rx51_peripherals_init(void) board_smc91x_init(); rx51_add_gpio_keys(); rx51_init_wl1251(); + rx51_init_tsc2005(); rx51_init_si4713(); spi_register_board_info(rx51_peripherals_spi_board_info, ARRAY_SIZE(rx51_peripherals_spi_board_info)); diff --git a/arch/arm/mach-omap2/board-ti8168evm.c b/arch/arm/mach-omap2/board-ti8168evm.c index 74713e3993e..ab9a7a9e9d6 100644 --- a/arch/arm/mach-omap2/board-ti8168evm.c +++ b/arch/arm/mach-omap2/board-ti8168evm.c @@ -1,5 +1,5 @@ /* - * Code for TI8168 EVM. + * Code for TI8168/TI8148 EVM. * * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/ * @@ -23,30 +23,45 @@ #include <plat/irqs.h> #include <plat/board.h> #include "common.h" +#include <plat/usb.h> -static struct omap_board_config_kernel ti8168_evm_config[] __initdata = { +static struct omap_musb_board_data musb_board_data = { + .set_phy_power = ti81xx_musb_phy_power, + .interface_type = MUSB_INTERFACE_ULPI, + .mode = MUSB_OTG, + .power = 500, }; -static void __init ti8168_evm_init(void) +static struct omap_board_config_kernel ti81xx_evm_config[] __initdata = { +}; + +static void __init ti81xx_evm_init(void) { omap_serial_init(); omap_sdrc_init(NULL, NULL); - omap_board_config = ti8168_evm_config; - omap_board_config_size = ARRAY_SIZE(ti8168_evm_config); -} - -static void __init ti8168_evm_map_io(void) -{ - omapti816x_map_common_io(); + omap_board_config = ti81xx_evm_config; + omap_board_config_size = ARRAY_SIZE(ti81xx_evm_config); + usb_musb_init(&musb_board_data); } MACHINE_START(TI8168EVM, "ti8168evm") /* Maintainer: Texas Instruments */ .atag_offset = 0x100, - .map_io = ti8168_evm_map_io, - .init_early = ti816x_init_early, - .init_irq = ti816x_init_irq, + .map_io = ti81xx_map_io, + .init_early = ti81xx_init_early, + .init_irq = ti81xx_init_irq, + .timer = &omap3_timer, + .init_machine = ti81xx_evm_init, + .restart = omap_prcm_restart, +MACHINE_END + +MACHINE_START(TI8148EVM, "ti8148evm") + /* Maintainer: Texas Instruments */ + .atag_offset = 0x100, + .map_io = ti81xx_map_io, + .init_early = ti81xx_init_early, + .init_irq = ti81xx_init_irq, .timer = &omap3_timer, - .init_machine = ti8168_evm_init, + .init_machine = ti81xx_evm_init, .restart = omap_prcm_restart, MACHINE_END diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 1f3481f8d69..f57ed5baecc 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -35,7 +35,7 @@ #include "cm-regbits-24xx.h" #include "cm-regbits-34xx.h" -u8 cpu_mask; +u16 cpu_mask; /* * clkdm_control: if true, then when a clock is enabled in the diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index 2311bc21722..b8c2a686481 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -132,7 +132,7 @@ void omap2_clk_print_new_rates(const char *hfclkin_ck_name, const char *core_ck_name, const char *mpu_ck_name); -extern u8 cpu_mask; +extern u16 cpu_mask; extern const struct clkops clkops_omap2_dflt_wait; extern const struct clkops clkops_dummy; diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c index 5d0064a4fb5..d75e5f6b8a0 100644 --- a/arch/arm/mach-omap2/clock3xxx_data.c +++ b/arch/arm/mach-omap2/clock3xxx_data.c @@ -2480,6 +2480,16 @@ static struct clk uart4_fck = { .recalc = &followparent_recalc, }; +static struct clk uart4_fck_am35xx = { + .name = "uart4_fck", + .ops = &clkops_omap2_dflt_wait, + .parent = &per_48m_fck, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP3430_EN_UART4_SHIFT, + .clkdm_name = "core_l4_clkdm", + .recalc = &followparent_recalc, +}; + static struct clk gpt2_fck = { .name = "gpt2_fck", .ops = &clkops_omap2_dflt_wait, @@ -3287,7 +3297,7 @@ static struct omap_clk omap3xxx_clks[] = { CLK(NULL, "cpefuse_fck", &cpefuse_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), - CLK("usbhs-omap.0", "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), + CLK("usbhs_omap", "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), CLK("omap-mcbsp.1", "prcm_fck", &core_96m_fck, CK_3XXX), CLK("omap-mcbsp.5", "prcm_fck", &core_96m_fck, CK_3XXX), CLK(NULL, "core_96m_fck", &core_96m_fck, CK_3XXX), @@ -3323,7 +3333,7 @@ static struct omap_clk omap3xxx_clks[] = { CLK(NULL, "pka_ick", &pka_ick, CK_34XX | CK_36XX), CLK(NULL, "core_l4_ick", &core_l4_ick, CK_3XXX), CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), - CLK("usbhs-omap.0", "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), + CLK("usbhs_omap", "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), CLK("omap_hsmmc.2", "ick", &mmchs3_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), CLK(NULL, "icr_ick", &icr_ick, CK_34XX | CK_36XX), CLK("omap-aes", "ick", &aes2_ick, CK_34XX | CK_36XX), @@ -3369,20 +3379,18 @@ static struct omap_clk omap3xxx_clks[] = { CLK(NULL, "cam_ick", &cam_ick, CK_34XX | CK_36XX), CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_34XX | CK_36XX), CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), - CLK("usbhs-omap.0", "hs_fck", &usbhost_120m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), - CLK("usbhs-omap.0", "fs_fck", &usbhost_48m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), CLK(NULL, "usbhost_ick", &usbhost_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), - CLK("usbhs-omap.0", "usbhost_ick", &usbhost_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), - CLK("usbhs-omap.0", "utmi_p1_gfclk", &dummy_ck, CK_3XXX), - CLK("usbhs-omap.0", "utmi_p2_gfclk", &dummy_ck, CK_3XXX), - CLK("usbhs-omap.0", "xclk60mhsp1_ck", &dummy_ck, CK_3XXX), - CLK("usbhs-omap.0", "xclk60mhsp2_ck", &dummy_ck, CK_3XXX), - CLK("usbhs-omap.0", "usb_host_hs_utmi_p1_clk", &dummy_ck, CK_3XXX), - CLK("usbhs-omap.0", "usb_host_hs_utmi_p2_clk", &dummy_ck, CK_3XXX), - CLK("usbhs-omap.0", "usb_tll_hs_usb_ch0_clk", &dummy_ck, CK_3XXX), - CLK("usbhs-omap.0", "usb_tll_hs_usb_ch1_clk", &dummy_ck, CK_3XXX), - CLK("usbhs-omap.0", "init_60m_fclk", &dummy_ck, CK_3XXX), + CLK("usbhs_omap", "usbhost_ick", &usbhost_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), + CLK("usbhs_omap", "utmi_p1_gfclk", &dummy_ck, CK_3XXX), + CLK("usbhs_omap", "utmi_p2_gfclk", &dummy_ck, CK_3XXX), + CLK("usbhs_omap", "xclk60mhsp1_ck", &dummy_ck, CK_3XXX), + CLK("usbhs_omap", "xclk60mhsp2_ck", &dummy_ck, CK_3XXX), + CLK("usbhs_omap", "usb_host_hs_utmi_p1_clk", &dummy_ck, CK_3XXX), + CLK("usbhs_omap", "usb_host_hs_utmi_p2_clk", &dummy_ck, CK_3XXX), + CLK("usbhs_omap", "usb_tll_hs_usb_ch0_clk", &dummy_ck, CK_3XXX), + CLK("usbhs_omap", "usb_tll_hs_usb_ch1_clk", &dummy_ck, CK_3XXX), + CLK("usbhs_omap", "init_60m_fclk", &dummy_ck, CK_3XXX), CLK(NULL, "usim_fck", &usim_fck, CK_3430ES2PLUS | CK_36XX), CLK(NULL, "gpt1_fck", &gpt1_fck, CK_3XXX), CLK(NULL, "wkup_32k_fck", &wkup_32k_fck, CK_3XXX), @@ -3403,6 +3411,7 @@ static struct omap_clk omap3xxx_clks[] = { CLK(NULL, "per_48m_fck", &per_48m_fck, CK_3XXX), CLK(NULL, "uart3_fck", &uart3_fck, CK_3XXX), CLK(NULL, "uart4_fck", &uart4_fck, CK_36XX), + CLK(NULL, "uart4_fck", &uart4_fck_am35xx, CK_3505 | CK_3517), CLK(NULL, "gpt2_fck", &gpt2_fck, CK_3XXX), CLK(NULL, "gpt3_fck", &gpt3_fck, CK_3XXX), CLK(NULL, "gpt4_fck", &gpt4_fck, CK_3XXX), @@ -3517,6 +3526,10 @@ int __init omap3xxx_clk_init(void) } else if (cpu_is_ti816x()) { cpu_mask = RATE_IN_TI816X; cpu_clkflg = CK_TI816X; + } else if (cpu_is_am33xx()) { + cpu_mask = RATE_IN_AM33XX; + } else if (cpu_is_ti814x()) { + cpu_mask = RATE_IN_TI814X; } else if (cpu_is_omap34xx()) { if (omap_rev() == OMAP3430_REV_ES1_0) { cpu_mask = RATE_IN_3430ES1; @@ -3600,7 +3613,7 @@ int __init omap3xxx_clk_init(void) * Lock DPLL5 -- here only until other device init code can * handle this */ - if (!cpu_is_ti816x() && (omap_rev() >= OMAP3430_REV_ES2_0)) + if (!cpu_is_ti81xx() && (omap_rev() >= OMAP3430_REV_ES2_0)) omap3_clk_lock_dpll5(); /* Avoid sleeping during omap3_core_dpll_m2_set_rate() */ diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c index 0798a802497..08e86d793a1 100644 --- a/arch/arm/mach-omap2/clock44xx_data.c +++ b/arch/arm/mach-omap2/clock44xx_data.c @@ -1206,6 +1206,14 @@ static const struct clksel ocp_abe_iclk_div[] = { { .parent = NULL }, }; +static struct clk mpu_periphclk = { + .name = "mpu_periphclk", + .parent = &dpll_mpu_ck, + .ops = &clkops_null, + .fixed_div = 2, + .recalc = &omap_fixed_divisor_recalc, +}; + static struct clk ocp_abe_iclk = { .name = "ocp_abe_iclk", .parent = &aess_fclk, @@ -3189,6 +3197,7 @@ static struct omap_clk omap44xx_clks[] = { CLK(NULL, "l4_div_ck", &l4_div_ck, CK_443X), CLK(NULL, "lp_clk_div_ck", &lp_clk_div_ck, CK_443X), CLK(NULL, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, CK_443X), + CLK("smp_twd", NULL, &mpu_periphclk, CK_443X), CLK(NULL, "ocp_abe_iclk", &ocp_abe_iclk, CK_443X), CLK(NULL, "per_abe_24m_fclk", &per_abe_24m_fclk, CK_443X), CLK(NULL, "per_abe_nc_fclk", &per_abe_nc_fclk, CK_443X), @@ -3295,7 +3304,7 @@ static struct omap_clk omap44xx_clks[] = { CLK(NULL, "uart2_fck", &uart2_fck, CK_443X), CLK(NULL, "uart3_fck", &uart3_fck, CK_443X), CLK(NULL, "uart4_fck", &uart4_fck, CK_443X), - CLK("usbhs-omap.0", "fs_fck", &usb_host_fs_fck, CK_443X), + CLK("usbhs_omap", "fs_fck", &usb_host_fs_fck, CK_443X), CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk, CK_443X), CLK(NULL, "usb_host_hs_utmi_p1_clk", &usb_host_hs_utmi_p1_clk, CK_443X), CLK(NULL, "utmi_p2_gfclk", &utmi_p2_gfclk, CK_443X), @@ -3306,7 +3315,7 @@ static struct omap_clk omap44xx_clks[] = { CLK(NULL, "usb_host_hs_hsic60m_p2_clk", &usb_host_hs_hsic60m_p2_clk, CK_443X), CLK(NULL, "usb_host_hs_hsic480m_p2_clk", &usb_host_hs_hsic480m_p2_clk, CK_443X), CLK(NULL, "usb_host_hs_func48mclk", &usb_host_hs_func48mclk, CK_443X), - CLK("usbhs-omap.0", "hs_fck", &usb_host_hs_fck, CK_443X), + CLK("usbhs_omap", "hs_fck", &usb_host_hs_fck, CK_443X), CLK(NULL, "otg_60m_gfclk", &otg_60m_gfclk, CK_443X), CLK(NULL, "usb_otg_hs_xclk", &usb_otg_hs_xclk, CK_443X), CLK("musb-omap2430", "ick", &usb_otg_hs_ick, CK_443X), @@ -3314,7 +3323,7 @@ static struct omap_clk omap44xx_clks[] = { CLK(NULL, "usb_tll_hs_usb_ch2_clk", &usb_tll_hs_usb_ch2_clk, CK_443X), CLK(NULL, "usb_tll_hs_usb_ch0_clk", &usb_tll_hs_usb_ch0_clk, CK_443X), CLK(NULL, "usb_tll_hs_usb_ch1_clk", &usb_tll_hs_usb_ch1_clk, CK_443X), - CLK("usbhs-omap.0", "usbtll_ick", &usb_tll_hs_ick, CK_443X), + CLK("usbhs_omap", "usbtll_ick", &usb_tll_hs_ick, CK_443X), CLK(NULL, "usim_ck", &usim_ck, CK_443X), CLK(NULL, "usim_fclk", &usim_fclk, CK_443X), CLK(NULL, "usim_fck", &usim_fck, CK_443X), @@ -3374,8 +3383,8 @@ static struct omap_clk omap44xx_clks[] = { CLK(NULL, "uart2_ick", &dummy_ck, CK_443X), CLK(NULL, "uart3_ick", &dummy_ck, CK_443X), CLK(NULL, "uart4_ick", &dummy_ck, CK_443X), - CLK("usbhs-omap.0", "usbhost_ick", &dummy_ck, CK_443X), - CLK("usbhs-omap.0", "usbtll_fck", &dummy_ck, CK_443X), + CLK("usbhs_omap", "usbhost_ick", &dummy_ck, CK_443X), + CLK("usbhs_omap", "usbtll_fck", &dummy_ck, CK_443X), CLK("omap_wdt", "ick", &dummy_ck, CK_443X), CLK("omap_timer.1", "32k_ck", &sys_32k_ck, CK_443X), CLK("omap_timer.2", "32k_ck", &sys_32k_ck, CK_443X), diff --git a/arch/arm/mach-omap2/common.c b/arch/arm/mach-omap2/common.c index 684b8a7cd40..aaf421178c9 100644 --- a/arch/arm/mach-omap2/common.c +++ b/arch/arm/mach-omap2/common.c @@ -110,23 +110,49 @@ void __init omap3_map_io(void) /* * Adjust TAP register base such that omap3_check_revision accesses the correct - * TI816X register for checking device ID (it adds 0x204 to tap base while - * TI816X DEVICE ID register is at offset 0x600 from control base). + * TI81XX register for checking device ID (it adds 0x204 to tap base while + * TI81XX DEVICE ID register is at offset 0x600 from control base). */ -#define TI816X_TAP_BASE (TI816X_CTRL_BASE + \ - TI816X_CONTROL_DEVICE_ID - 0x204) +#define TI81XX_TAP_BASE (TI81XX_CTRL_BASE + \ + TI81XX_CONTROL_DEVICE_ID - 0x204) -static struct omap_globals ti816x_globals = { +static struct omap_globals ti81xx_globals = { .class = OMAP343X_CLASS, - .tap = OMAP2_L4_IO_ADDRESS(TI816X_TAP_BASE), - .ctrl = OMAP2_L4_IO_ADDRESS(TI816X_CTRL_BASE), - .prm = OMAP2_L4_IO_ADDRESS(TI816X_PRCM_BASE), - .cm = OMAP2_L4_IO_ADDRESS(TI816X_PRCM_BASE), + .tap = OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE), + .ctrl = OMAP2_L4_IO_ADDRESS(TI81XX_CTRL_BASE), + .prm = OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE), + .cm = OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE), }; -void __init omap2_set_globals_ti816x(void) +void __init omap2_set_globals_ti81xx(void) { - __omap2_set_globals(&ti816x_globals); + __omap2_set_globals(&ti81xx_globals); +} + +void __init ti81xx_map_io(void) +{ + omapti81xx_map_common_io(); +} + +#define AM33XX_TAP_BASE (AM33XX_CTRL_BASE + \ + TI81XX_CONTROL_DEVICE_ID - 0x204) + +static struct omap_globals am33xx_globals = { + .class = AM335X_CLASS, + .tap = AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE), + .ctrl = AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE), + .prm = AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE), + .cm = AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE), +}; + +void __init omap2_set_globals_am33xx(void) +{ + __omap2_set_globals(&am33xx_globals); +} + +void __init am33xx_map_io(void) +{ + omapam33xx_map_common_io(); } #endif diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h index cda888a2e63..febffde2ff1 100644 --- a/arch/arm/mach-omap2/common.h +++ b/arch/arm/mach-omap2/common.h @@ -24,9 +24,11 @@ #ifndef __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H #define __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H +#ifndef __ASSEMBLER__ #include <linux/delay.h> #include <plat/common.h> +#include <asm/proc-fns.h> #ifdef CONFIG_SOC_OMAP2420 extern void omap242x_map_common_io(void); @@ -52,10 +54,18 @@ static inline void omap34xx_map_common_io(void) } #endif -#ifdef CONFIG_SOC_OMAPTI816X -extern void omapti816x_map_common_io(void); +#ifdef CONFIG_SOC_OMAPTI81XX +extern void omapti81xx_map_common_io(void); #else -static inline void omapti816x_map_common_io(void) +static inline void omapti81xx_map_common_io(void) +{ +} +#endif + +#ifdef CONFIG_SOC_OMAPAM33XX +extern void omapam33xx_map_common_io(void); +#else +static inline void omapam33xx_map_common_io(void) { } #endif @@ -82,7 +92,7 @@ void omap35xx_init_early(void); void omap3630_init_early(void); void omap3_init_early(void); /* Do not use this one */ void am35xx_init_early(void); -void ti816x_init_early(void); +void ti81xx_init_early(void); void omap4430_init_early(void); void omap_prcm_restart(char, const char *); @@ -107,7 +117,8 @@ void omap2_set_globals_242x(void); void omap2_set_globals_243x(void); void omap2_set_globals_3xxx(void); void omap2_set_globals_443x(void); -void omap2_set_globals_ti816x(void); +void omap2_set_globals_ti81xx(void); +void omap2_set_globals_am33xx(void); /* These get called from omap2_set_globals_xxxx(), do not call these */ void omap2_set_globals_tap(struct omap_globals *); @@ -118,7 +129,9 @@ void omap2_set_globals_prcm(struct omap_globals *); void omap242x_map_io(void); void omap243x_map_io(void); void omap3_map_io(void); +void am33xx_map_io(void); void omap4_map_io(void); +void ti81xx_map_io(void); /** * omap_test_timeout - busy-loop, testing a condition @@ -147,7 +160,7 @@ extern struct device *omap4_get_dsp_device(void); void omap2_init_irq(void); void omap3_init_irq(void); -void ti816x_init_irq(void); +void ti81xx_init_irq(void); extern int omap_irq_pending(void); void omap_intc_save_context(void); void omap_intc_restore_context(void); @@ -157,23 +170,23 @@ void omap3_intc_resume_idle(void); void omap2_intc_handle_irq(struct pt_regs *regs); void omap3_intc_handle_irq(struct pt_regs *regs); -/* - * wfi used in low power code. Directly opcode is used instead - * of instruction to avoid mulit-omap build break - */ -#ifdef CONFIG_THUMB2_KERNEL -#define do_wfi() __asm__ __volatile__ ("wfi" : : : "memory") -#else -#define do_wfi() \ - __asm__ __volatile__ (".word 0xe320f003" : : : "memory") +#ifdef CONFIG_CACHE_L2X0 +extern void __iomem *omap4_get_l2cache_base(void); #endif -#ifdef CONFIG_CACHE_L2X0 -extern void __iomem *l2cache_base; +#ifdef CONFIG_SMP +extern void __iomem *omap4_get_scu_base(void); +#else +static inline void __iomem *omap4_get_scu_base(void) +{ + return NULL; +} #endif extern void __init gic_init_irq(void); extern void omap_smc1(u32 fn, u32 arg); +extern void __iomem *omap4_get_sar_ram_base(void); +extern void omap_do_wfi(void); #ifdef CONFIG_SMP /* Needed for secondary core boot */ @@ -183,4 +196,44 @@ extern void omap_auxcoreboot_addr(u32 cpu_addr); extern u32 omap_read_auxcoreboot0(void); #endif +#if defined(CONFIG_SMP) && defined(CONFIG_PM) +extern int omap4_mpuss_init(void); +extern int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state); +extern int omap4_finish_suspend(unsigned long cpu_state); +extern void omap4_cpu_resume(void); +extern int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state); +extern u32 omap4_mpuss_read_prev_context_state(void); +#else +static inline int omap4_enter_lowpower(unsigned int cpu, + unsigned int power_state) +{ + cpu_do_idle(); + return 0; +} + +static inline int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state) +{ + cpu_do_idle(); + return 0; +} + +static inline int omap4_mpuss_init(void) +{ + return 0; +} + +static inline int omap4_finish_suspend(unsigned long cpu_state) +{ + return 0; +} + +static inline void omap4_cpu_resume(void) +{} + +static inline u32 omap4_mpuss_read_prev_context_state(void) +{ + return 0; +} +#endif +#endif /* __ASSEMBLER__ */ #endif /* __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H */ diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h index d4ef75d5a38..0ba68d3764b 100644 --- a/arch/arm/mach-omap2/control.h +++ b/arch/arm/mach-omap2/control.h @@ -52,8 +52,8 @@ #define OMAP343X_CONTROL_PADCONFS_WKUP 0xa00 #define OMAP343X_CONTROL_GENERAL_WKUP 0xa60 -/* TI816X spefic control submodules */ -#define TI816X_CONTROL_DEVCONF 0x600 +/* TI81XX spefic control submodules */ +#define TI81XX_CONTROL_DEVCONF 0x600 /* Control register offsets - read/write with omap_ctrl_{read,write}{bwl}() */ @@ -244,8 +244,8 @@ #define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250 #define OMAP3_PADCONF_SAD2D_IDLEACK 0x254 -/* TI816X CONTROL_DEVCONF register offsets */ -#define TI816X_CONTROL_DEVICE_ID (TI816X_CONTROL_DEVCONF + 0x000) +/* TI81XX CONTROL_DEVCONF register offsets */ +#define TI81XX_CONTROL_DEVICE_ID (TI81XX_CONTROL_DEVCONF + 0x000) /* * REVISIT: This list of registers is not comprehensive - there are more diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c index e20332f4abd..464cffde58f 100644 --- a/arch/arm/mach-omap2/cpuidle34xx.c +++ b/arch/arm/mach-omap2/cpuidle34xx.c @@ -25,12 +25,12 @@ #include <linux/sched.h> #include <linux/cpuidle.h> #include <linux/export.h> +#include <linux/cpu_pm.h> #include <plat/prcm.h> #include <plat/irqs.h> #include "powerdomain.h" #include "clockdomain.h" -#include <plat/serial.h> #include "pm.h" #include "control.h" @@ -124,9 +124,23 @@ static int omap3_enter_idle(struct cpuidle_device *dev, pwrdm_for_each_clkdm(core_pd, _cpuidle_deny_idle); } + /* + * Call idle CPU PM enter notifier chain so that + * VFP context is saved. + */ + if (mpu_state == PWRDM_POWER_OFF) + cpu_pm_enter(); + /* Execute ARM wfi */ omap_sram_idle(); + /* + * Call idle CPU PM enter notifier chain to restore + * VFP context. + */ + if (pwrdm_read_prev_pwrst(mpu_pd) == PWRDM_POWER_OFF) + cpu_pm_exit(); + /* Re-allow idle for C1 */ if (index == 0) { pwrdm_for_each_clkdm(mpu_pd, _cpuidle_allow_idle); @@ -245,11 +259,6 @@ static int omap3_enter_idle_bm(struct cpuidle_device *dev, struct omap3_idle_statedata *cx; int ret; - if (!omap3_can_sleep()) { - new_state_idx = drv->safe_state_index; - goto select_state; - } - /* * Prevent idle completely if CAM is active. * CAM does not have wakeup capability in OMAP3. diff --git a/arch/arm/mach-omap2/cpuidle44xx.c b/arch/arm/mach-omap2/cpuidle44xx.c new file mode 100644 index 00000000000..cfdbb86bc84 --- /dev/null +++ b/arch/arm/mach-omap2/cpuidle44xx.c @@ -0,0 +1,245 @@ +/* + * OMAP4 CPU idle Routines + * + * Copyright (C) 2011 Texas Instruments, Inc. + * Santosh Shilimkar <santosh.shilimkar@ti.com> + * Rajendra Nayak <rnayak@ti.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/sched.h> +#include <linux/cpuidle.h> +#include <linux/cpu_pm.h> +#include <linux/export.h> +#include <linux/clockchips.h> + +#include <asm/proc-fns.h> + +#include "common.h" +#include "pm.h" +#include "prm.h" + +#ifdef CONFIG_CPU_IDLE + +/* Machine specific information to be recorded in the C-state driver_data */ +struct omap4_idle_statedata { + u32 cpu_state; + u32 mpu_logic_state; + u32 mpu_state; + u8 valid; +}; + +static struct cpuidle_params cpuidle_params_table[] = { + /* C1 - CPU0 ON + CPU1 ON + MPU ON */ + {.exit_latency = 2 + 2 , .target_residency = 5, .valid = 1}, + /* C2- CPU0 OFF + CPU1 OFF + MPU CSWR */ + {.exit_latency = 328 + 440 , .target_residency = 960, .valid = 1}, + /* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */ + {.exit_latency = 460 + 518 , .target_residency = 1100, .valid = 1}, +}; + +#define OMAP4_NUM_STATES ARRAY_SIZE(cpuidle_params_table) + +struct omap4_idle_statedata omap4_idle_data[OMAP4_NUM_STATES]; +static struct powerdomain *mpu_pd, *cpu0_pd, *cpu1_pd; + +/** + * omap4_enter_idle - Programs OMAP4 to enter the specified state + * @dev: cpuidle device + * @drv: cpuidle driver + * @index: the index of state to be entered + * + * Called from the CPUidle framework to program the device to the + * specified low power state selected by the governor. + * Returns the amount of time spent in the low power state. + */ +static int omap4_enter_idle(struct cpuidle_device *dev, + struct cpuidle_driver *drv, + int index) +{ + struct omap4_idle_statedata *cx = + cpuidle_get_statedata(&dev->states_usage[index]); + struct timespec ts_preidle, ts_postidle, ts_idle; + u32 cpu1_state; + int idle_time; + int new_state_idx; + int cpu_id = smp_processor_id(); + + /* Used to keep track of the total time in idle */ + getnstimeofday(&ts_preidle); + + local_irq_disable(); + local_fiq_disable(); + + /* + * CPU0 has to stay ON (i.e in C1) until CPU1 is OFF state. + * This is necessary to honour hardware recommondation + * of triggeing all the possible low power modes once CPU1 is + * out of coherency and in OFF mode. + * Update dev->last_state so that governor stats reflects right + * data. + */ + cpu1_state = pwrdm_read_pwrst(cpu1_pd); + if (cpu1_state != PWRDM_POWER_OFF) { + new_state_idx = drv->safe_state_index; + cx = cpuidle_get_statedata(&dev->states_usage[new_state_idx]); + } + + if (index > 0) + clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu_id); + + /* + * Call idle CPU PM enter notifier chain so that + * VFP and per CPU interrupt context is saved. + */ + if (cx->cpu_state == PWRDM_POWER_OFF) + cpu_pm_enter(); + + pwrdm_set_logic_retst(mpu_pd, cx->mpu_logic_state); + omap_set_pwrdm_state(mpu_pd, cx->mpu_state); + + /* + * Call idle CPU cluster PM enter notifier chain + * to save GIC and wakeupgen context. + */ + if ((cx->mpu_state == PWRDM_POWER_RET) && + (cx->mpu_logic_state == PWRDM_POWER_OFF)) + cpu_cluster_pm_enter(); + + omap4_enter_lowpower(dev->cpu, cx->cpu_state); + + /* + * Call idle CPU PM exit notifier chain to restore + * VFP and per CPU IRQ context. Only CPU0 state is + * considered since CPU1 is managed by CPU hotplug. + */ + if (pwrdm_read_prev_pwrst(cpu0_pd) == PWRDM_POWER_OFF) + cpu_pm_exit(); + + /* + * Call idle CPU cluster PM exit notifier chain + * to restore GIC and wakeupgen context. + */ + if (omap4_mpuss_read_prev_context_state()) + cpu_cluster_pm_exit(); + + if (index > 0) + clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu_id); + + getnstimeofday(&ts_postidle); + ts_idle = timespec_sub(ts_postidle, ts_preidle); + + local_irq_enable(); + local_fiq_enable(); + + idle_time = ts_idle.tv_nsec / NSEC_PER_USEC + ts_idle.tv_sec * \ + USEC_PER_SEC; + + /* Update cpuidle counters */ + dev->last_residency = idle_time; + + return index; +} + +DEFINE_PER_CPU(struct cpuidle_device, omap4_idle_dev); + +struct cpuidle_driver omap4_idle_driver = { + .name = "omap4_idle", + .owner = THIS_MODULE, +}; + +static inline void _fill_cstate(struct cpuidle_driver *drv, + int idx, const char *descr) +{ + struct cpuidle_state *state = &drv->states[idx]; + + state->exit_latency = cpuidle_params_table[idx].exit_latency; + state->target_residency = cpuidle_params_table[idx].target_residency; + state->flags = CPUIDLE_FLAG_TIME_VALID; + state->enter = omap4_enter_idle; + sprintf(state->name, "C%d", idx + 1); + strncpy(state->desc, descr, CPUIDLE_DESC_LEN); +} + +static inline struct omap4_idle_statedata *_fill_cstate_usage( + struct cpuidle_device *dev, + int idx) +{ + struct omap4_idle_statedata *cx = &omap4_idle_data[idx]; + struct cpuidle_state_usage *state_usage = &dev->states_usage[idx]; + + cx->valid = cpuidle_params_table[idx].valid; + cpuidle_set_statedata(state_usage, cx); + + return cx; +} + + + +/** + * omap4_idle_init - Init routine for OMAP4 idle + * + * Registers the OMAP4 specific cpuidle driver to the cpuidle + * framework with the valid set of states. + */ +int __init omap4_idle_init(void) +{ + struct omap4_idle_statedata *cx; + struct cpuidle_device *dev; + struct cpuidle_driver *drv = &omap4_idle_driver; + unsigned int cpu_id = 0; + + mpu_pd = pwrdm_lookup("mpu_pwrdm"); + cpu0_pd = pwrdm_lookup("cpu0_pwrdm"); + cpu1_pd = pwrdm_lookup("cpu1_pwrdm"); + if ((!mpu_pd) || (!cpu0_pd) || (!cpu1_pd)) + return -ENODEV; + + + drv->safe_state_index = -1; + dev = &per_cpu(omap4_idle_dev, cpu_id); + dev->cpu = cpu_id; + + /* C1 - CPU0 ON + CPU1 ON + MPU ON */ + _fill_cstate(drv, 0, "MPUSS ON"); + drv->safe_state_index = 0; + cx = _fill_cstate_usage(dev, 0); + cx->valid = 1; /* C1 is always valid */ + cx->cpu_state = PWRDM_POWER_ON; + cx->mpu_state = PWRDM_POWER_ON; + cx->mpu_logic_state = PWRDM_POWER_RET; + + /* C2 - CPU0 OFF + CPU1 OFF + MPU CSWR */ + _fill_cstate(drv, 1, "MPUSS CSWR"); + cx = _fill_cstate_usage(dev, 1); + cx->cpu_state = PWRDM_POWER_OFF; + cx->mpu_state = PWRDM_POWER_RET; + cx->mpu_logic_state = PWRDM_POWER_RET; + + /* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */ + _fill_cstate(drv, 2, "MPUSS OSWR"); + cx = _fill_cstate_usage(dev, 2); + cx->cpu_state = PWRDM_POWER_OFF; + cx->mpu_state = PWRDM_POWER_RET; + cx->mpu_logic_state = PWRDM_POWER_OFF; + + drv->state_count = OMAP4_NUM_STATES; + cpuidle_register_driver(&omap4_idle_driver); + + dev->state_count = OMAP4_NUM_STATES; + if (cpuidle_register_device(dev)) { + pr_err("%s: CPUidle register device failed\n", __func__); + return -EIO; + } + + return 0; +} +#else +int __init omap4_idle_init(void) +{ + return 0; +} +#endif /* CONFIG_CPU_IDLE */ diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c index c15cfada5f1..46dfd1ae8f7 100644 --- a/arch/arm/mach-omap2/devices.c +++ b/arch/arm/mach-omap2/devices.c @@ -28,6 +28,7 @@ #include <plat/board.h> #include <plat/mcbsp.h> #include <plat/mmc.h> +#include <plat/iommu.h> #include <plat/dma.h> #include <plat/omap_hwmod.h> #include <plat/omap_device.h> @@ -211,9 +212,15 @@ static struct platform_device omap3isp_device = { .resource = omap3isp_resources, }; +static struct omap_iommu_arch_data omap3_isp_iommu = { + .name = "isp", +}; + int omap3_init_camera(struct isp_platform_data *pdata) { omap3isp_device.dev.platform_data = pdata; + omap3isp_device.dev.archdata.iommu = &omap3_isp_iommu; + return platform_device_register(&omap3isp_device); } @@ -336,6 +343,27 @@ static void omap_init_mcpdm(void) static inline void omap_init_mcpdm(void) {} #endif +#if defined(CONFIG_SND_OMAP_SOC_DMIC) || \ + defined(CONFIG_SND_OMAP_SOC_DMIC_MODULE) + +static void omap_init_dmic(void) +{ + struct omap_hwmod *oh; + struct platform_device *pdev; + + oh = omap_hwmod_lookup("dmic"); + if (!oh) { + printk(KERN_ERR "Could not look up mcpdm hw_mod\n"); + return; + } + + pdev = omap_device_build("omap-dmic", -1, oh, NULL, 0, NULL, 0, 0); + WARN(IS_ERR(pdev), "Can't build omap_device for omap-dmic.\n"); +} +#else +static inline void omap_init_dmic(void) {} +#endif + #if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE) #include <plat/mcspi.h> @@ -681,6 +709,7 @@ static int __init omap2_init_devices(void) */ omap_init_audio(); omap_init_mcpdm(); + omap_init_dmic(); omap_init_camera(); omap_init_mbox(); omap_init_mcspi(); diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c index f4a1020559a..bd844af13af 100644 --- a/arch/arm/mach-omap2/hsmmc.c +++ b/arch/arm/mach-omap2/hsmmc.c @@ -171,6 +171,17 @@ static void omap4_hsmmc1_after_set_reg(struct device *dev, int slot, } } +static void hsmmc2_select_input_clk_src(struct omap_mmc_platform_data *mmc) +{ + u32 reg; + + if (mmc->slots[0].internal_clock) { + reg = omap_ctrl_readl(control_devconf1_offset); + reg |= OMAP2_MMCSDIO2ADPCLKISEL; + omap_ctrl_writel(reg, control_devconf1_offset); + } +} + static void hsmmc23_before_set_reg(struct device *dev, int slot, int power_on, int vdd) { @@ -179,16 +190,19 @@ static void hsmmc23_before_set_reg(struct device *dev, int slot, if (mmc->slots[0].remux) mmc->slots[0].remux(dev, slot, power_on); - if (power_on) { - /* Only MMC2 supports a CLKIN */ - if (mmc->slots[0].internal_clock) { - u32 reg; + if (power_on) + hsmmc2_select_input_clk_src(mmc); +} - reg = omap_ctrl_readl(control_devconf1_offset); - reg |= OMAP2_MMCSDIO2ADPCLKISEL; - omap_ctrl_writel(reg, control_devconf1_offset); - } - } +static int am35x_hsmmc2_set_power(struct device *dev, int slot, + int power_on, int vdd) +{ + struct omap_mmc_platform_data *mmc = dev->platform_data; + + if (power_on) + hsmmc2_select_input_clk_src(mmc); + + return 0; } static int nop_mmc_set_power(struct device *dev, int slot, int power_on, @@ -200,10 +214,12 @@ static int nop_mmc_set_power(struct device *dev, int slot, int power_on, static inline void omap_hsmmc_mux(struct omap_mmc_platform_data *mmc_controller, int controller_nr) { - if (gpio_is_valid(mmc_controller->slots[0].switch_pin)) + if (gpio_is_valid(mmc_controller->slots[0].switch_pin) && + (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES)) omap_mux_init_gpio(mmc_controller->slots[0].switch_pin, OMAP_PIN_INPUT_PULLUP); - if (gpio_is_valid(mmc_controller->slots[0].gpio_wp)) + if (gpio_is_valid(mmc_controller->slots[0].gpio_wp) && + (mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES)) omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp, OMAP_PIN_INPUT_PULLUP); if (cpu_is_omap34xx()) { @@ -296,6 +312,7 @@ static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c, mmc->slots[0].name = hc_name; mmc->nr_slots = 1; mmc->slots[0].caps = c->caps; + mmc->slots[0].pm_caps = c->pm_caps; mmc->slots[0].internal_clock = !c->ext_clock; mmc->dma_mask = 0xffffffff; if (cpu_is_omap44xx()) @@ -336,11 +353,17 @@ static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c, * * temporary HACK: ocr_mask instead of fixed supply */ - mmc->slots[0].ocr_mask = c->ocr_mask; - - if (cpu_is_omap3517() || cpu_is_omap3505()) - mmc->slots[0].set_power = nop_mmc_set_power; + if (cpu_is_omap3505() || cpu_is_omap3517()) + mmc->slots[0].ocr_mask = MMC_VDD_165_195 | + MMC_VDD_26_27 | + MMC_VDD_27_28 | + MMC_VDD_29_30 | + MMC_VDD_30_31 | + MMC_VDD_31_32; else + mmc->slots[0].ocr_mask = c->ocr_mask; + + if (!cpu_is_omap3517() && !cpu_is_omap3505()) mmc->slots[0].features |= HSMMC_HAS_PBIAS; if (cpu_is_omap44xx() && (omap_rev() > OMAP4430_REV_ES1_0)) @@ -363,6 +386,9 @@ static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c, } } + if (cpu_is_omap3517() || cpu_is_omap3505()) + mmc->slots[0].set_power = nop_mmc_set_power; + /* OMAP3630 HSMMC1 supports only 4-bit */ if (cpu_is_omap3630() && (c->caps & MMC_CAP_8_BIT_DATA)) { @@ -372,6 +398,9 @@ static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c, } break; case 2: + if (cpu_is_omap3517() || cpu_is_omap3505()) + mmc->slots[0].set_power = am35x_hsmmc2_set_power; + if (c->ext_clock) c->transceiver = 1; if (c->transceiver && (c->caps & MMC_CAP_8_BIT_DATA)) { diff --git a/arch/arm/mach-omap2/hsmmc.h b/arch/arm/mach-omap2/hsmmc.h index f757e78d4d4..c4409730c4b 100644 --- a/arch/arm/mach-omap2/hsmmc.h +++ b/arch/arm/mach-omap2/hsmmc.h @@ -12,6 +12,7 @@ struct omap2_hsmmc_info { u8 mmc; /* controller 1/2/3 */ u32 caps; /* 4/8 wires and any additional host * capabilities OR'd (ref. linux/mmc/host.h) */ + u32 pm_caps; /* PM capabilities */ bool transceiver; /* MMC-2 option */ bool ext_clock; /* use external pin for input clock */ bool cover_only; /* No card detect - just cover switch */ diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c index 27ad722df63..6c5826605ea 100644 --- a/arch/arm/mach-omap2/id.c +++ b/arch/arm/mach-omap2/id.c @@ -226,7 +226,7 @@ static void __init omap4_check_features(void) } } -static void __init ti816x_check_features(void) +static void __init ti81xx_check_features(void) { omap_features = OMAP3_HAS_NEON; } @@ -340,6 +340,29 @@ static void __init omap3_check_revision(const char **cpu_rev) break; } break; + case 0xb944: + omap_revision = AM335X_REV_ES1_0; + *cpu_rev = "1.0"; + case 0xb8f2: + switch (rev) { + case 0: + /* FALLTHROUGH */ + case 1: + omap_revision = TI8148_REV_ES1_0; + *cpu_rev = "1.0"; + break; + case 2: + omap_revision = TI8148_REV_ES2_0; + *cpu_rev = "2.0"; + break; + case 3: + /* FALLTHROUGH */ + default: + omap_revision = TI8148_REV_ES2_1; + *cpu_rev = "2.1"; + break; + } + break; default: /* Unknown default to latest silicon rev as default */ omap_revision = OMAP3630_REV_ES1_2; @@ -367,7 +390,7 @@ static void __init omap4_check_revision(void) * Few initial 4430 ES2.0 samples IDCODE is same as ES1.0 * Use ARM register to detect the correct ES version */ - if (!rev && (hawkeye != 0xb94e)) { + if (!rev && (hawkeye != 0xb94e) && (hawkeye != 0xb975)) { idcode = read_cpuid(CPUID_ID); rev = (idcode & 0xf) - 1; } @@ -389,8 +412,11 @@ static void __init omap4_check_revision(void) omap_revision = OMAP4430_REV_ES2_1; break; case 4: - default: omap_revision = OMAP4430_REV_ES2_2; + break; + case 6: + default: + omap_revision = OMAP4430_REV_ES2_3; } break; case 0xb94e: @@ -401,9 +427,17 @@ static void __init omap4_check_revision(void) break; } break; + case 0xb975: + switch (rev) { + case 0: + default: + omap_revision = OMAP4470_REV_ES1_0; + break; + } + break; default: /* Unknown default to latest silicon rev as default */ - omap_revision = OMAP4430_REV_ES2_2; + omap_revision = OMAP4430_REV_ES2_3; } pr_info("OMAP%04x ES%d.%d\n", omap_rev() >> 16, @@ -432,6 +466,10 @@ static void __init omap3_cpuinfo(const char *cpu_rev) cpu_name = (omap3_has_sgx()) ? "AM3517" : "AM3505"; } else if (cpu_is_ti816x()) { cpu_name = "TI816X"; + } else if (cpu_is_am335x()) { + cpu_name = "AM335X"; + } else if (cpu_is_ti814x()) { + cpu_name = "TI814X"; } else if (omap3_has_iva() && omap3_has_sgx()) { /* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */ cpu_name = "OMAP3430/3530"; @@ -472,11 +510,11 @@ void __init omap2_check_revision(void) } else if (cpu_is_omap34xx()) { omap3_check_revision(&cpu_rev); - /* TI816X doesn't have feature register */ - if (!cpu_is_ti816x()) + /* TI81XX doesn't have feature register */ + if (!cpu_is_ti81xx()) omap3_check_features(); else - ti816x_check_features(); + ti81xx_check_features(); omap3_cpuinfo(cpu_rev); return; diff --git a/arch/arm/mach-omap2/include/mach/barriers.h b/arch/arm/mach-omap2/include/mach/barriers.h new file mode 100644 index 00000000000..4fa72c7cc7c --- /dev/null +++ b/arch/arm/mach-omap2/include/mach/barriers.h @@ -0,0 +1,31 @@ +/* + * OMAP memory barrier header. + * + * Copyright (C) 2011 Texas Instruments, Inc. + * Santosh Shilimkar <santosh.shilimkar@ti.com> + * Richard Woodruff <r-woodruff2@ti.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __MACH_BARRIERS_H +#define __MACH_BARRIERS_H + +extern void omap_bus_sync(void); + +#define rmb() dsb() +#define wmb() do { dsb(); outer_sync(); omap_bus_sync(); } while (0) +#define mb() wmb() + +#endif /* __MACH_BARRIERS_H */ diff --git a/arch/arm/mach-omap2/include/mach/debug-macro.S b/arch/arm/mach-omap2/include/mach/debug-macro.S index 13f98e59cfe..cdfc2a1f0e7 100644 --- a/arch/arm/mach-omap2/include/mach/debug-macro.S +++ b/arch/arm/mach-omap2/include/mach/debug-macro.S @@ -66,11 +66,11 @@ omap_uart_lsr: .word 0 beq 34f @ configure OMAP3UART4 cmp \rp, #OMAP4UART4 @ only on 44xx beq 44f @ configure OMAP4UART4 - cmp \rp, #TI816XUART1 @ ti816x UART offsets different + cmp \rp, #TI81XXUART1 @ ti81Xx UART offsets different beq 81f @ configure UART1 - cmp \rp, #TI816XUART2 @ ti816x UART offsets different + cmp \rp, #TI81XXUART2 @ ti81Xx UART offsets different beq 82f @ configure UART2 - cmp \rp, #TI816XUART3 @ ti816x UART offsets different + cmp \rp, #TI81XXUART3 @ ti81Xx UART offsets different beq 83f @ configure UART3 cmp \rp, #ZOOM_UART @ only on zoom2/3 beq 95f @ configure ZOOM_UART @@ -94,11 +94,11 @@ omap_uart_lsr: .word 0 b 98f 44: mov \rp, #UART_OFFSET(OMAP4_UART4_BASE) b 98f -81: mov \rp, #UART_OFFSET(TI816X_UART1_BASE) +81: mov \rp, #UART_OFFSET(TI81XX_UART1_BASE) b 98f -82: mov \rp, #UART_OFFSET(TI816X_UART2_BASE) +82: mov \rp, #UART_OFFSET(TI81XX_UART2_BASE) b 98f -83: mov \rp, #UART_OFFSET(TI816X_UART3_BASE) +83: mov \rp, #UART_OFFSET(TI81XX_UART3_BASE) b 98f 95: ldr \rp, =ZOOM_UART_BASE diff --git a/arch/arm/mach-omap2/include/mach/omap-secure.h b/arch/arm/mach-omap2/include/mach/omap-secure.h new file mode 100644 index 00000000000..c90a43589ab --- /dev/null +++ b/arch/arm/mach-omap2/include/mach/omap-secure.h @@ -0,0 +1,57 @@ +/* + * omap-secure.h: OMAP Secure infrastructure header. + * + * Copyright (C) 2011 Texas Instruments, Inc. + * Santosh Shilimkar <santosh.shilimkar@ti.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef OMAP_ARCH_OMAP_SECURE_H +#define OMAP_ARCH_OMAP_SECURE_H + +/* Monitor error code */ +#define API_HAL_RET_VALUE_NS2S_CONVERSION_ERROR 0xFFFFFFFE +#define API_HAL_RET_VALUE_SERVICE_UNKNWON 0xFFFFFFFF + +/* HAL API error codes */ +#define API_HAL_RET_VALUE_OK 0x00 +#define API_HAL_RET_VALUE_FAIL 0x01 + +/* Secure HAL API flags */ +#define FLAG_START_CRITICAL 0x4 +#define FLAG_IRQFIQ_MASK 0x3 +#define FLAG_IRQ_ENABLE 0x2 +#define FLAG_FIQ_ENABLE 0x1 +#define NO_FLAG 0x0 + +/* Maximum Secure memory storage size */ +#define OMAP_SECURE_RAM_STORAGE (88 * SZ_1K) + +/* Secure low power HAL API index */ +#define OMAP4_HAL_SAVESECURERAM_INDEX 0x1a +#define OMAP4_HAL_SAVEHW_INDEX 0x1b +#define OMAP4_HAL_SAVEALL_INDEX 0x1c +#define OMAP4_HAL_SAVEGIC_INDEX 0x1d + +/* Secure Monitor mode APIs */ +#define OMAP4_MON_SCU_PWR_INDEX 0x108 +#define OMAP4_MON_L2X0_DBG_CTRL_INDEX 0x100 +#define OMAP4_MON_L2X0_CTRL_INDEX 0x102 +#define OMAP4_MON_L2X0_AUXCTRL_INDEX 0x109 +#define OMAP4_MON_L2X0_PREFETCH_INDEX 0x113 + +/* Secure PPA(Primary Protected Application) APIs */ +#define OMAP4_PPA_L2_POR_INDEX 0x23 +#define OMAP4_PPA_CPU_ACTRL_SMP_INDEX 0x25 + +#ifndef __ASSEMBLER__ + +extern u32 omap_secure_dispatcher(u32 idx, u32 flag, u32 nargs, + u32 arg1, u32 arg2, u32 arg3, u32 arg4); +extern u32 omap_smc2(u32 id, u32 falg, u32 pargs); +extern phys_addr_t omap_secure_ram_mempool_base(void); + +#endif /* __ASSEMBLER__ */ +#endif /* OMAP_ARCH_OMAP_SECURE_H */ diff --git a/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h b/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h new file mode 100644 index 00000000000..d79321b0f2a --- /dev/null +++ b/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h @@ -0,0 +1,39 @@ +/* + * OMAP WakeupGen header file + * + * Copyright (C) 2011 Texas Instruments, Inc. + * Santosh Shilimkar <santosh.shilimkar@ti.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef OMAP_ARCH_WAKEUPGEN_H +#define OMAP_ARCH_WAKEUPGEN_H + +#define OMAP_WKG_CONTROL_0 0x00 +#define OMAP_WKG_ENB_A_0 0x10 +#define OMAP_WKG_ENB_B_0 0x14 +#define OMAP_WKG_ENB_C_0 0x18 +#define OMAP_WKG_ENB_D_0 0x1c +#define OMAP_WKG_ENB_SECURE_A_0 0x20 +#define OMAP_WKG_ENB_SECURE_B_0 0x24 +#define OMAP_WKG_ENB_SECURE_C_0 0x28 +#define OMAP_WKG_ENB_SECURE_D_0 0x2c +#define OMAP_WKG_ENB_A_1 0x410 +#define OMAP_WKG_ENB_B_1 0x414 +#define OMAP_WKG_ENB_C_1 0x418 +#define OMAP_WKG_ENB_D_1 0x41c +#define OMAP_WKG_ENB_SECURE_A_1 0x420 +#define OMAP_WKG_ENB_SECURE_B_1 0x424 +#define OMAP_WKG_ENB_SECURE_C_1 0x428 +#define OMAP_WKG_ENB_SECURE_D_1 0x42c +#define OMAP_AUX_CORE_BOOT_0 0x800 +#define OMAP_AUX_CORE_BOOT_1 0x804 +#define OMAP_PTMSYNCREQ_MASK 0xc00 +#define OMAP_PTMSYNCREQ_EN 0xc04 +#define OMAP_TIMESTAMPCYCLELO 0xc08 +#define OMAP_TIMESTAMPCYCLEHI 0xc0c + +extern int __init omap_wakeupgen_init(void); +#endif diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index 3f565dd2ea8..3f174d51f67 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -176,14 +176,31 @@ static struct map_desc omap34xx_io_desc[] __initdata = { }; #endif -#ifdef CONFIG_SOC_OMAPTI816X -static struct map_desc omapti816x_io_desc[] __initdata = { +#ifdef CONFIG_SOC_OMAPTI81XX +static struct map_desc omapti81xx_io_desc[] __initdata = { + { + .virtual = L4_34XX_VIRT, + .pfn = __phys_to_pfn(L4_34XX_PHYS), + .length = L4_34XX_SIZE, + .type = MT_DEVICE + } +}; +#endif + +#ifdef CONFIG_SOC_OMAPAM33XX +static struct map_desc omapam33xx_io_desc[] __initdata = { { .virtual = L4_34XX_VIRT, .pfn = __phys_to_pfn(L4_34XX_PHYS), .length = L4_34XX_SIZE, .type = MT_DEVICE }, + { + .virtual = L4_WK_AM33XX_VIRT, + .pfn = __phys_to_pfn(L4_WK_AM33XX_PHYS), + .length = L4_WK_AM33XX_SIZE, + .type = MT_DEVICE + } }; #endif @@ -237,6 +254,15 @@ static struct map_desc omap44xx_io_desc[] __initdata = { .length = L4_EMU_44XX_SIZE, .type = MT_DEVICE, }, +#ifdef CONFIG_OMAP4_ERRATA_I688 + { + .virtual = OMAP4_SRAM_VA, + .pfn = __phys_to_pfn(OMAP4_SRAM_PA), + .length = PAGE_SIZE, + .type = MT_MEMORY_SO, + }, +#endif + }; #endif @@ -263,10 +289,17 @@ void __init omap34xx_map_common_io(void) } #endif -#ifdef CONFIG_SOC_OMAPTI816X -void __init omapti816x_map_common_io(void) +#ifdef CONFIG_SOC_OMAPTI81XX +void __init omapti81xx_map_common_io(void) +{ + iotable_init(omapti81xx_io_desc, ARRAY_SIZE(omapti81xx_io_desc)); +} +#endif + +#ifdef CONFIG_SOC_OMAPAM33XX +void __init omapam33xx_map_common_io(void) { - iotable_init(omapti816x_io_desc, ARRAY_SIZE(omapti816x_io_desc)); + iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc)); } #endif @@ -418,9 +451,9 @@ void __init am35xx_init_early(void) omap3_init_early(); } -void __init ti816x_init_early(void) +void __init ti81xx_init_early(void) { - omap2_set_globals_ti816x(); + omap2_set_globals_ti81xx(); omap_common_init_early(); omap3xxx_voltagedomains_init(); omap3xxx_powerdomains_init(); diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c index 42b1d659191..1fef061f792 100644 --- a/arch/arm/mach-omap2/irq.c +++ b/arch/arm/mach-omap2/irq.c @@ -193,7 +193,7 @@ void __init omap3_init_irq(void) omap_init_irq(OMAP34XX_IC_BASE, 96); } -void __init ti816x_init_irq(void) +void __init ti81xx_init_irq(void) { omap_init_irq(OMAP34XX_IC_BASE, 128); } diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c index 28fcb27005d..fb4bcf81a18 100644 --- a/arch/arm/mach-omap2/mcbsp.c +++ b/arch/arm/mach-omap2/mcbsp.c @@ -156,6 +156,9 @@ static int omap_init_mcbsp(struct omap_hwmod *oh, void *unused) else /* The FIFO has 128 locations */ pdata->buffer_size = 0x80; + } else if (oh->class->rev == MCBSP_CONFIG_TYPE4) { + /* The FIFO has 128 locations for all instances */ + pdata->buffer_size = 0x80; } if (oh->class->rev >= MCBSP_CONFIG_TYPE3) diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c index 655e9480eb9..e1cc75d1a57 100644 --- a/arch/arm/mach-omap2/mux.c +++ b/arch/arm/mach-omap2/mux.c @@ -32,6 +32,8 @@ #include <linux/debugfs.h> #include <linux/seq_file.h> #include <linux/uaccess.h> +#include <linux/irq.h> +#include <linux/interrupt.h> #include <asm/system.h> @@ -39,6 +41,7 @@ #include "control.h" #include "mux.h" +#include "prm.h" #define OMAP_MUX_BASE_OFFSET 0x30 /* Offset from CTRL_BASE */ #define OMAP_MUX_BASE_SZ 0x5ca @@ -306,7 +309,8 @@ omap_hwmod_mux_init(struct omap_device_pad *bpads, int nr_pads) pad->idle = bpad->idle; pad->off = bpad->off; - if (pad->flags & OMAP_DEVICE_PAD_REMUX) + if (pad->flags & + (OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP)) nr_pads_dynamic++; pr_debug("%s: Initialized %s\n", __func__, pad->name); @@ -331,7 +335,8 @@ omap_hwmod_mux_init(struct omap_device_pad *bpads, int nr_pads) for (i = 0; i < hmux->nr_pads; i++) { struct omap_device_pad *pad = &hmux->pads[i]; - if (pad->flags & OMAP_DEVICE_PAD_REMUX) { + if (pad->flags & + (OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP)) { pr_debug("%s: pad %s tagged dynamic\n", __func__, pad->name); hmux->pads_dynamic[nr_pads_dynamic] = pad; @@ -351,6 +356,78 @@ err1: return NULL; } +/** + * omap_hwmod_mux_scan_wakeups - omap hwmod scan wakeup pads + * @hmux: Pads for a hwmod + * @mpu_irqs: MPU irq array for a hwmod + * + * Scans the wakeup status of pads for a single hwmod. If an irq + * array is defined for this mux, the parser will call the registered + * ISRs for corresponding pads, otherwise the parser will stop at the + * first wakeup active pad and return. Returns true if there is a + * pending and non-served wakeup event for the mux, otherwise false. + */ +static bool omap_hwmod_mux_scan_wakeups(struct omap_hwmod_mux_info *hmux, + struct omap_hwmod_irq_info *mpu_irqs) +{ + int i, irq; + unsigned int val; + u32 handled_irqs = 0; + + for (i = 0; i < hmux->nr_pads_dynamic; i++) { + struct omap_device_pad *pad = hmux->pads_dynamic[i]; + + if (!(pad->flags & OMAP_DEVICE_PAD_WAKEUP) || + !(pad->idle & OMAP_WAKEUP_EN)) + continue; + + val = omap_mux_read(pad->partition, pad->mux->reg_offset); + if (!(val & OMAP_WAKEUP_EVENT)) + continue; + + if (!hmux->irqs) + return true; + + irq = hmux->irqs[i]; + /* make sure we only handle each irq once */ + if (handled_irqs & 1 << irq) + continue; + + handled_irqs |= 1 << irq; + + generic_handle_irq(mpu_irqs[irq].irq); + } + + return false; +} + +/** + * _omap_hwmod_mux_handle_irq - Process wakeup events for a single hwmod + * + * Checks a single hwmod for every wakeup capable pad to see if there is an + * active wakeup event. If this is the case, call the corresponding ISR. + */ +static int _omap_hwmod_mux_handle_irq(struct omap_hwmod *oh, void *data) +{ + if (!oh->mux || !oh->mux->enabled) + return 0; + if (omap_hwmod_mux_scan_wakeups(oh->mux, oh->mpu_irqs)) + generic_handle_irq(oh->mpu_irqs[0].irq); + return 0; +} + +/** + * omap_hwmod_mux_handle_irq - Process pad wakeup irqs. + * + * Calls a function for each registered omap_hwmod to check + * pad wakeup statuses. + */ +static irqreturn_t omap_hwmod_mux_handle_irq(int irq, void *unused) +{ + omap_hwmod_for_each(_omap_hwmod_mux_handle_irq, NULL); + return IRQ_HANDLED; +} + /* Assumes the calling function takes care of locking */ void omap_hwmod_mux(struct omap_hwmod_mux_info *hmux, u8 state) { @@ -715,6 +792,7 @@ static void __init omap_mux_free_names(struct omap_mux *m) static int __init omap_mux_late_init(void) { struct omap_mux_partition *partition; + int ret; list_for_each_entry(partition, &mux_partitions, node) { struct omap_mux_entry *e, *tmp; @@ -735,6 +813,13 @@ static int __init omap_mux_late_init(void) } } + ret = request_irq(omap_prcm_event_to_irq("io"), + omap_hwmod_mux_handle_irq, IRQF_SHARED | IRQF_NO_SUSPEND, + "hwmod_io", omap_mux_late_init); + + if (ret) + pr_warning("mux: Failed to setup hwmod io irq %d\n", ret); + omap_mux_dbg_init(); return 0; diff --git a/arch/arm/mach-omap2/omap-headsmp.S b/arch/arm/mach-omap2/omap-headsmp.S index 4ee6aeca885..b13ef7ef5ef 100644 --- a/arch/arm/mach-omap2/omap-headsmp.S +++ b/arch/arm/mach-omap2/omap-headsmp.S @@ -18,11 +18,6 @@ #include <linux/linkage.h> #include <linux/init.h> -/* Physical address needed since MMU not enabled yet on secondary core */ -#define OMAP4_AUX_CORE_BOOT1_PA 0x48281804 - - __INIT - /* * OMAP4 specific entry point for secondary CPU to jump from ROM * code. This routine also provides a holding flag into which diff --git a/arch/arm/mach-omap2/omap-hotplug.c b/arch/arm/mach-omap2/omap-hotplug.c index e5a1c3f40a8..adbe4d8c7ca 100644 --- a/arch/arm/mach-omap2/omap-hotplug.c +++ b/arch/arm/mach-omap2/omap-hotplug.c @@ -22,6 +22,8 @@ #include "common.h" +#include "powerdomain.h" + int platform_cpu_kill(unsigned int cpu) { return 1; @@ -33,6 +35,8 @@ int platform_cpu_kill(unsigned int cpu) */ void platform_cpu_die(unsigned int cpu) { + unsigned int this_cpu; + flush_cache_all(); dsb(); @@ -40,15 +44,15 @@ void platform_cpu_die(unsigned int cpu) * we're ready for shutdown now, so do it */ if (omap_modify_auxcoreboot0(0x0, 0x200) != 0x0) - printk(KERN_CRIT "Secure clear status failed\n"); + pr_err("Secure clear status failed\n"); for (;;) { /* - * Execute WFI + * Enter into low power state */ - do_wfi(); - - if (omap_read_auxcoreboot0() == cpu) { + omap4_hotplug_cpu(cpu, PWRDM_POWER_OFF); + this_cpu = smp_processor_id(); + if (omap_read_auxcoreboot0() == this_cpu) { /* * OK, proper wakeup, we're done */ diff --git a/arch/arm/mach-omap2/omap-mpuss-lowpower.c b/arch/arm/mach-omap2/omap-mpuss-lowpower.c new file mode 100644 index 00000000000..1d5d0105655 --- /dev/null +++ b/arch/arm/mach-omap2/omap-mpuss-lowpower.c @@ -0,0 +1,398 @@ +/* + * OMAP MPUSS low power code + * + * Copyright (C) 2011 Texas Instruments, Inc. + * Santosh Shilimkar <santosh.shilimkar@ti.com> + * + * OMAP4430 MPUSS mainly consists of dual Cortex-A9 with per-CPU + * Local timer and Watchdog, GIC, SCU, PL310 L2 cache controller, + * CPU0 and CPU1 LPRM modules. + * CPU0, CPU1 and MPUSS each have there own power domain and + * hence multiple low power combinations of MPUSS are possible. + * + * The CPU0 and CPU1 can't support Closed switch Retention (CSWR) + * because the mode is not supported by hw constraints of dormant + * mode. While waking up from the dormant mode, a reset signal + * to the Cortex-A9 processor must be asserted by the external + * power controller. + * + * With architectural inputs and hardware recommendations, only + * below modes are supported from power gain vs latency point of view. + * + * CPU0 CPU1 MPUSS + * ---------------------------------------------- + * ON ON ON + * ON(Inactive) OFF ON(Inactive) + * OFF OFF CSWR + * OFF OFF OSWR + * OFF OFF OFF(Device OFF *TBD) + * ---------------------------------------------- + * + * Note: CPU0 is the master core and it is the last CPU to go down + * and first to wake-up when MPUSS low power states are excercised + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/io.h> +#include <linux/errno.h> +#include <linux/linkage.h> +#include <linux/smp.h> + +#include <asm/cacheflush.h> +#include <asm/tlbflush.h> +#include <asm/smp_scu.h> +#include <asm/system.h> +#include <asm/pgalloc.h> +#include <asm/suspend.h> +#include <asm/hardware/cache-l2x0.h> + +#include <plat/omap44xx.h> + +#include "common.h" +#include "omap4-sar-layout.h" +#include "pm.h" +#include "prcm_mpu44xx.h" +#include "prminst44xx.h" +#include "prcm44xx.h" +#include "prm44xx.h" +#include "prm-regbits-44xx.h" + +#ifdef CONFIG_SMP + +struct omap4_cpu_pm_info { + struct powerdomain *pwrdm; + void __iomem *scu_sar_addr; + void __iomem *wkup_sar_addr; + void __iomem *l2x0_sar_addr; +}; + +static DEFINE_PER_CPU(struct omap4_cpu_pm_info, omap4_pm_info); +static struct powerdomain *mpuss_pd; +static void __iomem *sar_base; + +/* + * Program the wakeup routine address for the CPU0 and CPU1 + * used for OFF or DORMANT wakeup. + */ +static inline void set_cpu_wakeup_addr(unsigned int cpu_id, u32 addr) +{ + struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id); + + __raw_writel(addr, pm_info->wkup_sar_addr); +} + +/* + * Set the CPUx powerdomain's previous power state + */ +static inline void set_cpu_next_pwrst(unsigned int cpu_id, + unsigned int power_state) +{ + struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id); + + pwrdm_set_next_pwrst(pm_info->pwrdm, power_state); +} + +/* + * Read CPU's previous power state + */ +static inline unsigned int read_cpu_prev_pwrst(unsigned int cpu_id) +{ + struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id); + + return pwrdm_read_prev_pwrst(pm_info->pwrdm); +} + +/* + * Clear the CPUx powerdomain's previous power state + */ +static inline void clear_cpu_prev_pwrst(unsigned int cpu_id) +{ + struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id); + + pwrdm_clear_all_prev_pwrst(pm_info->pwrdm); +} + +/* + * Store the SCU power status value to scratchpad memory + */ +static void scu_pwrst_prepare(unsigned int cpu_id, unsigned int cpu_state) +{ + struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id); + u32 scu_pwr_st; + + switch (cpu_state) { + case PWRDM_POWER_RET: + scu_pwr_st = SCU_PM_DORMANT; + break; + case PWRDM_POWER_OFF: + scu_pwr_st = SCU_PM_POWEROFF; + break; + case PWRDM_POWER_ON: + case PWRDM_POWER_INACTIVE: + default: + scu_pwr_st = SCU_PM_NORMAL; + break; + } + + __raw_writel(scu_pwr_st, pm_info->scu_sar_addr); +} + +/* Helper functions for MPUSS OSWR */ +static inline void mpuss_clear_prev_logic_pwrst(void) +{ + u32 reg; + + reg = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION, + OMAP4430_PRM_MPU_INST, OMAP4_RM_MPU_MPU_CONTEXT_OFFSET); + omap4_prminst_write_inst_reg(reg, OMAP4430_PRM_PARTITION, + OMAP4430_PRM_MPU_INST, OMAP4_RM_MPU_MPU_CONTEXT_OFFSET); +} + +static inline void cpu_clear_prev_logic_pwrst(unsigned int cpu_id) +{ + u32 reg; + + if (cpu_id) { + reg = omap4_prcm_mpu_read_inst_reg(OMAP4430_PRCM_MPU_CPU1_INST, + OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET); + omap4_prcm_mpu_write_inst_reg(reg, OMAP4430_PRCM_MPU_CPU1_INST, + OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET); + } else { + reg = omap4_prcm_mpu_read_inst_reg(OMAP4430_PRCM_MPU_CPU0_INST, + OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET); + omap4_prcm_mpu_write_inst_reg(reg, OMAP4430_PRCM_MPU_CPU0_INST, + OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET); + } +} + +/** + * omap4_mpuss_read_prev_context_state: + * Function returns the MPUSS previous context state + */ +u32 omap4_mpuss_read_prev_context_state(void) +{ + u32 reg; + + reg = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION, + OMAP4430_PRM_MPU_INST, OMAP4_RM_MPU_MPU_CONTEXT_OFFSET); + reg &= OMAP4430_LOSTCONTEXT_DFF_MASK; + return reg; +} + +/* + * Store the CPU cluster state for L2X0 low power operations. + */ +static void l2x0_pwrst_prepare(unsigned int cpu_id, unsigned int save_state) +{ + struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id); + + __raw_writel(save_state, pm_info->l2x0_sar_addr); +} + +/* + * Save the L2X0 AUXCTRL and POR value to SAR memory. Its used to + * in every restore MPUSS OFF path. + */ +#ifdef CONFIG_CACHE_L2X0 +static void save_l2x0_context(void) +{ + u32 val; + void __iomem *l2x0_base = omap4_get_l2cache_base(); + + val = __raw_readl(l2x0_base + L2X0_AUX_CTRL); + __raw_writel(val, sar_base + L2X0_AUXCTRL_OFFSET); + val = __raw_readl(l2x0_base + L2X0_PREFETCH_CTRL); + __raw_writel(val, sar_base + L2X0_PREFETCH_CTRL_OFFSET); +} +#else +static void save_l2x0_context(void) +{} +#endif + +/** + * omap4_enter_lowpower: OMAP4 MPUSS Low Power Entry Function + * The purpose of this function is to manage low power programming + * of OMAP4 MPUSS subsystem + * @cpu : CPU ID + * @power_state: Low power state. + * + * MPUSS states for the context save: + * save_state = + * 0 - Nothing lost and no need to save: MPUSS INACTIVE + * 1 - CPUx L1 and logic lost: MPUSS CSWR + * 2 - CPUx L1 and logic lost + GIC lost: MPUSS OSWR + * 3 - CPUx L1 and logic lost + GIC + L2 lost: DEVICE OFF + */ +int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state) +{ + unsigned int save_state = 0; + unsigned int wakeup_cpu; + + if (omap_rev() == OMAP4430_REV_ES1_0) + return -ENXIO; + + switch (power_state) { + case PWRDM_POWER_ON: + case PWRDM_POWER_INACTIVE: + save_state = 0; + break; + case PWRDM_POWER_OFF: + save_state = 1; + break; + case PWRDM_POWER_RET: + default: + /* + * CPUx CSWR is invalid hardware state. Also CPUx OSWR + * doesn't make much scense, since logic is lost and $L1 + * needs to be cleaned because of coherency. This makes + * CPUx OSWR equivalent to CPUX OFF and hence not supported + */ + WARN_ON(1); + return -ENXIO; + } + + pwrdm_pre_transition(); + + /* + * Check MPUSS next state and save interrupt controller if needed. + * In MPUSS OSWR or device OFF, interrupt controller contest is lost. + */ + mpuss_clear_prev_logic_pwrst(); + pwrdm_clear_all_prev_pwrst(mpuss_pd); + if ((pwrdm_read_next_pwrst(mpuss_pd) == PWRDM_POWER_RET) && + (pwrdm_read_logic_retst(mpuss_pd) == PWRDM_POWER_OFF)) + save_state = 2; + + clear_cpu_prev_pwrst(cpu); + cpu_clear_prev_logic_pwrst(cpu); + set_cpu_next_pwrst(cpu, power_state); + set_cpu_wakeup_addr(cpu, virt_to_phys(omap4_cpu_resume)); + scu_pwrst_prepare(cpu, power_state); + l2x0_pwrst_prepare(cpu, save_state); + + /* + * Call low level function with targeted low power state. + */ + cpu_suspend(save_state, omap4_finish_suspend); + + /* + * Restore the CPUx power state to ON otherwise CPUx + * power domain can transitions to programmed low power + * state while doing WFI outside the low powe code. On + * secure devices, CPUx does WFI which can result in + * domain transition + */ + wakeup_cpu = smp_processor_id(); + set_cpu_next_pwrst(wakeup_cpu, PWRDM_POWER_ON); + + pwrdm_post_transition(); + + return 0; +} + +/** + * omap4_hotplug_cpu: OMAP4 CPU hotplug entry + * @cpu : CPU ID + * @power_state: CPU low power state. + */ +int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state) +{ + unsigned int cpu_state = 0; + + if (omap_rev() == OMAP4430_REV_ES1_0) + return -ENXIO; + + if (power_state == PWRDM_POWER_OFF) + cpu_state = 1; + + clear_cpu_prev_pwrst(cpu); + set_cpu_next_pwrst(cpu, power_state); + set_cpu_wakeup_addr(cpu, virt_to_phys(omap_secondary_startup)); + scu_pwrst_prepare(cpu, power_state); + + /* + * CPU never retuns back if targetted power state is OFF mode. + * CPU ONLINE follows normal CPU ONLINE ptah via + * omap_secondary_startup(). + */ + omap4_finish_suspend(cpu_state); + + set_cpu_next_pwrst(cpu, PWRDM_POWER_ON); + return 0; +} + + +/* + * Initialise OMAP4 MPUSS + */ +int __init omap4_mpuss_init(void) +{ + struct omap4_cpu_pm_info *pm_info; + + if (omap_rev() == OMAP4430_REV_ES1_0) { + WARN(1, "Power Management not supported on OMAP4430 ES1.0\n"); + return -ENODEV; + } + + sar_base = omap4_get_sar_ram_base(); + + /* Initilaise per CPU PM information */ + pm_info = &per_cpu(omap4_pm_info, 0x0); + pm_info->scu_sar_addr = sar_base + SCU_OFFSET0; + pm_info->wkup_sar_addr = sar_base + CPU0_WAKEUP_NS_PA_ADDR_OFFSET; + pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET0; + pm_info->pwrdm = pwrdm_lookup("cpu0_pwrdm"); + if (!pm_info->pwrdm) { + pr_err("Lookup failed for CPU0 pwrdm\n"); + return -ENODEV; + } + + /* Clear CPU previous power domain state */ + pwrdm_clear_all_prev_pwrst(pm_info->pwrdm); + cpu_clear_prev_logic_pwrst(0); + + /* Initialise CPU0 power domain state to ON */ + pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON); + + pm_info = &per_cpu(omap4_pm_info, 0x1); + pm_info->scu_sar_addr = sar_base + SCU_OFFSET1; + pm_info->wkup_sar_addr = sar_base + CPU1_WAKEUP_NS_PA_ADDR_OFFSET; + pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET1; + pm_info->pwrdm = pwrdm_lookup("cpu1_pwrdm"); + if (!pm_info->pwrdm) { + pr_err("Lookup failed for CPU1 pwrdm\n"); + return -ENODEV; + } + + /* Clear CPU previous power domain state */ + pwrdm_clear_all_prev_pwrst(pm_info->pwrdm); + cpu_clear_prev_logic_pwrst(1); + + /* Initialise CPU1 power domain state to ON */ + pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON); + + mpuss_pd = pwrdm_lookup("mpu_pwrdm"); + if (!mpuss_pd) { + pr_err("Failed to lookup MPUSS power domain\n"); + return -ENODEV; + } + pwrdm_clear_all_prev_pwrst(mpuss_pd); + mpuss_clear_prev_logic_pwrst(); + + /* Save device type on scratchpad for low level code to use */ + if (omap_type() != OMAP2_DEVICE_TYPE_GP) + __raw_writel(1, sar_base + OMAP_TYPE_OFFSET); + else + __raw_writel(0, sar_base + OMAP_TYPE_OFFSET); + + save_l2x0_context(); + + return 0; +} + +#endif diff --git a/arch/arm/mach-omap2/omap-secure.c b/arch/arm/mach-omap2/omap-secure.c new file mode 100644 index 00000000000..69f3c72d959 --- /dev/null +++ b/arch/arm/mach-omap2/omap-secure.c @@ -0,0 +1,81 @@ +/* + * OMAP Secure API infrastructure. + * + * Copyright (C) 2011 Texas Instruments, Inc. + * Santosh Shilimkar <santosh.shilimkar@ti.com> + * + * + * This program is free software,you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/memblock.h> + +#include <asm/cacheflush.h> + +#include <mach/omap-secure.h> + +static phys_addr_t omap_secure_memblock_base; + +/** + * omap_sec_dispatcher: Routine to dispatch low power secure + * service routines + * @idx: The HAL API index + * @flag: The flag indicating criticality of operation + * @nargs: Number of valid arguments out of four. + * @arg1, arg2, arg3 args4: Parameters passed to secure API + * + * Return the non-zero error value on failure. + */ +u32 omap_secure_dispatcher(u32 idx, u32 flag, u32 nargs, u32 arg1, u32 arg2, + u32 arg3, u32 arg4) +{ + u32 ret; + u32 param[5]; + + param[0] = nargs; + param[1] = arg1; + param[2] = arg2; + param[3] = arg3; + param[4] = arg4; + + /* + * Secure API needs physical address + * pointer for the parameters + */ + flush_cache_all(); + outer_clean_range(__pa(param), __pa(param + 5)); + ret = omap_smc2(idx, flag, __pa(param)); + + return ret; +} + +/* Allocate the memory to save secure ram */ +int __init omap_secure_ram_reserve_memblock(void) +{ + phys_addr_t paddr; + u32 size = OMAP_SECURE_RAM_STORAGE; + + size = ALIGN(size, SZ_1M); + paddr = memblock_alloc(size, SZ_1M); + if (!paddr) { + pr_err("%s: failed to reserve %x bytes\n", + __func__, size); + return -ENOMEM; + } + memblock_free(paddr, size); + memblock_remove(paddr, size); + + omap_secure_memblock_base = paddr; + + return 0; +} + +phys_addr_t omap_secure_ram_mempool_base(void) +{ + return omap_secure_memblock_base; +} diff --git a/arch/arm/mach-omap2/omap44xx-smc.S b/arch/arm/mach-omap2/omap-smc.S index e69d37d9520..f6441c13cd8 100644 --- a/arch/arm/mach-omap2/omap44xx-smc.S +++ b/arch/arm/mach-omap2/omap-smc.S @@ -31,6 +31,29 @@ ENTRY(omap_smc1) ldmfd sp!, {r2-r12, pc} ENDPROC(omap_smc1) +/** + * u32 omap_smc2(u32 id, u32 falg, u32 pargs) + * Low level common routine for secure HAL and PPA APIs. + * @id: Application ID of HAL APIs + * @flag: Flag to indicate the criticality of operation + * @pargs: Physical address of parameter list starting + * with number of parametrs + */ +ENTRY(omap_smc2) + stmfd sp!, {r4-r12, lr} + mov r3, r2 + mov r2, r1 + mov r1, #0x0 @ Process ID + mov r6, #0xff + mov r12, #0x00 @ Secure Service ID + mov r7, #0 + mcr p15, 0, r7, c7, c5, 6 + dsb + dmb + smc #0 + ldmfd sp!, {r4-r12, pc} +ENDPROC(omap_smc2) + ENTRY(omap_modify_auxcoreboot0) stmfd sp!, {r1-r12, lr} ldr r12, =0x104 diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c index e99bc6cd471..c1bf3ef0ba0 100644 --- a/arch/arm/mach-omap2/omap-smp.c +++ b/arch/arm/mach-omap2/omap-smp.c @@ -24,17 +24,37 @@ #include <asm/hardware/gic.h> #include <asm/smp_scu.h> #include <mach/hardware.h> +#include <mach/omap-secure.h> #include "common.h" +#include "clockdomain.h" + /* SCU base address */ static void __iomem *scu_base; static DEFINE_SPINLOCK(boot_lock); +void __iomem *omap4_get_scu_base(void) +{ + return scu_base; +} + void __cpuinit platform_secondary_init(unsigned int cpu) { /* + * Configure ACTRL and enable NS SMP bit access on CPU1 on HS device. + * OMAP44XX EMU/HS devices - CPU0 SMP bit access is enabled in PPA + * init and for CPU1, a secure PPA API provided. CPU0 must be ON + * while executing NS_SMP API on CPU1 and PPA version must be 1.4.0+. + * OMAP443X GP devices- SMP bit isn't accessible. + * OMAP446X GP devices - SMP bit access is enabled on both CPUs. + */ + if (cpu_is_omap443x() && (omap_type() != OMAP2_DEVICE_TYPE_GP)) + omap_secure_dispatcher(OMAP4_PPA_CPU_ACTRL_SMP_INDEX, + 4, 0, 0, 0, 0, 0); + + /* * If any interrupts are already enabled for the primary * core (e.g. timer irq), then they will not have been enabled * for us: do so @@ -50,6 +70,8 @@ void __cpuinit platform_secondary_init(unsigned int cpu) int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) { + static struct clockdomain *cpu1_clkdm; + static bool booted; /* * Set synchronisation state between this boot processor * and the secondary one @@ -65,6 +87,29 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) omap_modify_auxcoreboot0(0x200, 0xfffffdff); flush_cache_all(); smp_wmb(); + + if (!cpu1_clkdm) + cpu1_clkdm = clkdm_lookup("mpu1_clkdm"); + + /* + * The SGI(Software Generated Interrupts) are not wakeup capable + * from low power states. This is known limitation on OMAP4 and + * needs to be worked around by using software forced clockdomain + * wake-up. To wakeup CPU1, CPU0 forces the CPU1 clockdomain to + * software force wakeup. The clockdomain is then put back to + * hardware supervised mode. + * More details can be found in OMAP4430 TRM - Version J + * Section : + * 4.3.4.2 Power States of CPU0 and CPU1 + */ + if (booted) { + clkdm_wakeup(cpu1_clkdm); + clkdm_allow_idle(cpu1_clkdm); + } else { + dsb_sev(); + booted = true; + } + gic_raise_softirq(cpumask_of(cpu), 1); /* diff --git a/arch/arm/mach-omap2/omap-wakeupgen.c b/arch/arm/mach-omap2/omap-wakeupgen.c new file mode 100644 index 00000000000..d3d8971d7f3 --- /dev/null +++ b/arch/arm/mach-omap2/omap-wakeupgen.c @@ -0,0 +1,389 @@ +/* + * OMAP WakeupGen Source file + * + * OMAP WakeupGen is the interrupt controller extension used along + * with ARM GIC to wake the CPU out from low power states on + * external interrupts. It is responsible for generating wakeup + * event from the incoming interrupts and enable bits. It is + * implemented in MPU always ON power domain. During normal operation, + * WakeupGen delivers external interrupts directly to the GIC. + * + * Copyright (C) 2011 Texas Instruments, Inc. + * Santosh Shilimkar <santosh.shilimkar@ti.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/irq.h> +#include <linux/platform_device.h> +#include <linux/cpu.h> +#include <linux/notifier.h> +#include <linux/cpu_pm.h> + +#include <asm/hardware/gic.h> + +#include <mach/omap-wakeupgen.h> +#include <mach/omap-secure.h> + +#include "omap4-sar-layout.h" +#include "common.h" + +#define NR_REG_BANKS 4 +#define MAX_IRQS 128 +#define WKG_MASK_ALL 0x00000000 +#define WKG_UNMASK_ALL 0xffffffff +#define CPU_ENA_OFFSET 0x400 +#define CPU0_ID 0x0 +#define CPU1_ID 0x1 + +static void __iomem *wakeupgen_base; +static void __iomem *sar_base; +static DEFINE_PER_CPU(u32 [NR_REG_BANKS], irqmasks); +static DEFINE_SPINLOCK(wakeupgen_lock); +static unsigned int irq_target_cpu[NR_IRQS]; + +/* + * Static helper functions. + */ +static inline u32 wakeupgen_readl(u8 idx, u32 cpu) +{ + return __raw_readl(wakeupgen_base + OMAP_WKG_ENB_A_0 + + (cpu * CPU_ENA_OFFSET) + (idx * 4)); +} + +static inline void wakeupgen_writel(u32 val, u8 idx, u32 cpu) +{ + __raw_writel(val, wakeupgen_base + OMAP_WKG_ENB_A_0 + + (cpu * CPU_ENA_OFFSET) + (idx * 4)); +} + +static inline void sar_writel(u32 val, u32 offset, u8 idx) +{ + __raw_writel(val, sar_base + offset + (idx * 4)); +} + +static void _wakeupgen_set_all(unsigned int cpu, unsigned int reg) +{ + u8 i; + + for (i = 0; i < NR_REG_BANKS; i++) + wakeupgen_writel(reg, i, cpu); +} + +static inline int _wakeupgen_get_irq_info(u32 irq, u32 *bit_posn, u8 *reg_index) +{ + unsigned int spi_irq; + + /* + * PPIs and SGIs are not supported. + */ + if (irq < OMAP44XX_IRQ_GIC_START) + return -EINVAL; + + /* + * Subtract the GIC offset. + */ + spi_irq = irq - OMAP44XX_IRQ_GIC_START; + if (spi_irq > MAX_IRQS) { + pr_err("omap wakeupGen: Invalid IRQ%d\n", irq); + return -EINVAL; + } + + /* + * Each WakeupGen register controls 32 interrupt. + * i.e. 1 bit per SPI IRQ + */ + *reg_index = spi_irq >> 5; + *bit_posn = spi_irq %= 32; + + return 0; +} + +static void _wakeupgen_clear(unsigned int irq, unsigned int cpu) +{ + u32 val, bit_number; + u8 i; + + if (_wakeupgen_get_irq_info(irq, &bit_number, &i)) + return; + + val = wakeupgen_readl(i, cpu); + val &= ~BIT(bit_number); + wakeupgen_writel(val, i, cpu); +} + +static void _wakeupgen_set(unsigned int irq, unsigned int cpu) +{ + u32 val, bit_number; + u8 i; + + if (_wakeupgen_get_irq_info(irq, &bit_number, &i)) + return; + + val = wakeupgen_readl(i, cpu); + val |= BIT(bit_number); + wakeupgen_writel(val, i, cpu); +} + +static void _wakeupgen_save_masks(unsigned int cpu) +{ + u8 i; + + for (i = 0; i < NR_REG_BANKS; i++) + per_cpu(irqmasks, cpu)[i] = wakeupgen_readl(i, cpu); +} + +static void _wakeupgen_restore_masks(unsigned int cpu) +{ + u8 i; + + for (i = 0; i < NR_REG_BANKS; i++) + wakeupgen_writel(per_cpu(irqmasks, cpu)[i], i, cpu); +} + +/* + * Architecture specific Mask extension + */ +static void wakeupgen_mask(struct irq_data *d) +{ + unsigned long flags; + + spin_lock_irqsave(&wakeupgen_lock, flags); + _wakeupgen_clear(d->irq, irq_target_cpu[d->irq]); + spin_unlock_irqrestore(&wakeupgen_lock, flags); +} + +/* + * Architecture specific Unmask extension + */ +static void wakeupgen_unmask(struct irq_data *d) +{ + unsigned long flags; + + spin_lock_irqsave(&wakeupgen_lock, flags); + _wakeupgen_set(d->irq, irq_target_cpu[d->irq]); + spin_unlock_irqrestore(&wakeupgen_lock, flags); +} + +/* + * Mask or unmask all interrupts on given CPU. + * 0 = Mask all interrupts on the 'cpu' + * 1 = Unmask all interrupts on the 'cpu' + * Ensure that the initial mask is maintained. This is faster than + * iterating through GIC registers to arrive at the correct masks. + */ +static void wakeupgen_irqmask_all(unsigned int cpu, unsigned int set) +{ + unsigned long flags; + + spin_lock_irqsave(&wakeupgen_lock, flags); + if (set) { + _wakeupgen_save_masks(cpu); + _wakeupgen_set_all(cpu, WKG_MASK_ALL); + } else { + _wakeupgen_set_all(cpu, WKG_UNMASK_ALL); + _wakeupgen_restore_masks(cpu); + } + spin_unlock_irqrestore(&wakeupgen_lock, flags); +} + +#ifdef CONFIG_CPU_PM +/* + * Save WakeupGen interrupt context in SAR BANK3. Restore is done by + * ROM code. WakeupGen IP is integrated along with GIC to manage the + * interrupt wakeups from CPU low power states. It manages + * masking/unmasking of Shared peripheral interrupts(SPI). So the + * interrupt enable/disable control should be in sync and consistent + * at WakeupGen and GIC so that interrupts are not lost. + */ +static void irq_save_context(void) +{ + u32 i, val; + + if (omap_rev() == OMAP4430_REV_ES1_0) + return; + + if (!sar_base) + sar_base = omap4_get_sar_ram_base(); + + for (i = 0; i < NR_REG_BANKS; i++) { + /* Save the CPUx interrupt mask for IRQ 0 to 127 */ + val = wakeupgen_readl(i, 0); + sar_writel(val, WAKEUPGENENB_OFFSET_CPU0, i); + val = wakeupgen_readl(i, 1); + sar_writel(val, WAKEUPGENENB_OFFSET_CPU1, i); + + /* + * Disable the secure interrupts for CPUx. The restore + * code blindly restores secure and non-secure interrupt + * masks from SAR RAM. Secure interrupts are not suppose + * to be enabled from HLOS. So overwrite the SAR location + * so that the secure interrupt remains disabled. + */ + sar_writel(0x0, WAKEUPGENENB_SECURE_OFFSET_CPU0, i); + sar_writel(0x0, WAKEUPGENENB_SECURE_OFFSET_CPU1, i); + } + + /* Save AuxBoot* registers */ + val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0); + __raw_writel(val, sar_base + AUXCOREBOOT0_OFFSET); + val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0); + __raw_writel(val, sar_base + AUXCOREBOOT1_OFFSET); + + /* Save SyncReq generation logic */ + val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0); + __raw_writel(val, sar_base + AUXCOREBOOT0_OFFSET); + val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0); + __raw_writel(val, sar_base + AUXCOREBOOT1_OFFSET); + + /* Save SyncReq generation logic */ + val = __raw_readl(wakeupgen_base + OMAP_PTMSYNCREQ_MASK); + __raw_writel(val, sar_base + PTMSYNCREQ_MASK_OFFSET); + val = __raw_readl(wakeupgen_base + OMAP_PTMSYNCREQ_EN); + __raw_writel(val, sar_base + PTMSYNCREQ_EN_OFFSET); + + /* Set the Backup Bit Mask status */ + val = __raw_readl(sar_base + SAR_BACKUP_STATUS_OFFSET); + val |= SAR_BACKUP_STATUS_WAKEUPGEN; + __raw_writel(val, sar_base + SAR_BACKUP_STATUS_OFFSET); +} + +/* + * Clear WakeupGen SAR backup status. + */ +void irq_sar_clear(void) +{ + u32 val; + val = __raw_readl(sar_base + SAR_BACKUP_STATUS_OFFSET); + val &= ~SAR_BACKUP_STATUS_WAKEUPGEN; + __raw_writel(val, sar_base + SAR_BACKUP_STATUS_OFFSET); +} + +/* + * Save GIC and Wakeupgen interrupt context using secure API + * for HS/EMU devices. + */ +static void irq_save_secure_context(void) +{ + u32 ret; + ret = omap_secure_dispatcher(OMAP4_HAL_SAVEGIC_INDEX, + FLAG_START_CRITICAL, + 0, 0, 0, 0, 0); + if (ret != API_HAL_RET_VALUE_OK) + pr_err("GIC and Wakeupgen context save failed\n"); +} +#endif + +#ifdef CONFIG_HOTPLUG_CPU +static int __cpuinit irq_cpu_hotplug_notify(struct notifier_block *self, + unsigned long action, void *hcpu) +{ + unsigned int cpu = (unsigned int)hcpu; + + switch (action) { + case CPU_ONLINE: + wakeupgen_irqmask_all(cpu, 0); + break; + case CPU_DEAD: + wakeupgen_irqmask_all(cpu, 1); + break; + } + return NOTIFY_OK; +} + +static struct notifier_block __refdata irq_hotplug_notifier = { + .notifier_call = irq_cpu_hotplug_notify, +}; + +static void __init irq_hotplug_init(void) +{ + register_hotcpu_notifier(&irq_hotplug_notifier); +} +#else +static void __init irq_hotplug_init(void) +{} +#endif + +#ifdef CONFIG_CPU_PM +static int irq_notifier(struct notifier_block *self, unsigned long cmd, void *v) +{ + switch (cmd) { + case CPU_CLUSTER_PM_ENTER: + if (omap_type() == OMAP2_DEVICE_TYPE_GP) + irq_save_context(); + else + irq_save_secure_context(); + break; + case CPU_CLUSTER_PM_EXIT: + if (omap_type() == OMAP2_DEVICE_TYPE_GP) + irq_sar_clear(); + break; + } + return NOTIFY_OK; +} + +static struct notifier_block irq_notifier_block = { + .notifier_call = irq_notifier, +}; + +static void __init irq_pm_init(void) +{ + cpu_pm_register_notifier(&irq_notifier_block); +} +#else +static void __init irq_pm_init(void) +{} +#endif + +/* + * Initialise the wakeupgen module. + */ +int __init omap_wakeupgen_init(void) +{ + int i; + unsigned int boot_cpu = smp_processor_id(); + + /* Not supported on OMAP4 ES1.0 silicon */ + if (omap_rev() == OMAP4430_REV_ES1_0) { + WARN(1, "WakeupGen: Not supported on OMAP4430 ES1.0\n"); + return -EPERM; + } + + /* Static mapping, never released */ + wakeupgen_base = ioremap(OMAP44XX_WKUPGEN_BASE, SZ_4K); + if (WARN_ON(!wakeupgen_base)) + return -ENOMEM; + + /* Clear all IRQ bitmasks at wakeupGen level */ + for (i = 0; i < NR_REG_BANKS; i++) { + wakeupgen_writel(0, i, CPU0_ID); + wakeupgen_writel(0, i, CPU1_ID); + } + + /* + * Override GIC architecture specific functions to add + * OMAP WakeupGen interrupt controller along with GIC + */ + gic_arch_extn.irq_mask = wakeupgen_mask; + gic_arch_extn.irq_unmask = wakeupgen_unmask; + gic_arch_extn.flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE; + + /* + * FIXME: Add support to set_smp_affinity() once the core + * GIC code has necessary hooks in place. + */ + + /* Associate all the IRQs to boot CPU like GIC init does. */ + for (i = 0; i < NR_IRQS; i++) + irq_target_cpu[i] = boot_cpu; + + irq_hotplug_init(); + irq_pm_init(); + + return 0; +} diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c index beecfdd56ea..bc16c818c6b 100644 --- a/arch/arm/mach-omap2/omap4-common.c +++ b/arch/arm/mach-omap2/omap4-common.c @@ -15,18 +15,73 @@ #include <linux/init.h> #include <linux/io.h> #include <linux/platform_device.h> +#include <linux/memblock.h> #include <asm/hardware/gic.h> #include <asm/hardware/cache-l2x0.h> +#include <asm/mach/map.h> #include <plat/irqs.h> +#include <plat/sram.h> #include <mach/hardware.h> +#include <mach/omap-wakeupgen.h> #include "common.h" +#include "omap4-sar-layout.h" #ifdef CONFIG_CACHE_L2X0 -void __iomem *l2cache_base; +static void __iomem *l2cache_base; +#endif + +static void __iomem *sar_ram_base; + +#ifdef CONFIG_OMAP4_ERRATA_I688 +/* Used to implement memory barrier on DRAM path */ +#define OMAP4_DRAM_BARRIER_VA 0xfe600000 + +void __iomem *dram_sync, *sram_sync; + +void omap_bus_sync(void) +{ + if (dram_sync && sram_sync) { + writel_relaxed(readl_relaxed(dram_sync), dram_sync); + writel_relaxed(readl_relaxed(sram_sync), sram_sync); + isb(); + } +} + +static int __init omap_barriers_init(void) +{ + struct map_desc dram_io_desc[1]; + phys_addr_t paddr; + u32 size; + + if (!cpu_is_omap44xx()) + return -ENODEV; + + size = ALIGN(PAGE_SIZE, SZ_1M); + paddr = memblock_alloc(size, SZ_1M); + if (!paddr) { + pr_err("%s: failed to reserve 4 Kbytes\n", __func__); + return -ENOMEM; + } + memblock_free(paddr, size); + memblock_remove(paddr, size); + dram_io_desc[0].virtual = OMAP4_DRAM_BARRIER_VA; + dram_io_desc[0].pfn = __phys_to_pfn(paddr); + dram_io_desc[0].length = size; + dram_io_desc[0].type = MT_MEMORY_SO; + iotable_init(dram_io_desc, ARRAY_SIZE(dram_io_desc)); + dram_sync = (void __iomem *) dram_io_desc[0].virtual; + sram_sync = (void __iomem *) OMAP4_SRAM_VA; + + pr_info("OMAP4: Map 0x%08llx to 0x%08lx for dram barrier\n", + (long long) paddr, dram_io_desc[0].virtual); + + return 0; +} +core_initcall(omap_barriers_init); #endif void __init gic_init_irq(void) @@ -42,11 +97,18 @@ void __init gic_init_irq(void) omap_irq_base = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512); BUG_ON(!omap_irq_base); + omap_wakeupgen_init(); + gic_init(0, 29, gic_dist_base_addr, omap_irq_base); } #ifdef CONFIG_CACHE_L2X0 +void __iomem *omap4_get_l2cache_base(void) +{ + return l2cache_base; +} + static void omap4_l2x0_disable(void) { /* Disable PL310 L2 Cache controller */ @@ -72,7 +134,8 @@ static int __init omap_l2_cache_init(void) /* Static mapping, never released */ l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K); - BUG_ON(!l2cache_base); + if (WARN_ON(!l2cache_base)) + return -ENOMEM; /* * 16-way associativity, parity disabled @@ -112,3 +175,30 @@ static int __init omap_l2_cache_init(void) } early_initcall(omap_l2_cache_init); #endif + +void __iomem *omap4_get_sar_ram_base(void) +{ + return sar_ram_base; +} + +/* + * SAR RAM used to save and restore the HW + * context in low power modes + */ +static int __init omap4_sar_ram_init(void) +{ + /* + * To avoid code running on other OMAPs in + * multi-omap builds + */ + if (!cpu_is_omap44xx()) + return -ENOMEM; + + /* Static mapping, never released */ + sar_ram_base = ioremap(OMAP44XX_SAR_RAM_BASE, SZ_16K); + if (WARN_ON(!sar_ram_base)) + return -ENOMEM; + + return 0; +} +early_initcall(omap4_sar_ram_init); diff --git a/arch/arm/mach-omap2/omap4-sar-layout.h b/arch/arm/mach-omap2/omap4-sar-layout.h new file mode 100644 index 00000000000..fe5b545ad44 --- /dev/null +++ b/arch/arm/mach-omap2/omap4-sar-layout.h @@ -0,0 +1,50 @@ +/* + * omap4-sar-layout.h: OMAP4 SAR RAM layout header file + * + * Copyright (C) 2011 Texas Instruments, Inc. + * Santosh Shilimkar <santosh.shilimkar@ti.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef OMAP_ARCH_OMAP4_SAR_LAYOUT_H +#define OMAP_ARCH_OMAP4_SAR_LAYOUT_H + +/* + * SAR BANK offsets from base address OMAP44XX_SAR_RAM_BASE + */ +#define SAR_BANK1_OFFSET 0x0000 +#define SAR_BANK2_OFFSET 0x1000 +#define SAR_BANK3_OFFSET 0x2000 +#define SAR_BANK4_OFFSET 0x3000 + +/* Scratch pad memory offsets from SAR_BANK1 */ +#define SCU_OFFSET0 0xd00 +#define SCU_OFFSET1 0xd04 +#define OMAP_TYPE_OFFSET 0xd10 +#define L2X0_SAVE_OFFSET0 0xd14 +#define L2X0_SAVE_OFFSET1 0xd18 +#define L2X0_AUXCTRL_OFFSET 0xd1c +#define L2X0_PREFETCH_CTRL_OFFSET 0xd20 + +/* CPUx Wakeup Non-Secure Physical Address offsets in SAR_BANK3 */ +#define CPU0_WAKEUP_NS_PA_ADDR_OFFSET 0xa04 +#define CPU1_WAKEUP_NS_PA_ADDR_OFFSET 0xa08 + +#define SAR_BACKUP_STATUS_OFFSET (SAR_BANK3_OFFSET + 0x500) +#define SAR_SECURE_RAM_SIZE_OFFSET (SAR_BANK3_OFFSET + 0x504) +#define SAR_SECRAM_SAVED_AT_OFFSET (SAR_BANK3_OFFSET + 0x508) + +/* WakeUpGen save restore offset from OMAP44XX_SAR_RAM_BASE */ +#define WAKEUPGENENB_OFFSET_CPU0 (SAR_BANK3_OFFSET + 0x684) +#define WAKEUPGENENB_SECURE_OFFSET_CPU0 (SAR_BANK3_OFFSET + 0x694) +#define WAKEUPGENENB_OFFSET_CPU1 (SAR_BANK3_OFFSET + 0x6a4) +#define WAKEUPGENENB_SECURE_OFFSET_CPU1 (SAR_BANK3_OFFSET + 0x6b4) +#define AUXCOREBOOT0_OFFSET (SAR_BANK3_OFFSET + 0x6c4) +#define AUXCOREBOOT1_OFFSET (SAR_BANK3_OFFSET + 0x6c8) +#define PTMSYNCREQ_MASK_OFFSET (SAR_BANK3_OFFSET + 0x6cc) +#define PTMSYNCREQ_EN_OFFSET (SAR_BANK3_OFFSET + 0x6d0) +#define SAR_BACKUP_STATUS_WAKEUPGEN 0x10 + +#endif diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index 529142aff76..5192cabb40e 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -136,6 +136,7 @@ #include <linux/list.h> #include <linux/mutex.h> #include <linux/spinlock.h> +#include <linux/slab.h> #include "common.h" #include <plat/cpu.h> @@ -381,6 +382,51 @@ static int _set_module_autoidle(struct omap_hwmod *oh, u8 autoidle, } /** + * _set_idle_ioring_wakeup - enable/disable IO pad wakeup on hwmod idle for mux + * @oh: struct omap_hwmod * + * @set_wake: bool value indicating to set (true) or clear (false) wakeup enable + * + * Set or clear the I/O pad wakeup flag in the mux entries for the + * hwmod @oh. This function changes the @oh->mux->pads_dynamic array + * in memory. If the hwmod is currently idled, and the new idle + * values don't match the previous ones, this function will also + * update the SCM PADCTRL registers. Otherwise, if the hwmod is not + * currently idled, this function won't touch the hardware: the new + * mux settings are written to the SCM PADCTRL registers when the + * hwmod is idled. No return value. + */ +static void _set_idle_ioring_wakeup(struct omap_hwmod *oh, bool set_wake) +{ + struct omap_device_pad *pad; + bool change = false; + u16 prev_idle; + int j; + + if (!oh->mux || !oh->mux->enabled) + return; + + for (j = 0; j < oh->mux->nr_pads_dynamic; j++) { + pad = oh->mux->pads_dynamic[j]; + + if (!(pad->flags & OMAP_DEVICE_PAD_WAKEUP)) + continue; + + prev_idle = pad->idle; + + if (set_wake) + pad->idle |= OMAP_WAKEUP_EN; + else + pad->idle &= ~OMAP_WAKEUP_EN; + + if (prev_idle != pad->idle) + change = true; + } + + if (change && oh->_state == _HWMOD_STATE_IDLE) + omap_hwmod_mux(oh->mux, _HWMOD_STATE_IDLE); +} + +/** * _enable_wakeup: set OCP_SYSCONFIG.ENAWAKEUP bit in the hardware * @oh: struct omap_hwmod * * @@ -706,27 +752,65 @@ static void _enable_module(struct omap_hwmod *oh) } /** - * _disable_module - enable CLKCTRL modulemode on OMAP4 + * _omap4_wait_target_disable - wait for a module to be disabled on OMAP4 + * @oh: struct omap_hwmod * + * + * Wait for a module @oh to enter slave idle. Returns 0 if the module + * does not have an IDLEST bit or if the module successfully enters + * slave idle; otherwise, pass along the return value of the + * appropriate *_cm*_wait_module_idle() function. + */ +static int _omap4_wait_target_disable(struct omap_hwmod *oh) +{ + if (!cpu_is_omap44xx()) + return 0; + + if (!oh) + return -EINVAL; + + if (oh->_int_flags & _HWMOD_NO_MPU_PORT) + return 0; + + if (oh->flags & HWMOD_NO_IDLEST) + return 0; + + return omap4_cminst_wait_module_idle(oh->clkdm->prcm_partition, + oh->clkdm->cm_inst, + oh->clkdm->clkdm_offs, + oh->prcm.omap4.clkctrl_offs); +} + +/** + * _omap4_disable_module - enable CLKCTRL modulemode on OMAP4 * @oh: struct omap_hwmod * * * Disable the PRCM module mode related to the hwmod @oh. - * No return value. + * Return EINVAL if the modulemode is not supported and 0 in case of success. */ -static void _disable_module(struct omap_hwmod *oh) +static int _omap4_disable_module(struct omap_hwmod *oh) { + int v; + /* The module mode does not exist prior OMAP4 */ - if (cpu_is_omap24xx() || cpu_is_omap34xx()) - return; + if (!cpu_is_omap44xx()) + return -EINVAL; if (!oh->clkdm || !oh->prcm.omap4.modulemode) - return; + return -EINVAL; - pr_debug("omap_hwmod: %s: _disable_module\n", oh->name); + pr_debug("omap_hwmod: %s: %s\n", oh->name, __func__); omap4_cminst_module_disable(oh->clkdm->prcm_partition, oh->clkdm->cm_inst, oh->clkdm->clkdm_offs, oh->prcm.omap4.clkctrl_offs); + + v = _omap4_wait_target_disable(oh); + if (v) + pr_warn("omap_hwmod: %s: _wait_target_disable failed\n", + oh->name); + + return 0; } /** @@ -1153,36 +1237,6 @@ static int _wait_target_ready(struct omap_hwmod *oh) } /** - * _wait_target_disable - wait for a module to be disabled - * @oh: struct omap_hwmod * - * - * Wait for a module @oh to enter slave idle. Returns 0 if the module - * does not have an IDLEST bit or if the module successfully enters - * slave idle; otherwise, pass along the return value of the - * appropriate *_cm*_wait_module_idle() function. - */ -static int _wait_target_disable(struct omap_hwmod *oh) -{ - /* TODO: For now just handle OMAP4+ */ - if (cpu_is_omap24xx() || cpu_is_omap34xx()) - return 0; - - if (!oh) - return -EINVAL; - - if (oh->_int_flags & _HWMOD_NO_MPU_PORT) - return 0; - - if (oh->flags & HWMOD_NO_IDLEST) - return 0; - - return omap4_cminst_wait_module_idle(oh->clkdm->prcm_partition, - oh->clkdm->cm_inst, - oh->clkdm->clkdm_offs, - oh->prcm.omap4.clkctrl_offs); -} - -/** * _lookup_hardreset - fill register bit info for this hwmod/reset line * @oh: struct omap_hwmod * * @name: name of the reset line in the context of this hwmod @@ -1441,6 +1495,25 @@ static int _enable(struct omap_hwmod *oh) pr_debug("omap_hwmod: %s: enabling\n", oh->name); + /* + * hwmods with HWMOD_INIT_NO_IDLE flag set are left + * in enabled state at init. + * Now that someone is really trying to enable them, + * just ensure that the hwmod mux is set. + */ + if (oh->_int_flags & _HWMOD_SKIP_ENABLE) { + /* + * If the caller has mux data populated, do the mux'ing + * which wouldn't have been done as part of the _enable() + * done during setup. + */ + if (oh->mux) + omap_hwmod_mux(oh->mux, _HWMOD_STATE_ENABLED); + + oh->_int_flags &= ~_HWMOD_SKIP_ENABLE; + return 0; + } + if (oh->_state != _HWMOD_STATE_INITIALIZED && oh->_state != _HWMOD_STATE_IDLE && oh->_state != _HWMOD_STATE_DISABLED) { @@ -1524,8 +1597,6 @@ static int _enable(struct omap_hwmod *oh) */ static int _idle(struct omap_hwmod *oh) { - int ret; - pr_debug("omap_hwmod: %s: idling\n", oh->name); if (oh->_state != _HWMOD_STATE_ENABLED) { @@ -1537,11 +1608,9 @@ static int _idle(struct omap_hwmod *oh) if (oh->class->sysc) _idle_sysc(oh); _del_initiator_dep(oh, mpu_oh); - _disable_module(oh); - ret = _wait_target_disable(oh); - if (ret) - pr_warn("omap_hwmod: %s: _wait_target_disable failed\n", - oh->name); + + _omap4_disable_module(oh); + /* * The module must be in idle mode before disabling any parents * clocks. Otherwise, the parent clock might be disabled before @@ -1642,11 +1711,7 @@ static int _shutdown(struct omap_hwmod *oh) if (oh->_state == _HWMOD_STATE_ENABLED) { _del_initiator_dep(oh, mpu_oh); /* XXX what about the other system initiators here? dma, dsp */ - _disable_module(oh); - ret = _wait_target_disable(oh); - if (ret) - pr_warn("omap_hwmod: %s: _wait_target_disable failed\n", - oh->name); + _omap4_disable_module(oh); _disable_clocks(oh); if (oh->clkdm) clkdm_hwmod_disable(oh->clkdm, oh); @@ -1744,8 +1809,10 @@ static int _setup(struct omap_hwmod *oh, void *data) * it should be set by the core code as a runtime flag during startup */ if ((oh->flags & HWMOD_INIT_NO_IDLE) && - (postsetup_state == _HWMOD_STATE_IDLE)) + (postsetup_state == _HWMOD_STATE_IDLE)) { + oh->_int_flags |= _HWMOD_SKIP_ENABLE; postsetup_state = _HWMOD_STATE_ENABLED; + } if (postsetup_state == _HWMOD_STATE_IDLE) _idle(oh); @@ -2416,6 +2483,7 @@ int omap_hwmod_enable_wakeup(struct omap_hwmod *oh) v = oh->_sysc_cache; _enable_wakeup(oh, &v); _write_sysconfig(v, oh); + _set_idle_ioring_wakeup(oh, true); spin_unlock_irqrestore(&oh->_lock, flags); return 0; @@ -2446,6 +2514,7 @@ int omap_hwmod_disable_wakeup(struct omap_hwmod *oh) v = oh->_sysc_cache; _disable_wakeup(oh, &v); _write_sysconfig(v, oh); + _set_idle_ioring_wakeup(oh, false); spin_unlock_irqrestore(&oh->_lock, flags); return 0; @@ -2662,3 +2731,57 @@ int omap_hwmod_no_setup_reset(struct omap_hwmod *oh) return 0; } + +/** + * omap_hwmod_pad_route_irq - route an I/O pad wakeup to a particular MPU IRQ + * @oh: struct omap_hwmod * containing hwmod mux entries + * @pad_idx: array index in oh->mux of the hwmod mux entry to route wakeup + * @irq_idx: the hwmod mpu_irqs array index of the IRQ to trigger on wakeup + * + * When an I/O pad wakeup arrives for the dynamic or wakeup hwmod mux + * entry number @pad_idx for the hwmod @oh, trigger the interrupt + * service routine for the hwmod's mpu_irqs array index @irq_idx. If + * this function is not called for a given pad_idx, then the ISR + * associated with @oh's first MPU IRQ will be triggered when an I/O + * pad wakeup occurs on that pad. Note that @pad_idx is the index of + * the _dynamic or wakeup_ entry: if there are other entries not + * marked with OMAP_DEVICE_PAD_WAKEUP or OMAP_DEVICE_PAD_REMUX, these + * entries are NOT COUNTED in the dynamic pad index. This function + * must be called separately for each pad that requires its interrupt + * to be re-routed this way. Returns -EINVAL if there is an argument + * problem or if @oh does not have hwmod mux entries or MPU IRQs; + * returns -ENOMEM if memory cannot be allocated; or 0 upon success. + * + * XXX This function interface is fragile. Rather than using array + * indexes, which are subject to unpredictable change, it should be + * using hwmod IRQ names, and some other stable key for the hwmod mux + * pad records. + */ +int omap_hwmod_pad_route_irq(struct omap_hwmod *oh, int pad_idx, int irq_idx) +{ + int nr_irqs; + + might_sleep(); + + if (!oh || !oh->mux || !oh->mpu_irqs || pad_idx < 0 || + pad_idx >= oh->mux->nr_pads_dynamic) + return -EINVAL; + + /* Check the number of available mpu_irqs */ + for (nr_irqs = 0; oh->mpu_irqs[nr_irqs].irq >= 0; nr_irqs++) + ; + + if (irq_idx >= nr_irqs) + return -EINVAL; + + if (!oh->mux->irqs) { + /* XXX What frees this? */ + oh->mux->irqs = kzalloc(sizeof(int) * oh->mux->nr_pads_dynamic, + GFP_KERNEL); + if (!oh->mux->irqs) + return -ENOMEM; + } + oh->mux->irqs[pad_idx] = irq_idx; + + return 0; +} diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index eef43e2e163..5324e8d93bc 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -84,6 +84,8 @@ static struct omap_hwmod omap3xxx_mcbsp4_hwmod; static struct omap_hwmod omap3xxx_mcbsp5_hwmod; static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod; static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod; +static struct omap_hwmod omap3xxx_usb_host_hs_hwmod; +static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod; /* L3 -> L4_CORE interface */ static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = { @@ -164,6 +166,7 @@ static struct omap_hwmod omap3xxx_uart1_hwmod; static struct omap_hwmod omap3xxx_uart2_hwmod; static struct omap_hwmod omap3xxx_uart3_hwmod; static struct omap_hwmod omap3xxx_uart4_hwmod; +static struct omap_hwmod am35xx_uart4_hwmod; static struct omap_hwmod omap3xxx_usbhsotg_hwmod; /* l3_core -> usbhsotg interface */ @@ -299,6 +302,23 @@ static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* AM35xx: L4 CORE -> UART4 interface */ +static struct omap_hwmod_addr_space am35xx_uart4_addr_space[] = { + { + .pa_start = OMAP3_UART4_AM35XX_BASE, + .pa_end = OMAP3_UART4_AM35XX_BASE + SZ_1K - 1, + .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, + }, +}; + +static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &am35xx_uart4_hwmod, + .clk = "uart4_ick", + .addr = am35xx_uart4_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* L4 CORE -> I2C1 interface */ static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = { .master = &omap3xxx_l4_core_hwmod, @@ -1162,6 +1182,7 @@ static struct omap_hwmod_class_sysconfig i2c_sysc = { SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .clockact = CLOCKACT_TEST_ICLK, .sysc_fields = &omap_hwmod_sysc_type1, }; @@ -1309,6 +1330,39 @@ static struct omap_hwmod omap3xxx_uart4_hwmod = { .class = &omap2_uart_class, }; +static struct omap_hwmod_irq_info am35xx_uart4_mpu_irqs[] = { + { .irq = INT_35XX_UART4_IRQ, }, +}; + +static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = { + { .name = "rx", .dma_req = AM35XX_DMA_UART4_RX, }, + { .name = "tx", .dma_req = AM35XX_DMA_UART4_TX, }, +}; + +static struct omap_hwmod_ocp_if *am35xx_uart4_slaves[] = { + &am35xx_l4_core__uart4, +}; + +static struct omap_hwmod am35xx_uart4_hwmod = { + .name = "uart4", + .mpu_irqs = am35xx_uart4_mpu_irqs, + .sdma_reqs = am35xx_uart4_sdma_reqs, + .main_clk = "uart4_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_UART4_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_EN_UART4_SHIFT, + }, + }, + .slaves = am35xx_uart4_slaves, + .slaves_cnt = ARRAY_SIZE(am35xx_uart4_slaves), + .class = &omap2_uart_class, +}; + + static struct omap_hwmod_class i2c_class = { .name = "i2c", .sysc = &i2c_sysc, @@ -1636,7 +1690,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = { static struct omap_hwmod omap3xxx_i2c1_hwmod = { .name = "i2c1", - .flags = HWMOD_16BIT_REG, + .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, .mpu_irqs = omap2_i2c1_mpu_irqs, .sdma_reqs = omap2_i2c1_sdma_reqs, .main_clk = "i2c1_fck", @@ -1670,7 +1724,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = { static struct omap_hwmod omap3xxx_i2c2_hwmod = { .name = "i2c2", - .flags = HWMOD_16BIT_REG, + .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, .mpu_irqs = omap2_i2c2_mpu_irqs, .sdma_reqs = omap2_i2c2_sdma_reqs, .main_clk = "i2c2_fck", @@ -1715,7 +1769,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = { static struct omap_hwmod omap3xxx_i2c3_hwmod = { .name = "i2c3", - .flags = HWMOD_16BIT_REG, + .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, .mpu_irqs = i2c3_mpu_irqs, .sdma_reqs = i2c3_sdma_reqs, .main_clk = "i2c3_fck", @@ -3072,7 +3126,35 @@ static struct omap_mmc_dev_attr mmc1_dev_attr = { .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, }; -static struct omap_hwmod omap3xxx_mmc1_hwmod = { +/* See 35xx errata 2.1.1.128 in SPRZ278F */ +static struct omap_mmc_dev_attr mmc1_pre_es3_dev_attr = { + .flags = (OMAP_HSMMC_SUPPORTS_DUAL_VOLT | + OMAP_HSMMC_BROKEN_MULTIBLOCK_READ), +}; + +static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = { + .name = "mmc1", + .mpu_irqs = omap34xx_mmc1_mpu_irqs, + .sdma_reqs = omap34xx_mmc1_sdma_reqs, + .opt_clks = omap34xx_mmc1_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks), + .main_clk = "mmchs1_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_MMC1_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT, + }, + }, + .dev_attr = &mmc1_pre_es3_dev_attr, + .slaves = omap3xxx_mmc1_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc1_slaves), + .class = &omap34xx_mmc_class, +}; + +static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = { .name = "mmc1", .mpu_irqs = omap34xx_mmc1_mpu_irqs, .sdma_reqs = omap34xx_mmc1_sdma_reqs, @@ -3115,7 +3197,34 @@ static struct omap_hwmod_ocp_if *omap3xxx_mmc2_slaves[] = { &omap3xxx_l4_core__mmc2, }; -static struct omap_hwmod omap3xxx_mmc2_hwmod = { +/* See 35xx errata 2.1.1.128 in SPRZ278F */ +static struct omap_mmc_dev_attr mmc2_pre_es3_dev_attr = { + .flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ, +}; + +static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = { + .name = "mmc2", + .mpu_irqs = omap34xx_mmc2_mpu_irqs, + .sdma_reqs = omap34xx_mmc2_sdma_reqs, + .opt_clks = omap34xx_mmc2_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks), + .main_clk = "mmchs2_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_MMC2_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT, + }, + }, + .dev_attr = &mmc2_pre_es3_dev_attr, + .slaves = omap3xxx_mmc2_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc2_slaves), + .class = &omap34xx_mmc_class, +}; + +static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = { .name = "mmc2", .mpu_irqs = omap34xx_mmc2_mpu_irqs, .sdma_reqs = omap34xx_mmc2_sdma_reqs, @@ -3177,13 +3286,223 @@ static struct omap_hwmod omap3xxx_mmc3_hwmod = { .class = &omap34xx_mmc_class, }; +/* + * 'usb_host_hs' class + * high-speed multi-port usb host controller + */ +static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = { + .master = &omap3xxx_usb_host_hs_hwmod, + .slave = &omap3xxx_l3_main_hwmod, + .clk = "core_l3_ick", + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_class_sysconfig omap3xxx_usb_host_hs_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY | + SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP | + SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap3xxx_usb_host_hs_hwmod_class = { + .name = "usb_host_hs", + .sysc = &omap3xxx_usb_host_hs_sysc, +}; + +static struct omap_hwmod_ocp_if *omap3xxx_usb_host_hs_masters[] = { + &omap3xxx_usb_host_hs__l3_main_2, +}; + +static struct omap_hwmod_addr_space omap3xxx_usb_host_hs_addrs[] = { + { + .name = "uhh", + .pa_start = 0x48064000, + .pa_end = 0x480643ff, + .flags = ADDR_TYPE_RT + }, + { + .name = "ohci", + .pa_start = 0x48064400, + .pa_end = 0x480647ff, + }, + { + .name = "ehci", + .pa_start = 0x48064800, + .pa_end = 0x48064cff, + }, + {} +}; + +static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_usb_host_hs_hwmod, + .clk = "usbhost_ick", + .addr = omap3xxx_usb_host_hs_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_ocp_if *omap3xxx_usb_host_hs_slaves[] = { + &omap3xxx_l4_core__usb_host_hs, +}; + +static struct omap_hwmod_opt_clk omap3xxx_usb_host_hs_opt_clks[] = { + { .role = "ehci_logic_fck", .clk = "usbhost_120m_fck", }, +}; + +static struct omap_hwmod_irq_info omap3xxx_usb_host_hs_irqs[] = { + { .name = "ohci-irq", .irq = 76 }, + { .name = "ehci-irq", .irq = 77 }, + { .irq = -1 } +}; + +static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = { + .name = "usb_host_hs", + .class = &omap3xxx_usb_host_hs_hwmod_class, + .clkdm_name = "l3_init_clkdm", + .mpu_irqs = omap3xxx_usb_host_hs_irqs, + .main_clk = "usbhost_48m_fck", + .prcm = { + .omap2 = { + .module_offs = OMAP3430ES2_USBHOST_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP3430ES2_EN_USBHOST1_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT, + .idlest_stdby_bit = OMAP3430ES2_ST_USBHOST_STDBY_SHIFT, + }, + }, + .opt_clks = omap3xxx_usb_host_hs_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(omap3xxx_usb_host_hs_opt_clks), + .slaves = omap3xxx_usb_host_hs_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_usb_host_hs_slaves), + .masters = omap3xxx_usb_host_hs_masters, + .masters_cnt = ARRAY_SIZE(omap3xxx_usb_host_hs_masters), + + /* + * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock + * id: i660 + * + * Description: + * In the following configuration : + * - USBHOST module is set to smart-idle mode + * - PRCM asserts idle_req to the USBHOST module ( This typically + * happens when the system is going to a low power mode : all ports + * have been suspended, the master part of the USBHOST module has + * entered the standby state, and SW has cut the functional clocks) + * - an USBHOST interrupt occurs before the module is able to answer + * idle_ack, typically a remote wakeup IRQ. + * Then the USB HOST module will enter a deadlock situation where it + * is no more accessible nor functional. + * + * Workaround: + * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE + */ + + /* + * Errata: USB host EHCI may stall when entering smart-standby mode + * Id: i571 + * + * Description: + * When the USBHOST module is set to smart-standby mode, and when it is + * ready to enter the standby state (i.e. all ports are suspended and + * all attached devices are in suspend mode), then it can wrongly assert + * the Mstandby signal too early while there are still some residual OCP + * transactions ongoing. If this condition occurs, the internal state + * machine may go to an undefined state and the USB link may be stuck + * upon the next resume. + * + * Workaround: + * Don't use smart standby; use only force standby, + * hence HWMOD_SWSUP_MSTANDBY + */ + + /* + * During system boot; If the hwmod framework resets the module + * the module will have smart idle settings; which can lead to deadlock + * (above Errata Id:i660); so, dont reset the module during boot; + * Use HWMOD_INIT_NO_RESET. + */ + + .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY | + HWMOD_INIT_NO_RESET, +}; + +/* + * 'usb_tll_hs' class + * usb_tll_hs module is the adapter on the usb_host_hs ports + */ +static struct omap_hwmod_class_sysconfig omap3xxx_usb_tll_hs_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | + SYSC_HAS_AUTOIDLE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap3xxx_usb_tll_hs_hwmod_class = { + .name = "usb_tll_hs", + .sysc = &omap3xxx_usb_tll_hs_sysc, +}; + +static struct omap_hwmod_irq_info omap3xxx_usb_tll_hs_irqs[] = { + { .name = "tll-irq", .irq = 78 }, + { .irq = -1 } +}; + +static struct omap_hwmod_addr_space omap3xxx_usb_tll_hs_addrs[] = { + { + .name = "tll", + .pa_start = 0x48062000, + .pa_end = 0x48062fff, + .flags = ADDR_TYPE_RT + }, + {} +}; + +static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_tll_hs = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_usb_tll_hs_hwmod, + .clk = "usbtll_ick", + .addr = omap3xxx_usb_tll_hs_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_ocp_if *omap3xxx_usb_tll_hs_slaves[] = { + &omap3xxx_l4_core__usb_tll_hs, +}; + +static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = { + .name = "usb_tll_hs", + .class = &omap3xxx_usb_tll_hs_hwmod_class, + .clkdm_name = "l3_init_clkdm", + .mpu_irqs = omap3xxx_usb_tll_hs_irqs, + .main_clk = "usbtll_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 3, + .module_bit = OMAP3430ES2_EN_USBTLL_SHIFT, + .idlest_reg_id = 3, + .idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT, + }, + }, + .slaves = omap3xxx_usb_tll_hs_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_usb_tll_hs_slaves), +}; + static __initdata struct omap_hwmod *omap3xxx_hwmods[] = { &omap3xxx_l3_main_hwmod, &omap3xxx_l4_core_hwmod, &omap3xxx_l4_per_hwmod, &omap3xxx_l4_wkup_hwmod, - &omap3xxx_mmc1_hwmod, - &omap3xxx_mmc2_hwmod, &omap3xxx_mmc3_hwmod, &omap3xxx_mpu_hwmod, @@ -3198,12 +3517,12 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = { &omap3xxx_timer9_hwmod, &omap3xxx_timer10_hwmod, &omap3xxx_timer11_hwmod, - &omap3xxx_timer12_hwmod, &omap3xxx_wd_timer2_hwmod, &omap3xxx_uart1_hwmod, &omap3xxx_uart2_hwmod, &omap3xxx_uart3_hwmod, + /* dss class */ &omap3xxx_dss_dispc_hwmod, &omap3xxx_dss_dsi1_hwmod, @@ -3245,6 +3564,12 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = { NULL, }; +/* GP-only hwmods */ +static __initdata struct omap_hwmod *omap3xxx_gp_hwmods[] = { + &omap3xxx_timer12_hwmod, + NULL +}; + /* 3430ES1-only hwmods */ static __initdata struct omap_hwmod *omap3430es1_hwmods[] = { &omap3430es1_dss_core_hwmod, @@ -3255,6 +3580,22 @@ static __initdata struct omap_hwmod *omap3430es1_hwmods[] = { static __initdata struct omap_hwmod *omap3430es2plus_hwmods[] = { &omap3xxx_dss_core_hwmod, &omap3xxx_usbhsotg_hwmod, + &omap3xxx_usb_host_hs_hwmod, + &omap3xxx_usb_tll_hs_hwmod, + NULL +}; + +/* <= 3430ES3-only hwmods */ +static struct omap_hwmod *omap3430_pre_es3_hwmods[] __initdata = { + &omap3xxx_pre_es3_mmc1_hwmod, + &omap3xxx_pre_es3_mmc2_hwmod, + NULL +}; + +/* 3430ES3+-only hwmods */ +static struct omap_hwmod *omap3430_es3plus_hwmods[] __initdata = { + &omap3xxx_es3plus_mmc1_hwmod, + &omap3xxx_es3plus_mmc2_hwmod, NULL }; @@ -3276,12 +3617,21 @@ static __initdata struct omap_hwmod *omap36xx_hwmods[] = { &omap36xx_sr2_hwmod, &omap3xxx_usbhsotg_hwmod, &omap3xxx_mailbox_hwmod, + &omap3xxx_usb_host_hs_hwmod, + &omap3xxx_usb_tll_hs_hwmod, + &omap3xxx_es3plus_mmc1_hwmod, + &omap3xxx_es3plus_mmc2_hwmod, NULL }; static __initdata struct omap_hwmod *am35xx_hwmods[] = { &omap3xxx_dss_core_hwmod, /* XXX ??? */ &am35xx_usbhsotg_hwmod, + &am35xx_uart4_hwmod, + &omap3xxx_usb_host_hs_hwmod, + &omap3xxx_usb_tll_hs_hwmod, + &omap3xxx_es3plus_mmc1_hwmod, + &omap3xxx_es3plus_mmc2_hwmod, NULL }; @@ -3296,6 +3646,13 @@ int __init omap3xxx_hwmod_init(void) if (r < 0) return r; + /* Register GP-only hwmods. */ + if (omap_type() == OMAP2_DEVICE_TYPE_GP) { + r = omap_hwmod_register(omap3xxx_gp_hwmods); + if (r < 0) + return r; + } + rev = omap_rev(); /* @@ -3334,6 +3691,21 @@ int __init omap3xxx_hwmod_init(void) h = omap3430es2plus_hwmods; }; + if (h) { + r = omap_hwmod_register(h); + if (r < 0) + return r; + } + + h = NULL; + if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 || + rev == OMAP3430_REV_ES2_1) { + h = omap3430_pre_es3_hwmods; + } else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 || + rev == OMAP3430_REV_ES3_1_2) { + h = omap3430_es3plus_hwmods; + }; + if (h) r = omap_hwmod_register(h); diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index daaf165af69..f9f15108176 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -70,6 +70,8 @@ static struct omap_hwmod omap44xx_mmc2_hwmod; static struct omap_hwmod omap44xx_mpu_hwmod; static struct omap_hwmod omap44xx_mpu_private_hwmod; static struct omap_hwmod omap44xx_usb_otg_hs_hwmod; +static struct omap_hwmod omap44xx_usb_host_hs_hwmod; +static struct omap_hwmod omap44xx_usb_tll_hs_hwmod; /* * Interconnects omap_hwmod structures @@ -2246,6 +2248,7 @@ static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = { SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | SIDLE_SMART_WKUP), + .clockact = CLOCKACT_TEST_ICLK, .sysc_fields = &omap_hwmod_sysc_type1, }; @@ -2300,7 +2303,7 @@ static struct omap_hwmod omap44xx_i2c1_hwmod = { .name = "i2c1", .class = &omap44xx_i2c_hwmod_class, .clkdm_name = "l4_per_clkdm", - .flags = HWMOD_16BIT_REG, + .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, .mpu_irqs = omap44xx_i2c1_irqs, .sdma_reqs = omap44xx_i2c1_sdma_reqs, .main_clk = "i2c1_fck", @@ -2356,7 +2359,7 @@ static struct omap_hwmod omap44xx_i2c2_hwmod = { .name = "i2c2", .class = &omap44xx_i2c_hwmod_class, .clkdm_name = "l4_per_clkdm", - .flags = HWMOD_16BIT_REG, + .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, .mpu_irqs = omap44xx_i2c2_irqs, .sdma_reqs = omap44xx_i2c2_sdma_reqs, .main_clk = "i2c2_fck", @@ -2412,7 +2415,7 @@ static struct omap_hwmod omap44xx_i2c3_hwmod = { .name = "i2c3", .class = &omap44xx_i2c_hwmod_class, .clkdm_name = "l4_per_clkdm", - .flags = HWMOD_16BIT_REG, + .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, .mpu_irqs = omap44xx_i2c3_irqs, .sdma_reqs = omap44xx_i2c3_sdma_reqs, .main_clk = "i2c3_fck", @@ -2468,7 +2471,7 @@ static struct omap_hwmod omap44xx_i2c4_hwmod = { .name = "i2c4", .class = &omap44xx_i2c_hwmod_class, .clkdm_name = "l4_per_clkdm", - .flags = HWMOD_16BIT_REG, + .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, .mpu_irqs = omap44xx_i2c4_irqs, .sdma_reqs = omap44xx_i2c4_sdma_reqs, .main_clk = "i2c4_fck", @@ -5276,6 +5279,207 @@ static struct omap_hwmod omap44xx_wd_timer3_hwmod = { .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer3_slaves), }; +/* + * 'usb_host_hs' class + * high-speed multi-port usb host controller + */ +static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = { + .master = &omap44xx_usb_host_hs_hwmod, + .slave = &omap44xx_l3_main_2_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | + MSTANDBY_SMART | MSTANDBY_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type2, +}; + +static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = { + .name = "usb_host_hs", + .sysc = &omap44xx_usb_host_hs_sysc, +}; + +static struct omap_hwmod_ocp_if *omap44xx_usb_host_hs_masters[] = { + &omap44xx_usb_host_hs__l3_main_2, +}; + +static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = { + { + .name = "uhh", + .pa_start = 0x4a064000, + .pa_end = 0x4a0647ff, + .flags = ADDR_TYPE_RT + }, + { + .name = "ohci", + .pa_start = 0x4a064800, + .pa_end = 0x4a064bff, + }, + { + .name = "ehci", + .pa_start = 0x4a064c00, + .pa_end = 0x4a064fff, + }, + {} +}; + +static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs[] = { + { .name = "ohci-irq", .irq = 76 + OMAP44XX_IRQ_GIC_START }, + { .name = "ehci-irq", .irq = 77 + OMAP44XX_IRQ_GIC_START }, + { .irq = -1 } +}; + +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_usb_host_hs_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_usb_host_hs_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_ocp_if *omap44xx_usb_host_hs_slaves[] = { + &omap44xx_l4_cfg__usb_host_hs, +}; + +static struct omap_hwmod omap44xx_usb_host_hs_hwmod = { + .name = "usb_host_hs", + .class = &omap44xx_usb_host_hs_hwmod_class, + .clkdm_name = "l3_init_clkdm", + .main_clk = "usb_host_hs_fck", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET, + .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .mpu_irqs = omap44xx_usb_host_hs_irqs, + .slaves = omap44xx_usb_host_hs_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_usb_host_hs_slaves), + .masters = omap44xx_usb_host_hs_masters, + .masters_cnt = ARRAY_SIZE(omap44xx_usb_host_hs_masters), + + /* + * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock + * id: i660 + * + * Description: + * In the following configuration : + * - USBHOST module is set to smart-idle mode + * - PRCM asserts idle_req to the USBHOST module ( This typically + * happens when the system is going to a low power mode : all ports + * have been suspended, the master part of the USBHOST module has + * entered the standby state, and SW has cut the functional clocks) + * - an USBHOST interrupt occurs before the module is able to answer + * idle_ack, typically a remote wakeup IRQ. + * Then the USB HOST module will enter a deadlock situation where it + * is no more accessible nor functional. + * + * Workaround: + * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE + */ + + /* + * Errata: USB host EHCI may stall when entering smart-standby mode + * Id: i571 + * + * Description: + * When the USBHOST module is set to smart-standby mode, and when it is + * ready to enter the standby state (i.e. all ports are suspended and + * all attached devices are in suspend mode), then it can wrongly assert + * the Mstandby signal too early while there are still some residual OCP + * transactions ongoing. If this condition occurs, the internal state + * machine may go to an undefined state and the USB link may be stuck + * upon the next resume. + * + * Workaround: + * Don't use smart standby; use only force standby, + * hence HWMOD_SWSUP_MSTANDBY + */ + + /* + * During system boot; If the hwmod framework resets the module + * the module will have smart idle settings; which can lead to deadlock + * (above Errata Id:i660); so, dont reset the module during boot; + * Use HWMOD_INIT_NO_RESET. + */ + + .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY | + HWMOD_INIT_NO_RESET, +}; + +/* + * 'usb_tll_hs' class + * usb_tll_hs module is the adapter on the usb_host_hs ports + */ +static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | + SYSC_HAS_AUTOIDLE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = { + .name = "usb_tll_hs", + .sysc = &omap44xx_usb_tll_hs_sysc, +}; + +static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs[] = { + { .name = "tll-irq", .irq = 78 + OMAP44XX_IRQ_GIC_START }, + { .irq = -1 } +}; + +static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs[] = { + { + .name = "tll", + .pa_start = 0x4a062000, + .pa_end = 0x4a063fff, + .flags = ADDR_TYPE_RT + }, + {} +}; + +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_usb_tll_hs_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_usb_tll_hs_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_ocp_if *omap44xx_usb_tll_hs_slaves[] = { + &omap44xx_l4_cfg__usb_tll_hs, +}; + +static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = { + .name = "usb_tll_hs", + .class = &omap44xx_usb_tll_hs_hwmod_class, + .clkdm_name = "l3_init_clkdm", + .main_clk = "usb_tll_hs_ick", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET, + .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, + .mpu_irqs = omap44xx_usb_tll_hs_irqs, + .slaves = omap44xx_usb_tll_hs_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_usb_tll_hs_slaves), +}; + static __initdata struct omap_hwmod *omap44xx_hwmods[] = { /* dmm class */ @@ -5415,13 +5619,16 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = { &omap44xx_uart3_hwmod, &omap44xx_uart4_hwmod, + /* usb host class */ + &omap44xx_usb_host_hs_hwmod, + &omap44xx_usb_tll_hs_hwmod, + /* usb_otg_hs class */ &omap44xx_usb_otg_hs_hwmod, /* wd_timer class */ &omap44xx_wd_timer2_hwmod, &omap44xx_wd_timer3_hwmod, - NULL, }; diff --git a/arch/arm/mach-omap2/omap_phy_internal.c b/arch/arm/mach-omap2/omap_phy_internal.c index 58775e3c847..4c90477e6f8 100644 --- a/arch/arm/mach-omap2/omap_phy_internal.c +++ b/arch/arm/mach-omap2/omap_phy_internal.c @@ -260,3 +260,38 @@ void am35x_set_mode(u8 musb_mode) omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2); } + +void ti81xx_musb_phy_power(u8 on) +{ + void __iomem *scm_base = NULL; + u32 usbphycfg; + + scm_base = ioremap(TI81XX_SCM_BASE, SZ_2K); + if (!scm_base) { + pr_err("system control module ioremap failed\n"); + return; + } + + usbphycfg = __raw_readl(scm_base + USBCTRL0); + + if (on) { + if (cpu_is_ti816x()) { + usbphycfg |= TI816X_USBPHY0_NORMAL_MODE; + usbphycfg &= ~TI816X_USBPHY_REFCLK_OSC; + } else if (cpu_is_ti814x()) { + usbphycfg &= ~(USBPHY_CM_PWRDN | USBPHY_OTG_PWRDN + | USBPHY_DPINPUT | USBPHY_DMINPUT); + usbphycfg |= (USBPHY_OTGVDET_EN | USBPHY_OTGSESSEND_EN + | USBPHY_DPOPBUFCTL | USBPHY_DMOPBUFCTL); + } + } else { + if (cpu_is_ti816x()) + usbphycfg &= ~TI816X_USBPHY0_NORMAL_MODE; + else if (cpu_is_ti814x()) + usbphycfg |= USBPHY_CM_PWRDN | USBPHY_OTG_PWRDN; + + } + __raw_writel(usbphycfg, scm_base + USBCTRL0); + + iounmap(scm_base); +} diff --git a/arch/arm/mach-omap2/opp2xxx.h b/arch/arm/mach-omap2/opp2xxx.h index 8affc66a92c..8fae534eb15 100644 --- a/arch/arm/mach-omap2/opp2xxx.h +++ b/arch/arm/mach-omap2/opp2xxx.h @@ -51,7 +51,7 @@ struct prcm_config { unsigned long cm_clksel2_pll; /* dpllx1 or x2 out */ unsigned long cm_clksel_mdm; /* modem dividers 2430 only */ unsigned long base_sdrc_rfr; /* base refresh timing for a set */ - unsigned char flags; + unsigned short flags; }; diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h index 4e166add2f3..b737b11e449 100644 --- a/arch/arm/mach-omap2/pm.h +++ b/arch/arm/mach-omap2/pm.h @@ -21,6 +21,7 @@ extern void omap_sram_idle(void); extern int omap3_can_sleep(void); extern int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state); extern int omap3_idle_init(void); +extern int omap4_idle_init(void); #if defined(CONFIG_PM_OPP) extern int omap3_opp_init(void); diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c index ef8595c8029..b8822f8b289 100644 --- a/arch/arm/mach-omap2/pm24xx.c +++ b/arch/arm/mach-omap2/pm24xx.c @@ -30,7 +30,6 @@ #include <linux/irq.h> #include <linux/time.h> #include <linux/gpio.h> -#include <linux/console.h> #include <asm/mach/time.h> #include <asm/mach/irq.h> @@ -127,27 +126,11 @@ static void omap2_enter_full_retention(void) if (omap_irq_pending()) goto no_sleep; - /* Block console output in case it is on one of the OMAP UARTs */ - if (!is_suspending()) - if (!console_trylock()) - goto no_sleep; - - omap_uart_prepare_idle(0); - omap_uart_prepare_idle(1); - omap_uart_prepare_idle(2); - /* Jump to SRAM suspend code */ omap2_sram_suspend(sdrc_read_reg(SDRC_DLLA_CTRL), OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL), OMAP_SDRC_REGADDR(SDRC_POWER)); - omap_uart_resume_idle(2); - omap_uart_resume_idle(1); - omap_uart_resume_idle(0); - - if (!is_suspending()) - console_unlock(); - no_sleep: omap2_gpio_resume_after_idle(); @@ -239,8 +222,6 @@ static int omap2_can_sleep(void) { if (omap2_fclks_active()) return 0; - if (!omap_uart_can_sleep()) - return 0; if (osc_ck->usecount > 1) return 0; if (omap_dma_running()) @@ -291,7 +272,6 @@ static int omap2_pm_suspend(void) mir1 = omap_readl(0x480fe0a4); omap_writel(1 << 5, 0x480fe0ac); - omap_uart_prepare_suspend(); omap2_enter_full_retention(); omap_writel(mir1, 0x480fe0a4); diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index fa637dfdda5..fc698757892 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c @@ -28,7 +28,6 @@ #include <linux/clk.h> #include <linux/delay.h> #include <linux/slab.h> -#include <linux/console.h> #include <trace/events/power.h> #include <asm/suspend.h> @@ -36,7 +35,6 @@ #include <plat/sram.h> #include "clockdomain.h" #include "powerdomain.h" -#include <plat/serial.h> #include <plat/sdrc.h> #include <plat/prcm.h> #include <plat/gpmc.h> @@ -54,15 +52,6 @@ #ifdef CONFIG_SUSPEND static suspend_state_t suspend_state = PM_SUSPEND_ON; -static inline bool is_suspending(void) -{ - return (suspend_state != PM_SUSPEND_ON) && console_suspend_enabled; -} -#else -static inline bool is_suspending(void) -{ - return false; -} #endif /* pm34xx errata defined in pm.h */ @@ -195,7 +184,7 @@ static void omap3_save_secure_ram_context(void) * that any peripheral wake-up events occurring while attempting to * clear the PM_WKST_x are detected and cleared. */ -static int prcm_clear_mod_irqs(s16 module, u8 regs) +static int prcm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits) { u32 wkst, fclk, iclk, clken; u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1; @@ -207,6 +196,7 @@ static int prcm_clear_mod_irqs(s16 module, u8 regs) wkst = omap2_prm_read_mod_reg(module, wkst_off); wkst &= omap2_prm_read_mod_reg(module, grpsel_off); + wkst &= ~ignore_bits; if (wkst) { iclk = omap2_cm_read_mod_reg(module, iclk_off); fclk = omap2_cm_read_mod_reg(module, fclk_off); @@ -222,6 +212,7 @@ static int prcm_clear_mod_irqs(s16 module, u8 regs) omap2_cm_set_mod_reg_bits(clken, module, fclk_off); omap2_prm_write_mod_reg(wkst, module, wkst_off); wkst = omap2_prm_read_mod_reg(module, wkst_off); + wkst &= ~ignore_bits; c++; } omap2_cm_write_mod_reg(iclk, module, iclk_off); @@ -231,76 +222,35 @@ static int prcm_clear_mod_irqs(s16 module, u8 regs) return c; } -static int _prcm_int_handle_wakeup(void) +static irqreturn_t _prcm_int_handle_io(int irq, void *unused) { int c; - c = prcm_clear_mod_irqs(WKUP_MOD, 1); - c += prcm_clear_mod_irqs(CORE_MOD, 1); - c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1); - if (omap_rev() > OMAP3430_REV_ES1_0) { - c += prcm_clear_mod_irqs(CORE_MOD, 3); - c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1); - } + c = prcm_clear_mod_irqs(WKUP_MOD, 1, + ~(OMAP3430_ST_IO_MASK | OMAP3430_ST_IO_CHAIN_MASK)); - return c; + return c ? IRQ_HANDLED : IRQ_NONE; } -/* - * PRCM Interrupt Handler - * - * The PRM_IRQSTATUS_MPU register indicates if there are any pending - * interrupts from the PRCM for the MPU. These bits must be cleared in - * order to clear the PRCM interrupt. The PRCM interrupt handler is - * implemented to simply clear the PRM_IRQSTATUS_MPU in order to clear - * the PRCM interrupt. Please note that bit 0 of the PRM_IRQSTATUS_MPU - * register indicates that a wake-up event is pending for the MPU and - * this bit can only be cleared if the all the wake-up events latched - * in the various PM_WKST_x registers have been cleared. The interrupt - * handler is implemented using a do-while loop so that if a wake-up - * event occurred during the processing of the prcm interrupt handler - * (setting a bit in the corresponding PM_WKST_x register and thus - * preventing us from clearing bit 0 of the PRM_IRQSTATUS_MPU register) - * this would be handled. - */ -static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id) +static irqreturn_t _prcm_int_handle_wakeup(int irq, void *unused) { - u32 irqenable_mpu, irqstatus_mpu; - int c = 0; - - irqenable_mpu = omap2_prm_read_mod_reg(OCP_MOD, - OMAP3_PRM_IRQENABLE_MPU_OFFSET); - irqstatus_mpu = omap2_prm_read_mod_reg(OCP_MOD, - OMAP3_PRM_IRQSTATUS_MPU_OFFSET); - irqstatus_mpu &= irqenable_mpu; - - do { - if (irqstatus_mpu & (OMAP3430_WKUP_ST_MASK | - OMAP3430_IO_ST_MASK)) { - c = _prcm_int_handle_wakeup(); - - /* - * Is the MPU PRCM interrupt handler racing with the - * IVA2 PRCM interrupt handler ? - */ - WARN(c == 0, "prcm: WARNING: PRCM indicated MPU wakeup " - "but no wakeup sources are marked\n"); - } else { - /* XXX we need to expand our PRCM interrupt handler */ - WARN(1, "prcm: WARNING: PRCM interrupt received, but " - "no code to handle it (%08x)\n", irqstatus_mpu); - } - - omap2_prm_write_mod_reg(irqstatus_mpu, OCP_MOD, - OMAP3_PRM_IRQSTATUS_MPU_OFFSET); - - irqstatus_mpu = omap2_prm_read_mod_reg(OCP_MOD, - OMAP3_PRM_IRQSTATUS_MPU_OFFSET); - irqstatus_mpu &= irqenable_mpu; + int c; - } while (irqstatus_mpu); + /* + * Clear all except ST_IO and ST_IO_CHAIN for wkup module, + * these are handled in a separate handler to avoid acking + * IO events before parsing in mux code + */ + c = prcm_clear_mod_irqs(WKUP_MOD, 1, + OMAP3430_ST_IO_MASK | OMAP3430_ST_IO_CHAIN_MASK); + c += prcm_clear_mod_irqs(CORE_MOD, 1, 0); + c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1, 0); + if (omap_rev() > OMAP3430_REV_ES1_0) { + c += prcm_clear_mod_irqs(CORE_MOD, 3, 0); + c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1, 0); + } - return IRQ_HANDLED; + return c ? IRQ_HANDLED : IRQ_NONE; } static void omap34xx_save_context(u32 *save) @@ -376,20 +326,11 @@ void omap_sram_idle(void) omap3_enable_io_chain(); } - /* Block console output in case it is on one of the OMAP UARTs */ - if (!is_suspending()) - if (per_next_state < PWRDM_POWER_ON || - core_next_state < PWRDM_POWER_ON) - if (!console_trylock()) - goto console_still_active; - pwrdm_pre_transition(); /* PER */ if (per_next_state < PWRDM_POWER_ON) { per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0; - omap_uart_prepare_idle(2); - omap_uart_prepare_idle(3); omap2_gpio_prepare_for_idle(per_going_off); if (per_next_state == PWRDM_POWER_OFF) omap3_per_save_context(); @@ -397,8 +338,6 @@ void omap_sram_idle(void) /* CORE */ if (core_next_state < PWRDM_POWER_ON) { - omap_uart_prepare_idle(0); - omap_uart_prepare_idle(1); if (core_next_state == PWRDM_POWER_OFF) { omap3_core_save_context(); omap3_cm_save_context(); @@ -447,8 +386,6 @@ void omap_sram_idle(void) omap3_sram_restore_context(); omap2_sms_restore_context(); } - omap_uart_resume_idle(0); - omap_uart_resume_idle(1); if (core_next_state == PWRDM_POWER_OFF) omap2_prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK, OMAP3430_GR_MOD, @@ -464,14 +401,8 @@ void omap_sram_idle(void) omap2_gpio_resume_after_idle(); if (per_prev_state == PWRDM_POWER_OFF) omap3_per_restore_context(); - omap_uart_resume_idle(2); - omap_uart_resume_idle(3); } - if (!is_suspending()) - console_unlock(); - -console_still_active: /* Disable IO-PAD and IO-CHAIN wakeup */ if (omap3_has_io_wakeup() && (per_next_state < PWRDM_POWER_ON || @@ -485,21 +416,11 @@ console_still_active: clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]); } -int omap3_can_sleep(void) -{ - if (!omap_uart_can_sleep()) - return 0; - return 1; -} - static void omap3_pm_idle(void) { local_irq_disable(); local_fiq_disable(); - if (!omap3_can_sleep()) - goto out; - if (omap_irq_pending() || need_resched()) goto out; @@ -533,7 +454,6 @@ static int omap3_pm_suspend(void) goto restore; } - omap_uart_prepare_suspend(); omap3_intc_suspend(); omap_sram_idle(); @@ -580,22 +500,27 @@ static int omap3_pm_begin(suspend_state_t state) { disable_hlt(); suspend_state = state; - omap_uart_enable_irqs(0); + omap_prcm_irq_prepare(); return 0; } static void omap3_pm_end(void) { suspend_state = PM_SUSPEND_ON; - omap_uart_enable_irqs(1); enable_hlt(); return; } +static void omap3_pm_finish(void) +{ + omap_prcm_irq_complete(); +} + static const struct platform_suspend_ops omap_pm_ops = { .begin = omap3_pm_begin, .end = omap3_pm_end, .enter = omap3_pm_enter, + .finish = omap3_pm_finish, .valid = suspend_valid_only_mem, }; #endif /* CONFIG_SUSPEND */ @@ -701,10 +626,6 @@ static void __init prcm_setup_regs(void) OMAP3430_GRPSEL_GPT1_MASK | OMAP3430_GRPSEL_GPT12_MASK, WKUP_MOD, OMAP3430_PM_MPUGRPSEL); - /* For some reason IO doesn't generate wakeup event even if - * it is selected to mpu wakeup goup */ - omap2_prm_write_mod_reg(OMAP3430_IO_EN_MASK | OMAP3430_WKUP_EN_MASK, - OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET); /* Enable PM_WKEN to support DSS LPR */ omap2_prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK, @@ -881,12 +802,21 @@ static int __init omap3_pm_init(void) * supervised mode for powerdomains */ prcm_setup_regs(); - ret = request_irq(INT_34XX_PRCM_MPU_IRQ, - (irq_handler_t)prcm_interrupt_handler, - IRQF_DISABLED, "prcm", NULL); + ret = request_irq(omap_prcm_event_to_irq("wkup"), + _prcm_int_handle_wakeup, IRQF_NO_SUSPEND, "pm_wkup", NULL); + + if (ret) { + pr_err("pm: Failed to request pm_wkup irq\n"); + goto err1; + } + + /* IO interrupt is shared with mux code */ + ret = request_irq(omap_prcm_event_to_irq("io"), + _prcm_int_handle_io, IRQF_SHARED | IRQF_NO_SUSPEND, "pm_io", + omap3_pm_init); + if (ret) { - printk(KERN_ERR "request_irq failed to register for 0x%x\n", - INT_34XX_PRCM_MPU_IRQ); + pr_err("pm: Failed to request pm_io irq\n"); goto err1; } diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c index 8edb015f561..c264ef7219c 100644 --- a/arch/arm/mach-omap2/pm44xx.c +++ b/arch/arm/mach-omap2/pm44xx.c @@ -1,8 +1,9 @@ /* * OMAP4 Power Management Routines * - * Copyright (C) 2010 Texas Instruments, Inc. + * Copyright (C) 2010-2011 Texas Instruments, Inc. * Rajendra Nayak <rnayak@ti.com> + * Santosh Shilimkar <santosh.shilimkar@ti.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -17,13 +18,16 @@ #include <linux/slab.h> #include "common.h" +#include "clockdomain.h" #include "powerdomain.h" +#include "pm.h" struct power_state { struct powerdomain *pwrdm; u32 next_state; #ifdef CONFIG_SUSPEND u32 saved_state; + u32 saved_logic_state; #endif struct list_head node; }; @@ -33,7 +37,50 @@ static LIST_HEAD(pwrst_list); #ifdef CONFIG_SUSPEND static int omap4_pm_suspend(void) { - do_wfi(); + struct power_state *pwrst; + int state, ret = 0; + u32 cpu_id = smp_processor_id(); + + /* Save current powerdomain state */ + list_for_each_entry(pwrst, &pwrst_list, node) { + pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm); + pwrst->saved_logic_state = pwrdm_read_logic_retst(pwrst->pwrdm); + } + + /* Set targeted power domain states by suspend */ + list_for_each_entry(pwrst, &pwrst_list, node) { + omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); + pwrdm_set_logic_retst(pwrst->pwrdm, PWRDM_POWER_OFF); + } + + /* + * For MPUSS to hit power domain retention(CSWR or OSWR), + * CPU0 and CPU1 power domains need to be in OFF or DORMANT state, + * since CPU power domain CSWR is not supported by hardware + * Only master CPU follows suspend path. All other CPUs follow + * CPU hotplug path in system wide suspend. On OMAP4, CPU power + * domain CSWR is not supported by hardware. + * More details can be found in OMAP4430 TRM section 4.3.4.2. + */ + omap4_enter_lowpower(cpu_id, PWRDM_POWER_OFF); + + /* Restore next powerdomain state */ + list_for_each_entry(pwrst, &pwrst_list, node) { + state = pwrdm_read_prev_pwrst(pwrst->pwrdm); + if (state > pwrst->next_state) { + pr_info("Powerdomain (%s) didn't enter " + "target state %d\n", + pwrst->pwrdm->name, pwrst->next_state); + ret = -1; + } + omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state); + pwrdm_set_logic_retst(pwrst->pwrdm, pwrst->saved_logic_state); + } + if (ret) + pr_crit("Could not enter target state in pm_suspend\n"); + else + pr_info("Successfully put all powerdomains to target state\n"); + return 0; } @@ -73,6 +120,22 @@ static const struct platform_suspend_ops omap_pm_ops = { }; #endif /* CONFIG_SUSPEND */ +/* + * Enable hardware supervised mode for all clockdomains if it's + * supported. Initiate sleep transition for other clockdomains, if + * they are not used + */ +static int __init clkdms_setup(struct clockdomain *clkdm, void *unused) +{ + if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO) + clkdm_allow_idle(clkdm); + else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP && + atomic_read(&clkdm->usecount) == 0) + clkdm_sleep(clkdm); + return 0; +} + + static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused) { struct power_state *pwrst; @@ -80,14 +143,48 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused) if (!pwrdm->pwrsts) return 0; + /* + * Skip CPU0 and CPU1 power domains. CPU1 is programmed + * through hotplug path and CPU0 explicitly programmed + * further down in the code path + */ + if (!strncmp(pwrdm->name, "cpu", 3)) + return 0; + + /* + * FIXME: Remove this check when core retention is supported + * Only MPUSS power domain is added in the list. + */ + if (strcmp(pwrdm->name, "mpu_pwrdm")) + return 0; + pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC); if (!pwrst) return -ENOMEM; + pwrst->pwrdm = pwrdm; - pwrst->next_state = PWRDM_POWER_ON; + pwrst->next_state = PWRDM_POWER_RET; list_add(&pwrst->node, &pwrst_list); - return pwrdm_set_next_pwrst(pwrst->pwrdm, pwrst->next_state); + return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); +} + +/** + * omap_default_idle - OMAP4 default ilde routine.' + * + * Implements OMAP4 memory, IO ordering requirements which can't be addressed + * with default arch_idle() hook. Used by all CPUs with !CONFIG_CPUIDLE and + * by secondary CPU with CONFIG_CPUIDLE. + */ +static void omap_default_idle(void) +{ + local_irq_disable(); + local_fiq_disable(); + + omap_do_wfi(); + + local_fiq_enable(); + local_irq_enable(); } /** @@ -99,10 +196,17 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused) static int __init omap4_pm_init(void) { int ret; + struct clockdomain *emif_clkdm, *mpuss_clkdm, *l3_1_clkdm; + struct clockdomain *ducati_clkdm, *l3_2_clkdm, *l4_per_clkdm; if (!cpu_is_omap44xx()) return -ENODEV; + if (omap_rev() == OMAP4430_REV_ES1_0) { + WARN(1, "Power Management not supported on OMAP4430 ES1.0\n"); + return -ENODEV; + } + pr_err("Power Management for TI OMAP4.\n"); ret = pwrdm_for_each(pwrdms_setup, NULL); @@ -111,10 +215,51 @@ static int __init omap4_pm_init(void) goto err2; } + /* + * The dynamic dependency between MPUSS -> MEMIF and + * MPUSS -> L4_PER/L3_* and DUCATI -> L3_* doesn't work as + * expected. The hardware recommendation is to enable static + * dependencies for these to avoid system lock ups or random crashes. + */ + mpuss_clkdm = clkdm_lookup("mpuss_clkdm"); + emif_clkdm = clkdm_lookup("l3_emif_clkdm"); + l3_1_clkdm = clkdm_lookup("l3_1_clkdm"); + l3_2_clkdm = clkdm_lookup("l3_2_clkdm"); + l4_per_clkdm = clkdm_lookup("l4_per_clkdm"); + ducati_clkdm = clkdm_lookup("ducati_clkdm"); + if ((!mpuss_clkdm) || (!emif_clkdm) || (!l3_1_clkdm) || + (!l3_2_clkdm) || (!ducati_clkdm) || (!l4_per_clkdm)) + goto err2; + + ret = clkdm_add_wkdep(mpuss_clkdm, emif_clkdm); + ret |= clkdm_add_wkdep(mpuss_clkdm, l3_1_clkdm); + ret |= clkdm_add_wkdep(mpuss_clkdm, l3_2_clkdm); + ret |= clkdm_add_wkdep(mpuss_clkdm, l4_per_clkdm); + ret |= clkdm_add_wkdep(ducati_clkdm, l3_1_clkdm); + ret |= clkdm_add_wkdep(ducati_clkdm, l3_2_clkdm); + if (ret) { + pr_err("Failed to add MPUSS -> L3/EMIF/L4PER, DUCATI -> L3 " + "wakeup dependency\n"); + goto err2; + } + + ret = omap4_mpuss_init(); + if (ret) { + pr_err("Failed to initialise OMAP4 MPUSS\n"); + goto err2; + } + + (void) clkdm_for_each(clkdms_setup, NULL); + #ifdef CONFIG_SUSPEND suspend_set_ops(&omap_pm_ops); #endif /* CONFIG_SUSPEND */ + /* Overwrite the default arch_idle() */ + pm_idle = omap_default_idle; + + omap4_idle_init(); + err2: return ret; } diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h index 0363dcb0ef9..5aa5435e3ff 100644 --- a/arch/arm/mach-omap2/prcm-common.h +++ b/arch/arm/mach-omap2/prcm-common.h @@ -4,7 +4,7 @@ /* * OMAP2/3 PRCM base and module definitions * - * Copyright (C) 2007-2009 Texas Instruments, Inc. + * Copyright (C) 2007-2009, 2011 Texas Instruments, Inc. * Copyright (C) 2007-2009 Nokia Corporation * * Written by Paul Walmsley @@ -201,6 +201,8 @@ #define OMAP3430_EN_MMC2_SHIFT 25 #define OMAP3430_EN_MMC1_MASK (1 << 24) #define OMAP3430_EN_MMC1_SHIFT 24 +#define OMAP3430_EN_UART4_MASK (1 << 23) +#define OMAP3430_EN_UART4_SHIFT 23 #define OMAP3430_EN_MCSPI4_MASK (1 << 21) #define OMAP3430_EN_MCSPI4_SHIFT 21 #define OMAP3430_EN_MCSPI3_MASK (1 << 20) @@ -408,6 +410,79 @@ extern void __iomem *prm_base; extern void __iomem *cm_base; extern void __iomem *cm2_base; + +/** + * struct omap_prcm_irq - describes a PRCM interrupt bit + * @name: a short name describing the interrupt type, e.g. "wkup" or "io" + * @offset: the bit shift of the interrupt inside the IRQ{ENABLE,STATUS} regs + * @priority: should this interrupt be handled before @priority=false IRQs? + * + * Describes interrupt bits inside the PRM_IRQ{ENABLE,STATUS}_MPU* registers. + * On systems with multiple PRM MPU IRQ registers, the bitfields read from + * the registers are concatenated, so @offset could be > 31 on these systems - + * see omap_prm_irq_handler() for more details. I/O ring interrupts should + * have @priority set to true. + */ +struct omap_prcm_irq { + const char *name; + unsigned int offset; + bool priority; +}; + +/** + * struct omap_prcm_irq_setup - PRCM interrupt controller details + * @ack: PRM register offset for the first PRM_IRQSTATUS_MPU register + * @mask: PRM register offset for the first PRM_IRQENABLE_MPU register + * @nr_regs: number of PRM_IRQ{STATUS,ENABLE}_MPU* registers + * @nr_irqs: number of entries in the @irqs array + * @irqs: ptr to an array of PRCM interrupt bits (see @nr_irqs) + * @irq: MPU IRQ asserted when a PRCM interrupt arrives + * @read_pending_irqs: fn ptr to determine if any PRCM IRQs are pending + * @ocp_barrier: fn ptr to force buffered PRM writes to complete + * @save_and_clear_irqen: fn ptr to save and clear IRQENABLE regs + * @restore_irqen: fn ptr to save and clear IRQENABLE regs + * @saved_mask: IRQENABLE regs are saved here during suspend + * @priority_mask: 1 bit per IRQ, set to 1 if omap_prcm_irq.priority = true + * @base_irq: base dynamic IRQ number, returned from irq_alloc_descs() in init + * @suspended: set to true after Linux suspend code has called our ->prepare() + * @suspend_save_flag: set to true after IRQ masks have been saved and disabled + * + * @saved_mask, @priority_mask, @base_irq, @suspended, and + * @suspend_save_flag are populated dynamically, and are not to be + * specified in static initializers. + */ +struct omap_prcm_irq_setup { + u16 ack; + u16 mask; + u8 nr_regs; + u8 nr_irqs; + const struct omap_prcm_irq *irqs; + int irq; + void (*read_pending_irqs)(unsigned long *events); + void (*ocp_barrier)(void); + void (*save_and_clear_irqen)(u32 *saved_mask); + void (*restore_irqen)(u32 *saved_mask); + u32 *saved_mask; + u32 *priority_mask; + int base_irq; + bool suspended; + bool suspend_save_flag; +}; + +/* OMAP_PRCM_IRQ: convenience macro for creating struct omap_prcm_irq records */ +#define OMAP_PRCM_IRQ(_name, _offset, _priority) { \ + .name = _name, \ + .offset = _offset, \ + .priority = _priority \ + } + +extern void omap_prcm_irq_cleanup(void); +extern int omap_prcm_register_chain_handler( + struct omap_prcm_irq_setup *irq_setup); +extern int omap_prcm_event_to_irq(const char *event); +extern void omap_prcm_irq_prepare(void); +extern void omap_prcm_irq_complete(void); + # endif #endif diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.c b/arch/arm/mach-omap2/prm2xxx_3xxx.c index 9a08ba39732..c1c4d86a79a 100644 --- a/arch/arm/mach-omap2/prm2xxx_3xxx.c +++ b/arch/arm/mach-omap2/prm2xxx_3xxx.c @@ -1,7 +1,7 @@ /* * OMAP2/3 PRM module functions * - * Copyright (C) 2010 Texas Instruments, Inc. + * Copyright (C) 2010-2011 Texas Instruments, Inc. * Copyright (C) 2010 Nokia Corporation * Benoît Cousson * Paul Walmsley @@ -27,6 +27,24 @@ #include "prm-regbits-24xx.h" #include "prm-regbits-34xx.h" +static const struct omap_prcm_irq omap3_prcm_irqs[] = { + OMAP_PRCM_IRQ("wkup", 0, 0), + OMAP_PRCM_IRQ("io", 9, 1), +}; + +static struct omap_prcm_irq_setup omap3_prcm_irq_setup = { + .ack = OMAP3_PRM_IRQSTATUS_MPU_OFFSET, + .mask = OMAP3_PRM_IRQENABLE_MPU_OFFSET, + .nr_regs = 1, + .irqs = omap3_prcm_irqs, + .nr_irqs = ARRAY_SIZE(omap3_prcm_irqs), + .irq = INT_34XX_PRCM_MPU_IRQ, + .read_pending_irqs = &omap3xxx_prm_read_pending_irqs, + .ocp_barrier = &omap3xxx_prm_ocp_barrier, + .save_and_clear_irqen = &omap3xxx_prm_save_and_clear_irqen, + .restore_irqen = &omap3xxx_prm_restore_irqen, +}; + u32 omap2_prm_read_mod_reg(s16 module, u16 idx) { return __raw_readl(prm_base + module + idx); @@ -212,3 +230,80 @@ u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset) { return omap2_prm_rmw_mod_reg_bits(mask, bits, OMAP3430_GR_MOD, offset); } + +/** + * omap3xxx_prm_read_pending_irqs - read pending PRM MPU IRQs into @events + * @events: ptr to a u32, preallocated by caller + * + * Read PRM_IRQSTATUS_MPU bits, AND'ed with the currently-enabled PRM + * MPU IRQs, and store the result into the u32 pointed to by @events. + * No return value. + */ +void omap3xxx_prm_read_pending_irqs(unsigned long *events) +{ + u32 mask, st; + + /* XXX Can the mask read be avoided (e.g., can it come from RAM?) */ + mask = omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET); + st = omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); + + events[0] = mask & st; +} + +/** + * omap3xxx_prm_ocp_barrier - force buffered MPU writes to the PRM to complete + * + * Force any buffered writes to the PRM IP block to complete. Needed + * by the PRM IRQ handler, which reads and writes directly to the IP + * block, to avoid race conditions after acknowledging or clearing IRQ + * bits. No return value. + */ +void omap3xxx_prm_ocp_barrier(void) +{ + omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_REVISION_OFFSET); +} + +/** + * omap3xxx_prm_save_and_clear_irqen - save/clear PRM_IRQENABLE_MPU reg + * @saved_mask: ptr to a u32 array to save IRQENABLE bits + * + * Save the PRM_IRQENABLE_MPU register to @saved_mask. @saved_mask + * must be allocated by the caller. Intended to be used in the PRM + * interrupt handler suspend callback. The OCP barrier is needed to + * ensure the write to disable PRM interrupts reaches the PRM before + * returning; otherwise, spurious interrupts might occur. No return + * value. + */ +void omap3xxx_prm_save_and_clear_irqen(u32 *saved_mask) +{ + saved_mask[0] = omap2_prm_read_mod_reg(OCP_MOD, + OMAP3_PRM_IRQENABLE_MPU_OFFSET); + omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET); + + /* OCP barrier */ + omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_REVISION_OFFSET); +} + +/** + * omap3xxx_prm_restore_irqen - set PRM_IRQENABLE_MPU register from args + * @saved_mask: ptr to a u32 array of IRQENABLE bits saved previously + * + * Restore the PRM_IRQENABLE_MPU register from @saved_mask. Intended + * to be used in the PRM interrupt handler resume callback to restore + * values saved by omap3xxx_prm_save_and_clear_irqen(). No OCP + * barrier should be needed here; any pending PRM interrupts will fire + * once the writes reach the PRM. No return value. + */ +void omap3xxx_prm_restore_irqen(u32 *saved_mask) +{ + omap2_prm_write_mod_reg(saved_mask[0], OCP_MOD, + OMAP3_PRM_IRQENABLE_MPU_OFFSET); +} + +static int __init omap3xxx_prcm_init(void) +{ + if (cpu_is_omap34xx()) + return omap_prcm_register_chain_handler(&omap3_prcm_irq_setup); + return 0; +} +subsys_initcall(omap3xxx_prcm_init); diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.h b/arch/arm/mach-omap2/prm2xxx_3xxx.h index cef533df086..70ac2a19dc5 100644 --- a/arch/arm/mach-omap2/prm2xxx_3xxx.h +++ b/arch/arm/mach-omap2/prm2xxx_3xxx.h @@ -1,7 +1,7 @@ /* * OMAP2/3 Power/Reset Management (PRM) register definitions * - * Copyright (C) 2007-2009 Texas Instruments, Inc. + * Copyright (C) 2007-2009, 2011 Texas Instruments, Inc. * Copyright (C) 2008-2010 Nokia Corporation * Paul Walmsley * @@ -314,6 +314,13 @@ void omap3_prm_vp_clear_txdone(u8 vp_id); extern u32 omap3_prm_vcvp_read(u8 offset); extern void omap3_prm_vcvp_write(u32 val, u8 offset); extern u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset); + +/* PRM interrupt-related functions */ +extern void omap3xxx_prm_read_pending_irqs(unsigned long *events); +extern void omap3xxx_prm_ocp_barrier(void); +extern void omap3xxx_prm_save_and_clear_irqen(u32 *saved_mask); +extern void omap3xxx_prm_restore_irqen(u32 *saved_mask); + #endif /* CONFIG_ARCH_OMAP4 */ #endif diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c index dd885eecf22..33dd655e6aa 100644 --- a/arch/arm/mach-omap2/prm44xx.c +++ b/arch/arm/mach-omap2/prm44xx.c @@ -27,6 +27,24 @@ #include "prcm44xx.h" #include "prminst44xx.h" +static const struct omap_prcm_irq omap4_prcm_irqs[] = { + OMAP_PRCM_IRQ("wkup", 0, 0), + OMAP_PRCM_IRQ("io", 9, 1), +}; + +static struct omap_prcm_irq_setup omap4_prcm_irq_setup = { + .ack = OMAP4_PRM_IRQSTATUS_MPU_OFFSET, + .mask = OMAP4_PRM_IRQENABLE_MPU_OFFSET, + .nr_regs = 2, + .irqs = omap4_prcm_irqs, + .nr_irqs = ARRAY_SIZE(omap4_prcm_irqs), + .irq = OMAP44XX_IRQ_PRCM, + .read_pending_irqs = &omap44xx_prm_read_pending_irqs, + .ocp_barrier = &omap44xx_prm_ocp_barrier, + .save_and_clear_irqen = &omap44xx_prm_save_and_clear_irqen, + .restore_irqen = &omap44xx_prm_restore_irqen, +}; + /* PRM low-level functions */ /* Read a register in a CM/PRM instance in the PRM module */ @@ -121,3 +139,101 @@ u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset) OMAP4430_PRM_DEVICE_INST, offset); } + +static inline u32 _read_pending_irq_reg(u16 irqen_offs, u16 irqst_offs) +{ + u32 mask, st; + + /* XXX read mask from RAM? */ + mask = omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST, irqen_offs); + st = omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST, irqst_offs); + + return mask & st; +} + +/** + * omap44xx_prm_read_pending_irqs - read pending PRM MPU IRQs into @events + * @events: ptr to two consecutive u32s, preallocated by caller + * + * Read PRM_IRQSTATUS_MPU* bits, AND'ed with the currently-enabled PRM + * MPU IRQs, and store the result into the two u32s pointed to by @events. + * No return value. + */ +void omap44xx_prm_read_pending_irqs(unsigned long *events) +{ + events[0] = _read_pending_irq_reg(OMAP4_PRM_IRQENABLE_MPU_OFFSET, + OMAP4_PRM_IRQSTATUS_MPU_OFFSET); + + events[1] = _read_pending_irq_reg(OMAP4_PRM_IRQENABLE_MPU_2_OFFSET, + OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET); +} + +/** + * omap44xx_prm_ocp_barrier - force buffered MPU writes to the PRM to complete + * + * Force any buffered writes to the PRM IP block to complete. Needed + * by the PRM IRQ handler, which reads and writes directly to the IP + * block, to avoid race conditions after acknowledging or clearing IRQ + * bits. No return value. + */ +void omap44xx_prm_ocp_barrier(void) +{ + omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST, + OMAP4_REVISION_PRM_OFFSET); +} + +/** + * omap44xx_prm_save_and_clear_irqen - save/clear PRM_IRQENABLE_MPU* regs + * @saved_mask: ptr to a u32 array to save IRQENABLE bits + * + * Save the PRM_IRQENABLE_MPU and PRM_IRQENABLE_MPU_2 registers to + * @saved_mask. @saved_mask must be allocated by the caller. + * Intended to be used in the PRM interrupt handler suspend callback. + * The OCP barrier is needed to ensure the write to disable PRM + * interrupts reaches the PRM before returning; otherwise, spurious + * interrupts might occur. No return value. + */ +void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask) +{ + saved_mask[0] = + omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST, + OMAP4_PRM_IRQSTATUS_MPU_OFFSET); + saved_mask[1] = + omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST, + OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET); + + omap4_prm_write_inst_reg(0, OMAP4430_PRM_DEVICE_INST, + OMAP4_PRM_IRQENABLE_MPU_OFFSET); + omap4_prm_write_inst_reg(0, OMAP4430_PRM_DEVICE_INST, + OMAP4_PRM_IRQENABLE_MPU_2_OFFSET); + + /* OCP barrier */ + omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST, + OMAP4_REVISION_PRM_OFFSET); +} + +/** + * omap44xx_prm_restore_irqen - set PRM_IRQENABLE_MPU* registers from args + * @saved_mask: ptr to a u32 array of IRQENABLE bits saved previously + * + * Restore the PRM_IRQENABLE_MPU and PRM_IRQENABLE_MPU_2 registers from + * @saved_mask. Intended to be used in the PRM interrupt handler resume + * callback to restore values saved by omap44xx_prm_save_and_clear_irqen(). + * No OCP barrier should be needed here; any pending PRM interrupts will fire + * once the writes reach the PRM. No return value. + */ +void omap44xx_prm_restore_irqen(u32 *saved_mask) +{ + omap4_prm_write_inst_reg(saved_mask[0], OMAP4430_PRM_DEVICE_INST, + OMAP4_PRM_IRQENABLE_MPU_OFFSET); + omap4_prm_write_inst_reg(saved_mask[1], OMAP4430_PRM_DEVICE_INST, + OMAP4_PRM_IRQENABLE_MPU_2_OFFSET); +} + +static int __init omap4xxx_prcm_init(void) +{ + if (cpu_is_omap44xx()) + return omap_prcm_register_chain_handler(&omap4_prcm_irq_setup); + return 0; +} +subsys_initcall(omap4xxx_prcm_init); diff --git a/arch/arm/mach-omap2/prm44xx.h b/arch/arm/mach-omap2/prm44xx.h index 3d66ccd849d..7978092946d 100644 --- a/arch/arm/mach-omap2/prm44xx.h +++ b/arch/arm/mach-omap2/prm44xx.h @@ -1,7 +1,7 @@ /* * OMAP44xx PRM instance offset macros * - * Copyright (C) 2009-2010 Texas Instruments, Inc. + * Copyright (C) 2009-2011 Texas Instruments, Inc. * Copyright (C) 2009-2010 Nokia Corporation * * Paul Walmsley (paul@pwsan.com) @@ -763,6 +763,12 @@ extern u32 omap4_prm_vcvp_read(u8 offset); extern void omap4_prm_vcvp_write(u32 val, u8 offset); extern u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset); +/* PRM interrupt-related functions */ +extern void omap44xx_prm_read_pending_irqs(unsigned long *events); +extern void omap44xx_prm_ocp_barrier(void); +extern void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask); +extern void omap44xx_prm_restore_irqen(u32 *saved_mask); + # endif #endif diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c new file mode 100644 index 00000000000..860118ab43e --- /dev/null +++ b/arch/arm/mach-omap2/prm_common.c @@ -0,0 +1,320 @@ +/* + * OMAP2+ common Power & Reset Management (PRM) IP block functions + * + * Copyright (C) 2011 Texas Instruments, Inc. + * Tero Kristo <t-kristo@ti.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * + * For historical purposes, the API used to configure the PRM + * interrupt handler refers to it as the "PRCM interrupt." The + * underlying registers are located in the PRM on OMAP3/4. + * + * XXX This code should eventually be moved to a PRM driver. + */ + +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/irq.h> +#include <linux/interrupt.h> +#include <linux/slab.h> + +#include <mach/system.h> +#include <plat/common.h> +#include <plat/prcm.h> +#include <plat/irqs.h> + +#include "prm2xxx_3xxx.h" +#include "prm44xx.h" + +/* + * OMAP_PRCM_MAX_NR_PENDING_REG: maximum number of PRM_IRQ*_MPU regs + * XXX this is technically not needed, since + * omap_prcm_register_chain_handler() could allocate this based on the + * actual amount of memory needed for the SoC + */ +#define OMAP_PRCM_MAX_NR_PENDING_REG 2 + +/* + * prcm_irq_chips: an array of all of the "generic IRQ chips" in use + * by the PRCM interrupt handler code. There will be one 'chip' per + * PRM_{IRQSTATUS,IRQENABLE}_MPU register pair. (So OMAP3 will have + * one "chip" and OMAP4 will have two.) + */ +static struct irq_chip_generic **prcm_irq_chips; + +/* + * prcm_irq_setup: the PRCM IRQ parameters for the hardware the code + * is currently running on. Defined and passed by initialization code + * that calls omap_prcm_register_chain_handler(). + */ +static struct omap_prcm_irq_setup *prcm_irq_setup; + +/* Private functions */ + +/* + * Move priority events from events to priority_events array + */ +static void omap_prcm_events_filter_priority(unsigned long *events, + unsigned long *priority_events) +{ + int i; + + for (i = 0; i < prcm_irq_setup->nr_regs; i++) { + priority_events[i] = + events[i] & prcm_irq_setup->priority_mask[i]; + events[i] ^= priority_events[i]; + } +} + +/* + * PRCM Interrupt Handler + * + * This is a common handler for the OMAP PRCM interrupts. Pending + * interrupts are detected by a call to prcm_pending_events and + * dispatched accordingly. Clearing of the wakeup events should be + * done by the SoC specific individual handlers. + */ +static void omap_prcm_irq_handler(unsigned int irq, struct irq_desc *desc) +{ + unsigned long pending[OMAP_PRCM_MAX_NR_PENDING_REG]; + unsigned long priority_pending[OMAP_PRCM_MAX_NR_PENDING_REG]; + struct irq_chip *chip = irq_desc_get_chip(desc); + unsigned int virtirq; + int nr_irqs = prcm_irq_setup->nr_regs * 32; + + /* + * If we are suspended, mask all interrupts from PRCM level, + * this does not ack them, and they will be pending until we + * re-enable the interrupts, at which point the + * omap_prcm_irq_handler will be executed again. The + * _save_and_clear_irqen() function must ensure that the PRM + * write to disable all IRQs has reached the PRM before + * returning, or spurious PRCM interrupts may occur during + * suspend. + */ + if (prcm_irq_setup->suspended) { + prcm_irq_setup->save_and_clear_irqen(prcm_irq_setup->saved_mask); + prcm_irq_setup->suspend_save_flag = true; + } + + /* + * Loop until all pending irqs are handled, since + * generic_handle_irq() can cause new irqs to come + */ + while (!prcm_irq_setup->suspended) { + prcm_irq_setup->read_pending_irqs(pending); + + /* No bit set, then all IRQs are handled */ + if (find_first_bit(pending, nr_irqs) >= nr_irqs) + break; + + omap_prcm_events_filter_priority(pending, priority_pending); + + /* + * Loop on all currently pending irqs so that new irqs + * cannot starve previously pending irqs + */ + + /* Serve priority events first */ + for_each_set_bit(virtirq, priority_pending, nr_irqs) + generic_handle_irq(prcm_irq_setup->base_irq + virtirq); + + /* Serve normal events next */ + for_each_set_bit(virtirq, pending, nr_irqs) + generic_handle_irq(prcm_irq_setup->base_irq + virtirq); + } + if (chip->irq_ack) + chip->irq_ack(&desc->irq_data); + if (chip->irq_eoi) + chip->irq_eoi(&desc->irq_data); + chip->irq_unmask(&desc->irq_data); + + prcm_irq_setup->ocp_barrier(); /* avoid spurious IRQs */ +} + +/* Public functions */ + +/** + * omap_prcm_event_to_irq - given a PRCM event name, returns the + * corresponding IRQ on which the handler should be registered + * @name: name of the PRCM interrupt bit to look up - see struct omap_prcm_irq + * + * Returns the Linux internal IRQ ID corresponding to @name upon success, + * or -ENOENT upon failure. + */ +int omap_prcm_event_to_irq(const char *name) +{ + int i; + + if (!prcm_irq_setup || !name) + return -ENOENT; + + for (i = 0; i < prcm_irq_setup->nr_irqs; i++) + if (!strcmp(prcm_irq_setup->irqs[i].name, name)) + return prcm_irq_setup->base_irq + + prcm_irq_setup->irqs[i].offset; + + return -ENOENT; +} + +/** + * omap_prcm_irq_cleanup - reverses memory allocated and other steps + * done by omap_prcm_register_chain_handler() + * + * No return value. + */ +void omap_prcm_irq_cleanup(void) +{ + int i; + + if (!prcm_irq_setup) { + pr_err("PRCM: IRQ handler not initialized; cannot cleanup\n"); + return; + } + + if (prcm_irq_chips) { + for (i = 0; i < prcm_irq_setup->nr_regs; i++) { + if (prcm_irq_chips[i]) + irq_remove_generic_chip(prcm_irq_chips[i], + 0xffffffff, 0, 0); + prcm_irq_chips[i] = NULL; + } + kfree(prcm_irq_chips); + prcm_irq_chips = NULL; + } + + kfree(prcm_irq_setup->saved_mask); + prcm_irq_setup->saved_mask = NULL; + + kfree(prcm_irq_setup->priority_mask); + prcm_irq_setup->priority_mask = NULL; + + irq_set_chained_handler(prcm_irq_setup->irq, NULL); + + if (prcm_irq_setup->base_irq > 0) + irq_free_descs(prcm_irq_setup->base_irq, + prcm_irq_setup->nr_regs * 32); + prcm_irq_setup->base_irq = 0; +} + +void omap_prcm_irq_prepare(void) +{ + prcm_irq_setup->suspended = true; +} + +void omap_prcm_irq_complete(void) +{ + prcm_irq_setup->suspended = false; + + /* If we have not saved the masks, do not attempt to restore */ + if (!prcm_irq_setup->suspend_save_flag) + return; + + prcm_irq_setup->suspend_save_flag = false; + + /* + * Re-enable all masked PRCM irq sources, this causes the PRCM + * interrupt to fire immediately if the events were masked + * previously in the chain handler + */ + prcm_irq_setup->restore_irqen(prcm_irq_setup->saved_mask); +} + +/** + * omap_prcm_register_chain_handler - initializes the prcm chained interrupt + * handler based on provided parameters + * @irq_setup: hardware data about the underlying PRM/PRCM + * + * Set up the PRCM chained interrupt handler on the PRCM IRQ. Sets up + * one generic IRQ chip per PRM interrupt status/enable register pair. + * Returns 0 upon success, -EINVAL if called twice or if invalid + * arguments are passed, or -ENOMEM on any other error. + */ +int omap_prcm_register_chain_handler(struct omap_prcm_irq_setup *irq_setup) +{ + int nr_regs = irq_setup->nr_regs; + u32 mask[OMAP_PRCM_MAX_NR_PENDING_REG]; + int offset, i; + struct irq_chip_generic *gc; + struct irq_chip_type *ct; + + if (!irq_setup) + return -EINVAL; + + if (prcm_irq_setup) { + pr_err("PRCM: already initialized; won't reinitialize\n"); + return -EINVAL; + } + + if (nr_regs > OMAP_PRCM_MAX_NR_PENDING_REG) { + pr_err("PRCM: nr_regs too large\n"); + return -EINVAL; + } + + prcm_irq_setup = irq_setup; + + prcm_irq_chips = kzalloc(sizeof(void *) * nr_regs, GFP_KERNEL); + prcm_irq_setup->saved_mask = kzalloc(sizeof(u32) * nr_regs, GFP_KERNEL); + prcm_irq_setup->priority_mask = kzalloc(sizeof(u32) * nr_regs, + GFP_KERNEL); + + if (!prcm_irq_chips || !prcm_irq_setup->saved_mask || + !prcm_irq_setup->priority_mask) { + pr_err("PRCM: kzalloc failed\n"); + goto err; + } + + memset(mask, 0, sizeof(mask)); + + for (i = 0; i < irq_setup->nr_irqs; i++) { + offset = irq_setup->irqs[i].offset; + mask[offset >> 5] |= 1 << (offset & 0x1f); + if (irq_setup->irqs[i].priority) + irq_setup->priority_mask[offset >> 5] |= + 1 << (offset & 0x1f); + } + + irq_set_chained_handler(irq_setup->irq, omap_prcm_irq_handler); + + irq_setup->base_irq = irq_alloc_descs(-1, 0, irq_setup->nr_regs * 32, + 0); + + if (irq_setup->base_irq < 0) { + pr_err("PRCM: failed to allocate irq descs: %d\n", + irq_setup->base_irq); + goto err; + } + + for (i = 0; i <= irq_setup->nr_regs; i++) { + gc = irq_alloc_generic_chip("PRCM", 1, + irq_setup->base_irq + i * 32, prm_base, + handle_level_irq); + + if (!gc) { + pr_err("PRCM: failed to allocate generic chip\n"); + goto err; + } + ct = gc->chip_types; + ct->chip.irq_ack = irq_gc_ack_set_bit; + ct->chip.irq_mask = irq_gc_mask_clr_bit; + ct->chip.irq_unmask = irq_gc_mask_set_bit; + + ct->regs.ack = irq_setup->ack + i * 4; + ct->regs.mask = irq_setup->mask + i * 4; + + irq_setup_generic_chip(gc, mask[i], 0, IRQ_NOREQUEST, 0); + prcm_irq_chips[i] = gc; + } + + return 0; + +err: + omap_prcm_irq_cleanup(); + return -ENOMEM; +} diff --git a/arch/arm/mach-omap2/sdram-nokia.c b/arch/arm/mach-omap2/sdram-nokia.c index ee3a8ad304c..7479d7ea137 100644 --- a/arch/arm/mach-omap2/sdram-nokia.c +++ b/arch/arm/mach-omap2/sdram-nokia.c @@ -1,7 +1,7 @@ /* * SDRC register values for Nokia boards * - * Copyright (C) 2008, 2010 Nokia Corporation + * Copyright (C) 2008, 2010-2011 Nokia Corporation * * Lauri Leukkunen <lauri.leukkunen@nokia.com> * @@ -107,14 +107,37 @@ static const struct sdram_timings nokia_195dot2mhz_timings[] = { }, }; +static const struct sdram_timings nokia_200mhz_timings[] = { + { + .casl = 3, + .tDAL = 30000, + .tDPL = 15000, + .tRRD = 10000, + .tRCD = 20000, + .tRP = 15000, + .tRAS = 40000, + .tRC = 55000, + .tRFC = 140000, + .tXSR = 200000, + + .tREF = 7800, + + .tXP = 2, + .tCKE = 4, + .tWTR = 2 + }, +}; + static const struct { long rate; struct sdram_timings const *data; } nokia_timings[] = { { 83000000, nokia_166mhz_timings }, { 97600000, nokia_97dot6mhz_timings }, + { 100000000, nokia_200mhz_timings }, { 166000000, nokia_166mhz_timings }, { 195200000, nokia_195dot2mhz_timings }, + { 200000000, nokia_200mhz_timings }, }; static struct omap_sdrc_params nokia_sdrc_params[ARRAY_SIZE(nokia_timings) + 1]; diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c index 42c326732a2..247d89478f2 100644 --- a/arch/arm/mach-omap2/serial.c +++ b/arch/arm/mach-omap2/serial.c @@ -19,26 +19,21 @@ */ #include <linux/kernel.h> #include <linux/init.h> -#include <linux/serial_reg.h> #include <linux/clk.h> #include <linux/io.h> #include <linux/delay.h> #include <linux/platform_device.h> #include <linux/slab.h> -#include <linux/serial_8250.h> #include <linux/pm_runtime.h> #include <linux/console.h> -#ifdef CONFIG_SERIAL_OMAP #include <plat/omap-serial.h> -#endif - #include "common.h" #include <plat/board.h> -#include <plat/clock.h> #include <plat/dma.h> #include <plat/omap_hwmod.h> #include <plat/omap_device.h> +#include <plat/omap-pm.h> #include "prm2xxx_3xxx.h" #include "pm.h" @@ -47,603 +42,226 @@ #include "control.h" #include "mux.h" -#define UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV 0x52 -#define UART_OMAP_WER 0x17 /* Wake-up enable register */ - -#define UART_ERRATA_FIFO_FULL_ABORT (0x1 << 0) -#define UART_ERRATA_i202_MDR1_ACCESS (0x1 << 1) - /* - * NOTE: By default the serial timeout is disabled as it causes lost characters - * over the serial ports. This means that the UART clocks will stay on until - * disabled via sysfs. This also causes that any deeper omap sleep states are - * blocked. + * NOTE: By default the serial auto_suspend timeout is disabled as it causes + * lost characters over the serial ports. This means that the UART clocks will + * stay on until power/autosuspend_delay is set for the uart from sysfs. + * This also causes that any deeper omap sleep states are blocked. */ -#define DEFAULT_TIMEOUT 0 +#define DEFAULT_AUTOSUSPEND_DELAY -1 #define MAX_UART_HWMOD_NAME_LEN 16 struct omap_uart_state { int num; int can_sleep; - struct timer_list timer; - u32 timeout; - - void __iomem *wk_st; - void __iomem *wk_en; - u32 wk_mask; - u32 padconf; - u32 dma_enabled; - - struct clk *ick; - struct clk *fck; - int clocked; - - int irq; - int regshift; - int irqflags; - void __iomem *membase; - resource_size_t mapbase; struct list_head node; struct omap_hwmod *oh; struct platform_device *pdev; - - u32 errata; -#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) - int context_valid; - - /* Registers to be saved/restored for OFF-mode */ - u16 dll; - u16 dlh; - u16 ier; - u16 sysc; - u16 scr; - u16 wer; - u16 mcr; -#endif }; static LIST_HEAD(uart_list); static u8 num_uarts; +static u8 console_uart_id = -1; +static u8 no_console_suspend; +static u8 uart_debug; + +#define DEFAULT_RXDMA_POLLRATE 1 /* RX DMA polling rate (us) */ +#define DEFAULT_RXDMA_BUFSIZE 4096 /* RX DMA buffer size */ +#define DEFAULT_RXDMA_TIMEOUT (3 * HZ)/* RX DMA timeout (jiffies) */ + +static struct omap_uart_port_info omap_serial_default_info[] __initdata = { + { + .dma_enabled = false, + .dma_rx_buf_size = DEFAULT_RXDMA_BUFSIZE, + .dma_rx_poll_rate = DEFAULT_RXDMA_POLLRATE, + .dma_rx_timeout = DEFAULT_RXDMA_TIMEOUT, + .autosuspend_timeout = DEFAULT_AUTOSUSPEND_DELAY, + }, +}; -static inline unsigned int __serial_read_reg(struct uart_port *up, - int offset) -{ - offset <<= up->regshift; - return (unsigned int)__raw_readb(up->membase + offset); -} - -static inline unsigned int serial_read_reg(struct omap_uart_state *uart, - int offset) +#ifdef CONFIG_PM +static void omap_uart_enable_wakeup(struct platform_device *pdev, bool enable) { - offset <<= uart->regshift; - return (unsigned int)__raw_readb(uart->membase + offset); -} + struct omap_device *od = to_omap_device(pdev); -static inline void __serial_write_reg(struct uart_port *up, int offset, - int value) -{ - offset <<= up->regshift; - __raw_writeb(value, up->membase + offset); -} + if (!od) + return; -static inline void serial_write_reg(struct omap_uart_state *uart, int offset, - int value) -{ - offset <<= uart->regshift; - __raw_writeb(value, uart->membase + offset); + if (enable) + omap_hwmod_enable_wakeup(od->hwmods[0]); + else + omap_hwmod_disable_wakeup(od->hwmods[0]); } /* - * Internal UARTs need to be initialized for the 8250 autoconfig to work - * properly. Note that the TX watermark initialization may not be needed - * once the 8250.c watermark handling code is merged. + * Errata i291: [UART]:Cannot Acknowledge Idle Requests + * in Smartidle Mode When Configured for DMA Operations. + * WA: configure uart in force idle mode. */ - -static inline void __init omap_uart_reset(struct omap_uart_state *uart) +static void omap_uart_set_noidle(struct platform_device *pdev) { - serial_write_reg(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE); - serial_write_reg(uart, UART_OMAP_SCR, 0x08); - serial_write_reg(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_16X_MODE); -} - -#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3) + struct omap_device *od = to_omap_device(pdev); -/* - * Work Around for Errata i202 (3430 - 1.12, 3630 - 1.6) - * The access to uart register after MDR1 Access - * causes UART to corrupt data. - * - * Need a delay = - * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS) - * give 10 times as much - */ -static void omap_uart_mdr1_errataset(struct omap_uart_state *uart, u8 mdr1_val, - u8 fcr_val) -{ - u8 timeout = 255; - - serial_write_reg(uart, UART_OMAP_MDR1, mdr1_val); - udelay(2); - serial_write_reg(uart, UART_FCR, fcr_val | UART_FCR_CLEAR_XMIT | - UART_FCR_CLEAR_RCVR); - /* - * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and - * TX_FIFO_E bit is 1. - */ - while (UART_LSR_THRE != (serial_read_reg(uart, UART_LSR) & - (UART_LSR_THRE | UART_LSR_DR))) { - timeout--; - if (!timeout) { - /* Should *never* happen. we warn and carry on */ - dev_crit(&uart->pdev->dev, "Errata i202: timedout %x\n", - serial_read_reg(uart, UART_LSR)); - break; - } - udelay(1); - } + omap_hwmod_set_slave_idlemode(od->hwmods[0], HWMOD_IDLEMODE_NO); } -static void omap_uart_save_context(struct omap_uart_state *uart) +static void omap_uart_set_forceidle(struct platform_device *pdev) { - u16 lcr = 0; + struct omap_device *od = to_omap_device(pdev); - if (!enable_off_mode) - return; - - lcr = serial_read_reg(uart, UART_LCR); - serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B); - uart->dll = serial_read_reg(uart, UART_DLL); - uart->dlh = serial_read_reg(uart, UART_DLM); - serial_write_reg(uart, UART_LCR, lcr); - uart->ier = serial_read_reg(uart, UART_IER); - uart->sysc = serial_read_reg(uart, UART_OMAP_SYSC); - uart->scr = serial_read_reg(uart, UART_OMAP_SCR); - uart->wer = serial_read_reg(uart, UART_OMAP_WER); - serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_A); - uart->mcr = serial_read_reg(uart, UART_MCR); - serial_write_reg(uart, UART_LCR, lcr); - - uart->context_valid = 1; + omap_hwmod_set_slave_idlemode(od->hwmods[0], HWMOD_IDLEMODE_FORCE); } -static void omap_uart_restore_context(struct omap_uart_state *uart) -{ - u16 efr = 0; - - if (!enable_off_mode) - return; - - if (!uart->context_valid) - return; - - uart->context_valid = 0; - - if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS) - omap_uart_mdr1_errataset(uart, UART_OMAP_MDR1_DISABLE, 0xA0); - else - serial_write_reg(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE); - - serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B); - efr = serial_read_reg(uart, UART_EFR); - serial_write_reg(uart, UART_EFR, UART_EFR_ECB); - serial_write_reg(uart, UART_LCR, 0x0); /* Operational mode */ - serial_write_reg(uart, UART_IER, 0x0); - serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B); - serial_write_reg(uart, UART_DLL, uart->dll); - serial_write_reg(uart, UART_DLM, uart->dlh); - serial_write_reg(uart, UART_LCR, 0x0); /* Operational mode */ - serial_write_reg(uart, UART_IER, uart->ier); - serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_A); - serial_write_reg(uart, UART_MCR, uart->mcr); - serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B); - serial_write_reg(uart, UART_EFR, efr); - serial_write_reg(uart, UART_LCR, UART_LCR_WLEN8); - serial_write_reg(uart, UART_OMAP_SCR, uart->scr); - serial_write_reg(uart, UART_OMAP_WER, uart->wer); - serial_write_reg(uart, UART_OMAP_SYSC, uart->sysc); - - if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS) - omap_uart_mdr1_errataset(uart, UART_OMAP_MDR1_16X_MODE, 0xA1); - else - /* UART 16x mode */ - serial_write_reg(uart, UART_OMAP_MDR1, - UART_OMAP_MDR1_16X_MODE); -} #else -static inline void omap_uart_save_context(struct omap_uart_state *uart) {} -static inline void omap_uart_restore_context(struct omap_uart_state *uart) {} -#endif /* CONFIG_PM && CONFIG_ARCH_OMAP3 */ - -static inline void omap_uart_enable_clocks(struct omap_uart_state *uart) -{ - if (uart->clocked) - return; - - omap_device_enable(uart->pdev); - uart->clocked = 1; - omap_uart_restore_context(uart); -} - -#ifdef CONFIG_PM - -static inline void omap_uart_disable_clocks(struct omap_uart_state *uart) -{ - if (!uart->clocked) - return; - - omap_uart_save_context(uart); - uart->clocked = 0; - omap_device_idle(uart->pdev); -} - -static void omap_uart_enable_wakeup(struct omap_uart_state *uart) -{ - /* Set wake-enable bit */ - if (uart->wk_en && uart->wk_mask) { - u32 v = __raw_readl(uart->wk_en); - v |= uart->wk_mask; - __raw_writel(v, uart->wk_en); - } - - /* Ensure IOPAD wake-enables are set */ - if (cpu_is_omap34xx() && uart->padconf) { - u16 v = omap_ctrl_readw(uart->padconf); - v |= OMAP3_PADCONF_WAKEUPENABLE0; - omap_ctrl_writew(v, uart->padconf); - } -} - -static void omap_uart_disable_wakeup(struct omap_uart_state *uart) -{ - /* Clear wake-enable bit */ - if (uart->wk_en && uart->wk_mask) { - u32 v = __raw_readl(uart->wk_en); - v &= ~uart->wk_mask; - __raw_writel(v, uart->wk_en); - } - - /* Ensure IOPAD wake-enables are cleared */ - if (cpu_is_omap34xx() && uart->padconf) { - u16 v = omap_ctrl_readw(uart->padconf); - v &= ~OMAP3_PADCONF_WAKEUPENABLE0; - omap_ctrl_writew(v, uart->padconf); - } -} - -static void omap_uart_smart_idle_enable(struct omap_uart_state *uart, - int enable) -{ - u8 idlemode; - - if (enable) { - /** - * Errata 2.15: [UART]:Cannot Acknowledge Idle Requests - * in Smartidle Mode When Configured for DMA Operations. - */ - if (uart->dma_enabled) - idlemode = HWMOD_IDLEMODE_FORCE; - else - idlemode = HWMOD_IDLEMODE_SMART; - } else { - idlemode = HWMOD_IDLEMODE_NO; - } - - omap_hwmod_set_slave_idlemode(uart->oh, idlemode); -} - -static void omap_uart_block_sleep(struct omap_uart_state *uart) -{ - omap_uart_enable_clocks(uart); - - omap_uart_smart_idle_enable(uart, 0); - uart->can_sleep = 0; - if (uart->timeout) - mod_timer(&uart->timer, jiffies + uart->timeout); - else - del_timer(&uart->timer); -} - -static void omap_uart_allow_sleep(struct omap_uart_state *uart) -{ - if (device_may_wakeup(&uart->pdev->dev)) - omap_uart_enable_wakeup(uart); - else - omap_uart_disable_wakeup(uart); - - if (!uart->clocked) - return; - - omap_uart_smart_idle_enable(uart, 1); - uart->can_sleep = 1; - del_timer(&uart->timer); -} - -static void omap_uart_idle_timer(unsigned long data) -{ - struct omap_uart_state *uart = (struct omap_uart_state *)data; - - omap_uart_allow_sleep(uart); -} - -void omap_uart_prepare_idle(int num) -{ - struct omap_uart_state *uart; - - list_for_each_entry(uart, &uart_list, node) { - if (num == uart->num && uart->can_sleep) { - omap_uart_disable_clocks(uart); - return; - } - } -} - -void omap_uart_resume_idle(int num) -{ - struct omap_uart_state *uart; - - list_for_each_entry(uart, &uart_list, node) { - if (num == uart->num && uart->can_sleep) { - omap_uart_enable_clocks(uart); - - /* Check for IO pad wakeup */ - if (cpu_is_omap34xx() && uart->padconf) { - u16 p = omap_ctrl_readw(uart->padconf); - - if (p & OMAP3_PADCONF_WAKEUPEVENT0) - omap_uart_block_sleep(uart); - } - - /* Check for normal UART wakeup */ - if (__raw_readl(uart->wk_st) & uart->wk_mask) - omap_uart_block_sleep(uart); - return; - } - } -} - -void omap_uart_prepare_suspend(void) -{ - struct omap_uart_state *uart; - - list_for_each_entry(uart, &uart_list, node) { - omap_uart_allow_sleep(uart); - } -} - -int omap_uart_can_sleep(void) -{ - struct omap_uart_state *uart; - int can_sleep = 1; - - list_for_each_entry(uart, &uart_list, node) { - if (!uart->clocked) - continue; - - if (!uart->can_sleep) { - can_sleep = 0; - continue; - } - - /* This UART can now safely sleep. */ - omap_uart_allow_sleep(uart); - } - - return can_sleep; -} +static void omap_uart_enable_wakeup(struct platform_device *pdev, bool enable) +{} +static void omap_uart_set_noidle(struct platform_device *pdev) {} +static void omap_uart_set_forceidle(struct platform_device *pdev) {} +#endif /* CONFIG_PM */ -/** - * omap_uart_interrupt() - * - * This handler is used only to detect that *any* UART interrupt has - * occurred. It does _nothing_ to handle the interrupt. Rather, - * any UART interrupt will trigger the inactivity timer so the - * UART will not idle or sleep for its timeout period. - * - **/ -/* static int first_interrupt; */ -static irqreturn_t omap_uart_interrupt(int irq, void *dev_id) -{ - struct omap_uart_state *uart = dev_id; +#ifdef CONFIG_OMAP_MUX +static struct omap_device_pad default_uart1_pads[] __initdata = { + { + .name = "uart1_cts.uart1_cts", + .enable = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0, + }, + { + .name = "uart1_rts.uart1_rts", + .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0, + }, + { + .name = "uart1_tx.uart1_tx", + .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0, + }, + { + .name = "uart1_rx.uart1_rx", + .flags = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP, + .enable = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0, + .idle = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0, + }, +}; - omap_uart_block_sleep(uart); +static struct omap_device_pad default_uart2_pads[] __initdata = { + { + .name = "uart2_cts.uart2_cts", + .enable = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0, + }, + { + .name = "uart2_rts.uart2_rts", + .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0, + }, + { + .name = "uart2_tx.uart2_tx", + .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0, + }, + { + .name = "uart2_rx.uart2_rx", + .flags = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP, + .enable = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0, + .idle = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0, + }, +}; - return IRQ_NONE; -} +static struct omap_device_pad default_uart3_pads[] __initdata = { + { + .name = "uart3_cts_rctx.uart3_cts_rctx", + .enable = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0, + }, + { + .name = "uart3_rts_sd.uart3_rts_sd", + .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0, + }, + { + .name = "uart3_tx_irtx.uart3_tx_irtx", + .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0, + }, + { + .name = "uart3_rx_irrx.uart3_rx_irrx", + .flags = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP, + .enable = OMAP_PIN_INPUT | OMAP_MUX_MODE0, + .idle = OMAP_PIN_INPUT | OMAP_MUX_MODE0, + }, +}; -static void omap_uart_idle_init(struct omap_uart_state *uart) -{ - int ret; - - uart->can_sleep = 0; - uart->timeout = DEFAULT_TIMEOUT; - setup_timer(&uart->timer, omap_uart_idle_timer, - (unsigned long) uart); - if (uart->timeout) - mod_timer(&uart->timer, jiffies + uart->timeout); - omap_uart_smart_idle_enable(uart, 0); - - if (cpu_is_omap34xx() && !cpu_is_ti816x()) { - u32 mod = (uart->num > 1) ? OMAP3430_PER_MOD : CORE_MOD; - u32 wk_mask = 0; - u32 padconf = 0; - - /* XXX These PRM accesses do not belong here */ - uart->wk_en = OMAP34XX_PRM_REGADDR(mod, PM_WKEN1); - uart->wk_st = OMAP34XX_PRM_REGADDR(mod, PM_WKST1); - switch (uart->num) { - case 0: - wk_mask = OMAP3430_ST_UART1_MASK; - padconf = 0x182; - break; - case 1: - wk_mask = OMAP3430_ST_UART2_MASK; - padconf = 0x17a; - break; - case 2: - wk_mask = OMAP3430_ST_UART3_MASK; - padconf = 0x19e; - break; - case 3: - wk_mask = OMAP3630_ST_UART4_MASK; - padconf = 0x0d2; - break; - } - uart->wk_mask = wk_mask; - uart->padconf = padconf; - } else if (cpu_is_omap24xx()) { - u32 wk_mask = 0; - u32 wk_en = PM_WKEN1, wk_st = PM_WKST1; - - switch (uart->num) { - case 0: - wk_mask = OMAP24XX_ST_UART1_MASK; - break; - case 1: - wk_mask = OMAP24XX_ST_UART2_MASK; - break; - case 2: - wk_en = OMAP24XX_PM_WKEN2; - wk_st = OMAP24XX_PM_WKST2; - wk_mask = OMAP24XX_ST_UART3_MASK; - break; - } - uart->wk_mask = wk_mask; - if (cpu_is_omap2430()) { - uart->wk_en = OMAP2430_PRM_REGADDR(CORE_MOD, wk_en); - uart->wk_st = OMAP2430_PRM_REGADDR(CORE_MOD, wk_st); - } else if (cpu_is_omap2420()) { - uart->wk_en = OMAP2420_PRM_REGADDR(CORE_MOD, wk_en); - uart->wk_st = OMAP2420_PRM_REGADDR(CORE_MOD, wk_st); - } - } else { - uart->wk_en = NULL; - uart->wk_st = NULL; - uart->wk_mask = 0; - uart->padconf = 0; - } +static struct omap_device_pad default_omap36xx_uart4_pads[] __initdata = { + { + .name = "gpmc_wait2.uart4_tx", + .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0, + }, + { + .name = "gpmc_wait3.uart4_rx", + .flags = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP, + .enable = OMAP_PIN_INPUT | OMAP_MUX_MODE2, + .idle = OMAP_PIN_INPUT | OMAP_MUX_MODE2, + }, +}; - uart->irqflags |= IRQF_SHARED; - ret = request_threaded_irq(uart->irq, NULL, omap_uart_interrupt, - IRQF_SHARED, "serial idle", (void *)uart); - WARN_ON(ret); -} +static struct omap_device_pad default_omap4_uart4_pads[] __initdata = { + { + .name = "uart4_tx.uart4_tx", + .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0, + }, + { + .name = "uart4_rx.uart4_rx", + .flags = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP, + .enable = OMAP_PIN_INPUT | OMAP_MUX_MODE0, + .idle = OMAP_PIN_INPUT | OMAP_MUX_MODE0, + }, +}; -void omap_uart_enable_irqs(int enable) +static void omap_serial_fill_default_pads(struct omap_board_data *bdata) { - int ret; - struct omap_uart_state *uart; - - list_for_each_entry(uart, &uart_list, node) { - if (enable) { - pm_runtime_put_sync(&uart->pdev->dev); - ret = request_threaded_irq(uart->irq, NULL, - omap_uart_interrupt, - IRQF_SHARED, - "serial idle", - (void *)uart); - } else { - pm_runtime_get_noresume(&uart->pdev->dev); - free_irq(uart->irq, (void *)uart); + switch (bdata->id) { + case 0: + bdata->pads = default_uart1_pads; + bdata->pads_cnt = ARRAY_SIZE(default_uart1_pads); + break; + case 1: + bdata->pads = default_uart2_pads; + bdata->pads_cnt = ARRAY_SIZE(default_uart2_pads); + break; + case 2: + bdata->pads = default_uart3_pads; + bdata->pads_cnt = ARRAY_SIZE(default_uart3_pads); + break; + case 3: + if (cpu_is_omap44xx()) { + bdata->pads = default_omap4_uart4_pads; + bdata->pads_cnt = + ARRAY_SIZE(default_omap4_uart4_pads); + } else if (cpu_is_omap3630()) { + bdata->pads = default_omap36xx_uart4_pads; + bdata->pads_cnt = + ARRAY_SIZE(default_omap36xx_uart4_pads); } + break; + default: + break; } } - -static ssize_t sleep_timeout_show(struct device *dev, - struct device_attribute *attr, - char *buf) -{ - struct platform_device *pdev = to_platform_device(dev); - struct omap_device *odev = to_omap_device(pdev); - struct omap_uart_state *uart = odev->hwmods[0]->dev_attr; - - return sprintf(buf, "%u\n", uart->timeout / HZ); -} - -static ssize_t sleep_timeout_store(struct device *dev, - struct device_attribute *attr, - const char *buf, size_t n) -{ - struct platform_device *pdev = to_platform_device(dev); - struct omap_device *odev = to_omap_device(pdev); - struct omap_uart_state *uart = odev->hwmods[0]->dev_attr; - unsigned int value; - - if (sscanf(buf, "%u", &value) != 1) { - dev_err(dev, "sleep_timeout_store: Invalid value\n"); - return -EINVAL; - } - - uart->timeout = value * HZ; - if (uart->timeout) - mod_timer(&uart->timer, jiffies + uart->timeout); - else - /* A zero value means disable timeout feature */ - omap_uart_block_sleep(uart); - - return n; -} - -static DEVICE_ATTR(sleep_timeout, 0644, sleep_timeout_show, - sleep_timeout_store); -#define DEV_CREATE_FILE(dev, attr) WARN_ON(device_create_file(dev, attr)) #else -static inline void omap_uart_idle_init(struct omap_uart_state *uart) {} -static void omap_uart_block_sleep(struct omap_uart_state *uart) -{ - /* Needed to enable UART clocks when built without CONFIG_PM */ - omap_uart_enable_clocks(uart); -} -#define DEV_CREATE_FILE(dev, attr) -#endif /* CONFIG_PM */ - -#ifndef CONFIG_SERIAL_OMAP -/* - * Override the default 8250 read handler: mem_serial_in() - * Empty RX fifo read causes an abort on omap3630 and omap4 - * This function makes sure that an empty rx fifo is not read on these silicons - * (OMAP1/2/3430 are not affected) - */ -static unsigned int serial_in_override(struct uart_port *up, int offset) -{ - if (UART_RX == offset) { - unsigned int lsr; - lsr = __serial_read_reg(up, UART_LSR); - if (!(lsr & UART_LSR_DR)) - return -EPERM; - } - - return __serial_read_reg(up, offset); -} +static void omap_serial_fill_default_pads(struct omap_board_data *bdata) {} +#endif -static void serial_out_override(struct uart_port *up, int offset, int value) +char *cmdline_find_option(char *str) { - unsigned int status, tmout = 10000; + extern char *saved_command_line; - status = __serial_read_reg(up, UART_LSR); - while (!(status & UART_LSR_THRE)) { - /* Wait up to 10ms for the character(s) to be sent. */ - if (--tmout == 0) - break; - udelay(1); - status = __serial_read_reg(up, UART_LSR); - } - __serial_write_reg(up, offset, value); + return strstr(saved_command_line, str); } -#endif static int __init omap_serial_early_init(void) { - int i = 0; - do { char oh_name[MAX_UART_HWMOD_NAME_LEN]; struct omap_hwmod *oh; struct omap_uart_state *uart; + char uart_name[MAX_UART_HWMOD_NAME_LEN]; snprintf(oh_name, MAX_UART_HWMOD_NAME_LEN, - "uart%d", i + 1); + "uart%d", num_uarts + 1); oh = omap_hwmod_lookup(oh_name); if (!oh) break; @@ -653,21 +271,35 @@ static int __init omap_serial_early_init(void) return -ENODEV; uart->oh = oh; - uart->num = i++; + uart->num = num_uarts++; list_add_tail(&uart->node, &uart_list); - num_uarts++; - - /* - * NOTE: omap_hwmod_setup*() has not yet been called, - * so no hwmod functions will work yet. - */ - - /* - * During UART early init, device need to be probed - * to determine SoC specific init before omap_device - * is ready. Therefore, don't allow idle here - */ - uart->oh->flags |= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET; + snprintf(uart_name, MAX_UART_HWMOD_NAME_LEN, + "%s%d", OMAP_SERIAL_NAME, uart->num); + + if (cmdline_find_option(uart_name)) { + console_uart_id = uart->num; + + if (console_loglevel >= 10) { + uart_debug = true; + pr_info("%s used as console in debug mode" + " uart%d clocks will not be" + " gated", uart_name, uart->num); + } + + if (cmdline_find_option("no_console_suspend")) + no_console_suspend = true; + + /* + * omap-uart can be used for earlyprintk logs + * So if omap-uart is used as console then prevent + * uart reset and idle to get logs from omap-uart + * until uart console driver is available to take + * care for console messages. + * Idling or resetting omap-uart while printing logs + * early boot logs can stall the boot-up. + */ + oh->flags |= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET; + } } while (1); return 0; @@ -677,6 +309,7 @@ core_initcall(omap_serial_early_init); /** * omap_serial_init_port() - initialize single serial port * @bdata: port specific board data pointer + * @info: platform specific data pointer * * This function initialies serial driver for given port only. * Platforms can call this function instead of omap_serial_init() @@ -685,7 +318,8 @@ core_initcall(omap_serial_early_init); * Don't mix calls to omap_serial_init_port() and omap_serial_init(), * use only one of the two. */ -void __init omap_serial_init_port(struct omap_board_data *bdata) +void __init omap_serial_init_port(struct omap_board_data *bdata, + struct omap_uart_port_info *info) { struct omap_uart_state *uart; struct omap_hwmod *oh; @@ -693,15 +327,7 @@ void __init omap_serial_init_port(struct omap_board_data *bdata) void *pdata = NULL; u32 pdata_size = 0; char *name; -#ifndef CONFIG_SERIAL_OMAP - struct plat_serial8250_port ports[2] = { - {}, - {.flags = 0}, - }; - struct plat_serial8250_port *p = &ports[0]; -#else struct omap_uart_port_info omap_up; -#endif if (WARN_ON(!bdata)) return; @@ -713,66 +339,34 @@ void __init omap_serial_init_port(struct omap_board_data *bdata) list_for_each_entry(uart, &uart_list, node) if (bdata->id == uart->num) break; + if (!info) + info = omap_serial_default_info; oh = uart->oh; - uart->dma_enabled = 0; -#ifndef CONFIG_SERIAL_OMAP - name = "serial8250"; - - /* - * !! 8250 driver does not use standard IORESOURCE* It - * has it's own custom pdata that can be taken from - * the hwmod resource data. But, this needs to be - * done after the build. - * - * ?? does it have to be done before the register ?? - * YES, because platform_device_data_add() copies - * pdata, it does not use a pointer. - */ - p->flags = UPF_BOOT_AUTOCONF; - p->iotype = UPIO_MEM; - p->regshift = 2; - p->uartclk = OMAP24XX_BASE_BAUD * 16; - p->irq = oh->mpu_irqs[0].irq; - p->mapbase = oh->slaves[0]->addr->pa_start; - p->membase = omap_hwmod_get_mpu_rt_va(oh); - p->irqflags = IRQF_SHARED; - p->private_data = uart; - - /* - * omap44xx, ti816x: Never read empty UART fifo - * omap3xxx: Never read empty UART fifo on UARTs - * with IP rev >=0x52 - */ - uart->regshift = p->regshift; - uart->membase = p->membase; - if (cpu_is_omap44xx() || cpu_is_ti816x()) - uart->errata |= UART_ERRATA_FIFO_FULL_ABORT; - else if ((serial_read_reg(uart, UART_OMAP_MVER) & 0xFF) - >= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV) - uart->errata |= UART_ERRATA_FIFO_FULL_ABORT; - - if (uart->errata & UART_ERRATA_FIFO_FULL_ABORT) { - p->serial_in = serial_in_override; - p->serial_out = serial_out_override; - } - - pdata = &ports[0]; - pdata_size = 2 * sizeof(struct plat_serial8250_port); -#else - name = DRIVER_NAME; - omap_up.dma_enabled = uart->dma_enabled; + omap_up.dma_enabled = info->dma_enabled; omap_up.uartclk = OMAP24XX_BASE_BAUD * 16; - omap_up.mapbase = oh->slaves[0]->addr->pa_start; - omap_up.membase = omap_hwmod_get_mpu_rt_va(oh); - omap_up.irqflags = IRQF_SHARED; - omap_up.flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ; + omap_up.flags = UPF_BOOT_AUTOCONF; + omap_up.get_context_loss_count = omap_pm_get_dev_context_loss_count; + omap_up.set_forceidle = omap_uart_set_forceidle; + omap_up.set_noidle = omap_uart_set_noidle; + omap_up.enable_wakeup = omap_uart_enable_wakeup; + omap_up.dma_rx_buf_size = info->dma_rx_buf_size; + omap_up.dma_rx_timeout = info->dma_rx_timeout; + omap_up.dma_rx_poll_rate = info->dma_rx_poll_rate; + omap_up.autosuspend_timeout = info->autosuspend_timeout; + + /* Enable the MDR1 Errata i202 for OMAP2430/3xxx/44xx */ + if (!cpu_is_omap2420() && !cpu_is_ti816x()) + omap_up.errata |= UART_ERRATA_i202_MDR1_ACCESS; + + /* Enable DMA Mode Force Idle Errata i291 for omap34xx/3630 */ + if (cpu_is_omap34xx() || cpu_is_omap3630()) + omap_up.errata |= UART_ERRATA_i291_DMA_FORCEIDLE; pdata = &omap_up; pdata_size = sizeof(struct omap_uart_port_info); -#endif if (WARN_ON(!oh)) return; @@ -782,64 +376,29 @@ void __init omap_serial_init_port(struct omap_board_data *bdata) WARN(IS_ERR(pdev), "Could not build omap_device for %s: %s.\n", name, oh->name); - omap_device_disable_idle_on_suspend(pdev); + if ((console_uart_id == bdata->id) && no_console_suspend) + omap_device_disable_idle_on_suspend(pdev); + oh->mux = omap_hwmod_mux_init(bdata->pads, bdata->pads_cnt); - uart->irq = oh->mpu_irqs[0].irq; - uart->regshift = 2; - uart->mapbase = oh->slaves[0]->addr->pa_start; - uart->membase = omap_hwmod_get_mpu_rt_va(oh); uart->pdev = pdev; oh->dev_attr = uart; - console_lock(); /* in case the earlycon is on the UART */ - - /* - * Because of early UART probing, UART did not get idled - * on init. Now that omap_device is ready, ensure full idle - * before doing omap_device_enable(). - */ - omap_hwmod_idle(uart->oh); - - omap_device_enable(uart->pdev); - omap_uart_idle_init(uart); - omap_uart_reset(uart); - omap_hwmod_enable_wakeup(uart->oh); - omap_device_idle(uart->pdev); - - /* - * Need to block sleep long enough for interrupt driven - * driver to start. Console driver is in polling mode - * so device needs to be kept enabled while polling driver - * is in use. - */ - if (uart->timeout) - uart->timeout = (30 * HZ); - omap_uart_block_sleep(uart); - uart->timeout = DEFAULT_TIMEOUT; - - console_unlock(); - - if ((cpu_is_omap34xx() && uart->padconf) || - (uart->wk_en && uart->wk_mask)) { + if (((cpu_is_omap34xx() || cpu_is_omap44xx()) && bdata->pads) + && !uart_debug) device_init_wakeup(&pdev->dev, true); - DEV_CREATE_FILE(&pdev->dev, &dev_attr_sleep_timeout); - } - - /* Enable the MDR1 errata for OMAP3 */ - if (cpu_is_omap34xx() && !cpu_is_ti816x()) - uart->errata |= UART_ERRATA_i202_MDR1_ACCESS; } /** - * omap_serial_init() - initialize all supported serial ports + * omap_serial_board_init() - initialize all supported serial ports + * @info: platform specific data pointer * * Initializes all available UARTs as serial ports. Platforms * can call this function when they want to have default behaviour * for serial ports (e.g initialize them all as serial ports). */ -void __init omap_serial_init(void) +void __init omap_serial_board_init(struct omap_uart_port_info *info) { struct omap_uart_state *uart; struct omap_board_data bdata; @@ -849,7 +408,25 @@ void __init omap_serial_init(void) bdata.flags = 0; bdata.pads = NULL; bdata.pads_cnt = 0; - omap_serial_init_port(&bdata); + if (cpu_is_omap44xx() || cpu_is_omap34xx()) + omap_serial_fill_default_pads(&bdata); + + if (!info) + omap_serial_init_port(&bdata, NULL); + else + omap_serial_init_port(&bdata, &info[uart->num]); } } + +/** + * omap_serial_init() - initialize all supported serial ports + * + * Initializes all available UARTs. + * Platforms can call this function when they want to have default behaviour + * for serial ports (e.g initialize them all as serial ports). + */ +void __init omap_serial_init(void) +{ + omap_serial_board_init(NULL); +} diff --git a/arch/arm/mach-omap2/sleep44xx.S b/arch/arm/mach-omap2/sleep44xx.S new file mode 100644 index 00000000000..abd28340049 --- /dev/null +++ b/arch/arm/mach-omap2/sleep44xx.S @@ -0,0 +1,379 @@ +/* + * OMAP44xx sleep code. + * + * Copyright (C) 2011 Texas Instruments, Inc. + * Santosh Shilimkar <santosh.shilimkar@ti.com> + * + * This program is free software,you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/linkage.h> +#include <asm/system.h> +#include <asm/smp_scu.h> +#include <asm/memory.h> +#include <asm/hardware/cache-l2x0.h> + +#include <plat/omap44xx.h> +#include <mach/omap-secure.h> + +#include "common.h" +#include "omap4-sar-layout.h" + +#if defined(CONFIG_SMP) && defined(CONFIG_PM) + +.macro DO_SMC + dsb + smc #0 + dsb +.endm + +ppa_zero_params: + .word 0x0 + +ppa_por_params: + .word 1, 0 + +/* + * ============================= + * == CPU suspend finisher == + * ============================= + * + * void omap4_finish_suspend(unsigned long cpu_state) + * + * This function code saves the CPU context and performs the CPU + * power down sequence. Calling WFI effectively changes the CPU + * power domains states to the desired target power state. + * + * @cpu_state : contains context save state (r0) + * 0 - No context lost + * 1 - CPUx L1 and logic lost: MPUSS CSWR + * 2 - CPUx L1 and logic lost + GIC lost: MPUSS OSWR + * 3 - CPUx L1 and logic lost + GIC + L2 lost: MPUSS OFF + * @return: This function never returns for CPU OFF and DORMANT power states. + * Post WFI, CPU transitions to DORMANT or OFF power state and on wake-up + * from this follows a full CPU reset path via ROM code to CPU restore code. + * The restore function pointer is stored at CPUx_WAKEUP_NS_PA_ADDR_OFFSET. + * It returns to the caller for CPU INACTIVE and ON power states or in case + * CPU failed to transition to targeted OFF/DORMANT state. + */ +ENTRY(omap4_finish_suspend) + stmfd sp!, {lr} + cmp r0, #0x0 + beq do_WFI @ No lowpower state, jump to WFI + + /* + * Flush all data from the L1 data cache before disabling + * SCTLR.C bit. + */ + bl omap4_get_sar_ram_base + ldr r9, [r0, #OMAP_TYPE_OFFSET] + cmp r9, #0x1 @ Check for HS device + bne skip_secure_l1_clean + mov r0, #SCU_PM_NORMAL + mov r1, #0xFF @ clean seucre L1 + stmfd r13!, {r4-r12, r14} + ldr r12, =OMAP4_MON_SCU_PWR_INDEX + DO_SMC + ldmfd r13!, {r4-r12, r14} +skip_secure_l1_clean: + bl v7_flush_dcache_all + + /* + * Clear the SCTLR.C bit to prevent further data cache + * allocation. Clearing SCTLR.C would make all the data accesses + * strongly ordered and would not hit the cache. + */ + mrc p15, 0, r0, c1, c0, 0 + bic r0, r0, #(1 << 2) @ Disable the C bit + mcr p15, 0, r0, c1, c0, 0 + isb + + /* + * Invalidate L1 data cache. Even though only invalidate is + * necessary exported flush API is used here. Doing clean + * on already clean cache would be almost NOP. + */ + bl v7_flush_dcache_all + + /* + * Switch the CPU from Symmetric Multiprocessing (SMP) mode + * to AsymmetricMultiprocessing (AMP) mode by programming + * the SCU power status to DORMANT or OFF mode. + * This enables the CPU to be taken out of coherency by + * preventing the CPU from receiving cache, TLB, or BTB + * maintenance operations broadcast by other CPUs in the cluster. + */ + bl omap4_get_sar_ram_base + mov r8, r0 + ldr r9, [r8, #OMAP_TYPE_OFFSET] + cmp r9, #0x1 @ Check for HS device + bne scu_gp_set + mrc p15, 0, r0, c0, c0, 5 @ Read MPIDR + ands r0, r0, #0x0f + ldreq r0, [r8, #SCU_OFFSET0] + ldrne r0, [r8, #SCU_OFFSET1] + mov r1, #0x00 + stmfd r13!, {r4-r12, r14} + ldr r12, =OMAP4_MON_SCU_PWR_INDEX + DO_SMC + ldmfd r13!, {r4-r12, r14} + b skip_scu_gp_set +scu_gp_set: + mrc p15, 0, r0, c0, c0, 5 @ Read MPIDR + ands r0, r0, #0x0f + ldreq r1, [r8, #SCU_OFFSET0] + ldrne r1, [r8, #SCU_OFFSET1] + bl omap4_get_scu_base + bl scu_power_mode +skip_scu_gp_set: + mrc p15, 0, r0, c1, c1, 2 @ Read NSACR data + tst r0, #(1 << 18) + mrcne p15, 0, r0, c1, c0, 1 + bicne r0, r0, #(1 << 6) @ Disable SMP bit + mcrne p15, 0, r0, c1, c0, 1 + isb + dsb +#ifdef CONFIG_CACHE_L2X0 + /* + * Clean and invalidate the L2 cache. + * Common cache-l2x0.c functions can't be used here since it + * uses spinlocks. We are out of coherency here with data cache + * disabled. The spinlock implementation uses exclusive load/store + * instruction which can fail without data cache being enabled. + * OMAP4 hardware doesn't support exclusive monitor which can + * overcome exclusive access issue. Because of this, CPU can + * lead to deadlock. + */ + bl omap4_get_sar_ram_base + mov r8, r0 + mrc p15, 0, r5, c0, c0, 5 @ Read MPIDR + ands r5, r5, #0x0f + ldreq r0, [r8, #L2X0_SAVE_OFFSET0] @ Retrieve L2 state from SAR + ldrne r0, [r8, #L2X0_SAVE_OFFSET1] @ memory. + cmp r0, #3 + bne do_WFI +#ifdef CONFIG_PL310_ERRATA_727915 + mov r0, #0x03 + mov r12, #OMAP4_MON_L2X0_DBG_CTRL_INDEX + DO_SMC +#endif + bl omap4_get_l2cache_base + mov r2, r0 + ldr r0, =0xffff + str r0, [r2, #L2X0_CLEAN_INV_WAY] +wait: + ldr r0, [r2, #L2X0_CLEAN_INV_WAY] + ldr r1, =0xffff + ands r0, r0, r1 + bne wait +#ifdef CONFIG_PL310_ERRATA_727915 + mov r0, #0x00 + mov r12, #OMAP4_MON_L2X0_DBG_CTRL_INDEX + DO_SMC +#endif +l2x_sync: + bl omap4_get_l2cache_base + mov r2, r0 + mov r0, #0x0 + str r0, [r2, #L2X0_CACHE_SYNC] +sync: + ldr r0, [r2, #L2X0_CACHE_SYNC] + ands r0, r0, #0x1 + bne sync +#endif + +do_WFI: + bl omap_do_wfi + + /* + * CPU is here when it failed to enter OFF/DORMANT or + * no low power state was attempted. + */ + mrc p15, 0, r0, c1, c0, 0 + tst r0, #(1 << 2) @ Check C bit enabled? + orreq r0, r0, #(1 << 2) @ Enable the C bit + mcreq p15, 0, r0, c1, c0, 0 + isb + + /* + * Ensure the CPU power state is set to NORMAL in + * SCU power state so that CPU is back in coherency. + * In non-coherent mode CPU can lock-up and lead to + * system deadlock. + */ + mrc p15, 0, r0, c1, c0, 1 + tst r0, #(1 << 6) @ Check SMP bit enabled? + orreq r0, r0, #(1 << 6) + mcreq p15, 0, r0, c1, c0, 1 + isb + bl omap4_get_sar_ram_base + mov r8, r0 + ldr r9, [r8, #OMAP_TYPE_OFFSET] + cmp r9, #0x1 @ Check for HS device + bne scu_gp_clear + mov r0, #SCU_PM_NORMAL + mov r1, #0x00 + stmfd r13!, {r4-r12, r14} + ldr r12, =OMAP4_MON_SCU_PWR_INDEX + DO_SMC + ldmfd r13!, {r4-r12, r14} + b skip_scu_gp_clear +scu_gp_clear: + bl omap4_get_scu_base + mov r1, #SCU_PM_NORMAL + bl scu_power_mode +skip_scu_gp_clear: + isb + dsb + ldmfd sp!, {pc} +ENDPROC(omap4_finish_suspend) + +/* + * ============================ + * == CPU resume entry point == + * ============================ + * + * void omap4_cpu_resume(void) + * + * ROM code jumps to this function while waking up from CPU + * OFF or DORMANT state. Physical address of the function is + * stored in the SAR RAM while entering to OFF or DORMANT mode. + * The restore function pointer is stored at CPUx_WAKEUP_NS_PA_ADDR_OFFSET. + */ +ENTRY(omap4_cpu_resume) + /* + * Configure ACTRL and enable NS SMP bit access on CPU1 on HS device. + * OMAP44XX EMU/HS devices - CPU0 SMP bit access is enabled in PPA + * init and for CPU1, a secure PPA API provided. CPU0 must be ON + * while executing NS_SMP API on CPU1 and PPA version must be 1.4.0+. + * OMAP443X GP devices- SMP bit isn't accessible. + * OMAP446X GP devices - SMP bit access is enabled on both CPUs. + */ + ldr r8, =OMAP44XX_SAR_RAM_BASE + ldr r9, [r8, #OMAP_TYPE_OFFSET] + cmp r9, #0x1 @ Skip if GP device + bne skip_ns_smp_enable + mrc p15, 0, r0, c0, c0, 5 + ands r0, r0, #0x0f + beq skip_ns_smp_enable +ppa_actrl_retry: + mov r0, #OMAP4_PPA_CPU_ACTRL_SMP_INDEX + adr r3, ppa_zero_params @ Pointer to parameters + mov r1, #0x0 @ Process ID + mov r2, #0x4 @ Flag + mov r6, #0xff + mov r12, #0x00 @ Secure Service ID + DO_SMC + cmp r0, #0x0 @ API returns 0 on success. + beq enable_smp_bit + b ppa_actrl_retry +enable_smp_bit: + mrc p15, 0, r0, c1, c0, 1 + tst r0, #(1 << 6) @ Check SMP bit enabled? + orreq r0, r0, #(1 << 6) + mcreq p15, 0, r0, c1, c0, 1 + isb +skip_ns_smp_enable: +#ifdef CONFIG_CACHE_L2X0 + /* + * Restore the L2 AUXCTRL and enable the L2 cache. + * OMAP4_MON_L2X0_AUXCTRL_INDEX = Program the L2X0 AUXCTRL + * OMAP4_MON_L2X0_CTRL_INDEX = Enable the L2 using L2X0 CTRL + * register r0 contains value to be programmed. + * L2 cache is already invalidate by ROM code as part + * of MPUSS OFF wakeup path. + */ + ldr r2, =OMAP44XX_L2CACHE_BASE + ldr r0, [r2, #L2X0_CTRL] + and r0, #0x0f + cmp r0, #1 + beq skip_l2en @ Skip if already enabled + ldr r3, =OMAP44XX_SAR_RAM_BASE + ldr r1, [r3, #OMAP_TYPE_OFFSET] + cmp r1, #0x1 @ Check for HS device + bne set_gp_por + ldr r0, =OMAP4_PPA_L2_POR_INDEX + ldr r1, =OMAP44XX_SAR_RAM_BASE + ldr r4, [r1, #L2X0_PREFETCH_CTRL_OFFSET] + adr r3, ppa_por_params + str r4, [r3, #0x04] + mov r1, #0x0 @ Process ID + mov r2, #0x4 @ Flag + mov r6, #0xff + mov r12, #0x00 @ Secure Service ID + DO_SMC + b set_aux_ctrl +set_gp_por: + ldr r1, =OMAP44XX_SAR_RAM_BASE + ldr r0, [r1, #L2X0_PREFETCH_CTRL_OFFSET] + ldr r12, =OMAP4_MON_L2X0_PREFETCH_INDEX @ Setup L2 PREFETCH + DO_SMC +set_aux_ctrl: + ldr r1, =OMAP44XX_SAR_RAM_BASE + ldr r0, [r1, #L2X0_AUXCTRL_OFFSET] + ldr r12, =OMAP4_MON_L2X0_AUXCTRL_INDEX @ Setup L2 AUXCTRL + DO_SMC + mov r0, #0x1 + ldr r12, =OMAP4_MON_L2X0_CTRL_INDEX @ Enable L2 cache + DO_SMC +skip_l2en: +#endif + + b cpu_resume @ Jump to generic resume +ENDPROC(omap4_cpu_resume) +#endif + +#ifndef CONFIG_OMAP4_ERRATA_I688 +ENTRY(omap_bus_sync) + mov pc, lr +ENDPROC(omap_bus_sync) +#endif + +ENTRY(omap_do_wfi) + stmfd sp!, {lr} + /* Drain interconnect write buffers. */ + bl omap_bus_sync + + /* + * Execute an ISB instruction to ensure that all of the + * CP15 register changes have been committed. + */ + isb + + /* + * Execute a barrier instruction to ensure that all cache, + * TLB and branch predictor maintenance operations issued + * by any CPU in the cluster have completed. + */ + dsb + dmb + + /* + * Execute a WFI instruction and wait until the + * STANDBYWFI output is asserted to indicate that the + * CPU is in idle and low power state. CPU can specualatively + * prefetch the instructions so add NOPs after WFI. Sixteen + * NOPs as per Cortex-A9 pipeline. + */ + wfi @ Wait For Interrupt + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + + ldmfd sp!, {pc} +ENDPROC(omap_do_wfi) diff --git a/arch/arm/mach-omap2/usb-host.c b/arch/arm/mach-omap2/usb-host.c index 89ae29847c5..771dc781b74 100644 --- a/arch/arm/mach-omap2/usb-host.c +++ b/arch/arm/mach-omap2/usb-host.c @@ -28,51 +28,28 @@ #include <mach/hardware.h> #include <mach/irqs.h> #include <plat/usb.h> +#include <plat/omap_device.h> #include "mux.h" #ifdef CONFIG_MFD_OMAP_USB_HOST -#define OMAP_USBHS_DEVICE "usbhs-omap" - -static struct resource usbhs_resources[] = { - { - .name = "uhh", - .flags = IORESOURCE_MEM, - }, - { - .name = "tll", - .flags = IORESOURCE_MEM, - }, - { - .name = "ehci", - .flags = IORESOURCE_MEM, - }, - { - .name = "ehci-irq", - .flags = IORESOURCE_IRQ, - }, - { - .name = "ohci", - .flags = IORESOURCE_MEM, - }, - { - .name = "ohci-irq", - .flags = IORESOURCE_IRQ, - } -}; - -static struct platform_device usbhs_device = { - .name = OMAP_USBHS_DEVICE, - .id = 0, - .num_resources = ARRAY_SIZE(usbhs_resources), - .resource = usbhs_resources, -}; +#define OMAP_USBHS_DEVICE "usbhs_omap" +#define USBHS_UHH_HWMODNAME "usb_host_hs" +#define USBHS_TLL_HWMODNAME "usb_tll_hs" static struct usbhs_omap_platform_data usbhs_data; static struct ehci_hcd_omap_platform_data ehci_data; static struct ohci_hcd_omap_platform_data ohci_data; +static struct omap_device_pm_latency omap_uhhtll_latency[] = { + { + .deactivate_func = omap_device_idle_hwmods, + .activate_func = omap_device_enable_hwmods, + .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST, + }, +}; + /* MUX settings for EHCI pins */ /* * setup_ehci_io_mux - initialize IO pad mux for USBHOST @@ -508,7 +485,10 @@ static void setup_4430ohci_io_mux(const enum usbhs_omap_port_mode *port_mode) void __init usbhs_init(const struct usbhs_omap_board_data *pdata) { - int i; + struct omap_hwmod *oh[2]; + struct omap_device *od; + int bus_id = -1; + int i; for (i = 0; i < OMAP3_HS_USB_PORTS; i++) { usbhs_data.port_mode[i] = pdata->port_mode[i]; @@ -523,44 +503,34 @@ void __init usbhs_init(const struct usbhs_omap_board_data *pdata) usbhs_data.ohci_data = &ohci_data; if (cpu_is_omap34xx()) { - usbhs_resources[0].start = OMAP34XX_UHH_CONFIG_BASE; - usbhs_resources[0].end = OMAP34XX_UHH_CONFIG_BASE + SZ_1K - 1; - usbhs_resources[1].start = OMAP34XX_USBTLL_BASE; - usbhs_resources[1].end = OMAP34XX_USBTLL_BASE + SZ_4K - 1; - usbhs_resources[2].start = OMAP34XX_EHCI_BASE; - usbhs_resources[2].end = OMAP34XX_EHCI_BASE + SZ_1K - 1; - usbhs_resources[3].start = INT_34XX_EHCI_IRQ; - usbhs_resources[4].start = OMAP34XX_OHCI_BASE; - usbhs_resources[4].end = OMAP34XX_OHCI_BASE + SZ_1K - 1; - usbhs_resources[5].start = INT_34XX_OHCI_IRQ; setup_ehci_io_mux(pdata->port_mode); setup_ohci_io_mux(pdata->port_mode); } else if (cpu_is_omap44xx()) { - usbhs_resources[0].start = OMAP44XX_UHH_CONFIG_BASE; - usbhs_resources[0].end = OMAP44XX_UHH_CONFIG_BASE + SZ_1K - 1; - usbhs_resources[1].start = OMAP44XX_USBTLL_BASE; - usbhs_resources[1].end = OMAP44XX_USBTLL_BASE + SZ_4K - 1; - usbhs_resources[2].start = OMAP44XX_HSUSB_EHCI_BASE; - usbhs_resources[2].end = OMAP44XX_HSUSB_EHCI_BASE + SZ_1K - 1; - usbhs_resources[3].start = OMAP44XX_IRQ_EHCI; - usbhs_resources[4].start = OMAP44XX_HSUSB_OHCI_BASE; - usbhs_resources[4].end = OMAP44XX_HSUSB_OHCI_BASE + SZ_1K - 1; - usbhs_resources[5].start = OMAP44XX_IRQ_OHCI; setup_4430ehci_io_mux(pdata->port_mode); setup_4430ohci_io_mux(pdata->port_mode); } - if (platform_device_add_data(&usbhs_device, - &usbhs_data, sizeof(usbhs_data)) < 0) { - printk(KERN_ERR "USBHS platform_device_add_data failed\n"); - goto init_end; + oh[0] = omap_hwmod_lookup(USBHS_UHH_HWMODNAME); + if (!oh[0]) { + pr_err("Could not look up %s\n", USBHS_UHH_HWMODNAME); + return; } - if (platform_device_register(&usbhs_device) < 0) - printk(KERN_ERR "USBHS platform_device_register failed\n"); + oh[1] = omap_hwmod_lookup(USBHS_TLL_HWMODNAME); + if (!oh[1]) { + pr_err("Could not look up %s\n", USBHS_TLL_HWMODNAME); + return; + } -init_end: - return; + od = omap_device_build_ss(OMAP_USBHS_DEVICE, bus_id, oh, 2, + (void *)&usbhs_data, sizeof(usbhs_data), + omap_uhhtll_latency, + ARRAY_SIZE(omap_uhhtll_latency), false); + if (IS_ERR(od)) { + pr_err("Could not build hwmod devices %s,%s\n", + USBHS_UHH_HWMODNAME, USBHS_TLL_HWMODNAME); + return; + } } #else @@ -570,5 +540,3 @@ void __init usbhs_init(const struct usbhs_omap_board_data *pdata) } #endif - - diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c index 267975086a7..8d5ed775dd5 100644 --- a/arch/arm/mach-omap2/usb-musb.c +++ b/arch/arm/mach-omap2/usb-musb.c @@ -93,6 +93,9 @@ void __init usb_musb_init(struct omap_musb_board_data *musb_board_data) if (cpu_is_omap3517() || cpu_is_omap3505()) { oh_name = "am35x_otg_hs"; name = "musb-am35x"; + } else if (cpu_is_ti81xx()) { + oh_name = "usb_otg_hs"; + name = "musb-ti81xx"; } else { oh_name = "usb_otg_hs"; name = "musb-omap2430"; diff --git a/arch/arm/mach-omap2/voltagedomains3xxx_data.c b/arch/arm/mach-omap2/voltagedomains3xxx_data.c index 474559d5b07..c005e2f5e38 100644 --- a/arch/arm/mach-omap2/voltagedomains3xxx_data.c +++ b/arch/arm/mach-omap2/voltagedomains3xxx_data.c @@ -31,6 +31,14 @@ * VDD data */ +/* OMAP3-common voltagedomain data */ + +static struct voltagedomain omap3_voltdm_wkup = { + .name = "wakeup", +}; + +/* 34xx/36xx voltagedomain data */ + static const struct omap_vfsm_instance omap3_vdd1_vfsm = { .voltsetup_reg = OMAP3_PRM_VOLTSETUP1_OFFSET, .voltsetup_mask = OMAP3430_SETUP_TIME1_MASK, @@ -63,10 +71,6 @@ static struct voltagedomain omap3_voltdm_core = { .vp = &omap3_vp_core, }; -static struct voltagedomain omap3_voltdm_wkup = { - .name = "wakeup", -}; - static struct voltagedomain *voltagedomains_omap3[] __initdata = { &omap3_voltdm_mpu, &omap3_voltdm_core, @@ -74,11 +78,30 @@ static struct voltagedomain *voltagedomains_omap3[] __initdata = { NULL, }; +/* AM35xx voltagedomain data */ + +static struct voltagedomain am35xx_voltdm_mpu = { + .name = "mpu_iva", +}; + +static struct voltagedomain am35xx_voltdm_core = { + .name = "core", +}; + +static struct voltagedomain *voltagedomains_am35xx[] __initdata = { + &am35xx_voltdm_mpu, + &am35xx_voltdm_core, + &omap3_voltdm_wkup, + NULL, +}; + + static const char *sys_clk_name __initdata = "sys_ck"; void __init omap3xxx_voltagedomains_init(void) { struct voltagedomain *voltdm; + struct voltagedomain **voltdms; int i; /* @@ -93,8 +116,13 @@ void __init omap3xxx_voltagedomains_init(void) omap3_voltdm_core.volt_data = omap34xx_vddcore_volt_data; } - for (i = 0; voltdm = voltagedomains_omap3[i], voltdm; i++) + if (cpu_is_omap3517() || cpu_is_omap3505()) + voltdms = voltagedomains_am35xx; + else + voltdms = voltagedomains_omap3; + + for (i = 0; voltdm = voltdms[i], voltdm; i++) voltdm->sys_clk.name = sys_clk_name; - voltdm_init(voltagedomains_omap3); + voltdm_init(voltdms); }; diff --git a/arch/arm/mach-orion5x/addr-map.c b/arch/arm/mach-orion5x/addr-map.c index 5ceafdccc45..3638e5c12b7 100644 --- a/arch/arm/mach-orion5x/addr-map.c +++ b/arch/arm/mach-orion5x/addr-map.c @@ -14,8 +14,8 @@ #include <linux/init.h> #include <linux/mbus.h> #include <linux/io.h> -#include <linux/errno.h> #include <mach/hardware.h> +#include <plat/addr-map.h> #include "common.h" /* @@ -41,7 +41,6 @@ /* * Generic Address Decode Windows bit settings */ -#define TARGET_DDR 0 #define TARGET_DEV_BUS 1 #define TARGET_PCI 3 #define TARGET_PCIE 4 @@ -57,27 +56,10 @@ #define ATTR_DEV_BOOT 0xf #define ATTR_SRAM 0x0 -/* - * Helpers to get DDR bank info - */ -#define ORION5X_DDR_REG(x) (ORION5X_DDR_VIRT_BASE | (x)) -#define DDR_BASE_CS(n) ORION5X_DDR_REG(0x1500 + ((n) << 3)) -#define DDR_SIZE_CS(n) ORION5X_DDR_REG(0x1504 + ((n) << 3)) - -/* - * CPU Address Decode Windows registers - */ -#define ORION5X_BRIDGE_REG(x) (ORION5X_BRIDGE_VIRT_BASE | (x)) -#define CPU_WIN_CTRL(n) ORION5X_BRIDGE_REG(0x000 | ((n) << 4)) -#define CPU_WIN_BASE(n) ORION5X_BRIDGE_REG(0x004 | ((n) << 4)) -#define CPU_WIN_REMAP_LO(n) ORION5X_BRIDGE_REG(0x008 | ((n) << 4)) -#define CPU_WIN_REMAP_HI(n) ORION5X_BRIDGE_REG(0x00c | ((n) << 4)) - - -struct mbus_dram_target_info orion5x_mbus_dram_info; static int __initdata win_alloc_count; -static int __init orion5x_cpu_win_can_remap(int win) +static int __init cpu_win_can_remap(const struct orion_addr_map_cfg *cfg, + const int win) { u32 dev, rev; @@ -91,116 +73,82 @@ static int __init orion5x_cpu_win_can_remap(int win) return 0; } -static int __init setup_cpu_win(int win, u32 base, u32 size, - u8 target, u8 attr, int remap) -{ - if (win >= 8) { - printk(KERN_ERR "setup_cpu_win: trying to allocate " - "window %d\n", win); - return -ENOSPC; - } - - writel(base & 0xffff0000, CPU_WIN_BASE(win)); - writel(((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1, - CPU_WIN_CTRL(win)); - - if (orion5x_cpu_win_can_remap(win)) { - if (remap < 0) - remap = base; - - writel(remap & 0xffff0000, CPU_WIN_REMAP_LO(win)); - writel(0, CPU_WIN_REMAP_HI(win)); - } - return 0; -} - -void __init orion5x_setup_cpu_mbus_bridge(void) -{ - int i; - int cs; +/* + * Description of the windows needed by the platform code + */ +static struct __initdata orion_addr_map_cfg addr_map_cfg = { + .num_wins = 8, + .cpu_win_can_remap = cpu_win_can_remap, + .bridge_virt_base = ORION5X_BRIDGE_VIRT_BASE, +}; +static const struct __initdata orion_addr_map_info addr_map_info[] = { /* - * First, disable and clear windows. + * Setup windows for PCI+PCIe IO+MEM space. */ - for (i = 0; i < 8; i++) { - writel(0, CPU_WIN_BASE(i)); - writel(0, CPU_WIN_CTRL(i)); - if (orion5x_cpu_win_can_remap(i)) { - writel(0, CPU_WIN_REMAP_LO(i)); - writel(0, CPU_WIN_REMAP_HI(i)); - } - } + { 0, ORION5X_PCIE_IO_PHYS_BASE, ORION5X_PCIE_IO_SIZE, + TARGET_PCIE, ATTR_PCIE_IO, ORION5X_PCIE_IO_BUS_BASE + }, + { 1, ORION5X_PCI_IO_PHYS_BASE, ORION5X_PCI_IO_SIZE, + TARGET_PCI, ATTR_PCI_IO, ORION5X_PCI_IO_BUS_BASE + }, + { 2, ORION5X_PCIE_MEM_PHYS_BASE, ORION5X_PCIE_MEM_SIZE, + TARGET_PCIE, ATTR_PCIE_MEM, -1 + }, + { 3, ORION5X_PCI_MEM_PHYS_BASE, ORION5X_PCI_MEM_SIZE, + TARGET_PCI, ATTR_PCI_MEM, -1 + }, + /* End marker */ + { -1, 0, 0, 0, 0, 0 } +}; +void __init orion5x_setup_cpu_mbus_bridge(void) +{ /* - * Setup windows for PCI+PCIe IO+MEM space. + * Disable, clear and configure windows. */ - setup_cpu_win(0, ORION5X_PCIE_IO_PHYS_BASE, ORION5X_PCIE_IO_SIZE, - TARGET_PCIE, ATTR_PCIE_IO, ORION5X_PCIE_IO_BUS_BASE); - setup_cpu_win(1, ORION5X_PCI_IO_PHYS_BASE, ORION5X_PCI_IO_SIZE, - TARGET_PCI, ATTR_PCI_IO, ORION5X_PCI_IO_BUS_BASE); - setup_cpu_win(2, ORION5X_PCIE_MEM_PHYS_BASE, ORION5X_PCIE_MEM_SIZE, - TARGET_PCIE, ATTR_PCIE_MEM, -1); - setup_cpu_win(3, ORION5X_PCI_MEM_PHYS_BASE, ORION5X_PCI_MEM_SIZE, - TARGET_PCI, ATTR_PCI_MEM, -1); + orion_config_wins(&addr_map_cfg, addr_map_info); win_alloc_count = 4; /* * Setup MBUS dram target info. */ - orion5x_mbus_dram_info.mbus_dram_target_id = TARGET_DDR; - - for (i = 0, cs = 0; i < 4; i++) { - u32 base = readl(DDR_BASE_CS(i)); - u32 size = readl(DDR_SIZE_CS(i)); - - /* - * Chip select enabled? - */ - if (size & 1) { - struct mbus_dram_window *w; - - w = &orion5x_mbus_dram_info.cs[cs++]; - w->cs_index = i; - w->mbus_attr = 0xf & ~(1 << i); - w->base = base & 0xffff0000; - w->size = (size | 0x0000ffff) + 1; - } - } - orion5x_mbus_dram_info.num_cs = cs; + orion_setup_cpu_mbus_target(&addr_map_cfg, ORION5X_DDR_WINDOW_CPU_BASE); } void __init orion5x_setup_dev_boot_win(u32 base, u32 size) { - setup_cpu_win(win_alloc_count++, base, size, - TARGET_DEV_BUS, ATTR_DEV_BOOT, -1); + orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, base, size, + TARGET_DEV_BUS, ATTR_DEV_BOOT, -1); } void __init orion5x_setup_dev0_win(u32 base, u32 size) { - setup_cpu_win(win_alloc_count++, base, size, - TARGET_DEV_BUS, ATTR_DEV_CS0, -1); + orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, base, size, + TARGET_DEV_BUS, ATTR_DEV_CS0, -1); } void __init orion5x_setup_dev1_win(u32 base, u32 size) { - setup_cpu_win(win_alloc_count++, base, size, - TARGET_DEV_BUS, ATTR_DEV_CS1, -1); + orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, base, size, + TARGET_DEV_BUS, ATTR_DEV_CS1, -1); } void __init orion5x_setup_dev2_win(u32 base, u32 size) { - setup_cpu_win(win_alloc_count++, base, size, - TARGET_DEV_BUS, ATTR_DEV_CS2, -1); + orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, base, size, + TARGET_DEV_BUS, ATTR_DEV_CS2, -1); } void __init orion5x_setup_pcie_wa_win(u32 base, u32 size) { - setup_cpu_win(win_alloc_count++, base, size, - TARGET_PCIE, ATTR_PCIE_WA, -1); + orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, base, size, + TARGET_PCIE, ATTR_PCIE_WA, -1); } -int __init orion5x_setup_sram_win(void) +void __init orion5x_setup_sram_win(void) { - return setup_cpu_win(win_alloc_count++, ORION5X_SRAM_PHYS_BASE, - ORION5X_SRAM_SIZE, TARGET_SRAM, ATTR_SRAM, -1); + orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, + ORION5X_SRAM_PHYS_BASE, ORION5X_SRAM_SIZE, + TARGET_SRAM, ATTR_SRAM, -1); } diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c index 41127e80cc1..0e28bae20bd 100644 --- a/arch/arm/mach-orion5x/common.c +++ b/arch/arm/mach-orion5x/common.c @@ -15,7 +15,6 @@ #include <linux/platform_device.h> #include <linux/dma-mapping.h> #include <linux/serial_8250.h> -#include <linux/mbus.h> #include <linux/mv643xx_i2c.h> #include <linux/ata_platform.h> #include <linux/delay.h> @@ -32,6 +31,7 @@ #include <plat/orion_nand.h> #include <plat/time.h> #include <plat/common.h> +#include <plat/addr-map.h> #include "common.h" /***************************************************************************** @@ -72,8 +72,7 @@ void __init orion5x_map_io(void) ****************************************************************************/ void __init orion5x_ehci0_init(void) { - orion_ehci_init(&orion5x_mbus_dram_info, - ORION5X_USB0_PHYS_BASE, IRQ_ORION5X_USB0_CTRL); + orion_ehci_init(ORION5X_USB0_PHYS_BASE, IRQ_ORION5X_USB0_CTRL); } @@ -82,8 +81,7 @@ void __init orion5x_ehci0_init(void) ****************************************************************************/ void __init orion5x_ehci1_init(void) { - orion_ehci_1_init(&orion5x_mbus_dram_info, - ORION5X_USB1_PHYS_BASE, IRQ_ORION5X_USB1_CTRL); + orion_ehci_1_init(ORION5X_USB1_PHYS_BASE, IRQ_ORION5X_USB1_CTRL); } @@ -92,7 +90,7 @@ void __init orion5x_ehci1_init(void) ****************************************************************************/ void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data) { - orion_ge00_init(eth_data, &orion5x_mbus_dram_info, + orion_ge00_init(eth_data, ORION5X_ETH_PHYS_BASE, IRQ_ORION5X_ETH_SUM, IRQ_ORION5X_ETH_ERR, orion5x_tclk); } @@ -122,8 +120,7 @@ void __init orion5x_i2c_init(void) ****************************************************************************/ void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data) { - orion_sata_init(sata_data, &orion5x_mbus_dram_info, - ORION5X_SATA_PHYS_BASE, IRQ_ORION5X_SATA); + orion_sata_init(sata_data, ORION5X_SATA_PHYS_BASE, IRQ_ORION5X_SATA); } @@ -159,8 +156,7 @@ void __init orion5x_uart1_init(void) ****************************************************************************/ void __init orion5x_xor_init(void) { - orion_xor0_init(&orion5x_mbus_dram_info, - ORION5X_XOR_PHYS_BASE, + orion_xor0_init(ORION5X_XOR_PHYS_BASE, ORION5X_XOR_PHYS_BASE + 0x200, IRQ_ORION5X_XOR0, IRQ_ORION5X_XOR1); } @@ -170,12 +166,7 @@ void __init orion5x_xor_init(void) ****************************************************************************/ static void __init orion5x_crypto_init(void) { - int ret; - - ret = orion5x_setup_sram_win(); - if (ret) - return; - + orion5x_setup_sram_win(); orion_crypto_init(ORION5X_CRYPTO_PHYS_BASE, ORION5X_SRAM_PHYS_BASE, SZ_8K, IRQ_ORION5X_CESA); } diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h index 37ef18de61b..d2513ac79ff 100644 --- a/arch/arm/mach-orion5x/common.h +++ b/arch/arm/mach-orion5x/common.h @@ -20,14 +20,13 @@ extern struct sys_timer orion5x_timer; * functions to map its interfaces and by the machine-setup to map its on- * board devices. Details in /mach-orion/addr-map.c */ -extern struct mbus_dram_target_info orion5x_mbus_dram_info; void orion5x_setup_cpu_mbus_bridge(void); void orion5x_setup_dev_boot_win(u32 base, u32 size); void orion5x_setup_dev0_win(u32 base, u32 size); void orion5x_setup_dev1_win(u32 base, u32 size); void orion5x_setup_dev2_win(u32 base, u32 size); void orion5x_setup_pcie_wa_win(u32 base, u32 size); -int orion5x_setup_sram_win(void); +void orion5x_setup_sram_win(void); void orion5x_ehci0_init(void); void orion5x_ehci1_init(void); diff --git a/arch/arm/mach-orion5x/include/mach/orion5x.h b/arch/arm/mach-orion5x/include/mach/orion5x.h index 0a28bbc7689..2745f5d95b3 100644 --- a/arch/arm/mach-orion5x/include/mach/orion5x.h +++ b/arch/arm/mach-orion5x/include/mach/orion5x.h @@ -69,7 +69,7 @@ ******************************************************************************/ #define ORION5X_DDR_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x00000) - +#define ORION5X_DDR_WINDOW_CPU_BASE (ORION5X_DDR_VIRT_BASE | 0x1500) #define ORION5X_DEV_BUS_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x10000) #define ORION5X_DEV_BUS_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x10000) #define ORION5X_DEV_BUS_REG(x) (ORION5X_DEV_BUS_VIRT_BASE | (x)) diff --git a/arch/arm/mach-orion5x/mpp.c b/arch/arm/mach-orion5x/mpp.c index b6ddd7a5db6..5b70026f478 100644 --- a/arch/arm/mach-orion5x/mpp.c +++ b/arch/arm/mach-orion5x/mpp.c @@ -10,7 +10,6 @@ #include <linux/kernel.h> #include <linux/init.h> -#include <linux/mbus.h> #include <linux/io.h> #include <mach/hardware.h> #include <plat/mpp.h> diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c index bc4a920e26e..09a045f0c40 100644 --- a/arch/arm/mach-orion5x/pci.c +++ b/arch/arm/mach-orion5x/pci.c @@ -18,6 +18,7 @@ #include <asm/irq.h> #include <asm/mach/pci.h> #include <plat/pcie.h> +#include <plat/addr-map.h> #include "common.h" /***************************************************************************** @@ -145,7 +146,7 @@ static int __init pcie_setup(struct pci_sys_data *sys) /* * Generic PCIe unit setup. */ - orion_pcie_setup(PCIE_BASE, &orion5x_mbus_dram_info); + orion_pcie_setup(PCIE_BASE); /* * Check whether to apply Orion-1/Orion-NAS PCIe config @@ -176,7 +177,7 @@ static int __init pcie_setup(struct pci_sys_data *sys) res[0].end = res[0].start + ORION5X_PCIE_IO_SIZE - 1; if (request_resource(&ioport_resource, &res[0])) panic("Request PCIe IO resource failed\n"); - sys->resource[0] = &res[0]; + pci_add_resource(&sys->resources, &res[0]); /* * IORESOURCE_MEM @@ -187,9 +188,8 @@ static int __init pcie_setup(struct pci_sys_data *sys) res[1].end = res[1].start + ORION5X_PCIE_MEM_SIZE - 1; if (request_resource(&iomem_resource, &res[1])) panic("Request PCIe Memory resource failed\n"); - sys->resource[1] = &res[1]; + pci_add_resource(&sys->resources, &res[1]); - sys->resource[2] = NULL; sys->io_offset = 0; return 1; @@ -477,7 +477,7 @@ static int __init pci_setup(struct pci_sys_data *sys) /* * Point PCI unit MBUS decode windows to DRAM space. */ - orion5x_setup_pci_wins(&orion5x_mbus_dram_info); + orion5x_setup_pci_wins(&orion_mbus_dram_info); /* * Master + Slave enable @@ -505,7 +505,7 @@ static int __init pci_setup(struct pci_sys_data *sys) res[0].end = res[0].start + ORION5X_PCI_IO_SIZE - 1; if (request_resource(&ioport_resource, &res[0])) panic("Request PCI IO resource failed\n"); - sys->resource[0] = &res[0]; + pci_add_resource(&sys->resources, &res[0]); /* * IORESOURCE_MEM @@ -516,9 +516,8 @@ static int __init pci_setup(struct pci_sys_data *sys) res[1].end = res[1].start + ORION5X_PCI_MEM_SIZE - 1; if (request_resource(&iomem_resource, &res[1])) panic("Request PCI Memory resource failed\n"); - sys->resource[1] = &res[1]; + pci_add_resource(&sys->resources, &res[1]); - sys->resource[2] = NULL; sys->io_offset = 0; return 1; @@ -579,9 +578,11 @@ struct pci_bus __init *orion5x_pci_sys_scan_bus(int nr, struct pci_sys_data *sys struct pci_bus *bus; if (nr == 0) { - bus = pci_scan_bus(sys->busnr, &pcie_ops, sys); + bus = pci_scan_root_bus(NULL, sys->busnr, &pcie_ops, sys, + &sys->resources); } else if (nr == 1 && !orion5x_pci_disabled) { - bus = pci_scan_bus(sys->busnr, &pci_ops, sys); + bus = pci_scan_root_bus(NULL, sys->busnr, &pci_ops, sys, + &sys->resources); } else { bus = NULL; BUG(); diff --git a/arch/arm/mach-picoxcell/Makefile b/arch/arm/mach-picoxcell/Makefile index c550b636348..e5ec4a8d9bc 100644 --- a/arch/arm/mach-picoxcell/Makefile +++ b/arch/arm/mach-picoxcell/Makefile @@ -1,3 +1,2 @@ obj-y := common.o obj-y += time.o -obj-y += io.o diff --git a/arch/arm/mach-picoxcell/common.c b/arch/arm/mach-picoxcell/common.c index ad871bd7b1a..a2e8ae8b582 100644 --- a/arch/arm/mach-picoxcell/common.c +++ b/arch/arm/mach-picoxcell/common.c @@ -7,6 +7,7 @@ * * All enquiries to support@picochip.com */ +#include <linux/delay.h> #include <linux/irq.h> #include <linux/irqdomain.h> #include <linux/of.h> @@ -16,15 +17,49 @@ #include <asm/mach/arch.h> #include <asm/hardware/vic.h> +#include <asm/mach/map.h> #include <mach/map.h> #include <mach/picoxcell_soc.h> #include "common.h" +#define WDT_CTRL_REG_EN_MASK (1 << 0) +#define WDT_CTRL_REG_OFFS (0x00) +#define WDT_TIMEOUT_REG_OFFS (0x04) +static void __iomem *wdt_regs; + +/* + * The machine restart method can be called from an atomic context so we won't + * be able to ioremap the regs then. + */ +static void picoxcell_setup_restart(void) +{ + struct device_node *np = of_find_compatible_node(NULL, NULL, + "snps,dw-apb-wdg"); + if (WARN(!np, "unable to setup watchdog restart")) + return; + + wdt_regs = of_iomap(np, 0); + WARN(!wdt_regs, "failed to remap watchdog regs"); +} + +static struct map_desc io_map __initdata = { + .virtual = PHYS_TO_IO(PICOXCELL_PERIPH_BASE), + .pfn = __phys_to_pfn(PICOXCELL_PERIPH_BASE), + .length = PICOXCELL_PERIPH_LENGTH, + .type = MT_DEVICE, +}; + +static void __init picoxcell_map_io(void) +{ + iotable_init(&io_map, 1); +} + static void __init picoxcell_init_machine(void) { of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); + picoxcell_setup_restart(); } static const char *picoxcell_dt_match[] = { @@ -43,12 +78,27 @@ static void __init picoxcell_init_irq(void) of_irq_init(vic_of_match); } +static void picoxcell_wdt_restart(char mode, const char *cmd) +{ + /* + * Configure the watchdog to reset with the shortest possible timeout + * and give it chance to do the reset. + */ + if (wdt_regs) { + writel_relaxed(WDT_CTRL_REG_EN_MASK, wdt_regs + WDT_CTRL_REG_OFFS); + writel_relaxed(0, wdt_regs + WDT_TIMEOUT_REG_OFFS); + /* No sleeping, possibly atomic. */ + mdelay(500); + } +} + DT_MACHINE_START(PICOXCELL, "Picochip picoXcell") .map_io = picoxcell_map_io, - .nr_irqs = ARCH_NR_IRQS, + .nr_irqs = NR_IRQS_LEGACY, .init_irq = picoxcell_init_irq, .handle_irq = vic_handle_irq, .timer = &picoxcell_timer, .init_machine = picoxcell_init_machine, .dt_compat = picoxcell_dt_match, + .restart = picoxcell_wdt_restart, MACHINE_END diff --git a/arch/arm/mach-picoxcell/common.h b/arch/arm/mach-picoxcell/common.h index 5263f0fa095..83d55ab956a 100644 --- a/arch/arm/mach-picoxcell/common.h +++ b/arch/arm/mach-picoxcell/common.h @@ -13,6 +13,5 @@ #include <asm/mach/time.h> extern struct sys_timer picoxcell_timer; -extern void picoxcell_map_io(void); #endif /* __PICOXCELL_COMMON_H__ */ diff --git a/arch/arm/mach-picoxcell/include/mach/irqs.h b/arch/arm/mach-picoxcell/include/mach/irqs.h index 4d13ed97091..59eac1ee282 100644 --- a/arch/arm/mach-picoxcell/include/mach/irqs.h +++ b/arch/arm/mach-picoxcell/include/mach/irqs.h @@ -1,8 +1,6 @@ /* * Copyright (c) 2011 Picochip Ltd., Jamie Iles * - * This file contains the hardware definitions of the picoXcell SoC devices. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or @@ -16,10 +14,7 @@ #ifndef __MACH_IRQS_H #define __MACH_IRQS_H -#define ARCH_NR_IRQS 64 -#define NR_IRQS (128 + ARCH_NR_IRQS) - -#define IRQ_VIC0_BASE 0 -#define IRQ_VIC1_BASE 32 +/* We dynamically allocate our irq_desc's. */ +#define NR_IRQS 0 #endif /* __MACH_IRQS_H */ diff --git a/arch/arm/mach-picoxcell/include/mach/memory.h b/arch/arm/mach-picoxcell/include/mach/memory.h deleted file mode 100644 index 40a8c178f10..00000000000 --- a/arch/arm/mach-picoxcell/include/mach/memory.h +++ /dev/null @@ -1 +0,0 @@ -/* empty */ diff --git a/arch/arm/mach-picoxcell/io.c b/arch/arm/mach-picoxcell/io.c deleted file mode 100644 index 39e9b9e8cc3..00000000000 --- a/arch/arm/mach-picoxcell/io.c +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Copyright (c) 2011 Picochip Ltd., Jamie Iles - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * All enquiries to support@picochip.com - */ -#include <linux/io.h> -#include <linux/mm.h> -#include <linux/module.h> -#include <linux/of.h> - -#include <asm/mach/map.h> - -#include <mach/map.h> -#include <mach/picoxcell_soc.h> - -#include "common.h" - -void __init picoxcell_map_io(void) -{ - struct map_desc io_map = { - .virtual = PHYS_TO_IO(PICOXCELL_PERIPH_BASE), - .pfn = __phys_to_pfn(PICOXCELL_PERIPH_BASE), - .length = PICOXCELL_PERIPH_LENGTH, - .type = MT_DEVICE, - }; - - iotable_init(&io_map, 1); -} diff --git a/arch/arm/mach-pxa/am200epd.c b/arch/arm/mach-pxa/am200epd.c index 4cb069fd9af..ccdac4b6a46 100644 --- a/arch/arm/mach-pxa/am200epd.c +++ b/arch/arm/mach-pxa/am200epd.c @@ -138,7 +138,7 @@ static void am200_cleanup(struct metronomefb_par *par) { int i; - free_irq(IRQ_GPIO(RDY_GPIO_PIN), par); + free_irq(PXA_GPIO_TO_IRQ(RDY_GPIO_PIN), par); for (i = 0; i < ARRAY_SIZE(gpios); i++) gpio_free(gpios[i]); @@ -292,7 +292,7 @@ static int am200_setup_irq(struct fb_info *info) { int ret; - ret = request_irq(IRQ_GPIO(RDY_GPIO_PIN), am200_handle_irq, + ret = request_irq(PXA_GPIO_TO_IRQ(RDY_GPIO_PIN), am200_handle_irq, IRQF_DISABLED|IRQF_TRIGGER_FALLING, "AM200", info->par); if (ret) diff --git a/arch/arm/mach-pxa/am300epd.c b/arch/arm/mach-pxa/am300epd.c index fa8bad235d9..76c4b949403 100644 --- a/arch/arm/mach-pxa/am300epd.c +++ b/arch/arm/mach-pxa/am300epd.c @@ -176,7 +176,7 @@ static void am300_cleanup(struct broadsheetfb_par *par) { int i; - free_irq(IRQ_GPIO(RDY_GPIO_PIN), par); + free_irq(PXA_GPIO_TO_IRQ(RDY_GPIO_PIN), par); for (i = 0; i < ARRAY_SIZE(gpios); i++) gpio_free(gpios[i]); @@ -240,7 +240,7 @@ static int am300_setup_irq(struct fb_info *info) int ret; struct broadsheetfb_par *par = info->par; - ret = request_irq(IRQ_GPIO(RDY_GPIO_PIN), am300_handle_irq, + ret = request_irq(PXA_GPIO_TO_IRQ(RDY_GPIO_PIN), am300_handle_irq, IRQF_DISABLED|IRQF_TRIGGER_RISING, "AM300", par); if (ret) diff --git a/arch/arm/mach-pxa/balloon3.c b/arch/arm/mach-pxa/balloon3.c index 82514f5c38f..c35456f02ac 100644 --- a/arch/arm/mach-pxa/balloon3.c +++ b/arch/arm/mach-pxa/balloon3.c @@ -13,6 +13,7 @@ * published by the Free Software Foundation. */ +#include <linux/export.h> #include <linux/init.h> #include <linux/platform_device.h> #include <linux/interrupt.h> @@ -179,7 +180,7 @@ static unsigned long balloon3_ac97_pin_config[] __initdata = { }; static struct ucb1400_pdata vpac270_ucb1400_pdata = { - .irq = IRQ_GPIO(BALLOON3_GPIO_CODEC_IRQ), + .irq = PXA_GPIO_TO_IRQ(BALLOON3_GPIO_CODEC_IRQ), }; diff --git a/arch/arm/mach-pxa/capc7117.c b/arch/arm/mach-pxa/capc7117.c index c2f0be040d2..c91727d1fe0 100644 --- a/arch/arm/mach-pxa/capc7117.c +++ b/arch/arm/mach-pxa/capc7117.c @@ -50,8 +50,8 @@ static struct resource capc7117_ide_resources[] = { .flags = IORESOURCE_MEM }, [2] = { - .start = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO76)), - .end = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO76)), + .start = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO76)), + .end = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO76)), .flags = IORESOURCE_IRQ | IRQF_TRIGGER_RISING } }; @@ -80,7 +80,7 @@ static void __init capc7117_ide_init(void) static struct plat_serial8250_port ti16c752_platform_data[] = { [0] = { .mapbase = 0x14000000, - .irq = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO78)), + .irq = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO78)), .irqflags = IRQF_TRIGGER_RISING, .flags = TI16C752_FLAGS, .iotype = UPIO_MEM, @@ -89,7 +89,7 @@ static struct plat_serial8250_port ti16c752_platform_data[] = { }, [1] = { .mapbase = 0x14000040, - .irq = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO79)), + .irq = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO79)), .irqflags = IRQF_TRIGGER_RISING, .flags = TI16C752_FLAGS, .iotype = UPIO_MEM, @@ -98,7 +98,7 @@ static struct plat_serial8250_port ti16c752_platform_data[] = { }, [2] = { .mapbase = 0x14000080, - .irq = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO80)), + .irq = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO80)), .irqflags = IRQF_TRIGGER_RISING, .flags = TI16C752_FLAGS, .iotype = UPIO_MEM, @@ -107,7 +107,7 @@ static struct plat_serial8250_port ti16c752_platform_data[] = { }, [3] = { .mapbase = 0x140000c0, - .irq = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO81)), + .irq = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO81)), .irqflags = IRQF_TRIGGER_RISING, .flags = TI16C752_FLAGS, .iotype = UPIO_MEM, diff --git a/arch/arm/mach-pxa/cm-x270.c b/arch/arm/mach-pxa/cm-x270.c index 13518a70539..431ef56700c 100644 --- a/arch/arm/mach-pxa/cm-x270.c +++ b/arch/arm/mach-pxa/cm-x270.c @@ -33,7 +33,7 @@ /* GPIO IRQ usage */ #define GPIO83_MMC_IRQ (83) -#define CMX270_MMC_IRQ IRQ_GPIO(GPIO83_MMC_IRQ) +#define CMX270_MMC_IRQ PXA_GPIO_TO_IRQ(GPIO83_MMC_IRQ) /* MMC power enable */ #define GPIO105_MMC_POWER (105) @@ -380,7 +380,7 @@ static struct spi_board_info cm_x270_spi_devices[] __initdata = { .modalias = "libertas_spi", .max_speed_hz = 13000000, .bus_num = 2, - .irq = gpio_to_irq(95), + .irq = PXA_GPIO_TO_IRQ(95), .chip_select = 0, .controller_data = &cm_x270_libertas_chip, .platform_data = &cm_x270_libertas_pdata, diff --git a/arch/arm/mach-pxa/cm-x2xx.c b/arch/arm/mach-pxa/cm-x2xx.c index ec170a552c2..8fa4ad27edf 100644 --- a/arch/arm/mach-pxa/cm-x2xx.c +++ b/arch/arm/mach-pxa/cm-x2xx.c @@ -58,8 +58,8 @@ extern void cmx270_init(void); #define CMX255_GPIO_IT8152_IRQ (0) #define CMX270_GPIO_IT8152_IRQ (22) -#define CMX255_ETHIRQ IRQ_GPIO(GPIO22_ETHIRQ) -#define CMX270_ETHIRQ IRQ_GPIO(GPIO10_ETHIRQ) +#define CMX255_ETHIRQ PXA_GPIO_TO_IRQ(GPIO22_ETHIRQ) +#define CMX270_ETHIRQ PXA_GPIO_TO_IRQ(GPIO10_ETHIRQ) #if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE) static struct resource cmx255_dm9000_resource[] = { diff --git a/arch/arm/mach-pxa/cm-x300.c b/arch/arm/mach-pxa/cm-x300.c index 7236974da0b..4b981b82d2a 100644 --- a/arch/arm/mach-pxa/cm-x300.c +++ b/arch/arm/mach-pxa/cm-x300.c @@ -64,7 +64,7 @@ #define GPIO82_MMC_IRQ (82) #define GPIO85_MMC_WP (85) -#define CM_X300_MMC_IRQ IRQ_GPIO(GPIO82_MMC_IRQ) +#define CM_X300_MMC_IRQ PXA_GPIO_TO_IRQ(GPIO82_MMC_IRQ) #define GPIO95_RTC_CS (95) #define GPIO96_RTC_WR (96) @@ -229,8 +229,8 @@ static struct resource dm9000_resources[] = { .flags = IORESOURCE_MEM, }, [2] = { - .start = IRQ_GPIO(mfp_to_gpio(MFP_PIN_GPIO99)), - .end = IRQ_GPIO(mfp_to_gpio(MFP_PIN_GPIO99)), + .start = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO99)), + .end = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO99)), .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, } }; diff --git a/arch/arm/mach-pxa/colibri-pxa270-income.c b/arch/arm/mach-pxa/colibri-pxa270-income.c index 80538b8806e..248804bb2c9 100644 --- a/arch/arm/mach-pxa/colibri-pxa270-income.c +++ b/arch/arm/mach-pxa/colibri-pxa270-income.c @@ -183,7 +183,7 @@ static inline void income_lcd_init(void) {} /****************************************************************************** * Backlight ******************************************************************************/ -#if defined(CONFIG_BACKLIGHT_PWM) || defined(CONFIG_BACKLIGHT_PWM__MODULE) +#if defined(CONFIG_BACKLIGHT_PWM) || defined(CONFIG_BACKLIGHT_PWM_MODULE) static struct platform_pwm_backlight_data income_backlight_data = { .pwm_id = 0, .max_brightness = 0x3ff, diff --git a/arch/arm/mach-pxa/colibri-pxa270.c b/arch/arm/mach-pxa/colibri-pxa270.c index 6a685165c9f..29d5d541f60 100644 --- a/arch/arm/mach-pxa/colibri-pxa270.c +++ b/arch/arm/mach-pxa/colibri-pxa270.c @@ -218,8 +218,8 @@ static struct resource colibri_pxa270_dm9000_resources[] = { .flags = IORESOURCE_MEM, }, { - .start = gpio_to_irq(GPIO114_COLIBRI_PXA270_ETH_IRQ), - .end = gpio_to_irq(GPIO114_COLIBRI_PXA270_ETH_IRQ), + .start = PXA_GPIO_TO_IRQ(GPIO114_COLIBRI_PXA270_ETH_IRQ), + .end = PXA_GPIO_TO_IRQ(GPIO114_COLIBRI_PXA270_ETH_IRQ), .flags = IORESOURCE_IRQ | IRQF_TRIGGER_RISING, }, }; @@ -249,7 +249,7 @@ static pxa2xx_audio_ops_t colibri_pxa270_ac97_pdata = { }; static struct ucb1400_pdata colibri_pxa270_ucb1400_pdata = { - .irq = gpio_to_irq(GPIO113_COLIBRI_PXA270_TS_IRQ), + .irq = PXA_GPIO_TO_IRQ(GPIO113_COLIBRI_PXA270_TS_IRQ), }; static struct platform_device colibri_pxa270_ucb1400_device = { diff --git a/arch/arm/mach-pxa/colibri-pxa300.c b/arch/arm/mach-pxa/colibri-pxa300.c index c01059a61f3..0846d210cb0 100644 --- a/arch/arm/mach-pxa/colibri-pxa300.c +++ b/arch/arm/mach-pxa/colibri-pxa300.c @@ -78,8 +78,8 @@ static struct resource colibri_asix_resource[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = gpio_to_irq(COLIBRI_ETH_IRQ_GPIO), - .end = gpio_to_irq(COLIBRI_ETH_IRQ_GPIO), + .start = PXA_GPIO_TO_IRQ(COLIBRI_ETH_IRQ_GPIO), + .end = PXA_GPIO_TO_IRQ(COLIBRI_ETH_IRQ_GPIO), .flags = IORESOURCE_IRQ | IRQF_TRIGGER_FALLING, } }; diff --git a/arch/arm/mach-pxa/colibri-pxa320.c b/arch/arm/mach-pxa/colibri-pxa320.c index 5028f2300d5..6ad3359063a 100644 --- a/arch/arm/mach-pxa/colibri-pxa320.c +++ b/arch/arm/mach-pxa/colibri-pxa320.c @@ -115,8 +115,8 @@ static struct resource colibri_asix_resource[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = gpio_to_irq(COLIBRI_ETH_IRQ_GPIO), - .end = gpio_to_irq(COLIBRI_ETH_IRQ_GPIO), + .start = PXA_GPIO_TO_IRQ(COLIBRI_ETH_IRQ_GPIO), + .end = PXA_GPIO_TO_IRQ(COLIBRI_ETH_IRQ_GPIO), .flags = IORESOURCE_IRQ | IRQF_TRIGGER_FALLING, } }; diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c index 9d4dc5970b9..11f1e735966 100644 --- a/arch/arm/mach-pxa/corgi.c +++ b/arch/arm/mach-pxa/corgi.c @@ -436,6 +436,14 @@ static struct platform_device corgiled_device = { }; /* + * Corgi Audio + */ +static struct platform_device corgi_audio_device = { + .name = "corgi-audio", + .id = -1, +}; + +/* * MMC/SD Device * * The card detect interrupt isn't debounced so we delay it by 250ms @@ -531,7 +539,7 @@ static struct spi_board_info corgi_spi_devices[] = { .chip_select = 0, .platform_data = &corgi_ads7846_info, .controller_data= &corgi_ads7846_chip, - .irq = gpio_to_irq(CORGI_GPIO_TP_INT), + .irq = PXA_GPIO_TO_IRQ(CORGI_GPIO_TP_INT), }, { .modalias = "corgi-lcd", .max_speed_hz = 50000, @@ -641,6 +649,7 @@ static struct platform_device *devices[] __initdata = { &corgifb_device, &corgikbd_device, &corgiled_device, + &corgi_audio_device, &sharpsl_nand_device, &sharpsl_rom_device, }; diff --git a/arch/arm/mach-pxa/corgi_pm.c b/arch/arm/mach-pxa/corgi_pm.c index 29034778bfd..39e265cfc86 100644 --- a/arch/arm/mach-pxa/corgi_pm.c +++ b/arch/arm/mach-pxa/corgi_pm.c @@ -15,6 +15,7 @@ #include <linux/kernel.h> #include <linux/delay.h> #include <linux/gpio.h> +#include <linux/gpio-pxa.h> #include <linux/interrupt.h> #include <linux/platform_device.h> #include <linux/apm-emulation.h> @@ -40,7 +41,9 @@ static struct gpio charger_gpios[] = { { CORGI_GPIO_ADC_TEMP_ON, GPIOF_OUT_INIT_LOW, "ADC Temp On" }, { CORGI_GPIO_CHRG_ON, GPIOF_OUT_INIT_LOW, "Charger On" }, { CORGI_GPIO_CHRG_UKN, GPIOF_OUT_INIT_LOW, "Charger Unknown" }, + { CORGI_GPIO_AC_IN, GPIOF_IN, "Charger Detection" }, { CORGI_GPIO_KEY_INT, GPIOF_IN, "Key Interrupt" }, + { CORGI_GPIO_WAKEUP, GPIOF_IN, "System wakeup notification" }, }; static void corgi_charger_init(void) @@ -90,7 +93,12 @@ static int corgi_should_wakeup(unsigned int resume_on_alarm) { int is_resume = 0; - dev_dbg(sharpsl_pm.dev, "GPLR0 = %x,%x\n", GPLR0, PEDR); + dev_dbg(sharpsl_pm.dev, "PEDR = %x, GPIO_AC_IN = %d, " + "GPIO_CHRG_FULL = %d, GPIO_KEY_INT = %d, GPIO_WAKEUP = %d\n", + PEDR, gpio_get_value(CORGI_GPIO_AC_IN), + gpio_get_value(CORGI_GPIO_CHRG_FULL), + gpio_get_value(CORGI_GPIO_KEY_INT), + gpio_get_value(CORGI_GPIO_WAKEUP)); if ((PEDR & GPIO_bit(CORGI_GPIO_AC_IN))) { if (sharpsl_pm.machinfo->read_devdata(SHARPSL_STATUS_ACIN)) { @@ -124,14 +132,21 @@ static int corgi_should_wakeup(unsigned int resume_on_alarm) static unsigned long corgi_charger_wakeup(void) { - return ~GPLR0 & ( GPIO_bit(CORGI_GPIO_AC_IN) | GPIO_bit(CORGI_GPIO_KEY_INT) | GPIO_bit(CORGI_GPIO_WAKEUP) ); + unsigned long ret; + + ret = (!gpio_get_value(CORGI_GPIO_AC_IN) << GPIO_bit(CORGI_GPIO_AC_IN)) + | (!gpio_get_value(CORGI_GPIO_KEY_INT) + << GPIO_bit(CORGI_GPIO_KEY_INT)) + | (!gpio_get_value(CORGI_GPIO_WAKEUP) + << GPIO_bit(CORGI_GPIO_WAKEUP)); + return ret; } unsigned long corgipm_read_devdata(int type) { switch(type) { case SHARPSL_STATUS_ACIN: - return ((GPLR(CORGI_GPIO_AC_IN) & GPIO_bit(CORGI_GPIO_AC_IN)) != 0); + return !gpio_get_value(CORGI_GPIO_AC_IN); case SHARPSL_STATUS_LOCK: return gpio_get_value(sharpsl_pm.machinfo->gpio_batlock); case SHARPSL_STATUS_CHRGFULL: diff --git a/arch/arm/mach-pxa/devices.c b/arch/arm/mach-pxa/devices.c index 2e0425404de..18fd177073f 100644 --- a/arch/arm/mach-pxa/devices.c +++ b/arch/arm/mach-pxa/devices.c @@ -415,9 +415,29 @@ static struct resource pxa_rtc_resources[] = { }, }; +static struct resource sa1100_rtc_resources[] = { + [0] = { + .start = 0x40900000, + .end = 0x409000ff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_RTC1Hz, + .end = IRQ_RTC1Hz, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = IRQ_RTCAlrm, + .end = IRQ_RTCAlrm, + .flags = IORESOURCE_IRQ, + }, +}; + struct platform_device sa1100_device_rtc = { .name = "sa1100-rtc", .id = -1, + .num_resources = ARRAY_SIZE(sa1100_rtc_resources), + .resource = sa1100_rtc_resources, }; struct platform_device pxa_device_rtc = { @@ -1051,6 +1071,36 @@ struct platform_device pxa3xx_device_ssp4 = { }; #endif /* CONFIG_PXA3xx || CONFIG_PXA95x */ +struct resource pxa_resource_gpio[] = { + { + .start = 0x40e00000, + .end = 0x40e0ffff, + .flags = IORESOURCE_MEM, + }, { + .start = IRQ_GPIO0, + .end = IRQ_GPIO0, + .name = "gpio0", + .flags = IORESOURCE_IRQ, + }, { + .start = IRQ_GPIO1, + .end = IRQ_GPIO1, + .name = "gpio1", + .flags = IORESOURCE_IRQ, + }, { + .start = IRQ_GPIO_2_x, + .end = IRQ_GPIO_2_x, + .name = "gpio_mux", + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device pxa_device_gpio = { + .name = "pxa-gpio", + .id = -1, + .num_resources = ARRAY_SIZE(pxa_resource_gpio), + .resource = pxa_resource_gpio, +}; + /* pxa2xx-spi platform-device ID equals respective SSP platform-device ID + 1. * See comment in arch/arm/mach-pxa/ssp.c::ssp_probe() */ void __init pxa2xx_set_spi_info(unsigned id, struct pxa2xx_spi_master *info) diff --git a/arch/arm/mach-pxa/devices.h b/arch/arm/mach-pxa/devices.h index 2fd5a8b3575..1475db10725 100644 --- a/arch/arm/mach-pxa/devices.h +++ b/arch/arm/mach-pxa/devices.h @@ -16,6 +16,7 @@ extern struct platform_device pxa_device_ficp; extern struct platform_device sa1100_device_rtc; extern struct platform_device pxa_device_rtc; extern struct platform_device pxa_device_ac97; +extern struct platform_device pxa_device_gpio; extern struct platform_device pxa27x_device_i2c_power; extern struct platform_device pxa27x_device_ohci; diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c index bd396ba67af..d80c0ba9a09 100644 --- a/arch/arm/mach-pxa/em-x270.c +++ b/arch/arm/mach-pxa/em-x270.c @@ -70,7 +70,7 @@ /* common GPIOs */ #define GPIO11_NAND_CS (11) #define GPIO41_ETHIRQ (41) -#define EM_X270_ETHIRQ IRQ_GPIO(GPIO41_ETHIRQ) +#define EM_X270_ETHIRQ PXA_GPIO_TO_IRQ(GPIO41_ETHIRQ) #define GPIO115_WLAN_PWEN (115) #define GPIO19_WLAN_STRAP (19) #define GPIO9_USB_VBUS_EN (9) @@ -805,7 +805,7 @@ static struct spi_board_info em_x270_spi_devices[] __initdata = { .modalias = "libertas_spi", .max_speed_hz = 13000000, .bus_num = 2, - .irq = IRQ_GPIO(116), + .irq = PXA_GPIO_TO_IRQ(116), .chip_select = 0, .controller_data = &em_x270_libertas_chip, .platform_data = &em_x270_libertas_pdata, @@ -1203,7 +1203,7 @@ static struct da903x_platform_data em_x270_da9030_info = { static struct i2c_board_info em_x270_i2c_pmic_info = { I2C_BOARD_INFO("da9030", 0x49), - .irq = IRQ_GPIO(0), + .irq = PXA_GPIO_TO_IRQ(0), .platform_data = &em_x270_da9030_info, }; diff --git a/arch/arm/mach-pxa/eseries.c b/arch/arm/mach-pxa/eseries.c index 69473db9775..4cb2391a782 100644 --- a/arch/arm/mach-pxa/eseries.c +++ b/arch/arm/mach-pxa/eseries.c @@ -119,8 +119,8 @@ struct resource eseries_tmio_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = IRQ_GPIO(GPIO_ESERIES_TMIO_IRQ), - .end = IRQ_GPIO(GPIO_ESERIES_TMIO_IRQ), + .start = PXA_GPIO_TO_IRQ(GPIO_ESERIES_TMIO_IRQ), + .end = PXA_GPIO_TO_IRQ(GPIO_ESERIES_TMIO_IRQ), .flags = IORESOURCE_IRQ, }, }; @@ -528,12 +528,18 @@ static struct platform_device e740_t7l66xb_device = { .resource = eseries_tmio_resources, }; +static struct platform_device e740_audio_device = { + .name = "e740-audio", + .id = -1, +}; + /* ----------------------------------------------------------------------- */ static struct platform_device *e740_devices[] __initdata = { &e740_fb_device, &e740_t7l66xb_device, &e7xx_gpio_vbus, + &e740_audio_device, }; static void __init e740_init(void) @@ -722,12 +728,18 @@ static struct platform_device e750_tc6393xb_device = { .resource = eseries_tmio_resources, }; +static struct platform_device e750_audio_device = { + .name = "e750-audio", + .id = -1, +}; + /* ------------------------------------------------------------- */ static struct platform_device *e750_devices[] __initdata = { &e750_fb_device, &e750_tc6393xb_device, &e7xx_gpio_vbus, + &e750_audio_device, }; static void __init e750_init(void) @@ -929,12 +941,18 @@ static struct platform_device e800_tc6393xb_device = { .resource = eseries_tmio_resources, }; +static struct platform_device e800_audio_device = { + .name = "e800-audio", + .id = -1, +}; + /* ----------------------------------------------------------------------- */ static struct platform_device *e800_devices[] __initdata = { &e800_fb_device, &e800_tc6393xb_device, &e800_gpio_vbus, + &e800_audio_device, }; static void __init e800_init(void) diff --git a/arch/arm/mach-pxa/hx4700.c b/arch/arm/mach-pxa/hx4700.c index ce16bdae96d..fb9b62dcf4c 100644 --- a/arch/arm/mach-pxa/hx4700.c +++ b/arch/arm/mach-pxa/hx4700.c @@ -252,8 +252,8 @@ static struct resource asic3_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = gpio_to_irq(GPIO12_HX4700_ASIC3_IRQ), - .end = gpio_to_irq(GPIO12_HX4700_ASIC3_IRQ), + .start = PXA_GPIO_TO_IRQ(GPIO12_HX4700_ASIC3_IRQ), + .end = PXA_GPIO_TO_IRQ(GPIO12_HX4700_ASIC3_IRQ), .flags = IORESOURCE_IRQ, }, /* SD part */ @@ -263,8 +263,8 @@ static struct resource asic3_resources[] = { .flags = IORESOURCE_MEM, }, [3] = { - .start = gpio_to_irq(GPIO66_HX4700_ASIC3_nSDIO_IRQ), - .end = gpio_to_irq(GPIO66_HX4700_ASIC3_nSDIO_IRQ), + .start = PXA_GPIO_TO_IRQ(GPIO66_HX4700_ASIC3_nSDIO_IRQ), + .end = PXA_GPIO_TO_IRQ(GPIO66_HX4700_ASIC3_nSDIO_IRQ), .flags = IORESOURCE_IRQ, }, }; @@ -587,7 +587,7 @@ static struct spi_board_info tsc2046_board_info[] __initdata = { .modalias = "ads7846", .bus_num = 2, .max_speed_hz = 2600000, /* 100 kHz sample rate */ - .irq = gpio_to_irq(GPIO58_HX4700_TSC2046_nPENIRQ), + .irq = PXA_GPIO_TO_IRQ(GPIO58_HX4700_TSC2046_nPENIRQ), .platform_data = &tsc2046_info, .controller_data = &tsc2046_chip, }, @@ -635,15 +635,15 @@ static struct resource power_supply_resources[] = { .name = "ac", .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE | IORESOURCE_IRQ_LOWEDGE, - .start = gpio_to_irq(GPIOD9_nAC_IN), - .end = gpio_to_irq(GPIOD9_nAC_IN), + .start = PXA_GPIO_TO_IRQ(GPIOD9_nAC_IN), + .end = PXA_GPIO_TO_IRQ(GPIOD9_nAC_IN), }, [1] = { .name = "usb", .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE | IORESOURCE_IRQ_LOWEDGE, - .start = gpio_to_irq(GPIOD14_nUSBC_DETECT), - .end = gpio_to_irq(GPIOD14_nUSBC_DETECT), + .start = PXA_GPIO_TO_IRQ(GPIOD14_nUSBC_DETECT), + .end = PXA_GPIO_TO_IRQ(GPIOD14_nUSBC_DETECT), }, }; diff --git a/arch/arm/mach-pxa/icontrol.c b/arch/arm/mach-pxa/icontrol.c index e239b82c99d..67400192ed3 100644 --- a/arch/arm/mach-pxa/icontrol.c +++ b/arch/arm/mach-pxa/icontrol.c @@ -86,7 +86,7 @@ static struct spi_board_info mcp251x_board_info[] = { .chip_select = 0, .platform_data = &mcp251x_info, .controller_data = &mcp251x_chip_info1, - .irq = gpio_to_irq(ICONTROL_MCP251x_nIRQ1) + .irq = PXA_GPIO_TO_IRQ(ICONTROL_MCP251x_nIRQ1) }, { .modalias = "mcp2515", @@ -95,7 +95,7 @@ static struct spi_board_info mcp251x_board_info[] = { .chip_select = 1, .platform_data = &mcp251x_info, .controller_data = &mcp251x_chip_info2, - .irq = gpio_to_irq(ICONTROL_MCP251x_nIRQ2) + .irq = PXA_GPIO_TO_IRQ(ICONTROL_MCP251x_nIRQ2) }, { .modalias = "mcp2515", @@ -104,7 +104,7 @@ static struct spi_board_info mcp251x_board_info[] = { .chip_select = 0, .platform_data = &mcp251x_info, .controller_data = &mcp251x_chip_info3, - .irq = gpio_to_irq(ICONTROL_MCP251x_nIRQ3) + .irq = PXA_GPIO_TO_IRQ(ICONTROL_MCP251x_nIRQ3) }, { .modalias = "mcp2515", @@ -113,7 +113,7 @@ static struct spi_board_info mcp251x_board_info[] = { .chip_select = 1, .platform_data = &mcp251x_info, .controller_data = &mcp251x_chip_info4, - .irq = gpio_to_irq(ICONTROL_MCP251x_nIRQ4) + .irq = PXA_GPIO_TO_IRQ(ICONTROL_MCP251x_nIRQ4) } }; diff --git a/arch/arm/mach-pxa/idp.c b/arch/arm/mach-pxa/idp.c index fbabd84e110..8af1840e12c 100644 --- a/arch/arm/mach-pxa/idp.c +++ b/arch/arm/mach-pxa/idp.c @@ -75,8 +75,8 @@ static struct resource smc91x_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = IRQ_GPIO(4), - .end = IRQ_GPIO(4), + .start = PXA_GPIO_TO_IRQ(4), + .end = PXA_GPIO_TO_IRQ(4), .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, } }; diff --git a/arch/arm/mach-pxa/include/mach/balloon3.h b/arch/arm/mach-pxa/include/mach/balloon3.h index 6d7eab3d086..f02fa1e6ba8 100644 --- a/arch/arm/mach-pxa/include/mach/balloon3.h +++ b/arch/arm/mach-pxa/include/mach/balloon3.h @@ -172,9 +172,9 @@ enum balloon3_features { /* Balloon3 Interrupts */ #define BALLOON3_IRQ(x) (IRQ_BOARD_START + (x)) -#define BALLOON3_AUX_NIRQ IRQ_GPIO(BALLOON3_GPIO_AUX_NIRQ) -#define BALLOON3_CODEC_IRQ IRQ_GPIO(BALLOON3_GPIO_CODEC_IRQ) -#define BALLOON3_S0_CD_IRQ IRQ_GPIO(BALLOON3_GPIO_S0_CD) +#define BALLOON3_AUX_NIRQ PXA_GPIO_TO_IRQ(BALLOON3_GPIO_AUX_NIRQ) +#define BALLOON3_CODEC_IRQ PXA_GPIO_TO_IRQ(BALLOON3_GPIO_CODEC_IRQ) +#define BALLOON3_S0_CD_IRQ PXA_GPIO_TO_IRQ(BALLOON3_GPIO_S0_CD) #define BALLOON3_NR_IRQS (IRQ_BOARD_START + 16) diff --git a/arch/arm/mach-pxa/include/mach/corgi.h b/arch/arm/mach-pxa/include/mach/corgi.h index 5dfd1195a5a..f3c3493b468 100644 --- a/arch/arm/mach-pxa/include/mach/corgi.h +++ b/arch/arm/mach-pxa/include/mach/corgi.h @@ -66,18 +66,18 @@ /* * Corgi Interrupts */ -#define CORGI_IRQ_GPIO_KEY_INT IRQ_GPIO(0) -#define CORGI_IRQ_GPIO_AC_IN IRQ_GPIO(1) -#define CORGI_IRQ_GPIO_WAKEUP IRQ_GPIO(3) -#define CORGI_IRQ_GPIO_AK_INT IRQ_GPIO(4) -#define CORGI_IRQ_GPIO_TP_INT IRQ_GPIO(5) -#define CORGI_IRQ_GPIO_nSD_DETECT IRQ_GPIO(9) -#define CORGI_IRQ_GPIO_nSD_INT IRQ_GPIO(10) -#define CORGI_IRQ_GPIO_MAIN_BAT_LOW IRQ_GPIO(11) -#define CORGI_IRQ_GPIO_CF_CD IRQ_GPIO(14) -#define CORGI_IRQ_GPIO_CHRG_FULL IRQ_GPIO(16) /* Battery fully charged */ -#define CORGI_IRQ_GPIO_CF_IRQ IRQ_GPIO(17) -#define CORGI_IRQ_GPIO_KEY_SENSE(a) IRQ_GPIO(58+(a)) /* Keyboard Sense lines */ +#define CORGI_IRQ_GPIO_KEY_INT PXA_GPIO_TO_IRQ(0) +#define CORGI_IRQ_GPIO_AC_IN PXA_GPIO_TO_IRQ(1) +#define CORGI_IRQ_GPIO_WAKEUP PXA_GPIO_TO_IRQ(3) +#define CORGI_IRQ_GPIO_AK_INT PXA_GPIO_TO_IRQ(4) +#define CORGI_IRQ_GPIO_TP_INT PXA_GPIO_TO_IRQ(5) +#define CORGI_IRQ_GPIO_nSD_DETECT PXA_GPIO_TO_IRQ(9) +#define CORGI_IRQ_GPIO_nSD_INT PXA_GPIO_TO_IRQ(10) +#define CORGI_IRQ_GPIO_MAIN_BAT_LOW PXA_GPIO_TO_IRQ(11) +#define CORGI_IRQ_GPIO_CF_CD PXA_GPIO_TO_IRQ(14) +#define CORGI_IRQ_GPIO_CHRG_FULL PXA_GPIO_TO_IRQ(16) /* Battery fully charged */ +#define CORGI_IRQ_GPIO_CF_IRQ PXA_GPIO_TO_IRQ(17) +#define CORGI_IRQ_GPIO_KEY_SENSE(a) PXA_GPIO_TO_IRQ(58+(a)) /* Keyboard Sense lines */ /* @@ -98,7 +98,7 @@ CORGI_SCP_MIC_BIAS ) #define CORGI_SCOOP_IO_OUT ( CORGI_SCP_MUTE_L | CORGI_SCP_MUTE_R ) -#define CORGI_SCOOP_GPIO_BASE (NR_BUILTIN_GPIO) +#define CORGI_SCOOP_GPIO_BASE (PXA_NR_BUILTIN_GPIO) #define CORGI_GPIO_LED_GREEN (CORGI_SCOOP_GPIO_BASE + 0) #define CORGI_GPIO_SWA (CORGI_SCOOP_GPIO_BASE + 1) /* Hinge Switch A */ #define CORGI_GPIO_SWB (CORGI_SCOOP_GPIO_BASE + 2) /* Hinge Switch B */ diff --git a/arch/arm/mach-pxa/include/mach/csb726.h b/arch/arm/mach-pxa/include/mach/csb726.h index 747ab1a71f2..2628e7b7211 100644 --- a/arch/arm/mach-pxa/include/mach/csb726.h +++ b/arch/arm/mach-pxa/include/mach/csb726.h @@ -19,8 +19,8 @@ #define CSB726_FLASH_SIZE (64 * 1024 * 1024) #define CSB726_FLASH_uMON (8 * 1024 * 1024) -#define CSB726_IRQ_LAN gpio_to_irq(CSB726_GPIO_IRQ_LAN) -#define CSB726_IRQ_SM501 gpio_to_irq(CSB726_GPIO_IRQ_SM501) +#define CSB726_IRQ_LAN PXA_GPIO_TO_IRQ(CSB726_GPIO_IRQ_LAN) +#define CSB726_IRQ_SM501 PXA_GPIO_TO_IRQ(CSB726_GPIO_IRQ_SM501) #endif diff --git a/arch/arm/mach-pxa/include/mach/gpio-pxa.h b/arch/arm/mach-pxa/include/mach/gpio-pxa.h deleted file mode 100644 index 41b4c93a96c..00000000000 --- a/arch/arm/mach-pxa/include/mach/gpio-pxa.h +++ /dev/null @@ -1,133 +0,0 @@ -/* - * Written by Philipp Zabel <philipp.zabel@gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ -#ifndef __MACH_PXA_GPIO_PXA_H -#define __MACH_PXA_GPIO_PXA_H - -#include <mach/irqs.h> -#include <mach/hardware.h> - -#define GPIO_REGS_VIRT io_p2v(0x40E00000) - -#define BANK_OFF(n) (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2)) -#define GPIO_REG(x) (*(volatile u32 *)(GPIO_REGS_VIRT + (x))) - -/* GPIO Pin Level Registers */ -#define GPLR0 GPIO_REG(BANK_OFF(0) + 0x00) -#define GPLR1 GPIO_REG(BANK_OFF(1) + 0x00) -#define GPLR2 GPIO_REG(BANK_OFF(2) + 0x00) -#define GPLR3 GPIO_REG(BANK_OFF(3) + 0x00) - -/* GPIO Pin Direction Registers */ -#define GPDR0 GPIO_REG(BANK_OFF(0) + 0x0c) -#define GPDR1 GPIO_REG(BANK_OFF(1) + 0x0c) -#define GPDR2 GPIO_REG(BANK_OFF(2) + 0x0c) -#define GPDR3 GPIO_REG(BANK_OFF(3) + 0x0c) - -/* GPIO Pin Output Set Registers */ -#define GPSR0 GPIO_REG(BANK_OFF(0) + 0x18) -#define GPSR1 GPIO_REG(BANK_OFF(1) + 0x18) -#define GPSR2 GPIO_REG(BANK_OFF(2) + 0x18) -#define GPSR3 GPIO_REG(BANK_OFF(3) + 0x18) - -/* GPIO Pin Output Clear Registers */ -#define GPCR0 GPIO_REG(BANK_OFF(0) + 0x24) -#define GPCR1 GPIO_REG(BANK_OFF(1) + 0x24) -#define GPCR2 GPIO_REG(BANK_OFF(2) + 0x24) -#define GPCR3 GPIO_REG(BANK_OFF(3) + 0x24) - -/* GPIO Rising Edge Detect Registers */ -#define GRER0 GPIO_REG(BANK_OFF(0) + 0x30) -#define GRER1 GPIO_REG(BANK_OFF(1) + 0x30) -#define GRER2 GPIO_REG(BANK_OFF(2) + 0x30) -#define GRER3 GPIO_REG(BANK_OFF(3) + 0x30) - -/* GPIO Falling Edge Detect Registers */ -#define GFER0 GPIO_REG(BANK_OFF(0) + 0x3c) -#define GFER1 GPIO_REG(BANK_OFF(1) + 0x3c) -#define GFER2 GPIO_REG(BANK_OFF(2) + 0x3c) -#define GFER3 GPIO_REG(BANK_OFF(3) + 0x3c) - -/* GPIO Edge Detect Status Registers */ -#define GEDR0 GPIO_REG(BANK_OFF(0) + 0x48) -#define GEDR1 GPIO_REG(BANK_OFF(1) + 0x48) -#define GEDR2 GPIO_REG(BANK_OFF(2) + 0x48) -#define GEDR3 GPIO_REG(BANK_OFF(3) + 0x48) - -/* GPIO Alternate Function Select Registers */ -#define GAFR0_L GPIO_REG(0x0054) -#define GAFR0_U GPIO_REG(0x0058) -#define GAFR1_L GPIO_REG(0x005C) -#define GAFR1_U GPIO_REG(0x0060) -#define GAFR2_L GPIO_REG(0x0064) -#define GAFR2_U GPIO_REG(0x0068) -#define GAFR3_L GPIO_REG(0x006C) -#define GAFR3_U GPIO_REG(0x0070) - -/* More handy macros. The argument is a literal GPIO number. */ - -#define GPIO_bit(x) (1 << ((x) & 0x1f)) - -#define GPLR(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x00) -#define GPDR(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x0c) -#define GPSR(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x18) -#define GPCR(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x24) -#define GRER(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x30) -#define GFER(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x3c) -#define GEDR(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x48) -#define GAFR(x) GPIO_REG(0x54 + (((x) & 0x70) >> 2)) - - -#define NR_BUILTIN_GPIO PXA_GPIO_IRQ_NUM - -#define gpio_to_bank(gpio) ((gpio) >> 5) - -#ifdef CONFIG_CPU_PXA26x -/* GPIO86/87/88/89 on PXA26x have their direction bits in GPDR2 inverted, - * as well as their Alternate Function value being '1' for GPIO in GAFRx. - */ -static inline int __gpio_is_inverted(unsigned gpio) -{ - return cpu_is_pxa25x() && gpio > 85; -} -#else -static inline int __gpio_is_inverted(unsigned gpio) { return 0; } -#endif - -/* - * On PXA25x and PXA27x, GAFRx and GPDRx together decide the alternate - * function of a GPIO, and GPDRx cannot be altered once configured. It - * is attributed as "occupied" here (I know this terminology isn't - * accurate, you are welcome to propose a better one :-) - */ -static inline int __gpio_is_occupied(unsigned gpio) -{ - if (cpu_is_pxa27x() || cpu_is_pxa25x()) { - int af = (GAFR(gpio) >> ((gpio & 0xf) * 2)) & 0x3; - int dir = GPDR(gpio) & GPIO_bit(gpio); - - if (__gpio_is_inverted(gpio)) - return af != 1 || dir == 0; - else - return af != 0 || dir != 0; - } else - return GPDR(gpio) & GPIO_bit(gpio); -} - -#include <plat/gpio-pxa.h> -#endif /* __MACH_PXA_GPIO_PXA_H */ diff --git a/arch/arm/mach-pxa/include/mach/gpio.h b/arch/arm/mach-pxa/include/mach/gpio.h index 004cade7bb1..0248e433bc9 100644 --- a/arch/arm/mach-pxa/include/mach/gpio.h +++ b/arch/arm/mach-pxa/include/mach/gpio.h @@ -25,24 +25,8 @@ #define __ASM_ARCH_PXA_GPIO_H #include <asm-generic/gpio.h> -/* The defines for the driver are needed for the accelerated accessors */ -#include "gpio-pxa.h" -#define gpio_to_irq(gpio) IRQ_GPIO(gpio) +#include <mach/irqs.h> +#include <mach/hardware.h> -static inline int irq_to_gpio(unsigned int irq) -{ - int gpio; - - if (irq == IRQ_GPIO0 || irq == IRQ_GPIO1) - return irq - IRQ_GPIO0; - - gpio = irq - PXA_GPIO_IRQ_BASE; - if (gpio >= 2 && gpio < NR_BUILTIN_GPIO) - return gpio; - - return -1; -} - -#include <plat/gpio.h> #endif diff --git a/arch/arm/mach-pxa/include/mach/gumstix.h b/arch/arm/mach-pxa/include/mach/gumstix.h index 9b898680b20..dba14b6503a 100644 --- a/arch/arm/mach-pxa/include/mach/gumstix.h +++ b/arch/arm/mach-pxa/include/mach/gumstix.h @@ -24,7 +24,7 @@ has detected a cable insertion; driven low otherwise. */ #define GPIO_GUMSTIX_USB_GPIOx 41 /* usb state change */ -#define GUMSTIX_USB_INTR_IRQ IRQ_GPIO(GPIO_GUMSTIX_USB_GPIOn) +#define GUMSTIX_USB_INTR_IRQ PXA_GPIO_TO_IRQ(GPIO_GUMSTIX_USB_GPIOn) #define GPIO_GUMSTIX_USB_GPIOn_MD (GPIO_GUMSTIX_USB_GPIOn | GPIO_IN) #define GPIO_GUMSTIX_USB_GPIOx_CON_MD (GPIO_GUMSTIX_USB_GPIOx | GPIO_OUT) @@ -35,7 +35,7 @@ has detected a cable insertion; driven low otherwise. */ */ #define GUMSTIX_GPIO_nSD_WP 22 /* SD Write Protect */ #define GUMSTIX_GPIO_nSD_DETECT 11 /* MMC/SD Card Detect */ -#define GUMSTIX_IRQ_GPIO_nSD_DETECT IRQ_GPIO(GUMSTIX_GPIO_nSD_DETECT) +#define GUMSTIX_IRQ_GPIO_nSD_DETECT PXA_GPIO_TO_IRQ(GUMSTIX_GPIO_nSD_DETECT) /* * SMC Ethernet definitions @@ -49,10 +49,10 @@ has detected a cable insertion; driven low otherwise. */ #define GPIO_GUMSTIX_ETH0 36 #define GPIO_GUMSTIX_ETH0_MD (GPIO_GUMSTIX_ETH0 | GPIO_IN) -#define GUMSTIX_ETH0_IRQ IRQ_GPIO(GPIO_GUMSTIX_ETH0) +#define GUMSTIX_ETH0_IRQ PXA_GPIO_TO_IRQ(GPIO_GUMSTIX_ETH0) #define GPIO_GUMSTIX_ETH1 27 #define GPIO_GUMSTIX_ETH1_MD (GPIO_GUMSTIX_ETH1 | GPIO_IN) -#define GUMSTIX_ETH1_IRQ IRQ_GPIO(GPIO_GUMSTIX_ETH1) +#define GUMSTIX_ETH1_IRQ PXA_GPIO_TO_IRQ(GPIO_GUMSTIX_ETH1) /* CF reset line */ @@ -63,18 +63,18 @@ has detected a cable insertion; driven low otherwise. */ #define GPIO4_nSTSCHG GPIO4_nBVD1 #define GPIO11_nCD 11 #define GPIO26_PRDY_nBSY 26 -#define GUMSTIX_S0_nSTSCHG_IRQ IRQ_GPIO(GPIO4_nSTSCHG) -#define GUMSTIX_S0_nCD_IRQ IRQ_GPIO(GPIO11_nCD) -#define GUMSTIX_S0_PRDY_nBSY_IRQ IRQ_GPIO(GPIO26_PRDY_nBSY) +#define GUMSTIX_S0_nSTSCHG_IRQ PXA_GPIO_TO_IRQ(GPIO4_nSTSCHG) +#define GUMSTIX_S0_nCD_IRQ PXA_GPIO_TO_IRQ(GPIO11_nCD) +#define GUMSTIX_S0_PRDY_nBSY_IRQ PXA_GPIO_TO_IRQ(GPIO26_PRDY_nBSY) /* CF slot 1 */ #define GPIO18_nBVD1 18 #define GPIO18_nSTSCHG GPIO18_nBVD1 #define GPIO36_nCD 36 #define GPIO27_PRDY_nBSY 27 -#define GUMSTIX_S1_nSTSCHG_IRQ IRQ_GPIO(GPIO18_nSTSCHG) -#define GUMSTIX_S1_nCD_IRQ IRQ_GPIO(GPIO36_nCD) -#define GUMSTIX_S1_PRDY_nBSY_IRQ IRQ_GPIO(GPIO27_PRDY_nBSY) +#define GUMSTIX_S1_nSTSCHG_IRQ PXA_GPIO_TO_IRQ(GPIO18_nSTSCHG) +#define GUMSTIX_S1_nCD_IRQ PXA_GPIO_TO_IRQ(GPIO36_nCD) +#define GUMSTIX_S1_PRDY_nBSY_IRQ PXA_GPIO_TO_IRQ(GPIO27_PRDY_nBSY) /* CF GPIO line modes */ #define GPIO4_nSTSCHG_MD (GPIO4_nSTSCHG | GPIO_IN) diff --git a/arch/arm/mach-pxa/include/mach/hx4700.h b/arch/arm/mach-pxa/include/mach/hx4700.h index 37408449ec2..8bc02913517 100644 --- a/arch/arm/mach-pxa/include/mach/hx4700.h +++ b/arch/arm/mach-pxa/include/mach/hx4700.h @@ -15,7 +15,7 @@ #include <linux/gpio.h> #include <linux/mfd/asic3.h> -#define HX4700_ASIC3_GPIO_BASE NR_BUILTIN_GPIO +#define HX4700_ASIC3_GPIO_BASE PXA_NR_BUILTIN_GPIO #define HX4700_EGPIO_BASE (HX4700_ASIC3_GPIO_BASE + ASIC3_NUM_GPIOS) #define HX4700_NR_IRQS (IRQ_BOARD_START + 70) diff --git a/arch/arm/mach-pxa/include/mach/idp.h b/arch/arm/mach-pxa/include/mach/idp.h index 5eff96fcc94..22a96f87232 100644 --- a/arch/arm/mach-pxa/include/mach/idp.h +++ b/arch/arm/mach-pxa/include/mach/idp.h @@ -131,28 +131,26 @@ #define PCC_VS2 (1 << 1) #define PCC_VS1 (1 << 0) -#define PCC_DETECT(x) (GPLR(7 + (x)) & GPIO_bit(7 + (x))) - /* A listing of interrupts used by external hardware devices */ -#define TOUCH_PANEL_IRQ IRQ_GPIO(5) -#define IDE_IRQ IRQ_GPIO(21) +#define TOUCH_PANEL_IRQ PXA_GPIO_TO_IRQ(5) +#define IDE_IRQ PXA_GPIO_TO_IRQ(21) #define TOUCH_PANEL_IRQ_EDGE IRQ_TYPE_EDGE_FALLING -#define ETHERNET_IRQ IRQ_GPIO(4) +#define ETHERNET_IRQ PXA_GPIO_TO_IRQ(4) #define ETHERNET_IRQ_EDGE IRQ_TYPE_EDGE_RISING #define IDE_IRQ_EDGE IRQ_TYPE_EDGE_RISING -#define PCMCIA_S0_CD_VALID IRQ_GPIO(7) +#define PCMCIA_S0_CD_VALID PXA_GPIO_TO_IRQ(7) #define PCMCIA_S0_CD_VALID_EDGE IRQ_TYPE_EDGE_BOTH -#define PCMCIA_S1_CD_VALID IRQ_GPIO(8) +#define PCMCIA_S1_CD_VALID PXA_GPIO_TO_IRQ(8) #define PCMCIA_S1_CD_VALID_EDGE IRQ_TYPE_EDGE_BOTH -#define PCMCIA_S0_RDYINT IRQ_GPIO(19) -#define PCMCIA_S1_RDYINT IRQ_GPIO(22) +#define PCMCIA_S0_RDYINT PXA_GPIO_TO_IRQ(19) +#define PCMCIA_S1_RDYINT PXA_GPIO_TO_IRQ(22) /* diff --git a/arch/arm/mach-pxa/include/mach/irqs.h b/arch/arm/mach-pxa/include/mach/irqs.h index 7cc5a781e99..32975adf3ca 100644 --- a/arch/arm/mach-pxa/include/mach/irqs.h +++ b/arch/arm/mach-pxa/include/mach/irqs.h @@ -88,10 +88,8 @@ #define IRQ_U2P PXA_IRQ(93) /* USB PHY D+/D- Lines (PXA935) */ #define PXA_GPIO_IRQ_BASE PXA_IRQ(96) -#define PXA_GPIO_IRQ_NUM (192) - -#define GPIO_2_x_TO_IRQ(x) (PXA_GPIO_IRQ_BASE + (x)) -#define IRQ_GPIO(x) (((x) < 2) ? (IRQ_GPIO0 + (x)) : GPIO_2_x_TO_IRQ(x)) +#define PXA_NR_BUILTIN_GPIO (192) +#define PXA_GPIO_TO_IRQ(x) (PXA_GPIO_IRQ_BASE + (x)) /* * The following interrupts are for board specific purposes. Since @@ -100,7 +98,7 @@ * By default, no board IRQ is reserved. It should be finished in * custom board since sparse IRQ is already enabled. */ -#define IRQ_BOARD_START (PXA_GPIO_IRQ_BASE + PXA_GPIO_IRQ_NUM) +#define IRQ_BOARD_START (PXA_GPIO_IRQ_BASE + PXA_NR_BUILTIN_GPIO) #define NR_IRQS (IRQ_BOARD_START) diff --git a/arch/arm/mach-pxa/include/mach/littleton.h b/arch/arm/mach-pxa/include/mach/littleton.h index b6238cbd8ae..8066be54e9f 100644 --- a/arch/arm/mach-pxa/include/mach/littleton.h +++ b/arch/arm/mach-pxa/include/mach/littleton.h @@ -1,13 +1,11 @@ #ifndef __ASM_ARCH_LITTLETON_H #define __ASM_ARCH_LITTLETON_H -#include <mach/gpio-pxa.h> - #define LITTLETON_ETH_PHYS 0x30000000 #define LITTLETON_GPIO_LCD_CS (17) -#define EXT0_GPIO_BASE (NR_BUILTIN_GPIO) +#define EXT0_GPIO_BASE (PXA_NR_BUILTIN_GPIO) #define EXT0_GPIO(x) (EXT0_GPIO_BASE + (x)) #define LITTLETON_NR_IRQS (IRQ_BOARD_START + 8) diff --git a/arch/arm/mach-pxa/include/mach/magician.h b/arch/arm/mach-pxa/include/mach/magician.h index 7cbfc5d3f9d..ba6a6e1d29e 100644 --- a/arch/arm/mach-pxa/include/mach/magician.h +++ b/arch/arm/mach-pxa/include/mach/magician.h @@ -78,7 +78,7 @@ * CPLD EGPIOs */ -#define MAGICIAN_EGPIO_BASE NR_BUILTIN_GPIO +#define MAGICIAN_EGPIO_BASE PXA_NR_BUILTIN_GPIO #define MAGICIAN_EGPIO(reg,bit) \ (MAGICIAN_EGPIO_BASE + 8*reg + bit) diff --git a/arch/arm/mach-pxa/include/mach/palmld.h b/arch/arm/mach-pxa/include/mach/palmld.h index ae536e86d8e..2c447133657 100644 --- a/arch/arm/mach-pxa/include/mach/palmld.h +++ b/arch/arm/mach-pxa/include/mach/palmld.h @@ -68,10 +68,10 @@ /* 20, 53 and 86 are usb related too */ /* INTERRUPTS */ -#define IRQ_GPIO_PALMLD_GPIO_RESET IRQ_GPIO(GPIO_NR_PALMLD_GPIO_RESET) -#define IRQ_GPIO_PALMLD_SD_DETECT_N IRQ_GPIO(GPIO_NR_PALMLD_SD_DETECT_N) -#define IRQ_GPIO_PALMLD_WM9712_IRQ IRQ_GPIO(GPIO_NR_PALMLD_WM9712_IRQ) -#define IRQ_GPIO_PALMLD_IDE_IRQ IRQ_GPIO(GPIO_NR_PALMLD_IDE_IRQ) +#define IRQ_GPIO_PALMLD_GPIO_RESET PXA_GPIO_TO_IRQ(GPIO_NR_PALMLD_GPIO_RESET) +#define IRQ_GPIO_PALMLD_SD_DETECT_N PXA_GPIO_TO_IRQ(GPIO_NR_PALMLD_SD_DETECT_N) +#define IRQ_GPIO_PALMLD_WM9712_IRQ PXA_GPIO_TO_IRQ(GPIO_NR_PALMLD_WM9712_IRQ) +#define IRQ_GPIO_PALMLD_IDE_IRQ PXA_GPIO_TO_IRQ(GPIO_NR_PALMLD_IDE_IRQ) /** HERE ARE INIT VALUES **/ diff --git a/arch/arm/mach-pxa/include/mach/palmt5.h b/arch/arm/mach-pxa/include/mach/palmt5.h index 6baf7469d4e..0bd4f036c72 100644 --- a/arch/arm/mach-pxa/include/mach/palmt5.h +++ b/arch/arm/mach-pxa/include/mach/palmt5.h @@ -48,10 +48,10 @@ #define GPIO_NR_PALMT5_BT_RESET 83 /* INTERRUPTS */ -#define IRQ_GPIO_PALMT5_SD_DETECT_N IRQ_GPIO(GPIO_NR_PALMT5_SD_DETECT_N) -#define IRQ_GPIO_PALMT5_WM9712_IRQ IRQ_GPIO(GPIO_NR_PALMT5_WM9712_IRQ) -#define IRQ_GPIO_PALMT5_USB_DETECT IRQ_GPIO(GPIO_NR_PALMT5_USB_DETECT) -#define IRQ_GPIO_PALMT5_GPIO_RESET IRQ_GPIO(GPIO_NR_PALMT5_GPIO_RESET) +#define IRQ_GPIO_PALMT5_SD_DETECT_N PXA_GPIO_TO_IRQ(GPIO_NR_PALMT5_SD_DETECT_N) +#define IRQ_GPIO_PALMT5_WM9712_IRQ PXA_GPIO_TO_IRQ(GPIO_NR_PALMT5_WM9712_IRQ) +#define IRQ_GPIO_PALMT5_USB_DETECT PXA_GPIO_TO_IRQ(GPIO_NR_PALMT5_USB_DETECT) +#define IRQ_GPIO_PALMT5_GPIO_RESET PXA_GPIO_TO_IRQ(GPIO_NR_PALMT5_GPIO_RESET) /** HERE ARE INIT VALUES **/ diff --git a/arch/arm/mach-pxa/include/mach/palmtc.h b/arch/arm/mach-pxa/include/mach/palmtc.h index 3f9dd3fd463..c383a21680b 100644 --- a/arch/arm/mach-pxa/include/mach/palmtc.h +++ b/arch/arm/mach-pxa/include/mach/palmtc.h @@ -52,8 +52,8 @@ #define GPIO_NR_PALMTC_IR_DISABLE 45 /* IRQs */ -#define IRQ_GPIO_PALMTC_SD_DETECT_N IRQ_GPIO(GPIO_NR_PALMTC_SD_DETECT_N) -#define IRQ_GPIO_PALMTC_WLAN_READY IRQ_GPIO(GPIO_NR_PALMTC_WLAN_READY) +#define IRQ_GPIO_PALMTC_SD_DETECT_N PXA_GPIO_TO_IRQ(GPIO_NR_PALMTC_SD_DETECT_N) +#define IRQ_GPIO_PALMTC_WLAN_READY PXA_GPIO_TO_IRQ(GPIO_NR_PALMTC_WLAN_READY) /* UCB1400 GPIOs */ #define GPIO_NR_PALMTC_POWER_DETECT (0x80 | 0x00) diff --git a/arch/arm/mach-pxa/include/mach/palmtx.h b/arch/arm/mach-pxa/include/mach/palmtx.h index 7074a6ed46c..f2e53038025 100644 --- a/arch/arm/mach-pxa/include/mach/palmtx.h +++ b/arch/arm/mach-pxa/include/mach/palmtx.h @@ -62,10 +62,10 @@ #define GPIO_NR_PALMTX_NAND_BUFFER_DIR 79 /* INTERRUPTS */ -#define IRQ_GPIO_PALMTX_SD_DETECT_N IRQ_GPIO(GPIO_NR_PALMTX_SD_DETECT_N) -#define IRQ_GPIO_PALMTX_WM9712_IRQ IRQ_GPIO(GPIO_NR_PALMTX_WM9712_IRQ) -#define IRQ_GPIO_PALMTX_USB_DETECT IRQ_GPIO(GPIO_NR_PALMTX_USB_DETECT) -#define IRQ_GPIO_PALMTX_GPIO_RESET IRQ_GPIO(GPIO_NR_PALMTX_GPIO_RESET) +#define IRQ_GPIO_PALMTX_SD_DETECT_N PXA_GPIO_TO_IRQ(GPIO_NR_PALMTX_SD_DETECT_N) +#define IRQ_GPIO_PALMTX_WM9712_IRQ PXA_GPIO_TO_IRQ(GPIO_NR_PALMTX_WM9712_IRQ) +#define IRQ_GPIO_PALMTX_USB_DETECT PXA_GPIO_TO_IRQ(GPIO_NR_PALMTX_USB_DETECT) +#define IRQ_GPIO_PALMTX_GPIO_RESET PXA_GPIO_TO_IRQ(GPIO_NR_PALMTX_GPIO_RESET) /** HERE ARE INIT VALUES **/ diff --git a/arch/arm/mach-pxa/include/mach/pcm027.h b/arch/arm/mach-pxa/include/mach/pcm027.h index 4bac588478a..6bf28de228b 100644 --- a/arch/arm/mach-pxa/include/mach/pcm027.h +++ b/arch/arm/mach-pxa/include/mach/pcm027.h @@ -34,7 +34,7 @@ /* I2C RTC */ #define PCM027_RTC_IRQ_GPIO 0 -#define PCM027_RTC_IRQ IRQ_GPIO(PCM027_RTC_IRQ_GPIO) +#define PCM027_RTC_IRQ PXA_GPIO_TO_IRQ(PCM027_RTC_IRQ_GPIO) #define PCM027_RTC_IRQ_EDGE IRQ_TYPE_EDGE_FALLING #define ADR_PCM027_RTC 0x51 /* I2C address */ @@ -43,21 +43,21 @@ /* Ethernet chip (SMSC91C111) */ #define PCM027_ETH_IRQ_GPIO 52 -#define PCM027_ETH_IRQ IRQ_GPIO(PCM027_ETH_IRQ_GPIO) +#define PCM027_ETH_IRQ PXA_GPIO_TO_IRQ(PCM027_ETH_IRQ_GPIO) #define PCM027_ETH_IRQ_EDGE IRQ_TYPE_EDGE_RISING #define PCM027_ETH_PHYS PXA_CS5_PHYS #define PCM027_ETH_SIZE (1*1024*1024) /* CAN controller SJA1000 (unsupported yet) */ #define PCM027_CAN_IRQ_GPIO 114 -#define PCM027_CAN_IRQ IRQ_GPIO(PCM027_CAN_IRQ_GPIO) +#define PCM027_CAN_IRQ PXA_GPIO_TO_IRQ(PCM027_CAN_IRQ_GPIO) #define PCM027_CAN_IRQ_EDGE IRQ_TYPE_EDGE_FALLING #define PCM027_CAN_PHYS 0x22000000 #define PCM027_CAN_SIZE 0x100 /* SPI GPIO expander (unsupported yet) */ #define PCM027_EGPIO_IRQ_GPIO 27 -#define PCM027_EGPIO_IRQ IRQ_GPIO(PCM027_EGPIO_IRQ_GPIO) +#define PCM027_EGPIO_IRQ PXA_GPIO_TO_IRQ(PCM027_EGPIO_IRQ_GPIO) #define PCM027_EGPIO_IRQ_EDGE IRQ_TYPE_EDGE_FALLING #define PCM027_EGPIO_CS 24 /* diff --git a/arch/arm/mach-pxa/include/mach/pcm990_baseboard.h b/arch/arm/mach-pxa/include/mach/pcm990_baseboard.h index 8a4383b776d..d72791695b2 100644 --- a/arch/arm/mach-pxa/include/mach/pcm990_baseboard.h +++ b/arch/arm/mach-pxa/include/mach/pcm990_baseboard.h @@ -28,14 +28,14 @@ /* CPLD's interrupt controller is connected to PCM-027 GPIO 9 */ #define PCM990_CTRL_INT_IRQ_GPIO 9 -#define PCM990_CTRL_INT_IRQ IRQ_GPIO(PCM990_CTRL_INT_IRQ_GPIO) +#define PCM990_CTRL_INT_IRQ PXA_GPIO_TO_IRQ(PCM990_CTRL_INT_IRQ_GPIO) #define PCM990_CTRL_INT_IRQ_EDGE IRQ_TYPE_EDGE_RISING #define PCM990_CTRL_PHYS PXA_CS1_PHYS /* 16-Bit */ #define PCM990_CTRL_BASE 0xea000000 #define PCM990_CTRL_SIZE (1*1024*1024) #define PCM990_CTRL_PWR_IRQ_GPIO 14 -#define PCM990_CTRL_PWR_IRQ IRQ_GPIO(PCM990_CTRL_PWR_IRQ_GPIO) +#define PCM990_CTRL_PWR_IRQ PXA_GPIO_TO_IRQ(PCM990_CTRL_PWR_IRQ_GPIO) #define PCM990_CTRL_PWR_IRQ_EDGE IRQ_TYPE_EDGE_RISING /* visible CPLD (U7) registers */ @@ -132,7 +132,7 @@ * IDE */ #define PCM990_IDE_IRQ_GPIO 13 -#define PCM990_IDE_IRQ IRQ_GPIO(PCM990_IDE_IRQ_GPIO) +#define PCM990_IDE_IRQ PXA_GPIO_TO_IRQ(PCM990_IDE_IRQ_GPIO) #define PCM990_IDE_IRQ_EDGE IRQ_TYPE_EDGE_RISING #define PCM990_IDE_PLD_PHYS 0x20000000 /* 16 bit wide */ #define PCM990_IDE_PLD_BASE 0xee000000 @@ -188,11 +188,11 @@ * Compact Flash */ #define PCM990_CF_IRQ_GPIO 11 -#define PCM990_CF_IRQ IRQ_GPIO(PCM990_CF_IRQ_GPIO) +#define PCM990_CF_IRQ PXA_GPIO_TO_IRQ(PCM990_CF_IRQ_GPIO) #define PCM990_CF_IRQ_EDGE IRQ_TYPE_EDGE_RISING #define PCM990_CF_CD_GPIO 12 -#define PCM990_CF_CD IRQ_GPIO(PCM990_CF_CD_GPIO) +#define PCM990_CF_CD PXA_GPIO_TO_IRQ(PCM990_CF_CD_GPIO) #define PCM990_CF_CD_EDGE IRQ_TYPE_EDGE_RISING #define PCM990_CF_PLD_PHYS 0x30000000 /* 16 bit wide */ @@ -258,14 +258,14 @@ * Wolfson AC97 Touch */ #define PCM990_AC97_IRQ_GPIO 10 -#define PCM990_AC97_IRQ IRQ_GPIO(PCM990_AC97_IRQ_GPIO) +#define PCM990_AC97_IRQ PXA_GPIO_TO_IRQ(PCM990_AC97_IRQ_GPIO) #define PCM990_AC97_IRQ_EDGE IRQ_TYPE_EDGE_RISING /* * MMC phyCORE */ #define PCM990_MMC0_IRQ_GPIO 9 -#define PCM990_MMC0_IRQ IRQ_GPIO(PCM990_MMC0_IRQ_GPIO) +#define PCM990_MMC0_IRQ PXA_GPIO_TO_IRQ(PCM990_MMC0_IRQ_GPIO) #define PCM990_MMC0_IRQ_EDGE IRQ_TYPE_EDGE_FALLING /* diff --git a/arch/arm/mach-pxa/include/mach/poodle.h b/arch/arm/mach-pxa/include/mach/poodle.h index 83d1cfd00fc..f32ff75dcca 100644 --- a/arch/arm/mach-pxa/include/mach/poodle.h +++ b/arch/arm/mach-pxa/include/mach/poodle.h @@ -47,18 +47,18 @@ #define POODLE_GPIO_DISCHARGE_ON (42) /* Enable battery discharge */ /* PXA GPIOs */ -#define POODLE_IRQ_GPIO_ON_KEY IRQ_GPIO(0) -#define POODLE_IRQ_GPIO_AC_IN IRQ_GPIO(1) -#define POODLE_IRQ_GPIO_HP_IN IRQ_GPIO(4) -#define POODLE_IRQ_GPIO_CO IRQ_GPIO(16) -#define POODLE_IRQ_GPIO_TP_INT IRQ_GPIO(5) -#define POODLE_IRQ_GPIO_WAKEUP IRQ_GPIO(11) -#define POODLE_IRQ_GPIO_GA_INT IRQ_GPIO(10) -#define POODLE_IRQ_GPIO_CF_IRQ IRQ_GPIO(17) -#define POODLE_IRQ_GPIO_CF_CD IRQ_GPIO(14) -#define POODLE_IRQ_GPIO_nSD_INT IRQ_GPIO(8) -#define POODLE_IRQ_GPIO_nSD_DETECT IRQ_GPIO(9) -#define POODLE_IRQ_GPIO_MAIN_BAT_LOW IRQ_GPIO(13) +#define POODLE_IRQ_GPIO_ON_KEY PXA_GPIO_TO_IRQ(0) +#define POODLE_IRQ_GPIO_AC_IN PXA_GPIO_TO_IRQ(1) +#define POODLE_IRQ_GPIO_HP_IN PXA_GPIO_TO_IRQ(4) +#define POODLE_IRQ_GPIO_CO PXA_GPIO_TO_IRQ(16) +#define POODLE_IRQ_GPIO_TP_INT PXA_GPIO_TO_IRQ(5) +#define POODLE_IRQ_GPIO_WAKEUP PXA_GPIO_TO_IRQ(11) +#define POODLE_IRQ_GPIO_GA_INT PXA_GPIO_TO_IRQ(10) +#define POODLE_IRQ_GPIO_CF_IRQ PXA_GPIO_TO_IRQ(17) +#define POODLE_IRQ_GPIO_CF_CD PXA_GPIO_TO_IRQ(14) +#define POODLE_IRQ_GPIO_nSD_INT PXA_GPIO_TO_IRQ(8) +#define POODLE_IRQ_GPIO_nSD_DETECT PXA_GPIO_TO_IRQ(9) +#define POODLE_IRQ_GPIO_MAIN_BAT_LOW PXA_GPIO_TO_IRQ(13) /* SCOOP GPIOs */ #define POODLE_SCOOP_CHARGE_ON SCOOP_GPCR_PA11 @@ -71,7 +71,7 @@ #define POODLE_SCOOP_IO_DIR ( POODLE_SCOOP_VPEN | POODLE_SCOOP_HS_OUT ) #define POODLE_SCOOP_IO_OUT ( 0 ) -#define POODLE_SCOOP_GPIO_BASE (NR_BUILTIN_GPIO) +#define POODLE_SCOOP_GPIO_BASE (PXA_NR_BUILTIN_GPIO) #define POODLE_GPIO_CHARGE_ON (POODLE_SCOOP_GPIO_BASE + 0) #define POODLE_GPIO_CP401 (POODLE_SCOOP_GPIO_BASE + 2) #define POODLE_GPIO_VPEN (POODLE_SCOOP_GPIO_BASE + 7) diff --git a/arch/arm/mach-pxa/include/mach/spitz.h b/arch/arm/mach-pxa/include/mach/spitz.h index 685749a51c4..0bfe6507c95 100644 --- a/arch/arm/mach-pxa/include/mach/spitz.h +++ b/arch/arm/mach-pxa/include/mach/spitz.h @@ -108,7 +108,7 @@ #define SPITZ_SCP_SUS_CLR (SPITZ_SCP_MUTE_L | SPITZ_SCP_MUTE_R | SPITZ_SCP_JK_A | SPITZ_SCP_ADC_TEMP_ON) #define SPITZ_SCP_SUS_SET 0 -#define SPITZ_SCP_GPIO_BASE (NR_BUILTIN_GPIO) +#define SPITZ_SCP_GPIO_BASE (PXA_NR_BUILTIN_GPIO) #define SPITZ_GPIO_LED_GREEN (SPITZ_SCP_GPIO_BASE + 0) #define SPITZ_GPIO_JK_B (SPITZ_SCP_GPIO_BASE + 1) #define SPITZ_GPIO_CHRG_ON (SPITZ_SCP_GPIO_BASE + 2) @@ -140,7 +140,7 @@ SPITZ_SCP2_BACKLIGHT_CONT | SPITZ_SCP2_BACKLIGHT_ON | SPITZ_SCP2_MIC_BIAS) #define SPITZ_SCP2_SUS_SET (SPITZ_SCP2_IR_ON | SPITZ_SCP2_RESERVED_1) -#define SPITZ_SCP2_GPIO_BASE (NR_BUILTIN_GPIO + 12) +#define SPITZ_SCP2_GPIO_BASE (PXA_NR_BUILTIN_GPIO + 12) #define SPITZ_GPIO_IR_ON (SPITZ_SCP2_GPIO_BASE + 0) #define SPITZ_GPIO_AKIN_PULLUP (SPITZ_SCP2_GPIO_BASE + 1) #define SPITZ_GPIO_RESERVED_1 (SPITZ_SCP2_GPIO_BASE + 2) @@ -152,7 +152,7 @@ #define SPITZ_GPIO_MIC_BIAS (SPITZ_SCP2_GPIO_BASE + 8) /* Akita IO Expander GPIOs */ -#define AKITA_IOEXP_GPIO_BASE (NR_BUILTIN_GPIO + 12) +#define AKITA_IOEXP_GPIO_BASE (PXA_NR_BUILTIN_GPIO + 12) #define AKITA_GPIO_RESERVED_0 (AKITA_IOEXP_GPIO_BASE + 0) #define AKITA_GPIO_RESERVED_1 (AKITA_IOEXP_GPIO_BASE + 1) #define AKITA_GPIO_MIC_BIAS (AKITA_IOEXP_GPIO_BASE + 2) @@ -164,23 +164,23 @@ /* Spitz IRQ Definitions */ -#define SPITZ_IRQ_GPIO_KEY_INT IRQ_GPIO(SPITZ_GPIO_KEY_INT) -#define SPITZ_IRQ_GPIO_AC_IN IRQ_GPIO(SPITZ_GPIO_AC_IN) -#define SPITZ_IRQ_GPIO_AK_INT IRQ_GPIO(SPITZ_GPIO_AK_INT) -#define SPITZ_IRQ_GPIO_HP_IN IRQ_GPIO(SPITZ_GPIO_HP_IN) -#define SPITZ_IRQ_GPIO_TP_INT IRQ_GPIO(SPITZ_GPIO_TP_INT) -#define SPITZ_IRQ_GPIO_SYNC IRQ_GPIO(SPITZ_GPIO_SYNC) -#define SPITZ_IRQ_GPIO_ON_KEY IRQ_GPIO(SPITZ_GPIO_ON_KEY) -#define SPITZ_IRQ_GPIO_SWA IRQ_GPIO(SPITZ_GPIO_SWA) -#define SPITZ_IRQ_GPIO_SWB IRQ_GPIO(SPITZ_GPIO_SWB) -#define SPITZ_IRQ_GPIO_BAT_COVER IRQ_GPIO(SPITZ_GPIO_BAT_COVER) -#define SPITZ_IRQ_GPIO_FATAL_BAT IRQ_GPIO(SPITZ_GPIO_FATAL_BAT) -#define SPITZ_IRQ_GPIO_CO IRQ_GPIO(SPITZ_GPIO_CO) -#define SPITZ_IRQ_GPIO_CF_IRQ IRQ_GPIO(SPITZ_GPIO_CF_IRQ) -#define SPITZ_IRQ_GPIO_CF_CD IRQ_GPIO(SPITZ_GPIO_CF_CD) -#define SPITZ_IRQ_GPIO_CF2_IRQ IRQ_GPIO(SPITZ_GPIO_CF2_IRQ) -#define SPITZ_IRQ_GPIO_nSD_INT IRQ_GPIO(SPITZ_GPIO_nSD_INT) -#define SPITZ_IRQ_GPIO_nSD_DETECT IRQ_GPIO(SPITZ_GPIO_nSD_DETECT) +#define SPITZ_IRQ_GPIO_KEY_INT PXA_GPIO_TO_IRQ(SPITZ_GPIO_KEY_INT) +#define SPITZ_IRQ_GPIO_AC_IN PXA_GPIO_TO_IRQ(SPITZ_GPIO_AC_IN) +#define SPITZ_IRQ_GPIO_AK_INT PXA_GPIO_TO_IRQ(SPITZ_GPIO_AK_INT) +#define SPITZ_IRQ_GPIO_HP_IN PXA_GPIO_TO_IRQ(SPITZ_GPIO_HP_IN) +#define SPITZ_IRQ_GPIO_TP_INT PXA_GPIO_TO_IRQ(SPITZ_GPIO_TP_INT) +#define SPITZ_IRQ_GPIO_SYNC PXA_GPIO_TO_IRQ(SPITZ_GPIO_SYNC) +#define SPITZ_IRQ_GPIO_ON_KEY PXA_GPIO_TO_IRQ(SPITZ_GPIO_ON_KEY) +#define SPITZ_IRQ_GPIO_SWA PXA_GPIO_TO_IRQ(SPITZ_GPIO_SWA) +#define SPITZ_IRQ_GPIO_SWB PXA_GPIO_TO_IRQ(SPITZ_GPIO_SWB) +#define SPITZ_IRQ_GPIO_BAT_COVER PXA_GPIO_TO_IRQ(SPITZ_GPIO_BAT_COVER) +#define SPITZ_IRQ_GPIO_FATAL_BAT PXA_GPIO_TO_IRQ(SPITZ_GPIO_FATAL_BAT) +#define SPITZ_IRQ_GPIO_CO PXA_GPIO_TO_IRQ(SPITZ_GPIO_CO) +#define SPITZ_IRQ_GPIO_CF_IRQ PXA_GPIO_TO_IRQ(SPITZ_GPIO_CF_IRQ) +#define SPITZ_IRQ_GPIO_CF_CD PXA_GPIO_TO_IRQ(SPITZ_GPIO_CF_CD) +#define SPITZ_IRQ_GPIO_CF2_IRQ PXA_GPIO_TO_IRQ(SPITZ_GPIO_CF2_IRQ) +#define SPITZ_IRQ_GPIO_nSD_INT PXA_GPIO_TO_IRQ(SPITZ_GPIO_nSD_INT) +#define SPITZ_IRQ_GPIO_nSD_DETECT PXA_GPIO_TO_IRQ(SPITZ_GPIO_nSD_DETECT) /* * Shared data structures diff --git a/arch/arm/mach-pxa/include/mach/tosa.h b/arch/arm/mach-pxa/include/mach/tosa.h index 1272c4b56ce..2bb0e862598 100644 --- a/arch/arm/mach-pxa/include/mach/tosa.h +++ b/arch/arm/mach-pxa/include/mach/tosa.h @@ -24,7 +24,7 @@ /* * SCOOP2 internal GPIOs */ -#define TOSA_SCOOP_GPIO_BASE NR_BUILTIN_GPIO +#define TOSA_SCOOP_GPIO_BASE PXA_NR_BUILTIN_GPIO #define TOSA_SCOOP_PXA_VCORE1 SCOOP_GPCR_PA11 #define TOSA_GPIO_TC6393XB_REST_IN (TOSA_SCOOP_GPIO_BASE + 1) #define TOSA_GPIO_IR_POWERDWN (TOSA_SCOOP_GPIO_BASE + 2) @@ -42,7 +42,7 @@ /* * SCOOP2 jacket GPIOs */ -#define TOSA_SCOOP_JC_GPIO_BASE (NR_BUILTIN_GPIO + 12) +#define TOSA_SCOOP_JC_GPIO_BASE (PXA_NR_BUILTIN_GPIO + 12) #define TOSA_GPIO_BT_LED (TOSA_SCOOP_JC_GPIO_BASE + 0) #define TOSA_GPIO_NOTE_LED (TOSA_SCOOP_JC_GPIO_BASE + 1) #define TOSA_GPIO_CHRG_ERR_LED (TOSA_SCOOP_JC_GPIO_BASE + 2) @@ -59,7 +59,7 @@ /* * TC6393XB GPIOs */ -#define TOSA_TC6393XB_GPIO_BASE (NR_BUILTIN_GPIO + 2 * 12) +#define TOSA_TC6393XB_GPIO_BASE (PXA_NR_BUILTIN_GPIO + 2 * 12) #define TOSA_GPIO_TG_ON (TOSA_TC6393XB_GPIO_BASE + 0) #define TOSA_GPIO_L_MUTE (TOSA_TC6393XB_GPIO_BASE + 1) @@ -141,30 +141,30 @@ /* * Interrupts */ -#define TOSA_IRQ_GPIO_WAKEUP IRQ_GPIO(TOSA_GPIO_WAKEUP) -#define TOSA_IRQ_GPIO_AC_IN IRQ_GPIO(TOSA_GPIO_AC_IN) -#define TOSA_IRQ_GPIO_RECORD_BTN IRQ_GPIO(TOSA_GPIO_RECORD_BTN) -#define TOSA_IRQ_GPIO_SYNC IRQ_GPIO(TOSA_GPIO_SYNC) -#define TOSA_IRQ_GPIO_USB_IN IRQ_GPIO(TOSA_GPIO_USB_IN) -#define TOSA_IRQ_GPIO_JACKET_DETECT IRQ_GPIO(TOSA_GPIO_JACKET_DETECT) -#define TOSA_IRQ_GPIO_nSD_INT IRQ_GPIO(TOSA_GPIO_nSD_INT) -#define TOSA_IRQ_GPIO_nSD_DETECT IRQ_GPIO(TOSA_GPIO_nSD_DETECT) -#define TOSA_IRQ_GPIO_BAT1_CRG IRQ_GPIO(TOSA_GPIO_BAT1_CRG) -#define TOSA_IRQ_GPIO_CF_CD IRQ_GPIO(TOSA_GPIO_CF_CD) -#define TOSA_IRQ_GPIO_BAT0_CRG IRQ_GPIO(TOSA_GPIO_BAT0_CRG) -#define TOSA_IRQ_GPIO_TC6393XB_INT IRQ_GPIO(TOSA_GPIO_TC6393XB_INT) -#define TOSA_IRQ_GPIO_BAT0_LOW IRQ_GPIO(TOSA_GPIO_BAT0_LOW) -#define TOSA_IRQ_GPIO_EAR_IN IRQ_GPIO(TOSA_GPIO_EAR_IN) -#define TOSA_IRQ_GPIO_CF_IRQ IRQ_GPIO(TOSA_GPIO_CF_IRQ) -#define TOSA_IRQ_GPIO_ON_KEY IRQ_GPIO(TOSA_GPIO_ON_KEY) -#define TOSA_IRQ_GPIO_VGA_LINE IRQ_GPIO(TOSA_GPIO_VGA_LINE) -#define TOSA_IRQ_GPIO_TP_INT IRQ_GPIO(TOSA_GPIO_TP_INT) -#define TOSA_IRQ_GPIO_JC_CF_IRQ IRQ_GPIO(TOSA_GPIO_JC_CF_IRQ) -#define TOSA_IRQ_GPIO_BAT_LOCKED IRQ_GPIO(TOSA_GPIO_BAT_LOCKED) -#define TOSA_IRQ_GPIO_BAT1_LOW IRQ_GPIO(TOSA_GPIO_BAT1_LOW) -#define TOSA_IRQ_GPIO_KEY_SENSE(a) IRQ_GPIO(69+(a)) - -#define TOSA_IRQ_GPIO_MAIN_BAT_LOW IRQ_GPIO(TOSA_GPIO_MAIN_BAT_LOW) +#define TOSA_IRQ_GPIO_WAKEUP PXA_GPIO_TO_IRQ(TOSA_GPIO_WAKEUP) +#define TOSA_IRQ_GPIO_AC_IN PXA_GPIO_TO_IRQ(TOSA_GPIO_AC_IN) +#define TOSA_IRQ_GPIO_RECORD_BTN PXA_GPIO_TO_IRQ(TOSA_GPIO_RECORD_BTN) +#define TOSA_IRQ_GPIO_SYNC PXA_GPIO_TO_IRQ(TOSA_GPIO_SYNC) +#define TOSA_IRQ_GPIO_USB_IN PXA_GPIO_TO_IRQ(TOSA_GPIO_USB_IN) +#define TOSA_IRQ_GPIO_JACKET_DETECT PXA_GPIO_TO_IRQ(TOSA_GPIO_JACKET_DETECT) +#define TOSA_IRQ_GPIO_nSD_INT PXA_GPIO_TO_IRQ(TOSA_GPIO_nSD_INT) +#define TOSA_IRQ_GPIO_nSD_DETECT PXA_GPIO_TO_IRQ(TOSA_GPIO_nSD_DETECT) +#define TOSA_IRQ_GPIO_BAT1_CRG PXA_GPIO_TO_IRQ(TOSA_GPIO_BAT1_CRG) +#define TOSA_IRQ_GPIO_CF_CD PXA_GPIO_TO_IRQ(TOSA_GPIO_CF_CD) +#define TOSA_IRQ_GPIO_BAT0_CRG PXA_GPIO_TO_IRQ(TOSA_GPIO_BAT0_CRG) +#define TOSA_IRQ_GPIO_TC6393XB_INT PXA_GPIO_TO_IRQ(TOSA_GPIO_TC6393XB_INT) +#define TOSA_IRQ_GPIO_BAT0_LOW PXA_GPIO_TO_IRQ(TOSA_GPIO_BAT0_LOW) +#define TOSA_IRQ_GPIO_EAR_IN PXA_GPIO_TO_IRQ(TOSA_GPIO_EAR_IN) +#define TOSA_IRQ_GPIO_CF_IRQ PXA_GPIO_TO_IRQ(TOSA_GPIO_CF_IRQ) +#define TOSA_IRQ_GPIO_ON_KEY PXA_GPIO_TO_IRQ(TOSA_GPIO_ON_KEY) +#define TOSA_IRQ_GPIO_VGA_LINE PXA_GPIO_TO_IRQ(TOSA_GPIO_VGA_LINE) +#define TOSA_IRQ_GPIO_TP_INT PXA_GPIO_TO_IRQ(TOSA_GPIO_TP_INT) +#define TOSA_IRQ_GPIO_JC_CF_IRQ PXA_GPIO_TO_IRQ(TOSA_GPIO_JC_CF_IRQ) +#define TOSA_IRQ_GPIO_BAT_LOCKED PXA_GPIO_TO_IRQ(TOSA_GPIO_BAT_LOCKED) +#define TOSA_IRQ_GPIO_BAT1_LOW PXA_GPIO_TO_IRQ(TOSA_GPIO_BAT1_LOW) +#define TOSA_IRQ_GPIO_KEY_SENSE(a) PXA_GPIO_TO_IRQ(69+(a)) + +#define TOSA_IRQ_GPIO_MAIN_BAT_LOW PXA_GPIO_TO_IRQ(TOSA_GPIO_MAIN_BAT_LOW) #define TOSA_KEY_SYNC KEY_102ND /* ??? */ diff --git a/arch/arm/mach-pxa/include/mach/trizeps4.h b/arch/arm/mach-pxa/include/mach/trizeps4.h index 903e1a2e664..d2ca01053f6 100644 --- a/arch/arm/mach-pxa/include/mach/trizeps4.h +++ b/arch/arm/mach-pxa/include/mach/trizeps4.h @@ -43,30 +43,30 @@ /* Ethernet Controller Davicom DM9000 */ #define GPIO_DM9000 101 -#define TRIZEPS4_ETH_IRQ IRQ_GPIO(GPIO_DM9000) +#define TRIZEPS4_ETH_IRQ PXA_GPIO_TO_IRQ(GPIO_DM9000) /* UCB1400 audio / TS-controller */ #define GPIO_UCB1400 1 -#define TRIZEPS4_UCB1400_IRQ IRQ_GPIO(GPIO_UCB1400) +#define TRIZEPS4_UCB1400_IRQ PXA_GPIO_TO_IRQ(GPIO_UCB1400) /* PCMCIA socket Compact Flash */ #define GPIO_PCD 11 /* PCMCIA Card Detect */ -#define TRIZEPS4_CD_IRQ IRQ_GPIO(GPIO_PCD) +#define TRIZEPS4_CD_IRQ PXA_GPIO_TO_IRQ(GPIO_PCD) #define GPIO_PRDY 13 /* READY / nINT */ -#define TRIZEPS4_READY_NINT IRQ_GPIO(GPIO_PRDY) +#define TRIZEPS4_READY_NINT PXA_GPIO_TO_IRQ(GPIO_PRDY) /* MMC socket */ #define GPIO_MMC_DET 12 -#define TRIZEPS4_MMC_IRQ IRQ_GPIO(GPIO_MMC_DET) +#define TRIZEPS4_MMC_IRQ PXA_GPIO_TO_IRQ(GPIO_MMC_DET) /* DOC NAND chip */ #define GPIO_DOC_LOCK 94 #define GPIO_DOC_IRQ 93 -#define TRIZEPS4_DOC_IRQ IRQ_GPIO(GPIO_DOC_IRQ) +#define TRIZEPS4_DOC_IRQ PXA_GPIO_TO_IRQ(GPIO_DOC_IRQ) /* SPI interface */ #define GPIO_SPI 53 -#define TRIZEPS4_SPI_IRQ IRQ_GPIO(GPIO_SPI) +#define TRIZEPS4_SPI_IRQ PXA_GPIO_TO_IRQ(GPIO_SPI) /* LEDS using tx2 / rx2 */ #define GPIO_SYS_BUSY_LED 46 @@ -74,7 +74,7 @@ /* Off-module PIC on ConXS board */ #define GPIO_PIC 0 -#define TRIZEPS4_PIC_IRQ IRQ_GPIO(GPIO_PIC) +#define TRIZEPS4_PIC_IRQ PXA_GPIO_TO_IRQ(GPIO_PIC) #ifdef CONFIG_MACH_TRIZEPS_CONXS /* for CONXS base board define these registers */ diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c index 532c5d3a97d..5dae15ea671 100644 --- a/arch/arm/mach-pxa/irq.c +++ b/arch/arm/mach-pxa/irq.c @@ -22,7 +22,6 @@ #include <mach/hardware.h> #include <mach/irqs.h> -#include <mach/gpio-pxa.h> #include "generic.h" @@ -92,44 +91,6 @@ static struct irq_chip pxa_internal_irq_chip = { .irq_unmask = pxa_unmask_irq, }; -/* - * GPIO IRQs for GPIO 0 and 1 - */ -static int pxa_set_low_gpio_type(struct irq_data *d, unsigned int type) -{ - int gpio = d->irq - IRQ_GPIO0; - - if (__gpio_is_occupied(gpio)) { - pr_err("%s failed: GPIO is configured\n", __func__); - return -EINVAL; - } - - if (type & IRQ_TYPE_EDGE_RISING) - GRER0 |= GPIO_bit(gpio); - else - GRER0 &= ~GPIO_bit(gpio); - - if (type & IRQ_TYPE_EDGE_FALLING) - GFER0 |= GPIO_bit(gpio); - else - GFER0 &= ~GPIO_bit(gpio); - - return 0; -} - -static void pxa_ack_low_gpio(struct irq_data *d) -{ - GEDR0 = (1 << (d->irq - IRQ_GPIO0)); -} - -static struct irq_chip pxa_low_gpio_chip = { - .name = "GPIO-l", - .irq_ack = pxa_ack_low_gpio, - .irq_mask = pxa_mask_irq, - .irq_unmask = pxa_unmask_irq, - .irq_set_type = pxa_set_low_gpio_type, -}; - asmlinkage void __exception_irq_entry icip_handle_irq(struct pt_regs *regs) { uint32_t icip, icmr, mask; @@ -160,26 +121,7 @@ asmlinkage void __exception_irq_entry ichp_handle_irq(struct pt_regs *regs) } while (1); } -static void __init pxa_init_low_gpio_irq(set_wake_t fn) -{ - int irq; - - /* clear edge detection on GPIO 0 and 1 */ - GFER0 &= ~0x3; - GRER0 &= ~0x3; - GEDR0 = 0x3; - - for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) { - irq_set_chip_and_handler(irq, &pxa_low_gpio_chip, - handle_edge_irq); - irq_set_chip_data(irq, irq_base(0)); - set_irq_flags(irq, IRQF_VALID); - } - - pxa_low_gpio_chip.irq_set_wake = fn; -} - -void __init pxa_init_irq(int irq_nr, set_wake_t fn) +void __init pxa_init_irq(int irq_nr, int (*fn)(struct irq_data *, unsigned int)) { int irq, i, n; @@ -209,7 +151,6 @@ void __init pxa_init_irq(int irq_nr, set_wake_t fn) __raw_writel(1, irq_base(0) + ICCR); pxa_internal_irq_chip.irq_set_wake = fn; - pxa_init_low_gpio_irq(fn); } #ifdef CONFIG_PM diff --git a/arch/arm/mach-pxa/littleton.c b/arch/arm/mach-pxa/littleton.c index c337c7eed51..1fb86edb857 100644 --- a/arch/arm/mach-pxa/littleton.c +++ b/arch/arm/mach-pxa/littleton.c @@ -124,8 +124,8 @@ static struct resource smc91x_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = IRQ_GPIO(mfp_to_gpio(MFP_PIN_GPIO90)), - .end = IRQ_GPIO(mfp_to_gpio(MFP_PIN_GPIO90)), + .start = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO90)), + .end = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO90)), .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE, } }; @@ -396,7 +396,7 @@ static struct i2c_board_info littleton_i2c_info[] = { .type = "da9034", .addr = 0x34, .platform_data = &littleton_da9034_info, - .irq = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO18)), + .irq = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO18)), }, [1] = { .type = "max7320", diff --git a/arch/arm/mach-pxa/lpd270.c b/arch/arm/mach-pxa/lpd270.c index 6119c015f39..cee9ce2fc0b 100644 --- a/arch/arm/mach-pxa/lpd270.c +++ b/arch/arm/mach-pxa/lpd270.c @@ -152,8 +152,8 @@ static void __init lpd270_init_irq(void) handle_level_irq); set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); } - irq_set_chained_handler(IRQ_GPIO(0), lpd270_irq_handler); - irq_set_irq_type(IRQ_GPIO(0), IRQ_TYPE_EDGE_FALLING); + irq_set_chained_handler(PXA_GPIO_TO_IRQ(0), lpd270_irq_handler); + irq_set_irq_type(PXA_GPIO_TO_IRQ(0), IRQ_TYPE_EDGE_FALLING); } diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c index 4b7a5287165..6ebd276aebe 100644 --- a/arch/arm/mach-pxa/lubbock.c +++ b/arch/arm/mach-pxa/lubbock.c @@ -170,8 +170,8 @@ static void __init lubbock_init_irq(void) set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); } - irq_set_chained_handler(IRQ_GPIO(0), lubbock_irq_handler); - irq_set_irq_type(IRQ_GPIO(0), IRQ_TYPE_EDGE_FALLING); + irq_set_chained_handler(PXA_GPIO_TO_IRQ(0), lubbock_irq_handler); + irq_set_irq_type(PXA_GPIO_TO_IRQ(0), IRQ_TYPE_EDGE_FALLING); } #ifdef CONFIG_PM diff --git a/arch/arm/mach-pxa/magician.c b/arch/arm/mach-pxa/magician.c index 4e6774fff42..3d6baf91396 100644 --- a/arch/arm/mach-pxa/magician.c +++ b/arch/arm/mach-pxa/magician.c @@ -184,8 +184,8 @@ static struct resource egpio_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = gpio_to_irq(GPIO13_MAGICIAN_CPLD_IRQ), - .end = gpio_to_irq(GPIO13_MAGICIAN_CPLD_IRQ), + .start = PXA_GPIO_TO_IRQ(GPIO13_MAGICIAN_CPLD_IRQ), + .end = PXA_GPIO_TO_IRQ(GPIO13_MAGICIAN_CPLD_IRQ), .flags = IORESOURCE_IRQ, }, }; @@ -468,8 +468,8 @@ static struct resource pasic3_resources[] = { }, /* No IRQ handler in the PASIC3, DS1WM needs an external IRQ */ [1] = { - .start = gpio_to_irq(GPIO107_MAGICIAN_DS1WM_IRQ), - .end = gpio_to_irq(GPIO107_MAGICIAN_DS1WM_IRQ), + .start = PXA_GPIO_TO_IRQ(GPIO107_MAGICIAN_DS1WM_IRQ), + .end = PXA_GPIO_TO_IRQ(GPIO107_MAGICIAN_DS1WM_IRQ), .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, } }; diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c index ca14555d5e1..1aebaf71946 100644 --- a/arch/arm/mach-pxa/mainstone.c +++ b/arch/arm/mach-pxa/mainstone.c @@ -178,8 +178,8 @@ static void __init mainstone_init_irq(void) MST_INTMSKENA = 0; MST_INTSETCLR = 0; - irq_set_chained_handler(IRQ_GPIO(0), mainstone_irq_handler); - irq_set_irq_type(IRQ_GPIO(0), IRQ_TYPE_EDGE_FALLING); + irq_set_chained_handler(PXA_GPIO_TO_IRQ(0), mainstone_irq_handler); + irq_set_irq_type(PXA_GPIO_TO_IRQ(0), IRQ_TYPE_EDGE_FALLING); } #ifdef CONFIG_PM diff --git a/arch/arm/mach-pxa/mfp-pxa2xx.c b/arch/arm/mach-pxa/mfp-pxa2xx.c index 43a5f6861ca..f14775536b8 100644 --- a/arch/arm/mach-pxa/mfp-pxa2xx.c +++ b/arch/arm/mach-pxa/mfp-pxa2xx.c @@ -13,6 +13,7 @@ * published by the Free Software Foundation. */ #include <linux/gpio.h> +#include <linux/gpio-pxa.h> #include <linux/module.h> #include <linux/kernel.h> #include <linux/init.h> @@ -20,7 +21,6 @@ #include <mach/pxa2xx-regs.h> #include <mach/mfp-pxa2xx.h> -#include <mach/gpio-pxa.h> #include "generic.h" @@ -29,6 +29,10 @@ #define GAFR_L(x) __GAFR(0, x) #define GAFR_U(x) __GAFR(1, x) +#define BANK_OFF(n) (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2)) +#define GPLR(x) __REG2(0x40E00000, BANK_OFF((x) >> 5)) +#define GPDR(x) __REG2(0x40E00000, BANK_OFF((x) >> 5) + 0x0c) + #define PWER_WE35 (1 << 24) struct gpio_desc { diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c index 924a3b5f8da..e80a3db735c 100644 --- a/arch/arm/mach-pxa/mioa701.c +++ b/arch/arm/mach-pxa/mioa701.c @@ -53,6 +53,7 @@ #include <mach/pxa27x-udc.h> #include <mach/camera.h> #include <mach/audio.h> +#include <mach/smemc.h> #include <media/soc_camera.h> #include <mach/mioa701.h> @@ -390,24 +391,19 @@ static struct pxamci_platform_data mioa701_mci_info = { }; /* FlashRAM */ -static struct resource strataflash_resource = { +static struct resource docg3_resource = { .start = PXA_CS0_PHYS, - .end = PXA_CS0_PHYS + SZ_64M - 1, + .end = PXA_CS0_PHYS + SZ_8K - 1, .flags = IORESOURCE_MEM, }; -static struct physmap_flash_data strataflash_data = { - .width = 2, - /* .set_vpp = mioa701_set_vpp, */ -}; - -static struct platform_device strataflash = { - .name = "physmap-flash", +static struct platform_device docg3 = { + .name = "docg3", .id = -1, - .resource = &strataflash_resource, + .resource = &docg3_resource, .num_resources = 1, .dev = { - .platform_data = &strataflash_data, + .platform_data = NULL, }, }; @@ -541,15 +537,15 @@ static struct pda_power_pdata power_pdata = { static struct resource power_resources[] = { [0] = { .name = "ac", - .start = gpio_to_irq(GPIO96_AC_DETECT), - .end = gpio_to_irq(GPIO96_AC_DETECT), + .start = PXA_GPIO_TO_IRQ(GPIO96_AC_DETECT), + .end = PXA_GPIO_TO_IRQ(GPIO96_AC_DETECT), .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE | IORESOURCE_IRQ_LOWEDGE, }, [1] = { .name = "usb", - .start = gpio_to_irq(GPIO13_nUSB_DETECT), - .end = gpio_to_irq(GPIO13_nUSB_DETECT), + .start = PXA_GPIO_TO_IRQ(GPIO13_nUSB_DETECT), + .end = PXA_GPIO_TO_IRQ(GPIO13_nUSB_DETECT), .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE | IORESOURCE_IRQ_LOWEDGE, }, @@ -685,7 +681,7 @@ static struct platform_device *devices[] __initdata = { &pxa2xx_pcm, &mioa701_sound, &power_dev, - &strataflash, + &docg3, &gpio_vbus, &mioa701_camera, &mioa701_board, @@ -720,6 +716,15 @@ static void __init mioa701_machine_init(void) RTTR = 32768 - 1; /* Reset crazy WinCE value */ UP2OCR = UP2OCR_HXOE; + /* + * Set up the flash memory : DiskOnChip G3 on first static memory bank + */ + __raw_writel(0x7ff02dd8, MSC0); + __raw_writel(0x0001c391, MCMEM0); + __raw_writel(0x0001c391, MCATT0); + __raw_writel(0x0001c391, MCIO0); + + pxa2xx_mfp_config(ARRAY_AND_SIZE(mioa701_pin_config)); pxa_set_ffuart_info(NULL); pxa_set_btuart_info(NULL); diff --git a/arch/arm/mach-pxa/mxm8x10.c b/arch/arm/mach-pxa/mxm8x10.c index 90928d6e1a5..83570a79e7d 100644 --- a/arch/arm/mach-pxa/mxm8x10.c +++ b/arch/arm/mach-pxa/mxm8x10.c @@ -417,8 +417,8 @@ static struct resource dm9k_resources[] = { .flags = IORESOURCE_MEM }, [2] = { - .start = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO9)), - .end = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO9)), + .start = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO9)), + .end = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO9)), .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE } }; diff --git a/arch/arm/mach-pxa/pcm990-baseboard.c b/arch/arm/mach-pxa/pcm990-baseboard.c index 6d38c6548b3..abab4e2b122 100644 --- a/arch/arm/mach-pxa/pcm990-baseboard.c +++ b/arch/arm/mach-pxa/pcm990-baseboard.c @@ -378,7 +378,7 @@ struct pxacamera_platform_data pcm990_pxacamera_platform_data = { #include <linux/i2c/pca953x.h> static struct pca953x_platform_data pca9536_data = { - .gpio_base = NR_BUILTIN_GPIO, + .gpio_base = PXA_NR_BUILTIN_GPIO, }; static int gpio_bus_switch = -EINVAL; @@ -406,9 +406,9 @@ static unsigned long pcm990_camera_query_bus_param(struct soc_camera_link *link) int ret; if (gpio_bus_switch < 0) { - ret = gpio_request(NR_BUILTIN_GPIO, "camera"); + ret = gpio_request(PXA_NR_BUILTIN_GPIO, "camera"); if (!ret) { - gpio_bus_switch = NR_BUILTIN_GPIO; + gpio_bus_switch = PXA_NR_BUILTIN_GPIO; gpio_direction_output(gpio_bus_switch, 0); } } diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c index b260ce872d2..744baee12c0 100644 --- a/arch/arm/mach-pxa/poodle.c +++ b/arch/arm/mach-pxa/poodle.c @@ -158,6 +158,11 @@ static struct scoop_pcmcia_config poodle_pcmcia_config = { EXPORT_SYMBOL(poodle_scoop_device); +static struct platform_device poodle_audio_device = { + .name = "poodle-audio", + .id = -1, +}; + /* LoCoMo device */ static struct resource locomo_resources[] = { [0] = { @@ -166,8 +171,8 @@ static struct resource locomo_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = IRQ_GPIO(10), - .end = IRQ_GPIO(10), + .start = PXA_GPIO_TO_IRQ(10), + .end = PXA_GPIO_TO_IRQ(10), .flags = IORESOURCE_IRQ, }, }; @@ -212,7 +217,7 @@ static struct spi_board_info poodle_spi_devices[] = { .bus_num = 1, .platform_data = &poodle_ads7846_info, .controller_data= &poodle_ads7846_chip, - .irq = gpio_to_irq(POODLE_GPIO_TP_INT), + .irq = PXA_GPIO_TO_IRQ(POODLE_GPIO_TP_INT), }, }; @@ -407,6 +412,7 @@ static struct platform_device sharpsl_rom_device = { static struct platform_device *devices[] __initdata = { &poodle_locomo_device, &poodle_scoop_device, + &poodle_audio_device, &sharpsl_nand_device, &sharpsl_rom_device, }; diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c index f05f9486b0c..adf058fa97e 100644 --- a/arch/arm/mach-pxa/pxa25x.c +++ b/arch/arm/mach-pxa/pxa25x.c @@ -17,6 +17,7 @@ * need be. */ #include <linux/gpio.h> +#include <linux/gpio-pxa.h> #include <linux/module.h> #include <linux/kernel.h> #include <linux/init.h> @@ -208,6 +209,8 @@ static struct clk_lookup pxa25x_clkregs[] = { INIT_CLKREG(&clk_pxa25x_gpio11, NULL, "GPIO11_CLK"), INIT_CLKREG(&clk_pxa25x_gpio12, NULL, "GPIO12_CLK"), INIT_CLKREG(&clk_pxa25x_mem, "pxa2xx-pcmcia", NULL), + INIT_CLKREG(&clk_dummy, "pxa-gpio", NULL), + INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL), }; static struct clk_lookup pxa25x_hwuart_clkreg = @@ -287,7 +290,7 @@ static inline void pxa25x_init_pm(void) {} static int pxa25x_set_wake(struct irq_data *d, unsigned int on) { - int gpio = irq_to_gpio(d->irq); + int gpio = pxa_irq_to_gpio(d->irq); uint32_t mask = 0; if (gpio >= 0 && gpio < 85) @@ -312,14 +315,12 @@ set_pwer: void __init pxa25x_init_irq(void) { pxa_init_irq(32, pxa25x_set_wake); - pxa_init_gpio(IRQ_GPIO_2_x, 2, 84, pxa25x_set_wake); } #ifdef CONFIG_CPU_PXA26x void __init pxa26x_init_irq(void) { pxa_init_irq(32, pxa25x_set_wake); - pxa_init_gpio(IRQ_GPIO_2_x, 2, 89, pxa25x_set_wake); } #endif diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c index bc5a98ebaa7..180bd8675d4 100644 --- a/arch/arm/mach-pxa/pxa27x.c +++ b/arch/arm/mach-pxa/pxa27x.c @@ -12,6 +12,7 @@ * published by the Free Software Foundation. */ #include <linux/gpio.h> +#include <linux/gpio-pxa.h> #include <linux/module.h> #include <linux/kernel.h> #include <linux/init.h> @@ -229,6 +230,8 @@ static struct clk_lookup pxa27x_clkregs[] = { INIT_CLKREG(&clk_pxa27x_im, NULL, "IMCLK"), INIT_CLKREG(&clk_pxa27x_memc, NULL, "MEMCLK"), INIT_CLKREG(&clk_pxa27x_mem, "pxa2xx-pcmcia", NULL), + INIT_CLKREG(&clk_dummy, "pxa-gpio", NULL), + INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL), }; #ifdef CONFIG_PM @@ -355,7 +358,7 @@ static inline void pxa27x_init_pm(void) {} */ static int pxa27x_set_wake(struct irq_data *d, unsigned int on) { - int gpio = irq_to_gpio(d->irq); + int gpio = pxa_irq_to_gpio(d->irq); uint32_t mask; if (gpio >= 0 && gpio < 128) @@ -386,7 +389,6 @@ static int pxa27x_set_wake(struct irq_data *d, unsigned int on) void __init pxa27x_init_irq(void) { pxa_init_irq(34, pxa27x_set_wake); - pxa_init_gpio(IRQ_GPIO_2_x, 2, 120, pxa27x_set_wake); } static struct map_desc pxa27x_io_desc[] __initdata = { @@ -422,6 +424,7 @@ void __init pxa27x_set_i2c_power_info(struct i2c_pxa_platform_data *info) } static struct platform_device *devices[] __initdata = { + &pxa_device_gpio, &pxa27x_device_udc, &pxa_device_pmu, &pxa_device_i2s, diff --git a/arch/arm/mach-pxa/pxa300.c b/arch/arm/mach-pxa/pxa300.c index 40bb16501d8..0388eda7878 100644 --- a/arch/arm/mach-pxa/pxa300.c +++ b/arch/arm/mach-pxa/pxa300.c @@ -89,6 +89,7 @@ static DEFINE_PXA3_CKEN(gcu, PXA300_GCU, 0, 0); static struct clk_lookup common_clkregs[] = { INIT_CLKREG(&clk_common_nand, "pxa3xx-nand", NULL), INIT_CLKREG(&clk_gcu, "pxa3xx-gcu", NULL), + INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL), }; static DEFINE_PXA3_CKEN(pxa310_mmc3, MMC3, 19500000, 0); diff --git a/arch/arm/mach-pxa/pxa320.c b/arch/arm/mach-pxa/pxa320.c index 8d614ecd8e9..d487e1ff4c9 100644 --- a/arch/arm/mach-pxa/pxa320.c +++ b/arch/arm/mach-pxa/pxa320.c @@ -83,6 +83,7 @@ static DEFINE_PXA3_CKEN(gcu, PXA320_GCU, 0, 0); static struct clk_lookup pxa320_clkregs[] = { INIT_CLKREG(&clk_pxa320_nand, "pxa3xx-nand", NULL), INIT_CLKREG(&clk_gcu, "pxa3xx-gcu", NULL), + INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL), }; static int __init pxa320_init(void) diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c index 0737c59b88a..f107c71c758 100644 --- a/arch/arm/mach-pxa/pxa3xx.c +++ b/arch/arm/mach-pxa/pxa3xx.c @@ -25,7 +25,6 @@ #include <asm/mach/map.h> #include <asm/suspend.h> #include <mach/hardware.h> -#include <mach/gpio-pxa.h> #include <mach/pxa3xx-regs.h> #include <mach/reset.h> #include <mach/ohci.h> @@ -56,6 +55,7 @@ static DEFINE_PXA3_CKEN(pxa3xx_pwm0, PWM0, 13000000, 0); static DEFINE_PXA3_CKEN(pxa3xx_pwm1, PWM1, 13000000, 0); static DEFINE_PXA3_CKEN(pxa3xx_mmc1, MMC1, 19500000, 0); static DEFINE_PXA3_CKEN(pxa3xx_mmc2, MMC2, 19500000, 0); +static DEFINE_PXA3_CKEN(pxa3xx_gpio, GPIO, 13000000, 0); static DEFINE_CK(pxa3xx_lcd, LCD, &clk_pxa3xx_hsio_ops); static DEFINE_CK(pxa3xx_smemc, SMC, &clk_pxa3xx_smemc_ops); @@ -67,6 +67,7 @@ static struct clk_lookup pxa3xx_clkregs[] = { INIT_CLKREG(&clk_pxa3xx_pout, NULL, "CLK_POUT"), /* Power I2C clock is always on */ INIT_CLKREG(&clk_dummy, "pxa3xx-pwri2c.1", NULL), + INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL), INIT_CLKREG(&clk_pxa3xx_lcd, "pxa2xx-fb", NULL), INIT_CLKREG(&clk_pxa3xx_camera, NULL, "CAMCLK"), INIT_CLKREG(&clk_pxa3xx_ac97, NULL, "AC97CLK"), @@ -88,6 +89,7 @@ static struct clk_lookup pxa3xx_clkregs[] = { INIT_CLKREG(&clk_pxa3xx_mmc1, "pxa2xx-mci.0", NULL), INIT_CLKREG(&clk_pxa3xx_mmc2, "pxa2xx-mci.1", NULL), INIT_CLKREG(&clk_pxa3xx_smemc, "pxa2xx-pcmcia", NULL), + INIT_CLKREG(&clk_pxa3xx_gpio, "pxa-gpio", NULL), }; #ifdef CONFIG_PM @@ -365,7 +367,8 @@ static struct irq_chip pxa_ext_wakeup_chip = { .irq_set_type = pxa_set_ext_wakeup_type, }; -static void __init pxa_init_ext_wakeup_irq(set_wake_t fn) +static void __init pxa_init_ext_wakeup_irq(int (*fn)(struct irq_data *, + unsigned int)) { int irq; @@ -388,7 +391,6 @@ void __init pxa3xx_init_irq(void) pxa_init_irq(56, pxa3xx_set_wake); pxa_init_ext_wakeup_irq(pxa3xx_set_wake); - pxa_init_gpio(IRQ_GPIO_2_x, 2, 127, NULL); } static struct map_desc pxa3xx_io_desc[] __initdata = { @@ -417,6 +419,7 @@ void __init pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info) } static struct platform_device *devices[] __initdata = { + &pxa_device_gpio, &pxa27x_device_udc, &pxa_device_pmu, &pxa_device_i2s, diff --git a/arch/arm/mach-pxa/pxa95x.c b/arch/arm/mach-pxa/pxa95x.c index 51371b39d2a..fccc644702e 100644 --- a/arch/arm/mach-pxa/pxa95x.c +++ b/arch/arm/mach-pxa/pxa95x.c @@ -20,7 +20,6 @@ #include <linux/syscore_ops.h> #include <mach/hardware.h> -#include <mach/gpio-pxa.h> #include <mach/pxa3xx-regs.h> #include <mach/pxa930.h> #include <mach/reset.h> @@ -212,11 +211,13 @@ static DEFINE_PXA3_CKEN(pxa95x_ssp3, SSP3, 13000000, 0); static DEFINE_PXA3_CKEN(pxa95x_ssp4, SSP4, 13000000, 0); static DEFINE_PXA3_CKEN(pxa95x_pwm0, PWM0, 13000000, 0); static DEFINE_PXA3_CKEN(pxa95x_pwm1, PWM1, 13000000, 0); +static DEFINE_PXA3_CKEN(pxa95x_gpio, GPIO, 13000000, 0); static struct clk_lookup pxa95x_clkregs[] = { INIT_CLKREG(&clk_pxa95x_pout, NULL, "CLK_POUT"), /* Power I2C clock is always on */ INIT_CLKREG(&clk_dummy, "pxa3xx-pwri2c.1", NULL), + INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL), INIT_CLKREG(&clk_pxa95x_lcd, "pxa2xx-fb", NULL), INIT_CLKREG(&clk_pxa95x_ffuart, "pxa2xx-uart.0", NULL), INIT_CLKREG(&clk_pxa95x_btuart, "pxa2xx-uart.1", NULL), @@ -230,12 +231,12 @@ static struct clk_lookup pxa95x_clkregs[] = { INIT_CLKREG(&clk_pxa95x_ssp4, "pxa27x-ssp.3", NULL), INIT_CLKREG(&clk_pxa95x_pwm0, "pxa27x-pwm.0", NULL), INIT_CLKREG(&clk_pxa95x_pwm1, "pxa27x-pwm.1", NULL), + INIT_CLKREG(&clk_pxa95x_gpio, "pxa-gpio", NULL), }; void __init pxa95x_init_irq(void) { pxa_init_irq(96, NULL); - pxa_init_gpio(IRQ_GPIO_2_x, 2, 127, NULL); } /* @@ -248,6 +249,7 @@ void __init pxa95x_set_i2c_power_info(struct i2c_pxa_platform_data *info) } static struct platform_device *devices[] __initdata = { + &pxa_device_gpio, &sa1100_device_rtc, &pxa_device_rtc, &pxa27x_device_ssp1, diff --git a/arch/arm/mach-pxa/raumfeld.c b/arch/arm/mach-pxa/raumfeld.c index 4962b167662..22818c7694a 100644 --- a/arch/arm/mach-pxa/raumfeld.c +++ b/arch/arm/mach-pxa/raumfeld.c @@ -292,8 +292,8 @@ static struct resource smc91x_resources[] = { .flags = IORESOURCE_MEM, }, { - .start = gpio_to_irq(GPIO_ETH_IRQ), - .end = gpio_to_irq(GPIO_ETH_IRQ), + .start = PXA_GPIO_TO_IRQ(GPIO_ETH_IRQ), + .end = PXA_GPIO_TO_IRQ(GPIO_ETH_IRQ), .flags = IORESOURCE_IRQ | IRQF_TRIGGER_FALLING, } }; @@ -672,7 +672,7 @@ static struct lis3lv02d_platform_data lis3_pdata = { .chip_select = 1, \ .controller_data = (void *) GPIO_ACCEL_CS, \ .platform_data = &lis3_pdata, \ - .irq = gpio_to_irq(GPIO_ACCEL_IRQ), \ + .irq = PXA_GPIO_TO_IRQ(GPIO_ACCEL_IRQ), \ } #define SPI_DAC7512 \ @@ -956,7 +956,7 @@ static struct eeti_ts_platform_data eeti_ts_pdata = { static struct i2c_board_info raumfeld_controller_i2c_board_info __initdata = { .type = "eeti_ts", .addr = 0x0a, - .irq = gpio_to_irq(GPIO_TOUCH_IRQ), + .irq = PXA_GPIO_TO_IRQ(GPIO_TOUCH_IRQ), .platform_data = &eeti_ts_pdata, }; diff --git a/arch/arm/mach-pxa/saar.c b/arch/arm/mach-pxa/saar.c index 878707056e6..0fe354efb93 100644 --- a/arch/arm/mach-pxa/saar.c +++ b/arch/arm/mach-pxa/saar.c @@ -96,8 +96,8 @@ static struct resource smc91x_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO97)), - .end = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO97)), + .start = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO97)), + .end = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO97)), .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, } }; @@ -502,7 +502,7 @@ static struct i2c_board_info saar_i2c_info[] = { .type = "da9034", .addr = 0x34, .platform_data = &saar_da9034_info, - .irq = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO83)), + .irq = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO83)), }, }; diff --git a/arch/arm/mach-pxa/saarb.c b/arch/arm/mach-pxa/saarb.c index b6dbaca460c..febc809ed5a 100644 --- a/arch/arm/mach-pxa/saarb.c +++ b/arch/arm/mach-pxa/saarb.c @@ -92,7 +92,7 @@ static struct i2c_board_info saarb_i2c_info[] = { .type = "88PM860x", .addr = 0x34, .platform_data = &saarb_pm8607_info, - .irq = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO83)), + .irq = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO83)), }, }; diff --git a/arch/arm/mach-pxa/sharpsl_pm.c b/arch/arm/mach-pxa/sharpsl_pm.c index 785880f67b6..8d5168d253a 100644 --- a/arch/arm/mach-pxa/sharpsl_pm.c +++ b/arch/arm/mach-pxa/sharpsl_pm.c @@ -907,24 +907,24 @@ static int __devinit sharpsl_pm_probe(struct platform_device *pdev) gpio_direction_input(sharpsl_pm.machinfo->gpio_batlock); /* Register interrupt handlers */ - if (request_irq(IRQ_GPIO(sharpsl_pm.machinfo->gpio_acin), sharpsl_ac_isr, IRQF_DISABLED | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, "AC Input Detect", sharpsl_ac_isr)) { - dev_err(sharpsl_pm.dev, "Could not get irq %d.\n", IRQ_GPIO(sharpsl_pm.machinfo->gpio_acin)); + if (request_irq(PXA_GPIO_TO_IRQ(sharpsl_pm.machinfo->gpio_acin), sharpsl_ac_isr, IRQF_DISABLED | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, "AC Input Detect", sharpsl_ac_isr)) { + dev_err(sharpsl_pm.dev, "Could not get irq %d.\n", PXA_GPIO_TO_IRQ(sharpsl_pm.machinfo->gpio_acin)); } - if (request_irq(IRQ_GPIO(sharpsl_pm.machinfo->gpio_batlock), sharpsl_fatal_isr, IRQF_DISABLED | IRQF_TRIGGER_FALLING, "Battery Cover", sharpsl_fatal_isr)) { - dev_err(sharpsl_pm.dev, "Could not get irq %d.\n", IRQ_GPIO(sharpsl_pm.machinfo->gpio_batlock)); + if (request_irq(PXA_GPIO_TO_IRQ(sharpsl_pm.machinfo->gpio_batlock), sharpsl_fatal_isr, IRQF_DISABLED | IRQF_TRIGGER_FALLING, "Battery Cover", sharpsl_fatal_isr)) { + dev_err(sharpsl_pm.dev, "Could not get irq %d.\n", PXA_GPIO_TO_IRQ(sharpsl_pm.machinfo->gpio_batlock)); } if (sharpsl_pm.machinfo->gpio_fatal) { - if (request_irq(IRQ_GPIO(sharpsl_pm.machinfo->gpio_fatal), sharpsl_fatal_isr, IRQF_DISABLED | IRQF_TRIGGER_FALLING, "Fatal Battery", sharpsl_fatal_isr)) { - dev_err(sharpsl_pm.dev, "Could not get irq %d.\n", IRQ_GPIO(sharpsl_pm.machinfo->gpio_fatal)); + if (request_irq(PXA_GPIO_TO_IRQ(sharpsl_pm.machinfo->gpio_fatal), sharpsl_fatal_isr, IRQF_DISABLED | IRQF_TRIGGER_FALLING, "Fatal Battery", sharpsl_fatal_isr)) { + dev_err(sharpsl_pm.dev, "Could not get irq %d.\n", PXA_GPIO_TO_IRQ(sharpsl_pm.machinfo->gpio_fatal)); } } if (sharpsl_pm.machinfo->batfull_irq) { /* Register interrupt handler. */ - if (request_irq(IRQ_GPIO(sharpsl_pm.machinfo->gpio_batfull), sharpsl_chrg_full_isr, IRQF_DISABLED | IRQF_TRIGGER_RISING, "CO", sharpsl_chrg_full_isr)) { - dev_err(sharpsl_pm.dev, "Could not get irq %d.\n", IRQ_GPIO(sharpsl_pm.machinfo->gpio_batfull)); + if (request_irq(PXA_GPIO_TO_IRQ(sharpsl_pm.machinfo->gpio_batfull), sharpsl_chrg_full_isr, IRQF_DISABLED | IRQF_TRIGGER_RISING, "CO", sharpsl_chrg_full_isr)) { + dev_err(sharpsl_pm.dev, "Could not get irq %d.\n", PXA_GPIO_TO_IRQ(sharpsl_pm.machinfo->gpio_batfull)); } } @@ -953,14 +953,14 @@ static int sharpsl_pm_remove(struct platform_device *pdev) led_trigger_unregister_simple(sharpsl_charge_led_trigger); - free_irq(IRQ_GPIO(sharpsl_pm.machinfo->gpio_acin), sharpsl_ac_isr); - free_irq(IRQ_GPIO(sharpsl_pm.machinfo->gpio_batlock), sharpsl_fatal_isr); + free_irq(PXA_GPIO_TO_IRQ(sharpsl_pm.machinfo->gpio_acin), sharpsl_ac_isr); + free_irq(PXA_GPIO_TO_IRQ(sharpsl_pm.machinfo->gpio_batlock), sharpsl_fatal_isr); if (sharpsl_pm.machinfo->gpio_fatal) - free_irq(IRQ_GPIO(sharpsl_pm.machinfo->gpio_fatal), sharpsl_fatal_isr); + free_irq(PXA_GPIO_TO_IRQ(sharpsl_pm.machinfo->gpio_fatal), sharpsl_fatal_isr); if (sharpsl_pm.machinfo->batfull_irq) - free_irq(IRQ_GPIO(sharpsl_pm.machinfo->gpio_batfull), sharpsl_chrg_full_isr); + free_irq(PXA_GPIO_TO_IRQ(sharpsl_pm.machinfo->gpio_batfull), sharpsl_chrg_full_isr); gpio_free(sharpsl_pm.machinfo->gpio_batlock); gpio_free(sharpsl_pm.machinfo->gpio_batfull); diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c index a7f81a3fd13..abf355d0c92 100644 --- a/arch/arm/mach-pxa/spitz.c +++ b/arch/arm/mach-pxa/spitz.c @@ -552,7 +552,7 @@ static struct spi_board_info spitz_spi_devices[] = { .chip_select = 0, .platform_data = &spitz_ads7846_info, .controller_data = &spitz_ads7846_chip, - .irq = gpio_to_irq(SPITZ_GPIO_TP_INT), + .irq = PXA_GPIO_TO_IRQ(SPITZ_GPIO_TP_INT), }, { .modalias = "corgi-lcd", .max_speed_hz = 50000, diff --git a/arch/arm/mach-pxa/spitz_pm.c b/arch/arm/mach-pxa/spitz_pm.c index 094279aefe9..34cbdac5152 100644 --- a/arch/arm/mach-pxa/spitz_pm.c +++ b/arch/arm/mach-pxa/spitz_pm.c @@ -15,6 +15,7 @@ #include <linux/kernel.h> #include <linux/delay.h> #include <linux/gpio.h> +#include <linux/gpio-pxa.h> #include <linux/interrupt.h> #include <linux/platform_device.h> #include <linux/apm-emulation.h> @@ -41,6 +42,7 @@ static int spitz_last_ac_status; static struct gpio spitz_charger_gpios[] = { { SPITZ_GPIO_KEY_INT, GPIOF_IN, "Keyboard Interrupt" }, { SPITZ_GPIO_SYNC, GPIOF_IN, "Sync" }, + { SPITZ_GPIO_AC_IN, GPIOF_IN, "Charger Detection" }, { SPITZ_GPIO_ADC_TEMP_ON, GPIOF_OUT_INIT_LOW, "ADC Temp On" }, { SPITZ_GPIO_JK_B, GPIOF_OUT_INIT_LOW, "JK B" }, { SPITZ_GPIO_CHRG_ON, GPIOF_OUT_INIT_LOW, "Charger On" }, @@ -169,14 +171,19 @@ static int spitz_should_wakeup(unsigned int resume_on_alarm) static unsigned long spitz_charger_wakeup(void) { - return (~GPLR0 & GPIO_bit(SPITZ_GPIO_KEY_INT)) | (GPLR0 & GPIO_bit(SPITZ_GPIO_SYNC)); + unsigned long ret; + ret = (!gpio_get_value(SPITZ_GPIO_KEY_INT) + << GPIO_bit(SPITZ_GPIO_KEY_INT)) + | (!gpio_get_value(SPITZ_GPIO_SYNC) + << GPIO_bit(SPITZ_GPIO_SYNC)); + return ret; } unsigned long spitzpm_read_devdata(int type) { switch (type) { case SHARPSL_STATUS_ACIN: - return (((~GPLR(SPITZ_GPIO_AC_IN)) & GPIO_bit(SPITZ_GPIO_AC_IN)) != 0); + return !gpio_get_value(SPITZ_GPIO_AC_IN); case SHARPSL_STATUS_LOCK: return gpio_get_value(sharpsl_pm.machinfo->gpio_batlock); case SHARPSL_STATUS_CHRGFULL: diff --git a/arch/arm/mach-pxa/stargate2.c b/arch/arm/mach-pxa/stargate2.c index 80d7f23ad0f..b0656e158d9 100644 --- a/arch/arm/mach-pxa/stargate2.c +++ b/arch/arm/mach-pxa/stargate2.c @@ -376,7 +376,7 @@ static struct spi_board_info spi_board_info[] __initdata = { .bus_num = 1, .chip_select = 0, .controller_data = &staccel_chip_info, - .irq = IRQ_GPIO(96), + .irq = PXA_GPIO_TO_IRQ(96), }, { .modalias = "cc2420", .max_speed_hz = 6500000, @@ -546,7 +546,7 @@ static struct i2c_board_info __initdata imote2_pwr_i2c_board_info[] = { .type = "da9030", .addr = 0x49, .platform_data = &imote2_da9030_pdata, - .irq = gpio_to_irq(1), + .irq = PXA_GPIO_TO_IRQ(1), }, }; @@ -560,18 +560,18 @@ static struct i2c_board_info __initdata imote2_i2c_board_info[] = { /* Through a nand gate - Also beware, on V2 sensor board the * pull up resistors are missing. */ - .irq = IRQ_GPIO(99), + .irq = PXA_GPIO_TO_IRQ(99), }, { /* ITS400 Sensor board only */ .type = "tsl2561", .addr = 0x49, /* Through a nand gate - Also beware, on V2 sensor board the * pull up resistors are missing. */ - .irq = IRQ_GPIO(99), + .irq = PXA_GPIO_TO_IRQ(99), }, { /* ITS400 Sensor board only */ .type = "tmp175", .addr = 0x4A, - .irq = IRQ_GPIO(96), + .irq = PXA_GPIO_TO_IRQ(96), }, { /* IMB400 Multimedia board */ .type = "wm8940", .addr = 0x1A, @@ -593,10 +593,16 @@ static struct pxa2xx_udc_mach_info imote2_udc_info __initdata = { .udc_command = sg2_udc_command, }; +static struct platform_device imote2_audio_device = { + .name = "imote2-audio", + .id = -1, +}; + static struct platform_device *imote2_devices[] = { &stargate2_flash_device, &imote2_leds, &sht15, + &imote2_audio_device, }; static void __init imote2_init(void) @@ -661,8 +667,8 @@ static struct resource smc91x_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = IRQ_GPIO(40), - .end = IRQ_GPIO(40), + .start = PXA_GPIO_TO_IRQ(40), + .end = PXA_GPIO_TO_IRQ(40), .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, } }; @@ -707,7 +713,7 @@ static int stargate2_mci_init(struct device *dev, } gpio_direction_input(SG2_GPIO_nSD_DETECT); - err = request_irq(IRQ_GPIO(SG2_GPIO_nSD_DETECT), + err = request_irq(PXA_GPIO_TO_IRQ(SG2_GPIO_nSD_DETECT), stargate2_detect_int, IRQ_TYPE_EDGE_BOTH, "MMC card detect", @@ -738,7 +744,7 @@ static void stargate2_mci_setpower(struct device *dev, unsigned int vdd) static void stargate2_mci_exit(struct device *dev, void *data) { - free_irq(IRQ_GPIO(SG2_GPIO_nSD_DETECT), data); + free_irq(PXA_GPIO_TO_IRQ(SG2_GPIO_nSD_DETECT), data); gpio_free(SG2_SD_POWER_ENABLE); gpio_free(SG2_GPIO_nSD_DETECT); } @@ -913,7 +919,7 @@ static struct i2c_board_info __initdata stargate2_pwr_i2c_board_info[] = { .type = "da9030", .addr = 0x49, .platform_data = &stargate2_da9030_pdata, - .irq = gpio_to_irq(1), + .irq = PXA_GPIO_TO_IRQ(1), }, }; @@ -938,18 +944,18 @@ static struct i2c_board_info __initdata stargate2_i2c_board_info[] = { /* Through a nand gate - Also beware, on V2 sensor board the * pull up resistors are missing. */ - .irq = IRQ_GPIO(99), + .irq = PXA_GPIO_TO_IRQ(99), }, { /* ITS400 Sensor board only */ .type = "tsl2561", .addr = 0x49, /* Through a nand gate - Also beware, on V2 sensor board the * pull up resistors are missing. */ - .irq = IRQ_GPIO(99), + .irq = PXA_GPIO_TO_IRQ(99), }, { /* ITS400 Sensor board only */ .type = "tmp175", .addr = 0x4A, - .irq = IRQ_GPIO(96), + .irq = PXA_GPIO_TO_IRQ(96), }, }; diff --git a/arch/arm/mach-pxa/tavorevb.c b/arch/arm/mach-pxa/tavorevb.c index 4fa36a3e383..9fb38e80e07 100644 --- a/arch/arm/mach-pxa/tavorevb.c +++ b/arch/arm/mach-pxa/tavorevb.c @@ -85,8 +85,8 @@ static struct resource smc91x_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO47)), - .end = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO47)), + .start = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO47)), + .end = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO47)), .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, } }; diff --git a/arch/arm/mach-pxa/tavorevb3.c b/arch/arm/mach-pxa/tavorevb3.c index 8a22879f0bb..f7d9305cfd7 100644 --- a/arch/arm/mach-pxa/tavorevb3.c +++ b/arch/arm/mach-pxa/tavorevb3.c @@ -101,7 +101,7 @@ static struct i2c_board_info evb3_i2c_info[] = { .type = "88PM860x", .addr = 0x34, .platform_data = &evb3_pm8607_info, - .irq = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO83)), + .irq = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO83)), }, }; diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c index dfe40f8705a..4d4eb60bad1 100644 --- a/arch/arm/mach-pxa/tosa.c +++ b/arch/arm/mach-pxa/tosa.c @@ -404,8 +404,8 @@ static struct pda_power_pdata tosa_power_data = { static struct resource tosa_power_resource[] = { { .name = "ac", - .start = gpio_to_irq(TOSA_GPIO_AC_IN), - .end = gpio_to_irq(TOSA_GPIO_AC_IN), + .start = PXA_GPIO_TO_IRQ(TOSA_GPIO_AC_IN), + .end = PXA_GPIO_TO_IRQ(TOSA_GPIO_AC_IN), .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE | IORESOURCE_IRQ_LOWEDGE, @@ -889,6 +889,11 @@ static struct platform_device wm9712_device = { .id = -1, }; +static struct platform_device tosa_audio_device = { + .name = "tosa-audio", + .id = -1, +}; + static struct platform_device *devices[] __initdata = { &tosascoop_device, &tosascoop_jc_device, @@ -901,6 +906,7 @@ static struct platform_device *devices[] __initdata = { &sharpsl_rom_device, &wm9712_device, &tosa_gpio_vbus, + &tosa_audio_device, }; static void tosa_poweroff(void) diff --git a/arch/arm/mach-pxa/viper.c b/arch/arm/mach-pxa/viper.c index afe2b749552..023d6ca789d 100644 --- a/arch/arm/mach-pxa/viper.c +++ b/arch/arm/mach-pxa/viper.c @@ -422,8 +422,8 @@ static struct resource smc91x_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = gpio_to_irq(VIPER_ETH_GPIO), - .end = gpio_to_irq(VIPER_ETH_GPIO), + .start = PXA_GPIO_TO_IRQ(VIPER_ETH_GPIO), + .end = PXA_GPIO_TO_IRQ(VIPER_ETH_GPIO), .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, }, [2] = { @@ -546,7 +546,7 @@ static struct plat_serial8250_port serial_platform_data[] = { /* External UARTs */ { .mapbase = VIPER_UARTA_PHYS, - .irq = gpio_to_irq(VIPER_UARTA_GPIO), + .irq = PXA_GPIO_TO_IRQ(VIPER_UARTA_GPIO), .irqflags = IRQF_TRIGGER_RISING, .uartclk = 1843200, .regshift = 1, @@ -556,7 +556,7 @@ static struct plat_serial8250_port serial_platform_data[] = { }, { .mapbase = VIPER_UARTB_PHYS, - .irq = gpio_to_irq(VIPER_UARTB_GPIO), + .irq = PXA_GPIO_TO_IRQ(VIPER_UARTB_GPIO), .irqflags = IRQF_TRIGGER_RISING, .uartclk = 1843200, .regshift = 1, @@ -596,8 +596,8 @@ static struct resource isp116x_resources[] = { .flags = IORESOURCE_MEM, }, [2] = { - .start = gpio_to_irq(VIPER_USB_GPIO), - .end = gpio_to_irq(VIPER_USB_GPIO), + .start = PXA_GPIO_TO_IRQ(VIPER_USB_GPIO), + .end = PXA_GPIO_TO_IRQ(VIPER_USB_GPIO), .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, }, }; diff --git a/arch/arm/mach-pxa/vpac270.c b/arch/arm/mach-pxa/vpac270.c index fed5fb08871..1f5cfa96f6d 100644 --- a/arch/arm/mach-pxa/vpac270.c +++ b/arch/arm/mach-pxa/vpac270.c @@ -395,8 +395,8 @@ static struct resource vpac270_dm9000_resources[] = { .flags = IORESOURCE_MEM, }, [2] = { - .start = IRQ_GPIO(GPIO114_VPAC270_ETH_IRQ), - .end = IRQ_GPIO(GPIO114_VPAC270_ETH_IRQ), + .start = PXA_GPIO_TO_IRQ(GPIO114_VPAC270_ETH_IRQ), + .end = PXA_GPIO_TO_IRQ(GPIO114_VPAC270_ETH_IRQ), .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, }, }; @@ -433,7 +433,7 @@ static pxa2xx_audio_ops_t vpac270_ac97_pdata = { }; static struct ucb1400_pdata vpac270_ucb1400_pdata = { - .irq = IRQ_GPIO(GPIO113_VPAC270_TS_IRQ), + .irq = PXA_GPIO_TO_IRQ(GPIO113_VPAC270_TS_IRQ), }; static struct platform_device vpac270_ucb1400_device = { @@ -610,8 +610,8 @@ static struct resource vpac270_ide_resources[] = { .flags = IORESOURCE_DMA }, [3] = { /* IDE IRQ pin */ - .start = gpio_to_irq(GPIO36_VPAC270_IDE_IRQ), - .end = gpio_to_irq(GPIO36_VPAC270_IDE_IRQ), + .start = PXA_GPIO_TO_IRQ(GPIO36_VPAC270_IDE_IRQ), + .end = PXA_GPIO_TO_IRQ(GPIO36_VPAC270_IDE_IRQ), .flags = IORESOURCE_IRQ } }; diff --git a/arch/arm/mach-pxa/z2.c b/arch/arm/mach-pxa/z2.c index d75f66ab8c3..b6476848b56 100644 --- a/arch/arm/mach-pxa/z2.c +++ b/arch/arm/mach-pxa/z2.c @@ -573,7 +573,7 @@ static struct spi_board_info spi_board_info[] __initdata = { .modalias = "libertas_spi", .platform_data = &z2_lbs_pdata, .controller_data = &z2_lbs_chip_info, - .irq = gpio_to_irq(GPIO36_ZIPITZ2_WIFI_IRQ), + .irq = PXA_GPIO_TO_IRQ(GPIO36_ZIPITZ2_WIFI_IRQ), .max_speed_hz = 13000000, .bus_num = 1, .chip_select = 0, diff --git a/arch/arm/mach-pxa/zeus.c b/arch/arm/mach-pxa/zeus.c index 9db35a7fcfc..a4dd1c34705 100644 --- a/arch/arm/mach-pxa/zeus.c +++ b/arch/arm/mach-pxa/zeus.c @@ -233,7 +233,7 @@ static struct plat_serial8250_port serial_platform_data[] = { /* FIXME: Shared IRQs on COM1-COM4 will not work properly on v1i1 hardware. */ { /* COM1 */ .mapbase = 0x10000000, - .irq = gpio_to_irq(ZEUS_UARTA_GPIO), + .irq = PXA_GPIO_TO_IRQ(ZEUS_UARTA_GPIO), .irqflags = IRQF_TRIGGER_RISING, .uartclk = 14745600, .regshift = 1, @@ -242,7 +242,7 @@ static struct plat_serial8250_port serial_platform_data[] = { }, { /* COM2 */ .mapbase = 0x10800000, - .irq = gpio_to_irq(ZEUS_UARTB_GPIO), + .irq = PXA_GPIO_TO_IRQ(ZEUS_UARTB_GPIO), .irqflags = IRQF_TRIGGER_RISING, .uartclk = 14745600, .regshift = 1, @@ -251,7 +251,7 @@ static struct plat_serial8250_port serial_platform_data[] = { }, { /* COM3 */ .mapbase = 0x11000000, - .irq = gpio_to_irq(ZEUS_UARTC_GPIO), + .irq = PXA_GPIO_TO_IRQ(ZEUS_UARTC_GPIO), .irqflags = IRQF_TRIGGER_RISING, .uartclk = 14745600, .regshift = 1, @@ -260,7 +260,7 @@ static struct plat_serial8250_port serial_platform_data[] = { }, { /* COM4 */ .mapbase = 0x11800000, - .irq = gpio_to_irq(ZEUS_UARTD_GPIO), + .irq = PXA_GPIO_TO_IRQ(ZEUS_UARTD_GPIO), .irqflags = IRQF_TRIGGER_RISING, .uartclk = 14745600, .regshift = 1, @@ -321,8 +321,8 @@ static struct resource zeus_dm9k0_resource[] = { .flags = IORESOURCE_MEM }, [2] = { - .start = gpio_to_irq(ZEUS_ETH0_GPIO), - .end = gpio_to_irq(ZEUS_ETH0_GPIO), + .start = PXA_GPIO_TO_IRQ(ZEUS_ETH0_GPIO), + .end = PXA_GPIO_TO_IRQ(ZEUS_ETH0_GPIO), .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE, }, }; @@ -339,8 +339,8 @@ static struct resource zeus_dm9k1_resource[] = { .flags = IORESOURCE_MEM, }, [2] = { - .start = gpio_to_irq(ZEUS_ETH1_GPIO), - .end = gpio_to_irq(ZEUS_ETH1_GPIO), + .start = PXA_GPIO_TO_IRQ(ZEUS_ETH1_GPIO), + .end = PXA_GPIO_TO_IRQ(ZEUS_ETH1_GPIO), .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE, }, }; @@ -423,7 +423,7 @@ static struct spi_board_info zeus_spi_board_info[] = { [0] = { .modalias = "mcp2515", .platform_data = &zeus_mcp2515_pdata, - .irq = gpio_to_irq(ZEUS_CAN_GPIO), + .irq = PXA_GPIO_TO_IRQ(ZEUS_CAN_GPIO), .max_speed_hz = 1*1000*1000, .bus_num = 3, .mode = SPI_MODE_0, @@ -753,7 +753,7 @@ static struct i2c_board_info __initdata zeus_i2c_devices[] = { { I2C_BOARD_INFO("pca9535", 0x20), .platform_data = &zeus_pca953x_pdata[2], - .irq = gpio_to_irq(ZEUS_EXTGPIO_GPIO), + .irq = PXA_GPIO_TO_IRQ(ZEUS_EXTGPIO_GPIO), }, { I2C_BOARD_INFO("lm75a", 0x48) }, { I2C_BOARD_INFO("24c01", 0x50) }, diff --git a/arch/arm/mach-pxa/zylonite.c b/arch/arm/mach-pxa/zylonite.c index 7678b1bf790..98eec80623e 100644 --- a/arch/arm/mach-pxa/zylonite.c +++ b/arch/arm/mach-pxa/zylonite.c @@ -408,8 +408,8 @@ static void __init zylonite_init(void) * Note: We depend that the bootloader set * the correct value to MSC register for SMC91x. */ - smc91x_resources[1].start = gpio_to_irq(gpio_eth_irq); - smc91x_resources[1].end = gpio_to_irq(gpio_eth_irq); + smc91x_resources[1].start = PXA_GPIO_TO_IRQ(gpio_eth_irq); + smc91x_resources[1].end = PXA_GPIO_TO_IRQ(gpio_eth_irq); platform_device_register(&smc91x_device); pxa_set_ac97_info(NULL); diff --git a/arch/arm/mach-pxa/zylonite_pxa300.c b/arch/arm/mach-pxa/zylonite_pxa300.c index 93c64d8d7de..86e59c043de 100644 --- a/arch/arm/mach-pxa/zylonite_pxa300.c +++ b/arch/arm/mach-pxa/zylonite_pxa300.c @@ -231,12 +231,12 @@ static struct i2c_board_info zylonite_i2c_board_info[] = { .type = "pca9539", .addr = 0x74, .platform_data = &gpio_exp[0], - .irq = IRQ_GPIO(18), + .irq = PXA_GPIO_TO_IRQ(18), }, { .type = "pca9539", .addr = 0x75, .platform_data = &gpio_exp[1], - .irq = IRQ_GPIO(19), + .irq = PXA_GPIO_TO_IRQ(19), }, }; diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c index d5ed5d4f77d..acd329afc3a 100644 --- a/arch/arm/mach-realview/core.c +++ b/arch/arm/mach-realview/core.c @@ -21,7 +21,7 @@ #include <linux/init.h> #include <linux/platform_device.h> #include <linux/dma-mapping.h> -#include <linux/sysdev.h> +#include <linux/device.h> #include <linux/interrupt.h> #include <linux/amba/bus.h> #include <linux/amba/clcd.h> diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c index f92a920cf50..0069561464f 100644 --- a/arch/arm/mach-realview/realview_eb.c +++ b/arch/arm/mach-realview/realview_eb.c @@ -21,7 +21,7 @@ #include <linux/init.h> #include <linux/platform_device.h> -#include <linux/sysdev.h> +#include <linux/device.h> #include <linux/amba/bus.h> #include <linux/amba/pl061.h> #include <linux/amba/mmci.h> diff --git a/arch/arm/mach-realview/realview_pb1176.c b/arch/arm/mach-realview/realview_pb1176.c index 8ec37b29e0f..8fe395568a4 100644 --- a/arch/arm/mach-realview/realview_pb1176.c +++ b/arch/arm/mach-realview/realview_pb1176.c @@ -21,7 +21,7 @@ #include <linux/init.h> #include <linux/platform_device.h> -#include <linux/sysdev.h> +#include <linux/device.h> #include <linux/amba/bus.h> #include <linux/amba/pl061.h> #include <linux/amba/mmci.h> diff --git a/arch/arm/mach-realview/realview_pb11mp.c b/arch/arm/mach-realview/realview_pb11mp.c index f035fda8b61..34a26011bb8 100644 --- a/arch/arm/mach-realview/realview_pb11mp.c +++ b/arch/arm/mach-realview/realview_pb11mp.c @@ -21,7 +21,7 @@ #include <linux/init.h> #include <linux/platform_device.h> -#include <linux/sysdev.h> +#include <linux/device.h> #include <linux/amba/bus.h> #include <linux/amba/pl061.h> #include <linux/amba/mmci.h> diff --git a/arch/arm/mach-realview/realview_pba8.c b/arch/arm/mach-realview/realview_pba8.c index 0109c8b440c..d26a6def1d6 100644 --- a/arch/arm/mach-realview/realview_pba8.c +++ b/arch/arm/mach-realview/realview_pba8.c @@ -21,7 +21,7 @@ #include <linux/init.h> #include <linux/platform_device.h> -#include <linux/sysdev.h> +#include <linux/device.h> #include <linux/amba/bus.h> #include <linux/amba/pl061.h> #include <linux/amba/mmci.h> diff --git a/arch/arm/mach-realview/realview_pbx.c b/arch/arm/mach-realview/realview_pbx.c index 0194b3e26dc..a250fb4124b 100644 --- a/arch/arm/mach-realview/realview_pbx.c +++ b/arch/arm/mach-realview/realview_pbx.c @@ -20,7 +20,7 @@ #include <linux/init.h> #include <linux/platform_device.h> -#include <linux/sysdev.h> +#include <linux/device.h> #include <linux/amba/bus.h> #include <linux/amba/pl061.h> #include <linux/amba/mmci.h> diff --git a/arch/arm/mach-s3c2410/bast-irq.c b/arch/arm/mach-s3c2410/bast-irq.c index bc53d2d16d1..ac7b2ad5c40 100644 --- a/arch/arm/mach-s3c2410/bast-irq.c +++ b/arch/arm/mach-s3c2410/bast-irq.c @@ -24,7 +24,7 @@ #include <linux/init.h> #include <linux/module.h> #include <linux/ioport.h> -#include <linux/sysdev.h> +#include <linux/device.h> #include <linux/io.h> #include <asm/mach-types.h> diff --git a/arch/arm/mach-s3c2410/cpu-freq.c b/arch/arm/mach-s3c2410/cpu-freq.c index 75189df995a..7dc6c46b5e2 100644 --- a/arch/arm/mach-s3c2410/cpu-freq.c +++ b/arch/arm/mach-s3c2410/cpu-freq.c @@ -16,7 +16,7 @@ #include <linux/interrupt.h> #include <linux/ioport.h> #include <linux/cpufreq.h> -#include <linux/sysdev.h> +#include <linux/device.h> #include <linux/clk.h> #include <linux/err.h> #include <linux/io.h> @@ -115,24 +115,25 @@ static struct s3c_cpufreq_info s3c2410_cpufreq_info = { .debug_io_show = s3c_cpufreq_debugfs_call(s3c2410_iotiming_debugfs), }; -static int s3c2410_cpufreq_add(struct sys_device *sysdev) +static int s3c2410_cpufreq_add(struct device *dev) { return s3c_cpufreq_register(&s3c2410_cpufreq_info); } -static struct sysdev_driver s3c2410_cpufreq_driver = { - .add = s3c2410_cpufreq_add, +static struct subsys_interface s3c2410_cpufreq_interface = { + .name = "s3c2410_cpufreq", + .subsys = &s3c2410_subsys, + .add_dev = s3c2410_cpufreq_add, }; static int __init s3c2410_cpufreq_init(void) { - return sysdev_driver_register(&s3c2410_sysclass, - &s3c2410_cpufreq_driver); + return subsys_interface_register(&s3c2410_cpufreq_interface); } arch_initcall(s3c2410_cpufreq_init); -static int s3c2410a_cpufreq_add(struct sys_device *sysdev) +static int s3c2410a_cpufreq_add(struct device *dev) { /* alter the maximum freq settings for S3C2410A. If a board knows * it only has a maximum of 200, then it should register its own @@ -143,17 +144,18 @@ static int s3c2410a_cpufreq_add(struct sys_device *sysdev) s3c2410_cpufreq_info.max.pclk = 66500000; s3c2410_cpufreq_info.name = "s3c2410a"; - return s3c2410_cpufreq_add(sysdev); + return s3c2410_cpufreq_add(dev); } -static struct sysdev_driver s3c2410a_cpufreq_driver = { - .add = s3c2410a_cpufreq_add, +static struct subsys_interface s3c2410a_cpufreq_interface = { + .name = "s3c2410a_cpufreq", + .subsys = &s3c2410a_subsys, + .add_dev = s3c2410a_cpufreq_add, }; static int __init s3c2410a_cpufreq_init(void) { - return sysdev_driver_register(&s3c2410a_sysclass, - &s3c2410a_cpufreq_driver); + return subsys_interface_register(&s3c2410a_cpufreq_interface); } arch_initcall(s3c2410a_cpufreq_init); diff --git a/arch/arm/mach-s3c2410/dma.c b/arch/arm/mach-s3c2410/dma.c index dbe43df8cfe..2afd00014a7 100644 --- a/arch/arm/mach-s3c2410/dma.c +++ b/arch/arm/mach-s3c2410/dma.c @@ -14,7 +14,7 @@ #include <linux/kernel.h> #include <linux/init.h> -#include <linux/sysdev.h> +#include <linux/device.h> #include <linux/serial_core.h> #include <mach/map.h> @@ -132,7 +132,7 @@ static struct s3c24xx_dma_order __initdata s3c2410_dma_order = { }, }; -static int __init s3c2410_dma_add(struct sys_device *sysdev) +static int __init s3c2410_dma_add(struct device *dev) { s3c2410_dma_init(); s3c24xx_dma_order_set(&s3c2410_dma_order); @@ -140,24 +140,28 @@ static int __init s3c2410_dma_add(struct sys_device *sysdev) } #if defined(CONFIG_CPU_S3C2410) -static struct sysdev_driver s3c2410_dma_driver = { - .add = s3c2410_dma_add, +static struct subsys_interface s3c2410_dma_interface = { + .name = "s3c2410_dma", + .subsys = &s3c2410_subsys, + .add_dev = s3c2410_dma_add, }; static int __init s3c2410_dma_drvinit(void) { - return sysdev_driver_register(&s3c2410_sysclass, &s3c2410_dma_driver); + return subsys_interface_register(&s3c2410_interface); } arch_initcall(s3c2410_dma_drvinit); -static struct sysdev_driver s3c2410a_dma_driver = { - .add = s3c2410_dma_add, +static struct subsys_interface s3c2410a_dma_interface = { + .name = "s3c2410a_dma", + .subsys = &s3c2410a_subsys, + .add_dev = s3c2410_dma_add, }; static int __init s3c2410a_dma_drvinit(void) { - return sysdev_driver_register(&s3c2410a_sysclass, &s3c2410a_dma_driver); + return subsys_interface_register(&s3c2410a_dma_interface); } arch_initcall(s3c2410a_dma_drvinit); @@ -165,13 +169,15 @@ arch_initcall(s3c2410a_dma_drvinit); #if defined(CONFIG_CPU_S3C2442) /* S3C2442 DMA contains the same selection table as the S3C2410 */ -static struct sysdev_driver s3c2442_dma_driver = { - .add = s3c2410_dma_add, +static struct subsys_interface s3c2442_dma_interface = { + .name = "s3c2442_dma", + .subsys = &s3c2442_subsys, + .add_dev = s3c2410_dma_add, }; static int __init s3c2442_dma_drvinit(void) { - return sysdev_driver_register(&s3c2442_sysclass, &s3c2442_dma_driver); + return subsys_interface_register(&s3c2442_dma_interface); } arch_initcall(s3c2442_dma_drvinit); diff --git a/arch/arm/mach-s3c2410/include/mach/dma.h b/arch/arm/mach-s3c2410/include/mach/dma.h index ae8e482b642..acbdfecd418 100644 --- a/arch/arm/mach-s3c2410/include/mach/dma.h +++ b/arch/arm/mach-s3c2410/include/mach/dma.h @@ -13,7 +13,7 @@ #ifndef __ASM_ARCH_DMA_H #define __ASM_ARCH_DMA_H __FILE__ -#include <linux/sysdev.h> +#include <linux/device.h> #define MAX_DMA_TRANSFER_SIZE 0x100000 /* Data Unit is half word */ @@ -202,7 +202,7 @@ struct s3c2410_dma_chan { struct s3c2410_dma_buf *end; /* end of queue */ /* system device */ - struct sys_device dev; + struct device dev; }; typedef unsigned long dma_device_t; diff --git a/arch/arm/mach-s3c2410/mach-bast.c b/arch/arm/mach-s3c2410/mach-bast.c index c6133c6ec18..feeaf73933d 100644 --- a/arch/arm/mach-s3c2410/mach-bast.c +++ b/arch/arm/mach-s3c2410/mach-bast.c @@ -165,22 +165,6 @@ static struct map_desc bast_iodesc[] __initdata = { #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE -static struct s3c24xx_uart_clksrc bast_serial_clocks[] = { - [0] = { - .name = "uclk", - .divisor = 1, - .min_baud = 0, - .max_baud = 0, - }, - [1] = { - .name = "pclk", - .divisor = 1, - .min_baud = 0, - .max_baud = 0, - } -}; - - static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = { [0] = { .hwport = 0, @@ -188,8 +172,6 @@ static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = { .ucon = UCON, .ulcon = ULCON, .ufcon = UFCON, - .clocks = bast_serial_clocks, - .clocks_size = ARRAY_SIZE(bast_serial_clocks), }, [1] = { .hwport = 1, @@ -197,8 +179,6 @@ static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = { .ucon = UCON, .ulcon = ULCON, .ufcon = UFCON, - .clocks = bast_serial_clocks, - .clocks_size = ARRAY_SIZE(bast_serial_clocks), }, /* port 2 is not actually used */ [2] = { @@ -207,8 +187,6 @@ static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = { .ucon = UCON, .ulcon = ULCON, .ufcon = UFCON, - .clocks = bast_serial_clocks, - .clocks_size = ARRAY_SIZE(bast_serial_clocks), } }; diff --git a/arch/arm/mach-s3c2410/mach-h1940.c b/arch/arm/mach-s3c2410/mach-h1940.c index ad9d865651d..41245a60398 100644 --- a/arch/arm/mach-s3c2410/mach-h1940.c +++ b/arch/arm/mach-s3c2410/mach-h1940.c @@ -18,7 +18,7 @@ #include <linux/memblock.h> #include <linux/timer.h> #include <linux/init.h> -#include <linux/sysdev.h> +#include <linux/device.h> #include <linux/serial_core.h> #include <linux/platform_device.h> #include <linux/io.h> diff --git a/arch/arm/mach-s3c2410/mach-qt2410.c b/arch/arm/mach-s3c2410/mach-qt2410.c index 58f2c17b9f0..91c16d9d245 100644 --- a/arch/arm/mach-s3c2410/mach-qt2410.c +++ b/arch/arm/mach-s3c2410/mach-qt2410.c @@ -28,7 +28,7 @@ #include <linux/timer.h> #include <linux/init.h> #include <linux/gpio.h> -#include <linux/sysdev.h> +#include <linux/device.h> #include <linux/platform_device.h> #include <linux/serial_core.h> #include <linux/spi/spi.h> diff --git a/arch/arm/mach-s3c2410/mach-vr1000.c b/arch/arm/mach-s3c2410/mach-vr1000.c index cc7032b5c65..dbe668a803e 100644 --- a/arch/arm/mach-s3c2410/mach-vr1000.c +++ b/arch/arm/mach-s3c2410/mach-vr1000.c @@ -110,23 +110,6 @@ static struct map_desc vr1000_iodesc[] __initdata = { #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE -/* uart clock source(s) */ - -static struct s3c24xx_uart_clksrc vr1000_serial_clocks[] = { - [0] = { - .name = "uclk", - .divisor = 1, - .min_baud = 0, - .max_baud = 0, - }, - [1] = { - .name = "pclk", - .divisor = 1, - .min_baud = 0, - .max_baud = 0. - } -}; - static struct s3c2410_uartcfg vr1000_uartcfgs[] __initdata = { [0] = { .hwport = 0, @@ -134,8 +117,6 @@ static struct s3c2410_uartcfg vr1000_uartcfgs[] __initdata = { .ucon = UCON, .ulcon = ULCON, .ufcon = UFCON, - .clocks = vr1000_serial_clocks, - .clocks_size = ARRAY_SIZE(vr1000_serial_clocks), }, [1] = { .hwport = 1, @@ -143,8 +124,6 @@ static struct s3c2410_uartcfg vr1000_uartcfgs[] __initdata = { .ucon = UCON, .ulcon = ULCON, .ufcon = UFCON, - .clocks = vr1000_serial_clocks, - .clocks_size = ARRAY_SIZE(vr1000_serial_clocks), }, /* port 2 is not actually used */ [2] = { @@ -153,9 +132,6 @@ static struct s3c2410_uartcfg vr1000_uartcfgs[] __initdata = { .ucon = UCON, .ulcon = ULCON, .ufcon = UFCON, - .clocks = vr1000_serial_clocks, - .clocks_size = ARRAY_SIZE(vr1000_serial_clocks), - } }; diff --git a/arch/arm/mach-s3c2410/pll.c b/arch/arm/mach-s3c2410/pll.c index 8338865e11c..c07438bfc99 100644 --- a/arch/arm/mach-s3c2410/pll.c +++ b/arch/arm/mach-s3c2410/pll.c @@ -25,7 +25,7 @@ #include <linux/types.h> #include <linux/kernel.h> #include <linux/module.h> -#include <linux/sysdev.h> +#include <linux/device.h> #include <linux/list.h> #include <linux/clk.h> #include <linux/err.h> @@ -66,30 +66,34 @@ static struct cpufreq_frequency_table pll_vals_12MHz[] = { { .frequency = 270000000, .index = PLLVAL(127, 1, 1), }, }; -static int s3c2410_plls_add(struct sys_device *dev) +static int s3c2410_plls_add(struct device *dev) { return s3c_plltab_register(pll_vals_12MHz, ARRAY_SIZE(pll_vals_12MHz)); } -static struct sysdev_driver s3c2410_plls_drv = { - .add = s3c2410_plls_add, +static struct subsys_interface s3c2410_plls_interface = { + .name = "s3c2410_plls", + .subsys = &s3c2410_subsys, + .add_dev = s3c2410_plls_add, }; static int __init s3c2410_pll_init(void) { - return sysdev_driver_register(&s3c2410_sysclass, &s3c2410_plls_drv); + return subsys_interface_register(&s3c2410_plls_interface); } arch_initcall(s3c2410_pll_init); -static struct sysdev_driver s3c2410a_plls_drv = { - .add = s3c2410_plls_add, +static struct subsys_interface s3c2410a_plls_interface = { + .name = "s3c2410a_plls", + .subsys = &s3c2410a_subsys, + .add_dev = s3c2410_plls_add, }; static int __init s3c2410a_pll_init(void) { - return sysdev_driver_register(&s3c2410a_sysclass, &s3c2410a_plls_drv); + return subsys_interface_register(&s3c2410a_plls_interface); } arch_initcall(s3c2410a_pll_init); diff --git a/arch/arm/mach-s3c2410/pm.c b/arch/arm/mach-s3c2410/pm.c index 4728f9aa7df..fda5385deff 100644 --- a/arch/arm/mach-s3c2410/pm.c +++ b/arch/arm/mach-s3c2410/pm.c @@ -24,7 +24,7 @@ #include <linux/suspend.h> #include <linux/errno.h> #include <linux/time.h> -#include <linux/sysdev.h> +#include <linux/device.h> #include <linux/syscore_ops.h> #include <linux/gpio.h> #include <linux/io.h> @@ -111,7 +111,7 @@ struct syscore_ops s3c2410_pm_syscore_ops = { .resume = s3c2410_pm_resume, }; -static int s3c2410_pm_add(struct sys_device *dev) +static int s3c2410_pm_add(struct device *dev) { pm_cpu_prep = s3c2410_pm_prepare; pm_cpu_sleep = s3c2410_cpu_suspend; @@ -120,52 +120,60 @@ static int s3c2410_pm_add(struct sys_device *dev) } #if defined(CONFIG_CPU_S3C2410) -static struct sysdev_driver s3c2410_pm_driver = { - .add = s3c2410_pm_add, +static struct subsys_interface s3c2410_pm_interface = { + .name = "s3c2410_pm", + .subsys = &s3c2410_subsys, + .add_dev = s3c2410_pm_add, }; /* register ourselves */ static int __init s3c2410_pm_drvinit(void) { - return sysdev_driver_register(&s3c2410_sysclass, &s3c2410_pm_driver); + return subsys_interface_register(&s3c2410_pm_interface); } arch_initcall(s3c2410_pm_drvinit); -static struct sysdev_driver s3c2410a_pm_driver = { - .add = s3c2410_pm_add, +static struct subsys_interface s3c2410a_pm_interface = { + .name = "s3c2410a_pm", + .subsys = &s3c2410a_subsys, + .add_dev = s3c2410_pm_add, }; static int __init s3c2410a_pm_drvinit(void) { - return sysdev_driver_register(&s3c2410a_sysclass, &s3c2410a_pm_driver); + return subsys_interface_register(&s3c2410a_pm_interface); } arch_initcall(s3c2410a_pm_drvinit); #endif #if defined(CONFIG_CPU_S3C2440) -static struct sysdev_driver s3c2440_pm_driver = { - .add = s3c2410_pm_add, +static struct subsys_interface s3c2440_pm_interface = { + .name = "s3c2440_pm", + .subsys = &s3c2440_subsys, + .add_dev = s3c2410_pm_add, }; static int __init s3c2440_pm_drvinit(void) { - return sysdev_driver_register(&s3c2440_sysclass, &s3c2440_pm_driver); + return subsys_interface_register(&s3c2440_pm_interface); } arch_initcall(s3c2440_pm_drvinit); #endif #if defined(CONFIG_CPU_S3C2442) -static struct sysdev_driver s3c2442_pm_driver = { - .add = s3c2410_pm_add, +static struct subsys_interface s3c2442_pm_interface = { + .name = "s3c2442_pm", + .subsys = &s3c2442_subsys, + .add_dev = s3c2410_pm_add, }; static int __init s3c2442_pm_drvinit(void) { - return sysdev_driver_register(&s3c2442_sysclass, &s3c2442_pm_driver); + return subsys_interface_register(&s3c2442_pm_interface); } arch_initcall(s3c2442_pm_drvinit); diff --git a/arch/arm/mach-s3c2410/s3c2410.c b/arch/arm/mach-s3c2410/s3c2410.c index 489c826e92a..061b6bb1a55 100644 --- a/arch/arm/mach-s3c2410/s3c2410.c +++ b/arch/arm/mach-s3c2410/s3c2410.c @@ -18,7 +18,7 @@ #include <linux/init.h> #include <linux/gpio.h> #include <linux/clk.h> -#include <linux/sysdev.h> +#include <linux/device.h> #include <linux/syscore_ops.h> #include <linux/serial_core.h> #include <linux/platform_device.h> @@ -124,30 +124,38 @@ static struct clk s3c2410_armclk = { .id = -1, }; +static struct clk_lookup s3c2410_clk_lookup[] = { + CLKDEV_INIT(NULL, "clk_uart_baud0", &clk_p), + CLKDEV_INIT(NULL, "clk_uart_baud1", &s3c24xx_uclk), +}; + void __init s3c2410_init_clocks(int xtal) { s3c24xx_register_baseclocks(xtal); s3c2410_setup_clocks(); s3c2410_baseclk_add(); s3c24xx_register_clock(&s3c2410_armclk); + clkdev_add_table(s3c2410_clk_lookup, ARRAY_SIZE(s3c2410_clk_lookup)); } -struct sysdev_class s3c2410_sysclass = { +struct bus_type s3c2410_subsys = { .name = "s3c2410-core", + .dev_name = "s3c2410-core", }; /* Note, we would have liked to name this s3c2410-core, but we cannot - * register two sysdev_class with the same name. + * register two subsystems with the same name. */ -struct sysdev_class s3c2410a_sysclass = { +struct bus_type s3c2410a_subsys = { .name = "s3c2410a-core", + .dev_name = "s3c2410a-core", }; -static struct sys_device s3c2410_sysdev = { - .cls = &s3c2410_sysclass, +static struct device s3c2410_dev = { + .bus = &s3c2410_subsys, }; -/* need to register class before we actually register the device, and +/* need to register the subsystem before we actually register the device, and * we also need to ensure that it has been initialised before any of the * drivers even try to use it (even if not on an s3c2410 based system) * as a driver which may support both 2410 and 2440 may try and use it. @@ -155,14 +163,14 @@ static struct sys_device s3c2410_sysdev = { static int __init s3c2410_core_init(void) { - return sysdev_class_register(&s3c2410_sysclass); + return subsys_system_register(&s3c2410_subsys, NULL); } core_initcall(s3c2410_core_init); static int __init s3c2410a_core_init(void) { - return sysdev_class_register(&s3c2410a_sysclass); + return subsys_system_register(&s3c2410a_subsys, NULL); } core_initcall(s3c2410a_core_init); @@ -176,12 +184,12 @@ int __init s3c2410_init(void) #endif register_syscore_ops(&s3c24xx_irq_syscore_ops); - return sysdev_register(&s3c2410_sysdev); + return device_register(&s3c2410_dev); } int __init s3c2410a_init(void) { - s3c2410_sysdev.cls = &s3c2410a_sysclass; + s3c2410_dev.bus = &s3c2410a_subsys; return s3c2410_init(); } diff --git a/arch/arm/mach-s3c2412/clock.c b/arch/arm/mach-s3c2412/clock.c index 140711db6c8..d10b695a906 100644 --- a/arch/arm/mach-s3c2412/clock.c +++ b/arch/arm/mach-s3c2412/clock.c @@ -26,7 +26,7 @@ #include <linux/list.h> #include <linux/errno.h> #include <linux/err.h> -#include <linux/sysdev.h> +#include <linux/device.h> #include <linux/clk.h> #include <linux/mutex.h> #include <linux/delay.h> @@ -659,6 +659,12 @@ static struct clk *clks[] __initdata = { &clk_armclk, }; +static struct clk_lookup s3c2412_clk_lookup[] = { + CLKDEV_INIT(NULL, "clk_uart_baud1", &s3c24xx_uclk), + CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p), + CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_usysclk), +}; + int __init s3c2412_baseclk_add(void) { unsigned long clkcon = __raw_readl(S3C2410_CLKCON); @@ -751,6 +757,7 @@ int __init s3c2412_baseclk_add(void) s3c2412_clkcon_enable(clkp, 0); } + clkdev_add_table(s3c2412_clk_lookup, ARRAY_SIZE(s3c2412_clk_lookup)); s3c_pwmclk_init(); return 0; } diff --git a/arch/arm/mach-s3c2412/cpu-freq.c b/arch/arm/mach-s3c2412/cpu-freq.c index eb3ea172133..d8664b7652c 100644 --- a/arch/arm/mach-s3c2412/cpu-freq.c +++ b/arch/arm/mach-s3c2412/cpu-freq.c @@ -16,7 +16,7 @@ #include <linux/interrupt.h> #include <linux/ioport.h> #include <linux/cpufreq.h> -#include <linux/sysdev.h> +#include <linux/device.h> #include <linux/delay.h> #include <linux/clk.h> #include <linux/err.h> @@ -194,7 +194,7 @@ static struct s3c_cpufreq_info s3c2412_cpufreq_info = { .debug_io_show = s3c_cpufreq_debugfs_call(s3c2412_iotiming_debugfs), }; -static int s3c2412_cpufreq_add(struct sys_device *sysdev) +static int s3c2412_cpufreq_add(struct device *dev) { unsigned long fclk_rate; @@ -244,14 +244,15 @@ err_fclk: return -ENOENT; } -static struct sysdev_driver s3c2412_cpufreq_driver = { - .add = s3c2412_cpufreq_add, +static struct subsys_interface s3c2412_cpufreq_interface = { + .name = "s3c2412_cpufreq", + .subsys = &s3c2412_subsys, + .add_dev = s3c2412_cpufreq_add, }; static int s3c2412_cpufreq_init(void) { - return sysdev_driver_register(&s3c2412_sysclass, - &s3c2412_cpufreq_driver); + return subsys_interface_register(&s3c2412_cpufreq_interface); } arch_initcall(s3c2412_cpufreq_init); diff --git a/arch/arm/mach-s3c2412/dma.c b/arch/arm/mach-s3c2412/dma.c index d2a7d5ef3e6..142acd3b5e1 100644 --- a/arch/arm/mach-s3c2412/dma.c +++ b/arch/arm/mach-s3c2412/dma.c @@ -14,7 +14,7 @@ #include <linux/kernel.h> #include <linux/init.h> -#include <linux/sysdev.h> +#include <linux/device.h> #include <linux/serial_core.h> #include <linux/io.h> @@ -159,19 +159,21 @@ static struct s3c24xx_dma_selection __initdata s3c2412_dma_sel = { .map_size = ARRAY_SIZE(s3c2412_dma_mappings), }; -static int __init s3c2412_dma_add(struct sys_device *sysdev) +static int __init s3c2412_dma_add(struct device *dev) { s3c2410_dma_init(); return s3c24xx_dma_init_map(&s3c2412_dma_sel); } -static struct sysdev_driver s3c2412_dma_driver = { - .add = s3c2412_dma_add, +static struct subsys_interface s3c2412_dma_interface = { + .name = "s3c2412_dma", + .subsys = &s3c2412_subsys, + .add_dev = s3c2412_dma_add, }; static int __init s3c2412_dma_init(void) { - return sysdev_driver_register(&s3c2412_sysclass, &s3c2412_dma_driver); + return subsys_interface_register(&s3c2412_dma_interface); } arch_initcall(s3c2412_dma_init); diff --git a/arch/arm/mach-s3c2412/irq.c b/arch/arm/mach-s3c2412/irq.c index 1a1aa220972..a8a46c1644f 100644 --- a/arch/arm/mach-s3c2412/irq.c +++ b/arch/arm/mach-s3c2412/irq.c @@ -23,7 +23,7 @@ #include <linux/module.h> #include <linux/interrupt.h> #include <linux/ioport.h> -#include <linux/sysdev.h> +#include <linux/device.h> #include <linux/io.h> #include <mach/hardware.h> @@ -170,7 +170,7 @@ static int s3c2412_irq_rtc_wake(struct irq_data *data, unsigned int state) static struct irq_chip s3c2412_irq_rtc_chip; -static int s3c2412_irq_add(struct sys_device *sysdev) +static int s3c2412_irq_add(struct device *dev) { unsigned int irqno; @@ -200,13 +200,15 @@ static int s3c2412_irq_add(struct sys_device *sysdev) return 0; } -static struct sysdev_driver s3c2412_irq_driver = { - .add = s3c2412_irq_add, +static struct subsys_interface s3c2412_irq_interface = { + .name = "s3c2412_irq", + .subsys = &s3c2412_subsys, + .add_dev = s3c2412_irq_add, }; static int s3c2412_irq_init(void) { - return sysdev_driver_register(&s3c2412_sysclass, &s3c2412_irq_driver); + return subsys_interface_register(&s3c2412_irq_interface); } arch_initcall(s3c2412_irq_init); diff --git a/arch/arm/mach-s3c2412/pm.c b/arch/arm/mach-s3c2412/pm.c index f4077efa51f..d1adfa65f66 100644 --- a/arch/arm/mach-s3c2412/pm.c +++ b/arch/arm/mach-s3c2412/pm.c @@ -16,7 +16,7 @@ #include <linux/list.h> #include <linux/timer.h> #include <linux/init.h> -#include <linux/sysdev.h> +#include <linux/device.h> #include <linux/syscore_ops.h> #include <linux/platform_device.h> #include <linux/io.h> @@ -56,7 +56,7 @@ static void s3c2412_pm_prepare(void) { } -static int s3c2412_pm_add(struct sys_device *sysdev) +static int s3c2412_pm_add(struct device *dev) { pm_cpu_prep = s3c2412_pm_prepare; pm_cpu_sleep = s3c2412_cpu_suspend; @@ -87,13 +87,15 @@ static struct sleep_save s3c2412_sleep[] = { SAVE_ITEM(S3C2413_GPJSLPCON), }; -static struct sysdev_driver s3c2412_pm_driver = { - .add = s3c2412_pm_add, +static struct subsys_interface s3c2412_pm_interface = { + .name = "s3c2412_pm", + .subsys = &s3c2412_subsys, + .add_dev = s3c2412_pm_add, }; static __init int s3c2412_pm_init(void) { - return sysdev_driver_register(&s3c2412_sysclass, &s3c2412_pm_driver); + return subsys_interface_register(&s3c2412_pm_interface); } arch_initcall(s3c2412_pm_init); diff --git a/arch/arm/mach-s3c2412/s3c2412.c b/arch/arm/mach-s3c2412/s3c2412.c index 867ce2e269f..aff6e85a97c 100644 --- a/arch/arm/mach-s3c2412/s3c2412.c +++ b/arch/arm/mach-s3c2412/s3c2412.c @@ -18,7 +18,7 @@ #include <linux/init.h> #include <linux/clk.h> #include <linux/delay.h> -#include <linux/sysdev.h> +#include <linux/device.h> #include <linux/syscore_ops.h> #include <linux/serial_core.h> #include <linux/platform_device.h> @@ -218,25 +218,26 @@ void __init s3c2412_init_clocks(int xtal) s3c2412_baseclk_add(); } -/* need to register class before we actually register the device, and +/* need to register the subsystem before we actually register the device, and * we also need to ensure that it has been initialised before any of the * drivers even try to use it (even if not on an s3c2412 based system) * as a driver which may support both 2410 and 2440 may try and use it. */ -struct sysdev_class s3c2412_sysclass = { +struct bus_type s3c2412_subsys = { .name = "s3c2412-core", + .dev_name = "s3c2412-core", }; static int __init s3c2412_core_init(void) { - return sysdev_class_register(&s3c2412_sysclass); + return subsys_system_register(&s3c2412_subsys, NULL); } core_initcall(s3c2412_core_init); -static struct sys_device s3c2412_sysdev = { - .cls = &s3c2412_sysclass, +static struct device s3c2412_dev = { + .bus = &s3c2412_subsys, }; int __init s3c2412_init(void) @@ -248,5 +249,5 @@ int __init s3c2412_init(void) #endif register_syscore_ops(&s3c24xx_irq_syscore_ops); - return sysdev_register(&s3c2412_sysdev); + return device_register(&s3c2412_dev); } diff --git a/arch/arm/mach-s3c2416/Makefile b/arch/arm/mach-s3c2416/Makefile index 7b805b279ca..ca0cd227f87 100644 --- a/arch/arm/mach-s3c2416/Makefile +++ b/arch/arm/mach-s3c2416/Makefile @@ -15,7 +15,6 @@ obj-$(CONFIG_S3C2416_PM) += pm.o #obj-$(CONFIG_S3C2416_DMA) += dma.o # Device setup -obj-$(CONFIG_S3C2416_SETUP_SDHCI) += setup-sdhci.o obj-$(CONFIG_S3C2416_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o # Machine support diff --git a/arch/arm/mach-s3c2416/clock.c b/arch/arm/mach-s3c2416/clock.c index afbbe8bc21d..59f54d1d7f8 100644 --- a/arch/arm/mach-s3c2416/clock.c +++ b/arch/arm/mach-s3c2416/clock.c @@ -90,39 +90,38 @@ static struct clksrc_clk hsmmc_div[] = { }, }; -static struct clksrc_clk hsmmc_mux[] = { - [0] = { - .clk = { - .name = "hsmmc-if", - .devname = "s3c-sdhci.0", - .ctrlbit = (1 << 6), - .enable = s3c2443_clkcon_enable_s, - }, - .sources = &(struct clksrc_sources) { - .nr_sources = 2, - .sources = (struct clk *[]) { - [0] = &hsmmc_div[0].clk, - [1] = NULL, /* to fix */ - }, - }, - .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 16 }, +static struct clksrc_clk hsmmc_mux0 = { + .clk = { + .name = "hsmmc-if", + .devname = "s3c-sdhci.0", + .ctrlbit = (1 << 6), + .enable = s3c2443_clkcon_enable_s, }, - [1] = { - .clk = { - .name = "hsmmc-if", - .devname = "s3c-sdhci.1", - .ctrlbit = (1 << 12), - .enable = s3c2443_clkcon_enable_s, + .sources = &(struct clksrc_sources) { + .nr_sources = 2, + .sources = (struct clk * []) { + [0] = &hsmmc_div[0].clk, + [1] = NULL, /* to fix */ }, - .sources = &(struct clksrc_sources) { - .nr_sources = 2, - .sources = (struct clk *[]) { - [0] = &hsmmc_div[1].clk, - [1] = NULL, /* to fix */ - }, + }, + .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 16 }, +}; + +static struct clksrc_clk hsmmc_mux1 = { + .clk = { + .name = "hsmmc-if", + .devname = "s3c-sdhci.1", + .ctrlbit = (1 << 12), + .enable = s3c2443_clkcon_enable_s, + }, + .sources = &(struct clksrc_sources) { + .nr_sources = 2, + .sources = (struct clk * []) { + [0] = &hsmmc_div[1].clk, + [1] = NULL, /* to fix */ }, - .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 17 }, }, + .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 17 }, }; static struct clk hsmmc0_clk = { @@ -144,8 +143,14 @@ static struct clksrc_clk *clksrcs[] __initdata = { &hsspi_mux, &hsmmc_div[0], &hsmmc_div[1], - &hsmmc_mux[0], - &hsmmc_mux[1], + &hsmmc_mux0, + &hsmmc_mux1, +}; + +static struct clk_lookup s3c2416_clk_lookup[] = { + CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &hsmmc0_clk), + CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &hsmmc_mux0.clk), + CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &hsmmc_mux1.clk), }; void __init s3c2416_init_clocks(int xtal) @@ -167,6 +172,7 @@ void __init s3c2416_init_clocks(int xtal) s3c_register_clksrc(clksrcs[ptr], 1); s3c24xx_register_clock(&hsmmc0_clk); + clkdev_add_table(s3c2416_clk_lookup, ARRAY_SIZE(s3c2416_clk_lookup)); s3c_pwmclk_init(); diff --git a/arch/arm/mach-s3c2416/irq.c b/arch/arm/mach-s3c2416/irq.c index 28ad20d4244..36df761061d 100644 --- a/arch/arm/mach-s3c2416/irq.c +++ b/arch/arm/mach-s3c2416/irq.c @@ -25,7 +25,7 @@ #include <linux/module.h> #include <linux/interrupt.h> #include <linux/ioport.h> -#include <linux/sysdev.h> +#include <linux/device.h> #include <linux/io.h> #include <mach/hardware.h> @@ -213,7 +213,7 @@ static int __init s3c2416_add_sub(unsigned int base, return 0; } -static int __init s3c2416_irq_add(struct sys_device *sysdev) +static int __init s3c2416_irq_add(struct device *dev) { printk(KERN_INFO "S3C2416: IRQ Support\n"); @@ -234,13 +234,15 @@ static int __init s3c2416_irq_add(struct sys_device *sysdev) return 0; } -static struct sysdev_driver s3c2416_irq_driver = { - .add = s3c2416_irq_add, +static struct subsys_interface s3c2416_irq_interface = { + .name = "s3c2416_irq", + .subsys = &s3c2416_subsys, + .add_dev = s3c2416_irq_add, }; static int __init s3c2416_irq_init(void) { - return sysdev_driver_register(&s3c2416_sysclass, &s3c2416_irq_driver); + return subsys_interface_register(&s3c2416_irq_interface); } arch_initcall(s3c2416_irq_init); diff --git a/arch/arm/mach-s3c2416/mach-smdk2416.c b/arch/arm/mach-s3c2416/mach-smdk2416.c index 66b71736609..eebe1e72b93 100644 --- a/arch/arm/mach-s3c2416/mach-smdk2416.c +++ b/arch/arm/mach-s3c2416/mach-smdk2416.c @@ -50,6 +50,7 @@ #include <plat/nand.h> #include <plat/sdhci.h> #include <plat/udc.h> +#include <linux/platform_data/s3c-hsudc.h> #include <plat/regs-fb-v4.h> #include <plat/fb.h> diff --git a/arch/arm/mach-s3c2416/pm.c b/arch/arm/mach-s3c2416/pm.c index 9ec54f1d8e7..3bdb15a0d41 100644 --- a/arch/arm/mach-s3c2416/pm.c +++ b/arch/arm/mach-s3c2416/pm.c @@ -10,7 +10,7 @@ * published by the Free Software Foundation. */ -#include <linux/sysdev.h> +#include <linux/device.h> #include <linux/syscore_ops.h> #include <linux/io.h> @@ -48,7 +48,7 @@ static void s3c2416_pm_prepare(void) __raw_writel(virt_to_phys(s3c_cpu_resume), S3C2412_INFORM1); } -static int s3c2416_pm_add(struct sys_device *sysdev) +static int s3c2416_pm_add(struct device *dev) { pm_cpu_prep = s3c2416_pm_prepare; pm_cpu_sleep = s3c2416_cpu_suspend; @@ -56,13 +56,15 @@ static int s3c2416_pm_add(struct sys_device *sysdev) return 0; } -static struct sysdev_driver s3c2416_pm_driver = { - .add = s3c2416_pm_add, +static struct subsys_interface s3c2416_pm_interface = { + .name = "s3c2416_pm", + .subsys = &s3c2416_subsys, + .add_dev = s3c2416_pm_add, }; static __init int s3c2416_pm_init(void) { - return sysdev_driver_register(&s3c2416_sysclass, &s3c2416_pm_driver); + return subsys_interface_register(&s3c2416_pm_interface); } arch_initcall(s3c2416_pm_init); diff --git a/arch/arm/mach-s3c2416/s3c2416.c b/arch/arm/mach-s3c2416/s3c2416.c index 46062232bbc..5287d2808d3 100644 --- a/arch/arm/mach-s3c2416/s3c2416.c +++ b/arch/arm/mach-s3c2416/s3c2416.c @@ -31,7 +31,7 @@ #include <linux/gpio.h> #include <linux/platform_device.h> #include <linux/serial_core.h> -#include <linux/sysdev.h> +#include <linux/device.h> #include <linux/syscore_ops.h> #include <linux/clk.h> #include <linux/io.h> @@ -67,12 +67,13 @@ static struct map_desc s3c2416_iodesc[] __initdata = { IODESC_ENT(TIMER), }; -struct sysdev_class s3c2416_sysclass = { +struct bus_type s3c2416_subsys = { .name = "s3c2416-core", + .dev_name = "s3c2416-core", }; -static struct sys_device s3c2416_sysdev = { - .cls = &s3c2416_sysclass, +static struct device s3c2416_dev = { + .bus = &s3c2416_subsys, }; void s3c2416_restart(char mode, const char *cmd) @@ -106,7 +107,7 @@ int __init s3c2416_init(void) #endif register_syscore_ops(&s3c24xx_irq_syscore_ops); - return sysdev_register(&s3c2416_sysdev); + return device_register(&s3c2416_dev); } void __init s3c2416_init_uarts(struct s3c2410_uartcfg *cfg, int no) @@ -134,7 +135,7 @@ void __init s3c2416_map_io(void) iotable_init(s3c2416_iodesc, ARRAY_SIZE(s3c2416_iodesc)); } -/* need to register class before we actually register the device, and +/* need to register the subsystem before we actually register the device, and * we also need to ensure that it has been initialised before any of the * drivers even try to use it (even if not on an s3c2416 based system) * as a driver which may support both 2443 and 2440 may try and use it. @@ -142,7 +143,7 @@ void __init s3c2416_map_io(void) static int __init s3c2416_core_init(void) { - return sysdev_class_register(&s3c2416_sysclass); + return subsys_system_register(&s3c2416_subsys, NULL); } core_initcall(s3c2416_core_init); diff --git a/arch/arm/mach-s3c2416/setup-sdhci.c b/arch/arm/mach-s3c2416/setup-sdhci.c deleted file mode 100644 index cee53955eb0..00000000000 --- a/arch/arm/mach-s3c2416/setup-sdhci.c +++ /dev/null @@ -1,24 +0,0 @@ -/* linux/arch/arm/mach-s3c2416/setup-sdhci.c - * - * Copyright 2010 Promwad Innovation Company - * Yauhen Kharuzhy <yauhen.kharuzhy@promwad.com> - * - * S3C2416 - Helper functions for settign up SDHCI device(s) (HSMMC) - * - * Based on mach-s3c64xx/setup-sdhci.c - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/types.h> - -/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */ - -char *s3c2416_hsmmc_clksrcs[4] = { - [0] = "hsmmc", - [1] = "hsmmc", - [2] = "hsmmc-if", - /* [3] = "48m", - note not successfully used yet */ -}; diff --git a/arch/arm/mach-s3c2440/clock.c b/arch/arm/mach-s3c2440/clock.c index f9e6bdaf41d..bedbc87a342 100644 --- a/arch/arm/mach-s3c2440/clock.c +++ b/arch/arm/mach-s3c2440/clock.c @@ -28,12 +28,12 @@ #include <linux/errno.h> #include <linux/err.h> #include <linux/device.h> -#include <linux/sysdev.h> #include <linux/interrupt.h> #include <linux/ioport.h> #include <linux/mutex.h> #include <linux/clk.h> #include <linux/io.h> +#include <linux/serial_core.h> #include <mach/hardware.h> #include <linux/atomic.h> @@ -43,6 +43,7 @@ #include <plat/clock.h> #include <plat/cpu.h> +#include <plat/regs-serial.h> /* S3C2440 extended clock support */ @@ -108,7 +109,47 @@ static struct clk s3c2440_clk_ac97 = { .ctrlbit = S3C2440_CLKCON_CAMERA, }; -static int s3c2440_clk_add(struct sys_device *sysdev) +static unsigned long s3c2440_fclk_n_getrate(struct clk *clk) +{ + unsigned long ucon0, ucon1, ucon2, divisor; + + /* the fun of calculating the uart divisors on the s3c2440 */ + ucon0 = __raw_readl(S3C24XX_VA_UART0 + S3C2410_UCON); + ucon1 = __raw_readl(S3C24XX_VA_UART1 + S3C2410_UCON); + ucon2 = __raw_readl(S3C24XX_VA_UART2 + S3C2410_UCON); + + ucon0 &= S3C2440_UCON0_DIVMASK; + ucon1 &= S3C2440_UCON1_DIVMASK; + ucon2 &= S3C2440_UCON2_DIVMASK; + + if (ucon0 != 0) + divisor = (ucon0 >> S3C2440_UCON_DIVSHIFT) + 6; + else if (ucon1 != 0) + divisor = (ucon1 >> S3C2440_UCON_DIVSHIFT) + 21; + else if (ucon2 != 0) + divisor = (ucon2 >> S3C2440_UCON_DIVSHIFT) + 36; + else + /* manual calims 44, seems to be 9 */ + divisor = 9; + + return clk_get_rate(clk->parent) / divisor; +} + +static struct clk s3c2440_clk_fclk_n = { + .name = "fclk_n", + .parent = &clk_f, + .ops = &(struct clk_ops) { + .get_rate = s3c2440_fclk_n_getrate, + }, +}; + +static struct clk_lookup s3c2440_clk_lookup[] = { + CLKDEV_INIT(NULL, "clk_uart_baud1", &s3c24xx_uclk), + CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p), + CLKDEV_INIT(NULL, "clk_uart_baud3", &s3c2440_clk_fclk_n), +}; + +static int s3c2440_clk_add(struct device *dev) { struct clk *clock_upll; struct clk *clock_h; @@ -126,10 +167,12 @@ static int s3c2440_clk_add(struct sys_device *sysdev) s3c2440_clk_cam.parent = clock_h; s3c2440_clk_ac97.parent = clock_p; s3c2440_clk_cam_upll.parent = clock_upll; + s3c24xx_register_clock(&s3c2440_clk_fclk_n); s3c24xx_register_clock(&s3c2440_clk_ac97); s3c24xx_register_clock(&s3c2440_clk_cam); s3c24xx_register_clock(&s3c2440_clk_cam_upll); + clkdev_add_table(s3c2440_clk_lookup, ARRAY_SIZE(s3c2440_clk_lookup)); clk_disable(&s3c2440_clk_ac97); clk_disable(&s3c2440_clk_cam); @@ -137,13 +180,15 @@ static int s3c2440_clk_add(struct sys_device *sysdev) return 0; } -static struct sysdev_driver s3c2440_clk_driver = { - .add = s3c2440_clk_add, +static struct subsys_interface s3c2440_clk_interface = { + .name = "s3c2440_clk", + .subsys = &s3c2440_subsys, + .add_dev = s3c2440_clk_add, }; -static __init int s3c24xx_clk_driver(void) +static __init int s3c24xx_clk_init(void) { - return sysdev_driver_register(&s3c2440_sysclass, &s3c2440_clk_driver); + return subsys_interface_register(&s3c2440_clk_interface); } -arch_initcall(s3c24xx_clk_driver); +arch_initcall(s3c24xx_clk_init); diff --git a/arch/arm/mach-s3c2440/dma.c b/arch/arm/mach-s3c2440/dma.c index 0e73f8f9d13..15b1ddf8f62 100644 --- a/arch/arm/mach-s3c2440/dma.c +++ b/arch/arm/mach-s3c2440/dma.c @@ -14,7 +14,7 @@ #include <linux/kernel.h> #include <linux/init.h> -#include <linux/sysdev.h> +#include <linux/device.h> #include <linux/serial_core.h> #include <mach/map.h> @@ -174,20 +174,22 @@ static struct s3c24xx_dma_order __initdata s3c2440_dma_order = { }, }; -static int __init s3c2440_dma_add(struct sys_device *sysdev) +static int __init s3c2440_dma_add(struct device *dev) { s3c2410_dma_init(); s3c24xx_dma_order_set(&s3c2440_dma_order); return s3c24xx_dma_init_map(&s3c2440_dma_sel); } -static struct sysdev_driver s3c2440_dma_driver = { - .add = s3c2440_dma_add, +static struct subsys_interface s3c2440_dma_interface = { + .name = "s3c2440_dma", + .subsys = &s3c2440_subsys, + .add_dev = s3c2440_dma_add, }; static int __init s3c2440_dma_init(void) { - return sysdev_driver_register(&s3c2440_sysclass, &s3c2440_dma_driver); + return subsys_interface_register(&s3c2440_dma_interface); } arch_initcall(s3c2440_dma_init); diff --git a/arch/arm/mach-s3c2440/irq.c b/arch/arm/mach-s3c2440/irq.c index eb1cc0f0705..4fee9bc6bcb 100644 --- a/arch/arm/mach-s3c2440/irq.c +++ b/arch/arm/mach-s3c2440/irq.c @@ -23,7 +23,7 @@ #include <linux/module.h> #include <linux/interrupt.h> #include <linux/ioport.h> -#include <linux/sysdev.h> +#include <linux/device.h> #include <linux/io.h> #include <mach/hardware.h> @@ -92,7 +92,7 @@ static struct irq_chip s3c_irq_wdtac97 = { .irq_ack = s3c_irq_wdtac97_ack, }; -static int s3c2440_irq_add(struct sys_device *sysdev) +static int s3c2440_irq_add(struct device *dev) { unsigned int irqno; @@ -113,13 +113,15 @@ static int s3c2440_irq_add(struct sys_device *sysdev) return 0; } -static struct sysdev_driver s3c2440_irq_driver = { - .add = s3c2440_irq_add, +static struct subsys_interface s3c2440_irq_interface = { + .name = "s3c2440_irq", + .subsys = &s3c2440_subsys, + .add_dev = s3c2440_irq_add, }; static int s3c2440_irq_init(void) { - return sysdev_driver_register(&s3c2440_sysclass, &s3c2440_irq_driver); + return subsys_interface_register(&s3c2440_irq_interface); } arch_initcall(s3c2440_irq_init); diff --git a/arch/arm/mach-s3c2440/mach-anubis.c b/arch/arm/mach-s3c2440/mach-anubis.c index 121ff8d2c88..24569550de1 100644 --- a/arch/arm/mach-s3c2440/mach-anubis.c +++ b/arch/arm/mach-s3c2440/mach-anubis.c @@ -98,22 +98,6 @@ static struct map_desc anubis_iodesc[] __initdata = { #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE -static struct s3c24xx_uart_clksrc anubis_serial_clocks[] = { - [0] = { - .name = "uclk", - .divisor = 1, - .min_baud = 0, - .max_baud = 0, - }, - [1] = { - .name = "pclk", - .divisor = 1, - .min_baud = 0, - .max_baud = 0, - } -}; - - static struct s3c2410_uartcfg anubis_uartcfgs[] __initdata = { [0] = { .hwport = 0, @@ -121,8 +105,7 @@ static struct s3c2410_uartcfg anubis_uartcfgs[] __initdata = { .ucon = UCON, .ulcon = ULCON, .ufcon = UFCON, - .clocks = anubis_serial_clocks, - .clocks_size = ARRAY_SIZE(anubis_serial_clocks), + .clk_sel = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2, }, [1] = { .hwport = 2, @@ -130,8 +113,7 @@ static struct s3c2410_uartcfg anubis_uartcfgs[] __initdata = { .ucon = UCON, .ulcon = ULCON, .ufcon = UFCON, - .clocks = anubis_serial_clocks, - .clocks_size = ARRAY_SIZE(anubis_serial_clocks), + .clk_sel = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2, }, }; diff --git a/arch/arm/mach-s3c2440/mach-at2440evb.c b/arch/arm/mach-s3c2440/mach-at2440evb.c index b7e334f07da..d6a9763110c 100644 --- a/arch/arm/mach-s3c2440/mach-at2440evb.c +++ b/arch/arm/mach-s3c2440/mach-at2440evb.c @@ -59,22 +59,6 @@ static struct map_desc at2440evb_iodesc[] __initdata = { #define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE) #define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE) -static struct s3c24xx_uart_clksrc at2440evb_serial_clocks[] = { - [0] = { - .name = "uclk", - .divisor = 1, - .min_baud = 0, - .max_baud = 0, - }, - [1] = { - .name = "pclk", - .divisor = 1, - .min_baud = 0, - .max_baud = 0, - } -}; - - static struct s3c2410_uartcfg at2440evb_uartcfgs[] __initdata = { [0] = { .hwport = 0, @@ -82,8 +66,7 @@ static struct s3c2410_uartcfg at2440evb_uartcfgs[] __initdata = { .ucon = UCON, .ulcon = ULCON, .ufcon = UFCON, - .clocks = at2440evb_serial_clocks, - .clocks_size = ARRAY_SIZE(at2440evb_serial_clocks), + .clk_sel = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2, }, [1] = { .hwport = 1, @@ -91,8 +74,7 @@ static struct s3c2410_uartcfg at2440evb_uartcfgs[] __initdata = { .ucon = UCON, .ulcon = ULCON, .ufcon = UFCON, - .clocks = at2440evb_serial_clocks, - .clocks_size = ARRAY_SIZE(at2440evb_serial_clocks), + .clk_sel = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2, }, }; diff --git a/arch/arm/mach-s3c2440/mach-mini2440.c b/arch/arm/mach-s3c2440/mach-mini2440.c index 437322ffd88..adbbb85bc4c 100644 --- a/arch/arm/mach-s3c2440/mach-mini2440.c +++ b/arch/arm/mach-s3c2440/mach-mini2440.c @@ -169,6 +169,24 @@ static struct s3c2410fb_display mini2440_lcd_cfg[] __initdata = { .lcdcon5 = (S3C2410_LCDCON5_FRM565 | S3C2410_LCDCON5_HWSWP), }, + /* mini2440 + 3.5" TFT (LCD-W35i, LQ035Q1DG06 type) + touchscreen*/ + [3] = { + _LCD_DECLARE( + /* clock */ + 7, + /* xres, margin_right, margin_left, hsync */ + 320, 68, 66, 4, + /* yres, margin_top, margin_bottom, vsync */ + 240, 4, 4, 9, + /* refresh rate */ + 60), + .lcdcon5 = (S3C2410_LCDCON5_FRM565 | + S3C2410_LCDCON5_INVVDEN | + S3C2410_LCDCON5_INVVFRAME | + S3C2410_LCDCON5_INVVLINE | + S3C2410_LCDCON5_INVVCLK | + S3C2410_LCDCON5_HWSWP), + }, }; /* todo - put into gpio header */ diff --git a/arch/arm/mach-s3c2440/mach-osiris.c b/arch/arm/mach-s3c2440/mach-osiris.c index e795715fba3..4c480ef734f 100644 --- a/arch/arm/mach-s3c2440/mach-osiris.c +++ b/arch/arm/mach-s3c2440/mach-osiris.c @@ -102,21 +102,6 @@ static struct map_desc osiris_iodesc[] __initdata = { #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE -static struct s3c24xx_uart_clksrc osiris_serial_clocks[] = { - [0] = { - .name = "uclk", - .divisor = 1, - .min_baud = 0, - .max_baud = 0, - }, - [1] = { - .name = "pclk", - .divisor = 1, - .min_baud = 0, - .max_baud = 0, - } -}; - static struct s3c2410_uartcfg osiris_uartcfgs[] __initdata = { [0] = { .hwport = 0, @@ -124,8 +109,7 @@ static struct s3c2410_uartcfg osiris_uartcfgs[] __initdata = { .ucon = UCON, .ulcon = ULCON, .ufcon = UFCON, - .clocks = osiris_serial_clocks, - .clocks_size = ARRAY_SIZE(osiris_serial_clocks), + .clk_sel = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2, }, [1] = { .hwport = 1, @@ -133,8 +117,7 @@ static struct s3c2410_uartcfg osiris_uartcfgs[] __initdata = { .ucon = UCON, .ulcon = ULCON, .ufcon = UFCON, - .clocks = osiris_serial_clocks, - .clocks_size = ARRAY_SIZE(osiris_serial_clocks), + .clk_sel = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2, }, [2] = { .hwport = 2, @@ -142,8 +125,7 @@ static struct s3c2410_uartcfg osiris_uartcfgs[] __initdata = { .ucon = UCON, .ulcon = ULCON, .ufcon = UFCON, - .clocks = osiris_serial_clocks, - .clocks_size = ARRAY_SIZE(osiris_serial_clocks), + .clk_sel = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2, } }; diff --git a/arch/arm/mach-s3c2440/mach-rx1950.c b/arch/arm/mach-s3c2440/mach-rx1950.c index 1c50d3e0917..80077f6472e 100644 --- a/arch/arm/mach-s3c2440/mach-rx1950.c +++ b/arch/arm/mach-s3c2440/mach-rx1950.c @@ -24,7 +24,7 @@ #include <linux/serial_core.h> #include <linux/input.h> #include <linux/gpio_keys.h> -#include <linux/sysdev.h> +#include <linux/device.h> #include <linux/pda_power.h> #include <linux/pwm_backlight.h> #include <linux/pwm.h> @@ -70,15 +70,6 @@ static struct map_desc rx1950_iodesc[] __initdata = { }; -static struct s3c24xx_uart_clksrc rx1950_serial_clocks[] = { - [0] = { - .name = "fclk", - .divisor = 0x0a, - .min_baud = 0, - .max_baud = 0, - }, -}; - static struct s3c2410_uartcfg rx1950_uartcfgs[] __initdata = { [0] = { .hwport = 0, @@ -86,8 +77,7 @@ static struct s3c2410_uartcfg rx1950_uartcfgs[] __initdata = { .ucon = 0x3c5, .ulcon = 0x03, .ufcon = 0x51, - .clocks = rx1950_serial_clocks, - .clocks_size = ARRAY_SIZE(rx1950_serial_clocks), + .clk_sel = S3C2410_UCON_CLKSEL3, }, [1] = { .hwport = 1, @@ -95,8 +85,7 @@ static struct s3c2410_uartcfg rx1950_uartcfgs[] __initdata = { .ucon = 0x3c5, .ulcon = 0x03, .ufcon = 0x51, - .clocks = rx1950_serial_clocks, - .clocks_size = ARRAY_SIZE(rx1950_serial_clocks), + .clk_sel = S3C2410_UCON_CLKSEL3, }, /* IR port */ [2] = { @@ -105,8 +94,7 @@ static struct s3c2410_uartcfg rx1950_uartcfgs[] __initdata = { .ucon = 0x3c5, .ulcon = 0x43, .ufcon = 0xf1, - .clocks = rx1950_serial_clocks, - .clocks_size = ARRAY_SIZE(rx1950_serial_clocks), + .clk_sel = S3C2410_UCON_CLKSEL3, }, }; diff --git a/arch/arm/mach-s3c2440/mach-rx3715.c b/arch/arm/mach-s3c2440/mach-rx3715.c index 4d20a016b85..20103bafbd4 100644 --- a/arch/arm/mach-s3c2440/mach-rx3715.c +++ b/arch/arm/mach-s3c2440/mach-rx3715.c @@ -20,7 +20,7 @@ #include <linux/init.h> #include <linux/tty.h> #include <linux/console.h> -#include <linux/sysdev.h> +#include <linux/device.h> #include <linux/platform_device.h> #include <linux/serial_core.h> #include <linux/serial.h> @@ -69,16 +69,6 @@ static struct map_desc rx3715_iodesc[] __initdata = { }, }; - -static struct s3c24xx_uart_clksrc rx3715_serial_clocks[] = { - [0] = { - .name = "fclk", - .divisor = 0, - .min_baud = 0, - .max_baud = 0, - } -}; - static struct s3c2410_uartcfg rx3715_uartcfgs[] = { [0] = { .hwport = 0, @@ -86,8 +76,7 @@ static struct s3c2410_uartcfg rx3715_uartcfgs[] = { .ucon = 0x3c5, .ulcon = 0x03, .ufcon = 0x51, - .clocks = rx3715_serial_clocks, - .clocks_size = ARRAY_SIZE(rx3715_serial_clocks), + .clk_sel = S3C2410_UCON_CLKSEL3, }, [1] = { .hwport = 1, @@ -95,8 +84,7 @@ static struct s3c2410_uartcfg rx3715_uartcfgs[] = { .ucon = 0x3c5, .ulcon = 0x03, .ufcon = 0x00, - .clocks = rx3715_serial_clocks, - .clocks_size = ARRAY_SIZE(rx3715_serial_clocks), + .clk_sel = S3C2410_UCON_CLKSEL3, }, /* IR port */ [2] = { @@ -105,8 +93,7 @@ static struct s3c2410_uartcfg rx3715_uartcfgs[] = { .ucon = 0x3c5, .ulcon = 0x43, .ufcon = 0x51, - .clocks = rx3715_serial_clocks, - .clocks_size = ARRAY_SIZE(rx3715_serial_clocks), + .clk_sel = S3C2410_UCON_CLKSEL3, } }; diff --git a/arch/arm/mach-s3c2440/s3c2440-cpufreq.c b/arch/arm/mach-s3c2440/s3c2440-cpufreq.c index 976002fb1b8..cf7596694ef 100644 --- a/arch/arm/mach-s3c2440/s3c2440-cpufreq.c +++ b/arch/arm/mach-s3c2440/s3c2440-cpufreq.c @@ -17,7 +17,7 @@ #include <linux/interrupt.h> #include <linux/ioport.h> #include <linux/cpufreq.h> -#include <linux/sysdev.h> +#include <linux/device.h> #include <linux/delay.h> #include <linux/clk.h> #include <linux/err.h> @@ -270,7 +270,7 @@ struct s3c_cpufreq_info s3c2440_cpufreq_info = { .debug_io_show = s3c_cpufreq_debugfs_call(s3c2410_iotiming_debugfs), }; -static int s3c2440_cpufreq_add(struct sys_device *sysdev) +static int s3c2440_cpufreq_add(struct device *dev) { xtal = s3c_cpufreq_clk_get(NULL, "xtal"); hclk = s3c_cpufreq_clk_get(NULL, "hclk"); @@ -285,27 +285,29 @@ static int s3c2440_cpufreq_add(struct sys_device *sysdev) return s3c_cpufreq_register(&s3c2440_cpufreq_info); } -static struct sysdev_driver s3c2440_cpufreq_driver = { - .add = s3c2440_cpufreq_add, +static struct subsys_interface s3c2440_cpufreq_interface = { + .name = "s3c2440_cpufreq", + .subsys = &s3c2440_subsys, + .add_dev = s3c2440_cpufreq_add, }; static int s3c2440_cpufreq_init(void) { - return sysdev_driver_register(&s3c2440_sysclass, - &s3c2440_cpufreq_driver); + return subsys_interface_register(&s3c2440_cpufreq_interface); } /* arch_initcall adds the clocks we need, so use subsys_initcall. */ subsys_initcall(s3c2440_cpufreq_init); -static struct sysdev_driver s3c2442_cpufreq_driver = { - .add = s3c2440_cpufreq_add, +static struct subsys_interface s3c2442_cpufreq_interface = { + .name = "s3c2442_cpufreq", + .subsys = &s3c2442_subsys, + .add_dev = s3c2440_cpufreq_add, }; static int s3c2442_cpufreq_init(void) { - return sysdev_driver_register(&s3c2442_sysclass, - &s3c2442_cpufreq_driver); + return subsys_interface_register(&s3c2442_cpufreq_interface); } subsys_initcall(s3c2442_cpufreq_init); diff --git a/arch/arm/mach-s3c2440/s3c2440-pll-12000000.c b/arch/arm/mach-s3c2440/s3c2440-pll-12000000.c index f105d5e8c47..b5368ae8d7f 100644 --- a/arch/arm/mach-s3c2440/s3c2440-pll-12000000.c +++ b/arch/arm/mach-s3c2440/s3c2440-pll-12000000.c @@ -14,7 +14,7 @@ #include <linux/types.h> #include <linux/kernel.h> -#include <linux/sysdev.h> +#include <linux/device.h> #include <linux/clk.h> #include <linux/err.h> @@ -51,7 +51,7 @@ static struct cpufreq_frequency_table s3c2440_plls_12[] __initdata = { { .frequency = 400000000, .index = PLLVAL(0x5c, 1, 1), }, /* FVco 800.000000 */ }; -static int s3c2440_plls12_add(struct sys_device *dev) +static int s3c2440_plls12_add(struct device *dev) { struct clk *xtal_clk; unsigned long xtal; @@ -72,25 +72,29 @@ static int s3c2440_plls12_add(struct sys_device *dev) return 0; } -static struct sysdev_driver s3c2440_plls12_drv = { - .add = s3c2440_plls12_add, +static struct subsys_interface s3c2440_plls12_interface = { + .name = "s3c2440_plls12", + .subsys = &s3c2440_subsys, + .add_dev = s3c2440_plls12_add, }; static int __init s3c2440_pll_12mhz(void) { - return sysdev_driver_register(&s3c2440_sysclass, &s3c2440_plls12_drv); + return subsys_interface_register(&s3c2440_plls12_interface); } arch_initcall(s3c2440_pll_12mhz); -static struct sysdev_driver s3c2442_plls12_drv = { - .add = s3c2440_plls12_add, +static struct subsys_interface s3c2442_plls12_interface = { + .name = "s3c2442_plls12", + .subsys = &s3c2442_subsys, + .add_dev = s3c2440_plls12_add, }; static int __init s3c2442_pll_12mhz(void) { - return sysdev_driver_register(&s3c2442_sysclass, &s3c2442_plls12_drv); + return subsys_interface_register(&s3c2442_plls12_interface); } diff --git a/arch/arm/mach-s3c2440/s3c2440-pll-16934400.c b/arch/arm/mach-s3c2440/s3c2440-pll-16934400.c index c8a8f90ef38..42f2b5cd239 100644 --- a/arch/arm/mach-s3c2440/s3c2440-pll-16934400.c +++ b/arch/arm/mach-s3c2440/s3c2440-pll-16934400.c @@ -14,7 +14,7 @@ #include <linux/types.h> #include <linux/kernel.h> -#include <linux/sysdev.h> +#include <linux/device.h> #include <linux/clk.h> #include <linux/err.h> @@ -79,7 +79,7 @@ static struct cpufreq_frequency_table s3c2440_plls_169344[] __initdata = { { .frequency = 402192000, .index = PLLVAL(87, 2, 1), }, /* FVco 804.384000 */ }; -static int s3c2440_plls169344_add(struct sys_device *dev) +static int s3c2440_plls169344_add(struct device *dev) { struct clk *xtal_clk; unsigned long xtal; @@ -100,28 +100,28 @@ static int s3c2440_plls169344_add(struct sys_device *dev) return 0; } -static struct sysdev_driver s3c2440_plls169344_drv = { - .add = s3c2440_plls169344_add, +static struct subsys_interface s3c2440_plls169344_interface = { + .name = "s3c2440_plls169344", + .subsys = &s3c2440_subsys, + .add_dev = s3c2440_plls169344_add, }; static int __init s3c2440_pll_16934400(void) { - return sysdev_driver_register(&s3c2440_sysclass, - &s3c2440_plls169344_drv); - + return subsys_interface_register(&s3c2440_plls169344_interface); } arch_initcall(s3c2440_pll_16934400); -static struct sysdev_driver s3c2442_plls169344_drv = { - .add = s3c2440_plls169344_add, +static struct subsys_interface s3c2442_plls169344_interface = { + .name = "s3c2442_plls169344", + .subsys = &s3c2442_subsys, + .add_dev = s3c2440_plls169344_add, }; static int __init s3c2442_pll_16934400(void) { - return sysdev_driver_register(&s3c2442_sysclass, - &s3c2442_plls169344_drv); - + return subsys_interface_register(&s3c2442_plls169344_interface); } arch_initcall(s3c2442_pll_16934400); diff --git a/arch/arm/mach-s3c2440/s3c2440.c b/arch/arm/mach-s3c2440/s3c2440.c index 42d73f1e0ce..517623a09fc 100644 --- a/arch/arm/mach-s3c2440/s3c2440.c +++ b/arch/arm/mach-s3c2440/s3c2440.c @@ -18,7 +18,7 @@ #include <linux/init.h> #include <linux/platform_device.h> #include <linux/serial_core.h> -#include <linux/sysdev.h> +#include <linux/device.h> #include <linux/syscore_ops.h> #include <linux/gpio.h> #include <linux/clk.h> @@ -41,8 +41,8 @@ #include <plat/gpio-cfg.h> #include <plat/gpio-cfg-helpers.h> -static struct sys_device s3c2440_sysdev = { - .cls = &s3c2440_sysclass, +static struct device s3c2440_dev = { + .bus = &s3c2440_subsys, }; int __init s3c2440_init(void) @@ -64,7 +64,7 @@ int __init s3c2440_init(void) /* register our system device for everything else */ - return sysdev_register(&s3c2440_sysdev); + return device_register(&s3c2440_dev); } void __init s3c2440_map_io(void) diff --git a/arch/arm/mach-s3c2440/s3c2442.c b/arch/arm/mach-s3c2440/s3c2442.c index 2c822e09392..8004e0497bf 100644 --- a/arch/arm/mach-s3c2440/s3c2442.c +++ b/arch/arm/mach-s3c2440/s3c2442.c @@ -28,7 +28,6 @@ #include <linux/errno.h> #include <linux/err.h> #include <linux/device.h> -#include <linux/sysdev.h> #include <linux/syscore_ops.h> #include <linux/interrupt.h> #include <linux/ioport.h> @@ -123,7 +122,7 @@ static struct clk s3c2442_clk_cam_upll = { }, }; -static int s3c2442_clk_add(struct sys_device *sysdev) +static int s3c2442_clk_add(struct device *dev) { struct clk *clock_upll; struct clk *clock_h; @@ -149,20 +148,22 @@ static int s3c2442_clk_add(struct sys_device *sysdev) return 0; } -static struct sysdev_driver s3c2442_clk_driver = { - .add = s3c2442_clk_add, +static struct subsys_interface s3c2442_clk_interface = { + .name = "s3c2442_clk", + .subsys = &s3c2442_subsys, + .add_dev = s3c2442_clk_add, }; static __init int s3c2442_clk_init(void) { - return sysdev_driver_register(&s3c2442_sysclass, &s3c2442_clk_driver); + return subsys_interface_register(&s3c2442_clk_interface); } arch_initcall(s3c2442_clk_init); -static struct sys_device s3c2442_sysdev = { - .cls = &s3c2442_sysclass, +static struct device s3c2442_dev = { + .bus = &s3c2442_subsys, }; int __init s3c2442_init(void) @@ -175,7 +176,7 @@ int __init s3c2442_init(void) register_syscore_ops(&s3c244x_pm_syscore_ops); register_syscore_ops(&s3c24xx_irq_syscore_ops); - return sysdev_register(&s3c2442_sysdev); + return device_register(&s3c2442_dev); } void __init s3c2442_map_io(void) diff --git a/arch/arm/mach-s3c2440/s3c244x-clock.c b/arch/arm/mach-s3c2440/s3c244x-clock.c index 7f5ea0a169a..b3fdbdda3d5 100644 --- a/arch/arm/mach-s3c2440/s3c244x-clock.c +++ b/arch/arm/mach-s3c2440/s3c244x-clock.c @@ -28,7 +28,6 @@ #include <linux/errno.h> #include <linux/err.h> #include <linux/device.h> -#include <linux/sysdev.h> #include <linux/interrupt.h> #include <linux/ioport.h> #include <linux/clk.h> @@ -73,7 +72,7 @@ static struct clk clk_arm = { }, }; -static int s3c244x_clk_add(struct sys_device *sysdev) +static int s3c244x_clk_add(struct device *dev) { unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN); unsigned long clkdivn; @@ -115,24 +114,28 @@ static int s3c244x_clk_add(struct sys_device *sysdev) return 0; } -static struct sysdev_driver s3c2440_clk_driver = { - .add = s3c244x_clk_add, +static struct subsys_interface s3c2440_clk_interface = { + .name = "s3c2440_clk", + .subsys = &s3c2440_subsys, + .add_dev = s3c244x_clk_add, }; static int s3c2440_clk_init(void) { - return sysdev_driver_register(&s3c2440_sysclass, &s3c2440_clk_driver); + return subsys_interface_register(&s3c2440_clk_interface); } arch_initcall(s3c2440_clk_init); -static struct sysdev_driver s3c2442_clk_driver = { - .add = s3c244x_clk_add, +static struct subsys_interface s3c2442_clk_interface = { + .name = "s3c2442_clk", + .subsys = &s3c2442_subsys, + .add_dev = s3c244x_clk_add, }; static int s3c2442_clk_init(void) { - return sysdev_driver_register(&s3c2442_sysclass, &s3c2442_clk_driver); + return subsys_interface_register(&s3c2442_clk_interface); } arch_initcall(s3c2442_clk_init); diff --git a/arch/arm/mach-s3c2440/s3c244x-irq.c b/arch/arm/mach-s3c2440/s3c244x-irq.c index c63e8f26d90..74d3dcf46a4 100644 --- a/arch/arm/mach-s3c2440/s3c244x-irq.c +++ b/arch/arm/mach-s3c2440/s3c244x-irq.c @@ -23,7 +23,7 @@ #include <linux/module.h> #include <linux/interrupt.h> #include <linux/ioport.h> -#include <linux/sysdev.h> +#include <linux/device.h> #include <linux/io.h> #include <mach/hardware.h> @@ -91,7 +91,7 @@ static struct irq_chip s3c_irq_cam = { .irq_ack = s3c_irq_cam_ack, }; -static int s3c244x_irq_add(struct sys_device *sysdev) +static int s3c244x_irq_add(struct device *dev) { unsigned int irqno; @@ -114,25 +114,29 @@ static int s3c244x_irq_add(struct sys_device *sysdev) return 0; } -static struct sysdev_driver s3c2440_irq_driver = { - .add = s3c244x_irq_add, +static struct subsys_interface s3c2440_irq_interface = { + .name = "s3c2440_irq", + .subsys = &s3c2440_subsys, + .add_dev = s3c244x_irq_add, }; static int s3c2440_irq_init(void) { - return sysdev_driver_register(&s3c2440_sysclass, &s3c2440_irq_driver); + return subsys_interface_register(&s3c2440_irq_interface); } arch_initcall(s3c2440_irq_init); -static struct sysdev_driver s3c2442_irq_driver = { - .add = s3c244x_irq_add, +static struct subsys_interface s3c2442_irq_interface = { + .name = "s3c2442_irq", + .subsys = &s3c2442_subsys, + .add_dev = s3c244x_irq_add, }; static int s3c2442_irq_init(void) { - return sysdev_driver_register(&s3c2442_sysclass, &s3c2442_irq_driver); + return subsys_interface_register(&s3c2442_irq_interface); } arch_initcall(s3c2442_irq_init); diff --git a/arch/arm/mach-s3c2440/s3c244x.c b/arch/arm/mach-s3c2440/s3c244x.c index 7e8a23d2098..36bc60f61d0 100644 --- a/arch/arm/mach-s3c2440/s3c244x.c +++ b/arch/arm/mach-s3c2440/s3c244x.c @@ -18,7 +18,7 @@ #include <linux/init.h> #include <linux/serial_core.h> #include <linux/platform_device.h> -#include <linux/sysdev.h> +#include <linux/device.h> #include <linux/syscore_ops.h> #include <linux/clk.h> #include <linux/io.h> @@ -135,17 +135,19 @@ void __init s3c244x_init_clocks(int xtal) s3c2410_baseclk_add(); } -/* Since the S3C2442 and S3C2440 share items, put both sysclasses here */ +/* Since the S3C2442 and S3C2440 share items, put both subsystems here */ -struct sysdev_class s3c2440_sysclass = { +struct bus_type s3c2440_subsys = { .name = "s3c2440-core", + .dev_name = "s3c2440-core", }; -struct sysdev_class s3c2442_sysclass = { +struct bus_type s3c2442_subsys = { .name = "s3c2442-core", + .dev_name = "s3c2442-core", }; -/* need to register class before we actually register the device, and +/* need to register the subsystem before we actually register the device, and * we also need to ensure that it has been initialised before any of the * drivers even try to use it (even if not on an s3c2440 based system) * as a driver which may support both 2410 and 2440 may try and use it. @@ -153,14 +155,14 @@ struct sysdev_class s3c2442_sysclass = { static int __init s3c2440_core_init(void) { - return sysdev_class_register(&s3c2440_sysclass); + return subsys_system_register(&s3c2440_subsys, NULL); } core_initcall(s3c2440_core_init); static int __init s3c2442_core_init(void) { - return sysdev_class_register(&s3c2442_sysclass); + return subsys_system_register(&s3c2442_subsys, NULL); } core_initcall(s3c2442_core_init); diff --git a/arch/arm/mach-s3c2443/clock.c b/arch/arm/mach-s3c2443/clock.c index 1c2c088aa2e..6dde2696f8f 100644 --- a/arch/arm/mach-s3c2443/clock.c +++ b/arch/arm/mach-s3c2443/clock.c @@ -27,7 +27,7 @@ #include <linux/list.h> #include <linux/errno.h> #include <linux/err.h> -#include <linux/sysdev.h> +#include <linux/device.h> #include <linux/clk.h> #include <linux/mutex.h> #include <linux/serial_core.h> diff --git a/arch/arm/mach-s3c2443/dma.c b/arch/arm/mach-s3c2443/dma.c index fe52151d2e8..de6b4a23c9e 100644 --- a/arch/arm/mach-s3c2443/dma.c +++ b/arch/arm/mach-s3c2443/dma.c @@ -14,7 +14,7 @@ #include <linux/kernel.h> #include <linux/init.h> -#include <linux/sysdev.h> +#include <linux/device.h> #include <linux/serial_core.h> #include <linux/io.h> @@ -135,19 +135,21 @@ static struct s3c24xx_dma_selection __initdata s3c2443_dma_sel = { .map_size = ARRAY_SIZE(s3c2443_dma_mappings), }; -static int __init s3c2443_dma_add(struct sys_device *sysdev) +static int __init s3c2443_dma_add(struct device *dev) { s3c24xx_dma_init(6, IRQ_S3C2443_DMA0, 0x100); return s3c24xx_dma_init_map(&s3c2443_dma_sel); } -static struct sysdev_driver s3c2443_dma_driver = { - .add = s3c2443_dma_add, +static struct subsys_interface s3c2443_dma_interface = { + .name = "s3c2443_dma", + .subsys = &s3c2443_subsys, + .add_dev = s3c2443_dma_add, }; static int __init s3c2443_dma_init(void) { - return sysdev_driver_register(&s3c2443_sysclass, &s3c2443_dma_driver); + return subsys_interface_register(&s3c2443_dma_interface); } arch_initcall(s3c2443_dma_init); diff --git a/arch/arm/mach-s3c2443/irq.c b/arch/arm/mach-s3c2443/irq.c index 83ecb1173fb..35e4ff24fb4 100644 --- a/arch/arm/mach-s3c2443/irq.c +++ b/arch/arm/mach-s3c2443/irq.c @@ -23,7 +23,7 @@ #include <linux/module.h> #include <linux/interrupt.h> #include <linux/ioport.h> -#include <linux/sysdev.h> +#include <linux/device.h> #include <linux/io.h> #include <mach/hardware.h> @@ -241,7 +241,7 @@ static int __init s3c2443_add_sub(unsigned int base, return 0; } -static int __init s3c2443_irq_add(struct sys_device *sysdev) +static int __init s3c2443_irq_add(struct device *dev) { printk("S3C2443: IRQ Support\n"); @@ -265,13 +265,15 @@ static int __init s3c2443_irq_add(struct sys_device *sysdev) return 0; } -static struct sysdev_driver s3c2443_irq_driver = { - .add = s3c2443_irq_add, +static struct subsys_interface s3c2443_irq_interface = { + .name = "s3c2443_irq", + .subsys = &s3c2443_subsys, + .add_dev = s3c2443_irq_add, }; static int __init s3c2443_irq_init(void) { - return sysdev_driver_register(&s3c2443_sysclass, &s3c2443_irq_driver); + return subsys_interface_register(&s3c2443_irq_interface); } arch_initcall(s3c2443_irq_init); diff --git a/arch/arm/mach-s3c2443/s3c2443.c b/arch/arm/mach-s3c2443/s3c2443.c index 4568ded338d..b9deaeb0dff 100644 --- a/arch/arm/mach-s3c2443/s3c2443.c +++ b/arch/arm/mach-s3c2443/s3c2443.c @@ -19,7 +19,7 @@ #include <linux/gpio.h> #include <linux/platform_device.h> #include <linux/serial_core.h> -#include <linux/sysdev.h> +#include <linux/device.h> #include <linux/clk.h> #include <linux/io.h> @@ -48,12 +48,13 @@ static struct map_desc s3c2443_iodesc[] __initdata = { IODESC_ENT(TIMER), }; -struct sysdev_class s3c2443_sysclass = { +struct bus_type s3c2443_subsys = { .name = "s3c2443-core", + .dev_name = "s3c2443-core", }; -static struct sys_device s3c2443_sysdev = { - .cls = &s3c2443_sysclass, +static struct device s3c2443_dev = { + .bus = &s3c2443_subsys, }; void s3c2443_restart(char mode, const char *cmd) @@ -77,7 +78,7 @@ int __init s3c2443_init(void) s3c_device_wdt.resource[1].start = IRQ_S3C2443_WDT; s3c_device_wdt.resource[1].end = IRQ_S3C2443_WDT; - return sysdev_register(&s3c2443_sysdev); + return device_register(&s3c2443_dev); } void __init s3c2443_init_uarts(struct s3c2410_uartcfg *cfg, int no) @@ -99,7 +100,7 @@ void __init s3c2443_map_io(void) iotable_init(s3c2443_iodesc, ARRAY_SIZE(s3c2443_iodesc)); } -/* need to register class before we actually register the device, and +/* need to register the subsystem before we actually register the device, and * we also need to ensure that it has been initialised before any of the * drivers even try to use it (even if not on an s3c2443 based system) * as a driver which may support both 2443 and 2440 may try and use it. @@ -107,7 +108,7 @@ void __init s3c2443_map_io(void) static int __init s3c2443_core_init(void) { - return sysdev_class_register(&s3c2443_sysclass); + return subsys_system_register(&s3c2443_subsys, NULL); } core_initcall(s3c2443_core_init); diff --git a/arch/arm/mach-s3c64xx/Kconfig b/arch/arm/mach-s3c64xx/Kconfig index 5552e048c2b..dd20c66cd70 100644 --- a/arch/arm/mach-s3c64xx/Kconfig +++ b/arch/arm/mach-s3c64xx/Kconfig @@ -8,6 +8,7 @@ config PLAT_S3C64XX bool depends on ARCH_S3C64XX select SAMSUNG_WAKEMASK + select PM_GENERIC_DOMAINS default y help Base platform code for any Samsung S3C64XX device @@ -77,6 +78,11 @@ config S3C64XX_SETUP_SDHCI_GPIO help Common setup code for S3C64XX SDHCI GPIO configurations +config S3C64XX_SETUP_SPI + bool + help + Common setup code for SPI GPIO configurations + # S36400 Macchine support config MACH_SMDK6400 @@ -188,7 +194,7 @@ config SMDK6410_WM1190_EV1 depends on MACH_SMDK6410 select REGULATOR select REGULATOR_WM8350 - select S3C24XX_GPIO_EXTRA64 + select SAMSUNG_GPIO_EXTRA64 select MFD_WM8350_I2C select MFD_WM8350_CONFIG_MODE_0 select MFD_WM8350_CONFIG_MODE_3 @@ -206,7 +212,7 @@ config SMDK6410_WM1192_EV1 depends on MACH_SMDK6410 select REGULATOR select REGULATOR_WM831X - select S3C24XX_GPIO_EXTRA64 + select SAMSUNG_GPIO_EXTRA64 select MFD_WM831X select MFD_WM831X_I2C help @@ -276,6 +282,7 @@ config MACH_WLF_CRAGG_6410 select S3C64XX_SETUP_IDE select S3C64XX_SETUP_FB_24BPP select S3C64XX_SETUP_KEYPAD + select S3C64XX_SETUP_SPI select SAMSUNG_DEV_ADC select SAMSUNG_DEV_KEYPAD select S3C_DEV_USB_HOST @@ -286,8 +293,8 @@ config MACH_WLF_CRAGG_6410 select S3C_DEV_I2C1 select S3C_DEV_WDT select S3C_DEV_RTC - select S3C64XX_DEV_SPI - select S3C24XX_GPIO_EXTRA128 + select S3C64XX_DEV_SPI0 + select SAMSUNG_GPIO_EXTRA128 select I2C help Machine support for the Wolfson Cragganmore S3C6410 variant. diff --git a/arch/arm/mach-s3c64xx/Makefile b/arch/arm/mach-s3c64xx/Makefile index f37016cebbe..1822ac2eba3 100644 --- a/arch/arm/mach-s3c64xx/Makefile +++ b/arch/arm/mach-s3c64xx/Makefile @@ -40,8 +40,8 @@ obj-$(CONFIG_S3C64XX_SETUP_I2C0) += setup-i2c0.o obj-$(CONFIG_S3C64XX_SETUP_I2C1) += setup-i2c1.o obj-$(CONFIG_S3C64XX_SETUP_IDE) += setup-ide.o obj-$(CONFIG_S3C64XX_SETUP_KEYPAD) += setup-keypad.o -obj-$(CONFIG_S3C64XX_SETUP_SDHCI) += setup-sdhci.o obj-$(CONFIG_S3C64XX_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o +obj-$(CONFIG_S3C64XX_SETUP_SPI) += setup-spi.o # Machine support diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c index 625219b9cef..31bb27dc4ae 100644 --- a/arch/arm/mach-s3c64xx/clock.c +++ b/arch/arm/mach-s3c64xx/clock.c @@ -184,18 +184,6 @@ static struct clk init_clocks_off[] = { .enable = s3c64xx_pclk_ctrl, .ctrlbit = S3C_CLKCON_PCLK_SPI1, }, { - .name = "spi_48m", - .devname = "s3c64xx-spi.0", - .parent = &clk_48m, - .enable = s3c64xx_sclk_ctrl, - .ctrlbit = S3C_CLKCON_SCLK_SPI0_48, - }, { - .name = "spi_48m", - .devname = "s3c64xx-spi.1", - .parent = &clk_48m, - .enable = s3c64xx_sclk_ctrl, - .ctrlbit = S3C_CLKCON_SCLK_SPI1_48, - }, { .name = "48m", .devname = "s3c-sdhci.0", .parent = &clk_48m, @@ -226,6 +214,22 @@ static struct clk init_clocks_off[] = { }, }; +static struct clk clk_48m_spi0 = { + .name = "spi_48m", + .devname = "s3c64xx-spi.0", + .parent = &clk_48m, + .enable = s3c64xx_sclk_ctrl, + .ctrlbit = S3C_CLKCON_SCLK_SPI0_48, +}; + +static struct clk clk_48m_spi1 = { + .name = "spi_48m", + .devname = "s3c64xx-spi.1", + .parent = &clk_48m, + .enable = s3c64xx_sclk_ctrl, + .ctrlbit = S3C_CLKCON_SCLK_SPI1_48, +}; + static struct clk init_clocks[] = { { .name = "lcd", @@ -243,24 +247,6 @@ static struct clk init_clocks[] = { .enable = s3c64xx_hclk_ctrl, .ctrlbit = S3C_CLKCON_HCLK_UHOST, }, { - .name = "hsmmc", - .devname = "s3c-sdhci.0", - .parent = &clk_h, - .enable = s3c64xx_hclk_ctrl, - .ctrlbit = S3C_CLKCON_HCLK_HSMMC0, - }, { - .name = "hsmmc", - .devname = "s3c-sdhci.1", - .parent = &clk_h, - .enable = s3c64xx_hclk_ctrl, - .ctrlbit = S3C_CLKCON_HCLK_HSMMC1, - }, { - .name = "hsmmc", - .devname = "s3c-sdhci.2", - .parent = &clk_h, - .enable = s3c64xx_hclk_ctrl, - .ctrlbit = S3C_CLKCON_HCLK_HSMMC2, - }, { .name = "otg", .parent = &clk_h, .enable = s3c64xx_hclk_ctrl, @@ -310,6 +296,29 @@ static struct clk init_clocks[] = { } }; +static struct clk clk_hsmmc0 = { + .name = "hsmmc", + .devname = "s3c-sdhci.0", + .parent = &clk_h, + .enable = s3c64xx_hclk_ctrl, + .ctrlbit = S3C_CLKCON_HCLK_HSMMC0, +}; + +static struct clk clk_hsmmc1 = { + .name = "hsmmc", + .devname = "s3c-sdhci.1", + .parent = &clk_h, + .enable = s3c64xx_hclk_ctrl, + .ctrlbit = S3C_CLKCON_HCLK_HSMMC1, +}; + +static struct clk clk_hsmmc2 = { + .name = "hsmmc", + .devname = "s3c-sdhci.2", + .parent = &clk_h, + .enable = s3c64xx_hclk_ctrl, + .ctrlbit = S3C_CLKCON_HCLK_HSMMC2, +}; static struct clk clk_fout_apll = { .name = "fout_apll", @@ -578,36 +587,6 @@ static struct clksrc_sources clkset_camif = { static struct clksrc_clk clksrcs[] = { { .clk = { - .name = "mmc_bus", - .devname = "s3c-sdhci.0", - .ctrlbit = S3C_CLKCON_SCLK_MMC0, - .enable = s3c64xx_sclk_ctrl, - }, - .reg_src = { .reg = S3C_CLK_SRC, .shift = 18, .size = 2 }, - .reg_div = { .reg = S3C_CLK_DIV1, .shift = 0, .size = 4 }, - .sources = &clkset_spi_mmc, - }, { - .clk = { - .name = "mmc_bus", - .devname = "s3c-sdhci.1", - .ctrlbit = S3C_CLKCON_SCLK_MMC1, - .enable = s3c64xx_sclk_ctrl, - }, - .reg_src = { .reg = S3C_CLK_SRC, .shift = 20, .size = 2 }, - .reg_div = { .reg = S3C_CLK_DIV1, .shift = 4, .size = 4 }, - .sources = &clkset_spi_mmc, - }, { - .clk = { - .name = "mmc_bus", - .devname = "s3c-sdhci.2", - .ctrlbit = S3C_CLKCON_SCLK_MMC2, - .enable = s3c64xx_sclk_ctrl, - }, - .reg_src = { .reg = S3C_CLK_SRC, .shift = 22, .size = 2 }, - .reg_div = { .reg = S3C_CLK_DIV1, .shift = 8, .size = 4 }, - .sources = &clkset_spi_mmc, - }, { - .clk = { .name = "usb-bus-host", .ctrlbit = S3C_CLKCON_SCLK_UHOST, .enable = s3c64xx_sclk_ctrl, @@ -617,35 +596,6 @@ static struct clksrc_clk clksrcs[] = { .sources = &clkset_uhost, }, { .clk = { - .name = "uclk1", - .ctrlbit = S3C_CLKCON_SCLK_UART, - .enable = s3c64xx_sclk_ctrl, - }, - .reg_src = { .reg = S3C_CLK_SRC, .shift = 13, .size = 1 }, - .reg_div = { .reg = S3C_CLK_DIV2, .shift = 16, .size = 4 }, - .sources = &clkset_uart, - }, { -/* Where does UCLK0 come from? */ - .clk = { - .name = "spi-bus", - .devname = "s3c64xx-spi.0", - .ctrlbit = S3C_CLKCON_SCLK_SPI0, - .enable = s3c64xx_sclk_ctrl, - }, - .reg_src = { .reg = S3C_CLK_SRC, .shift = 14, .size = 2 }, - .reg_div = { .reg = S3C_CLK_DIV2, .shift = 0, .size = 4 }, - .sources = &clkset_spi_mmc, - }, { - .clk = { - .name = "spi-bus", - .devname = "s3c64xx-spi.1", - .enable = s3c64xx_sclk_ctrl, - }, - .reg_src = { .reg = S3C_CLK_SRC, .shift = 16, .size = 2 }, - .reg_div = { .reg = S3C_CLK_DIV2, .shift = 4, .size = 4 }, - .sources = &clkset_spi_mmc, - }, { - .clk = { .name = "audio-bus", .devname = "samsung-i2s.0", .ctrlbit = S3C_CLKCON_SCLK_AUDIO0, @@ -695,6 +645,78 @@ static struct clksrc_clk clksrcs[] = { }, }; +/* Where does UCLK0 come from? */ +static struct clksrc_clk clk_sclk_uclk = { + .clk = { + .name = "uclk1", + .ctrlbit = S3C_CLKCON_SCLK_UART, + .enable = s3c64xx_sclk_ctrl, + }, + .reg_src = { .reg = S3C_CLK_SRC, .shift = 13, .size = 1 }, + .reg_div = { .reg = S3C_CLK_DIV2, .shift = 16, .size = 4 }, + .sources = &clkset_uart, +}; + +static struct clksrc_clk clk_sclk_mmc0 = { + .clk = { + .name = "mmc_bus", + .devname = "s3c-sdhci.0", + .ctrlbit = S3C_CLKCON_SCLK_MMC0, + .enable = s3c64xx_sclk_ctrl, + }, + .reg_src = { .reg = S3C_CLK_SRC, .shift = 18, .size = 2 }, + .reg_div = { .reg = S3C_CLK_DIV1, .shift = 0, .size = 4 }, + .sources = &clkset_spi_mmc, +}; + +static struct clksrc_clk clk_sclk_mmc1 = { + .clk = { + .name = "mmc_bus", + .devname = "s3c-sdhci.1", + .ctrlbit = S3C_CLKCON_SCLK_MMC1, + .enable = s3c64xx_sclk_ctrl, + }, + .reg_src = { .reg = S3C_CLK_SRC, .shift = 20, .size = 2 }, + .reg_div = { .reg = S3C_CLK_DIV1, .shift = 4, .size = 4 }, + .sources = &clkset_spi_mmc, +}; + +static struct clksrc_clk clk_sclk_mmc2 = { + .clk = { + .name = "mmc_bus", + .devname = "s3c-sdhci.2", + .ctrlbit = S3C_CLKCON_SCLK_MMC2, + .enable = s3c64xx_sclk_ctrl, + }, + .reg_src = { .reg = S3C_CLK_SRC, .shift = 22, .size = 2 }, + .reg_div = { .reg = S3C_CLK_DIV1, .shift = 8, .size = 4 }, + .sources = &clkset_spi_mmc, +}; + +static struct clksrc_clk clk_sclk_spi0 = { + .clk = { + .name = "spi-bus", + .devname = "s3c64xx-spi.0", + .ctrlbit = S3C_CLKCON_SCLK_SPI0, + .enable = s3c64xx_sclk_ctrl, + }, + .reg_src = { .reg = S3C_CLK_SRC, .shift = 14, .size = 2 }, + .reg_div = { .reg = S3C_CLK_DIV2, .shift = 0, .size = 4 }, + .sources = &clkset_spi_mmc, +}; + +static struct clksrc_clk clk_sclk_spi1 = { + .clk = { + .name = "spi-bus", + .devname = "s3c64xx-spi.1", + .ctrlbit = S3C_CLKCON_SCLK_SPI1, + .enable = s3c64xx_sclk_ctrl, + }, + .reg_src = { .reg = S3C_CLK_SRC, .shift = 16, .size = 2 }, + .reg_div = { .reg = S3C_CLK_DIV2, .shift = 4, .size = 4 }, + .sources = &clkset_spi_mmc, +}; + /* Clock initialisation code */ static struct clksrc_clk *init_parents[] = { @@ -703,6 +725,39 @@ static struct clksrc_clk *init_parents[] = { &clk_mout_mpll, }; +static struct clksrc_clk *clksrc_cdev[] = { + &clk_sclk_uclk, + &clk_sclk_mmc0, + &clk_sclk_mmc1, + &clk_sclk_mmc2, + &clk_sclk_spi0, + &clk_sclk_spi1, +}; + +static struct clk *clk_cdev[] = { + &clk_hsmmc0, + &clk_hsmmc1, + &clk_hsmmc2, + &clk_48m_spi0, + &clk_48m_spi1, +}; + +static struct clk_lookup s3c64xx_clk_lookup[] = { + CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p), + CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk), + CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &clk_hsmmc0), + CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &clk_hsmmc1), + CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.0", &clk_hsmmc2), + CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk), + CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk), + CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk), + CLKDEV_INIT(NULL, "spi_busclk0", &clk_p), + CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk), + CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &clk_48m_spi0), + CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk), + CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk2", &clk_48m_spi1), +}; + #define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1) void __init_or_cpufreq s3c64xx_setup_clocks(void) @@ -811,6 +866,8 @@ static struct clk *clks[] __initdata = { void __init s3c64xx_register_clocks(unsigned long xtal, unsigned armclk_divlimit) { + unsigned int cnt; + armclk_mask = armclk_divlimit; s3c24xx_register_baseclocks(xtal); @@ -821,7 +878,15 @@ void __init s3c64xx_register_clocks(unsigned long xtal, s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); + s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev)); + for (cnt = 0; cnt < ARRAY_SIZE(clk_cdev); cnt++) + s3c_disable_clocks(clk_cdev[cnt], 1); + s3c24xx_register_clocks(clks1, ARRAY_SIZE(clks1)); s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); + for (cnt = 0; cnt < ARRAY_SIZE(clksrc_cdev); cnt++) + s3c_register_clksrc(clksrc_cdev[cnt], 1); + clkdev_add_table(s3c64xx_clk_lookup, ARRAY_SIZE(s3c64xx_clk_lookup)); + s3c_pwmclk_init(); } diff --git a/arch/arm/mach-s3c64xx/common.c b/arch/arm/mach-s3c64xx/common.c index 35182ba049d..4a7394d4bd9 100644 --- a/arch/arm/mach-s3c64xx/common.c +++ b/arch/arm/mach-s3c64xx/common.c @@ -19,7 +19,6 @@ #include <linux/module.h> #include <linux/interrupt.h> #include <linux/ioport.h> -#include <linux/sysdev.h> #include <linux/serial_core.h> #include <linux/platform_device.h> #include <linux/io.h> @@ -139,12 +138,13 @@ static struct map_desc s3c_iodesc[] __initdata = { }, }; -struct sysdev_class s3c64xx_sysclass = { - .name = "s3c64xx-core", +static struct bus_type s3c64xx_subsys = { + .name = "s3c64xx-core", + .dev_name = "s3c64xx-core", }; -static struct sys_device s3c64xx_sysdev = { - .cls = &s3c64xx_sysclass, +static struct device s3c64xx_dev = { + .bus = &s3c64xx_subsys, }; /* read cpu identification code */ @@ -162,12 +162,12 @@ void __init s3c64xx_init_io(struct map_desc *mach_desc, int size) s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids)); } -static __init int s3c64xx_sysdev_init(void) +static __init int s3c64xx_dev_init(void) { - sysdev_class_register(&s3c64xx_sysclass); - return sysdev_register(&s3c64xx_sysdev); + subsys_system_register(&s3c64xx_subsys, NULL); + return device_register(&s3c64xx_dev); } -core_initcall(s3c64xx_sysdev_init); +core_initcall(s3c64xx_dev_init); /* * setup the sources the vic should advertise resume diff --git a/arch/arm/mach-s3c64xx/common.h b/arch/arm/mach-s3c64xx/common.h index 8dc8ab6d8d6..5eb9c9a7d73 100644 --- a/arch/arm/mach-s3c64xx/common.h +++ b/arch/arm/mach-s3c64xx/common.h @@ -26,7 +26,6 @@ void s3c64xx_setup_clocks(void); void s3c64xx_restart(char mode, const char *cmd); extern struct syscore_ops s3c64xx_irq_syscore_ops; -extern struct sysdev_class s3c64xx_sysclass; #ifdef CONFIG_CPU_S3C6400 diff --git a/arch/arm/mach-s3c64xx/dev-spi.c b/arch/arm/mach-s3c64xx/dev-spi.c deleted file mode 100644 index 3341fd11872..00000000000 --- a/arch/arm/mach-s3c64xx/dev-spi.c +++ /dev/null @@ -1,180 +0,0 @@ -/* linux/arch/arm/plat-s3c64xx/dev-spi.c - * - * Copyright (C) 2009 Samsung Electronics Ltd. - * Jaswinder Singh <jassi.brar@samsung.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/kernel.h> -#include <linux/string.h> -#include <linux/export.h> -#include <linux/platform_device.h> -#include <linux/dma-mapping.h> -#include <linux/gpio.h> - -#include <mach/dma.h> -#include <mach/map.h> -#include <mach/spi-clocks.h> -#include <mach/irqs.h> - -#include <plat/s3c64xx-spi.h> -#include <plat/gpio-cfg.h> -#include <plat/devs.h> - -static char *spi_src_clks[] = { - [S3C64XX_SPI_SRCCLK_PCLK] = "pclk", - [S3C64XX_SPI_SRCCLK_SPIBUS] = "spi-bus", - [S3C64XX_SPI_SRCCLK_48M] = "spi_48m", -}; - -/* SPI Controller platform_devices */ - -/* Since we emulate multi-cs capability, we do not touch the GPC-3,7. - * The emulated CS is toggled by board specific mechanism, as it can - * be either some immediate GPIO or some signal out of some other - * chip in between ... or some yet another way. - * We simply do not assume anything about CS. - */ -static int s3c64xx_spi_cfg_gpio(struct platform_device *pdev) -{ - unsigned int base; - - switch (pdev->id) { - case 0: - base = S3C64XX_GPC(0); - break; - - case 1: - base = S3C64XX_GPC(4); - break; - - default: - dev_err(&pdev->dev, "Invalid SPI Controller number!"); - return -EINVAL; - } - - s3c_gpio_cfgall_range(base, 3, - S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); - - return 0; -} - -static struct resource s3c64xx_spi0_resource[] = { - [0] = { - .start = S3C64XX_PA_SPI0, - .end = S3C64XX_PA_SPI0 + 0x100 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = DMACH_SPI0_TX, - .end = DMACH_SPI0_TX, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = DMACH_SPI0_RX, - .end = DMACH_SPI0_RX, - .flags = IORESOURCE_DMA, - }, - [3] = { - .start = IRQ_SPI0, - .end = IRQ_SPI0, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct s3c64xx_spi_info s3c64xx_spi0_pdata = { - .cfg_gpio = s3c64xx_spi_cfg_gpio, - .fifo_lvl_mask = 0x7f, - .rx_lvl_offset = 13, - .tx_st_done = 21, -}; - -static u64 spi_dmamask = DMA_BIT_MASK(32); - -struct platform_device s3c64xx_device_spi0 = { - .name = "s3c64xx-spi", - .id = 0, - .num_resources = ARRAY_SIZE(s3c64xx_spi0_resource), - .resource = s3c64xx_spi0_resource, - .dev = { - .dma_mask = &spi_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - .platform_data = &s3c64xx_spi0_pdata, - }, -}; -EXPORT_SYMBOL(s3c64xx_device_spi0); - -static struct resource s3c64xx_spi1_resource[] = { - [0] = { - .start = S3C64XX_PA_SPI1, - .end = S3C64XX_PA_SPI1 + 0x100 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = DMACH_SPI1_TX, - .end = DMACH_SPI1_TX, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = DMACH_SPI1_RX, - .end = DMACH_SPI1_RX, - .flags = IORESOURCE_DMA, - }, - [3] = { - .start = IRQ_SPI1, - .end = IRQ_SPI1, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct s3c64xx_spi_info s3c64xx_spi1_pdata = { - .cfg_gpio = s3c64xx_spi_cfg_gpio, - .fifo_lvl_mask = 0x7f, - .rx_lvl_offset = 13, - .tx_st_done = 21, -}; - -struct platform_device s3c64xx_device_spi1 = { - .name = "s3c64xx-spi", - .id = 1, - .num_resources = ARRAY_SIZE(s3c64xx_spi1_resource), - .resource = s3c64xx_spi1_resource, - .dev = { - .dma_mask = &spi_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - .platform_data = &s3c64xx_spi1_pdata, - }, -}; -EXPORT_SYMBOL(s3c64xx_device_spi1); - -void __init s3c64xx_spi_set_info(int cntrlr, int src_clk_nr, int num_cs) -{ - struct s3c64xx_spi_info *pd; - - /* Reject invalid configuration */ - if (!num_cs || src_clk_nr < 0 - || src_clk_nr > S3C64XX_SPI_SRCCLK_48M) { - printk(KERN_ERR "%s: Invalid SPI configuration\n", __func__); - return; - } - - switch (cntrlr) { - case 0: - pd = &s3c64xx_spi0_pdata; - break; - case 1: - pd = &s3c64xx_spi1_pdata; - break; - default: - printk(KERN_ERR "%s: Invalid SPI controller(%d)\n", - __func__, cntrlr); - return; - } - - pd->num_cs = num_cs; - pd->src_clk_nr = src_clk_nr; - pd->src_clk_name = spi_src_clks[src_clk_nr]; -} diff --git a/arch/arm/mach-s3c64xx/dma.c b/arch/arm/mach-s3c64xx/dma.c index 17d62f4f820..f2a7a172559 100644 --- a/arch/arm/mach-s3c64xx/dma.c +++ b/arch/arm/mach-s3c64xx/dma.c @@ -16,7 +16,7 @@ #include <linux/module.h> #include <linux/interrupt.h> #include <linux/dmapool.h> -#include <linux/sysdev.h> +#include <linux/device.h> #include <linux/errno.h> #include <linux/slab.h> #include <linux/delay.h> @@ -35,7 +35,7 @@ /* dma channel state information */ struct s3c64xx_dmac { - struct sys_device sysdev; + struct device dev; struct clk *clk; void __iomem *regs; struct s3c2410_dma_chan *channels; @@ -631,8 +631,9 @@ static irqreturn_t s3c64xx_dma_irq(int irq, void *pw) return IRQ_HANDLED; } -static struct sysdev_class dma_sysclass = { +static struct bus_type dma_subsys = { .name = "s3c64xx-dma", + .dev_name = "s3c64xx-dma", }; static int s3c64xx_dma_init1(int chno, enum dma_ch chbase, @@ -651,12 +652,12 @@ static int s3c64xx_dma_init1(int chno, enum dma_ch chbase, return -ENOMEM; } - dmac->sysdev.id = chno / 8; - dmac->sysdev.cls = &dma_sysclass; + dmac->dev.id = chno / 8; + dmac->dev.bus = &dma_subsys; - err = sysdev_register(&dmac->sysdev); + err = device_register(&dmac->dev); if (err) { - printk(KERN_ERR "%s: failed to register sysdevice\n", __func__); + printk(KERN_ERR "%s: failed to register device\n", __func__); goto err_alloc; } @@ -667,7 +668,7 @@ static int s3c64xx_dma_init1(int chno, enum dma_ch chbase, goto err_dev; } - snprintf(clkname, sizeof(clkname), "dma%d", dmac->sysdev.id); + snprintf(clkname, sizeof(clkname), "dma%d", dmac->dev.id); dmac->clk = clk_get(NULL, clkname); if (IS_ERR(dmac->clk)) { @@ -715,7 +716,7 @@ err_clk: err_map: iounmap(regs); err_dev: - sysdev_unregister(&dmac->sysdev); + device_unregister(&dmac->dev); err_alloc: kfree(dmac); return err; @@ -733,9 +734,9 @@ static int __init s3c64xx_dma_init(void) return -ENOMEM; } - ret = sysdev_class_register(&dma_sysclass); + ret = subsys_system_register(&dma_subsys, NULL); if (ret) { - printk(KERN_ERR "%s: failed to create sysclass\n", __func__); + printk(KERN_ERR "%s: failed to create subsys\n", __func__); return -ENOMEM; } diff --git a/arch/arm/mach-s3c64xx/include/mach/crag6410.h b/arch/arm/mach-s3c64xx/include/mach/crag6410.h index be9074e17df..5d55ab018b6 100644 --- a/arch/arm/mach-s3c64xx/include/mach/crag6410.h +++ b/arch/arm/mach-s3c64xx/include/mach/crag6410.h @@ -15,9 +15,11 @@ #define BANFF_PMIC_IRQ_BASE IRQ_BOARD_START #define GLENFARCLAS_PMIC_IRQ_BASE (IRQ_BOARD_START + 64) +#define CODEC_IRQ_BASE (IRQ_BOARD_START + 128) #define PCA935X_GPIO_BASE GPIO_BOARD_START -#define CODEC_GPIO_BASE (GPIO_BOARD_START + 8) -#define GLENFARCLAS_PMIC_GPIO_BASE (GPIO_BOARD_START + 16) +#define CODEC_GPIO_BASE (GPIO_BOARD_START + 8) +#define GLENFARCLAS_PMIC_GPIO_BASE (GPIO_BOARD_START + 32) +#define BANFF_PMIC_GPIO_BASE (GPIO_BOARD_START + 64) #endif diff --git a/arch/arm/mach-s3c64xx/include/mach/gpio.h b/arch/arm/mach-s3c64xx/include/mach/gpio.h index 6e34c2f6e67..8b540c42d5d 100644 --- a/arch/arm/mach-s3c64xx/include/mach/gpio.h +++ b/arch/arm/mach-s3c64xx/include/mach/gpio.h @@ -88,6 +88,6 @@ enum s3c_gpio_number { /* define the number of gpios we need to the one after the GPQ() range */ #define GPIO_BOARD_START (S3C64XX_GPQ(S3C64XX_GPIO_Q_NR) + 1) -#define BOARD_NR_GPIOS 16 +#define BOARD_NR_GPIOS (16 + CONFIG_SAMSUNG_GPIO_EXTRA) #define ARCH_NR_GPIOS (GPIO_BOARD_START + BOARD_NR_GPIOS) diff --git a/arch/arm/mach-s3c64xx/include/mach/irqs.h b/arch/arm/mach-s3c64xx/include/mach/irqs.h index 443f85b3c20..96d60e0d937 100644 --- a/arch/arm/mach-s3c64xx/include/mach/irqs.h +++ b/arch/arm/mach-s3c64xx/include/mach/irqs.h @@ -169,7 +169,7 @@ #define IRQ_BOARD_START (IRQ_EINT_GROUP9_BASE + IRQ_EINT_GROUP9_NR + 1) #ifdef CONFIG_MACH_WLF_CRAGG_6410 -#define IRQ_BOARD_NR 128 +#define IRQ_BOARD_NR 160 #elif defined(CONFIG_SMDK6410_WM1190_EV1) #define IRQ_BOARD_NR 64 #elif defined(CONFIG_SMDK6410_WM1192_EV1) diff --git a/arch/arm/mach-s3c64xx/include/mach/map.h b/arch/arm/mach-s3c64xx/include/mach/map.h index 23a1d71e4d5..8e2097bb208 100644 --- a/arch/arm/mach-s3c64xx/include/mach/map.h +++ b/arch/arm/mach-s3c64xx/include/mach/map.h @@ -115,6 +115,8 @@ #define S3C_PA_USB_HSOTG S3C64XX_PA_USB_HSOTG #define S3C_PA_RTC S3C64XX_PA_RTC #define S3C_PA_WDT S3C64XX_PA_WATCHDOG +#define S3C_PA_SPI0 S3C64XX_PA_SPI0 +#define S3C_PA_SPI1 S3C64XX_PA_SPI1 #define SAMSUNG_PA_ADC S3C64XX_PA_ADC #define SAMSUNG_PA_CFCON S3C64XX_PA_CFCON diff --git a/arch/arm/mach-s3c64xx/mach-crag6410-module.c b/arch/arm/mach-s3c64xx/mach-crag6410-module.c index f208154b138..cd3c97e2ee7 100644 --- a/arch/arm/mach-s3c64xx/mach-crag6410-module.c +++ b/arch/arm/mach-s3c64xx/mach-crag6410-module.c @@ -14,13 +14,43 @@ #include <linux/mfd/wm831x/irq.h> #include <linux/mfd/wm831x/gpio.h> +#include <linux/mfd/wm8994/pdata.h> +#include <sound/wm5100.h> #include <sound/wm8996.h> #include <sound/wm8962.h> #include <sound/wm9081.h> #include <mach/crag6410.h> +static struct wm5100_pdata wm5100_pdata = { + .ldo_ena = S3C64XX_GPN(7), + .irq_flags = IRQF_TRIGGER_HIGH, + .gpio_base = CODEC_GPIO_BASE, + + .in_mode = { + WM5100_IN_DIFF, + WM5100_IN_DIFF, + WM5100_IN_DIFF, + WM5100_IN_SE, + }, + + .hp_pol = CODEC_GPIO_BASE + 3, + .jack_modes = { + { WM5100_MICDET_MICBIAS3, 0, 0 }, + { WM5100_MICDET_MICBIAS2, 1, 1 }, + }, + + .gpio_defaults = { + 0, + 0, + 0, + 0, + 0x2, /* IRQ: CMOS output */ + 0x3, /* CLKOUT: CMOS output */ + }, +}; + static struct wm8996_retune_mobile_config wm8996_retune[] = { { .name = "Sub LPF", @@ -72,7 +102,6 @@ static struct wm8962_pdata wm8962_pdata __initdata = { 0x8000 | WM8962_GPIO_FN_DMICDAT, WM8962_GPIO_FN_IRQ, /* Open drain mode */ }, - .irq_active_low = true, }; static struct wm9081_pdata wm9081_pdata __initdata = { @@ -91,6 +120,7 @@ static const struct i2c_board_info wm1254_devs[] = { static const struct i2c_board_info wm1255_devs[] = { { I2C_BOARD_INFO("wm5100", 0x1a), + .platform_data = &wm5100_pdata, .irq = GLENFARCLAS_PMIC_IRQ_BASE + WM831X_IRQ_GPIO_2, }, { I2C_BOARD_INFO("wm9081", 0x6c), @@ -104,6 +134,24 @@ static const struct i2c_board_info wm1259_devs[] = { }, }; +static struct wm8994_pdata wm8994_pdata = { + .gpio_base = CODEC_GPIO_BASE, + .gpio_defaults = { + 0x3, /* IRQ out, active high, CMOS */ + }, + .irq_base = CODEC_IRQ_BASE, + .ldo = { + { .supply = "WALLVDD" }, + { .supply = "WALLVDD" }, + }, +}; + +static const struct i2c_board_info wm1277_devs[] = { + { I2C_BOARD_INFO("wm8958", 0x1a), /* WM8958 is the superset */ + .platform_data = &wm8994_pdata, + .irq = GLENFARCLAS_PMIC_IRQ_BASE + WM831X_IRQ_GPIO_2, + }, +}; static __devinitdata const struct { u8 id; @@ -125,6 +173,8 @@ static __devinitdata const struct { { .id = 0x3b, .name = "1255-EV1 Kilchoman", .i2c_devs = wm1255_devs, .num_i2c_devs = ARRAY_SIZE(wm1255_devs) }, { .id = 0x3c, .name = "1273-EV1 Longmorn" }, + { .id = 0x3d, .name = "1277-EV1 Littlemill", + .i2c_devs = wm1277_devs, .num_i2c_devs = ARRAY_SIZE(wm1277_devs) }, }; static __devinit int wlf_gf_module_probe(struct i2c_client *i2c, @@ -154,8 +204,8 @@ static __devinit int wlf_gf_module_probe(struct i2c_client *i2c, "Failed to register dev: %d\n", ret); } } else { - dev_warn(&i2c->dev, "Unknown module ID %d revision %d\n", - id, rev); + dev_warn(&i2c->dev, "Unknown module ID 0x%x revision %d\n", + id, rev + 1); } return 0; diff --git a/arch/arm/mach-s3c64xx/mach-crag6410.c b/arch/arm/mach-s3c64xx/mach-crag6410.c index f1c848aa4a1..1cc91d794c9 100644 --- a/arch/arm/mach-s3c64xx/mach-crag6410.c +++ b/arch/arm/mach-s3c64xx/mach-crag6410.c @@ -37,6 +37,8 @@ #include <linux/mfd/wm831x/irq.h> #include <linux/mfd/wm831x/gpio.h> +#include <sound/wm1250-ev1.h> + #include <asm/hardware/vic.h> #include <asm/mach/arch.h> #include <asm/mach-types.h> @@ -284,8 +286,13 @@ static struct platform_device lowland_device = { .id = -1, }; -static struct platform_device speyside_wm8962_device = { - .name = "speyside-wm8962", +static struct platform_device tobermory_device = { + .name = "tobermory", + .id = -1, +}; + +static struct platform_device littlemill_device = { + .name = "littlemill", .id = -1, }; @@ -340,7 +347,8 @@ static struct platform_device *crag6410_devices[] __initdata = { &crag6410_lcd_powerdev, &crag6410_backlight_device, &speyside_device, - &speyside_wm8962_device, + &tobermory_device, + &littlemill_device, &lowland_device, &wallvdd_device, }; @@ -374,6 +382,10 @@ static struct regulator_init_data vddarm __initdata = { .driver_data = &vddarm_pdata, }; +static struct regulator_consumer_supply vddint_consumers[] __initdata = { + REGULATOR_SUPPLY("vddint", NULL), +}; + static struct regulator_init_data vddint __initdata = { .constraints = { .name = "VDDINT", @@ -382,6 +394,9 @@ static struct regulator_init_data vddint __initdata = { .always_on = 1, .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, }, + .num_consumer_supplies = ARRAY_SIZE(vddint_consumers), + .consumer_supplies = vddint_consumers, + .supply_regulator = "WALLVDD", }; static struct regulator_init_data vddmem __initdata = { @@ -502,7 +517,8 @@ static struct wm831x_touch_pdata touch_pdata __initdata = { static struct wm831x_pdata crag_pmic_pdata __initdata = { .wm831x_num = 1, .irq_base = BANFF_PMIC_IRQ_BASE, - .gpio_base = GPIO_BOARD_START + 8, + .gpio_base = BANFF_PMIC_GPIO_BASE, + .soft_shutdown = true, .backup = &banff_backup_pdata, @@ -607,6 +623,7 @@ static struct wm831x_pdata glenfarclas_pmic_pdata __initdata = { .wm831x_num = 2, .irq_base = GLENFARCLAS_PMIC_IRQ_BASE, .gpio_base = GLENFARCLAS_PMIC_GPIO_BASE, + .soft_shutdown = true, .gpio_defaults = { /* GPIO1-3: IRQ inputs, rising edge triggered, CMOS */ @@ -624,6 +641,16 @@ static struct wm831x_pdata glenfarclas_pmic_pdata __initdata = { .disable_touch = true, }; +static struct wm1250_ev1_pdata wm1250_ev1_pdata = { + .gpios = { + [WM1250_EV1_GPIO_CLK_ENA] = S3C64XX_GPN(12), + [WM1250_EV1_GPIO_CLK_SEL0] = S3C64XX_GPL(12), + [WM1250_EV1_GPIO_CLK_SEL1] = S3C64XX_GPL(13), + [WM1250_EV1_GPIO_OSR] = S3C64XX_GPL(14), + [WM1250_EV1_GPIO_MASTER] = S3C64XX_GPL(8), + }, +}; + static struct i2c_board_info i2c_devs1[] __initdata = { { I2C_BOARD_INFO("wm8311", 0x34), .irq = S3C_EINT(0), @@ -633,7 +660,13 @@ static struct i2c_board_info i2c_devs1[] __initdata = { { I2C_BOARD_INFO("wlf-gf-module", 0x25) }, { I2C_BOARD_INFO("wlf-gf-module", 0x26) }, - { I2C_BOARD_INFO("wm1250-ev1", 0x27) }, + { I2C_BOARD_INFO("wm1250-ev1", 0x27), + .platform_data = &wm1250_ev1_pdata }, +}; + +static struct s3c2410_platform_i2c i2c1_pdata = { + .frequency = 400000, + .bus_num = 1, }; static void __init crag6410_map_io(void) @@ -694,7 +727,7 @@ static void __init crag6410_machine_init(void) s3c_sdhci2_set_platdata(&crag6410_hsmmc2_pdata); s3c_i2c0_set_platdata(&i2c0_pdata); - s3c_i2c1_set_platdata(NULL); + s3c_i2c1_set_platdata(&i2c1_pdata); s3c_fb_set_platdata(&crag6410_lcd_pdata); i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0)); @@ -706,7 +739,7 @@ static void __init crag6410_machine_init(void) regulator_has_full_constraints(); - s3c_pm_init(); + s3c64xx_pm_init(); } MACHINE_START(WLF_CRAGG_6410, "Wolfson Cragganmore 6410") diff --git a/arch/arm/mach-s3c64xx/pm.c b/arch/arm/mach-s3c64xx/pm.c index b375cd5c47c..055dac90e0e 100644 --- a/arch/arm/mach-s3c64xx/pm.c +++ b/arch/arm/mach-s3c64xx/pm.c @@ -17,10 +17,12 @@ #include <linux/serial_core.h> #include <linux/io.h> #include <linux/gpio.h> +#include <linux/pm_domain.h> #include <mach/map.h> #include <mach/irqs.h> +#include <plat/devs.h> #include <plat/pm.h> #include <plat/wakeup-mask.h> @@ -31,6 +33,148 @@ #include <mach/regs-gpio-memport.h> #include <mach/regs-modem.h> +struct s3c64xx_pm_domain { + char *const name; + u32 ena; + u32 pwr_stat; + struct generic_pm_domain pd; +}; + +static int s3c64xx_pd_off(struct generic_pm_domain *domain) +{ + struct s3c64xx_pm_domain *pd; + u32 val; + + pd = container_of(domain, struct s3c64xx_pm_domain, pd); + + val = __raw_readl(S3C64XX_NORMAL_CFG); + val &= ~(pd->ena); + __raw_writel(val, S3C64XX_NORMAL_CFG); + + return 0; +} + +static int s3c64xx_pd_on(struct generic_pm_domain *domain) +{ + struct s3c64xx_pm_domain *pd; + u32 val; + long retry = 1000000L; + + pd = container_of(domain, struct s3c64xx_pm_domain, pd); + + val = __raw_readl(S3C64XX_NORMAL_CFG); + val |= pd->ena; + __raw_writel(val, S3C64XX_NORMAL_CFG); + + /* Not all domains provide power status readback */ + if (pd->pwr_stat) { + do { + cpu_relax(); + if (__raw_readl(S3C64XX_BLK_PWR_STAT) & pd->pwr_stat) + break; + } while (retry--); + + if (!retry) { + pr_err("Failed to start domain %s\n", pd->name); + return -EBUSY; + } + } + + return 0; +} + +static struct s3c64xx_pm_domain s3c64xx_pm_irom = { + .name = "IROM", + .ena = S3C64XX_NORMALCFG_IROM_ON, + .pd = { + .power_off = s3c64xx_pd_off, + .power_on = s3c64xx_pd_on, + }, +}; + +static struct s3c64xx_pm_domain s3c64xx_pm_etm = { + .name = "ETM", + .ena = S3C64XX_NORMALCFG_DOMAIN_ETM_ON, + .pwr_stat = S3C64XX_BLKPWRSTAT_ETM, + .pd = { + .power_off = s3c64xx_pd_off, + .power_on = s3c64xx_pd_on, + }, +}; + +static struct s3c64xx_pm_domain s3c64xx_pm_s = { + .name = "S", + .ena = S3C64XX_NORMALCFG_DOMAIN_S_ON, + .pwr_stat = S3C64XX_BLKPWRSTAT_S, + .pd = { + .power_off = s3c64xx_pd_off, + .power_on = s3c64xx_pd_on, + }, +}; + +static struct s3c64xx_pm_domain s3c64xx_pm_f = { + .name = "F", + .ena = S3C64XX_NORMALCFG_DOMAIN_F_ON, + .pwr_stat = S3C64XX_BLKPWRSTAT_F, + .pd = { + .power_off = s3c64xx_pd_off, + .power_on = s3c64xx_pd_on, + }, +}; + +static struct s3c64xx_pm_domain s3c64xx_pm_p = { + .name = "P", + .ena = S3C64XX_NORMALCFG_DOMAIN_P_ON, + .pwr_stat = S3C64XX_BLKPWRSTAT_P, + .pd = { + .power_off = s3c64xx_pd_off, + .power_on = s3c64xx_pd_on, + }, +}; + +static struct s3c64xx_pm_domain s3c64xx_pm_i = { + .name = "I", + .ena = S3C64XX_NORMALCFG_DOMAIN_I_ON, + .pwr_stat = S3C64XX_BLKPWRSTAT_I, + .pd = { + .power_off = s3c64xx_pd_off, + .power_on = s3c64xx_pd_on, + }, +}; + +static struct s3c64xx_pm_domain s3c64xx_pm_g = { + .name = "G", + .ena = S3C64XX_NORMALCFG_DOMAIN_G_ON, + .pd = { + .power_off = s3c64xx_pd_off, + .power_on = s3c64xx_pd_on, + }, +}; + +static struct s3c64xx_pm_domain s3c64xx_pm_v = { + .name = "V", + .ena = S3C64XX_NORMALCFG_DOMAIN_V_ON, + .pwr_stat = S3C64XX_BLKPWRSTAT_V, + .pd = { + .power_off = s3c64xx_pd_off, + .power_on = s3c64xx_pd_on, + }, +}; + +static struct s3c64xx_pm_domain *s3c64xx_always_on_pm_domains[] = { + &s3c64xx_pm_irom, +}; + +static struct s3c64xx_pm_domain *s3c64xx_pm_domains[] = { + &s3c64xx_pm_etm, + &s3c64xx_pm_g, + &s3c64xx_pm_v, + &s3c64xx_pm_i, + &s3c64xx_pm_p, + &s3c64xx_pm_s, + &s3c64xx_pm_f, +}; + #ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK void s3c_pm_debug_smdkled(u32 set, u32 clear) { @@ -89,6 +233,8 @@ static struct sleep_save misc_save[] = { SAVE_ITEM(S3C64XX_SDMA_SEL), SAVE_ITEM(S3C64XX_MODEM_MIFPCON), + + SAVE_ITEM(S3C64XX_NORMAL_CFG), }; void s3c_pm_configure_extint(void) @@ -179,12 +325,44 @@ static void s3c64xx_pm_prepare(void) __raw_writel(__raw_readl(S3C64XX_WAKEUP_STAT), S3C64XX_WAKEUP_STAT); } -static int s3c64xx_pm_init(void) +int __init s3c64xx_pm_init(void) +{ + int i; + + s3c_pm_init(); + + for (i = 0; i < ARRAY_SIZE(s3c64xx_always_on_pm_domains); i++) + pm_genpd_init(&s3c64xx_always_on_pm_domains[i]->pd, + &pm_domain_always_on_gov, false); + + for (i = 0; i < ARRAY_SIZE(s3c64xx_pm_domains); i++) + pm_genpd_init(&s3c64xx_pm_domains[i]->pd, NULL, false); + + if (dev_get_platdata(&s3c_device_fb.dev)) + pm_genpd_add_device(&s3c64xx_pm_f.pd, &s3c_device_fb.dev); + + return 0; +} + +static __init int s3c64xx_pm_initcall(void) { + u32 val; + pm_cpu_prep = s3c64xx_pm_prepare; pm_cpu_sleep = s3c64xx_cpu_suspend; pm_uart_udivslot = 1; + /* + * Unconditionally disable power domains that contain only + * blocks which have no mainline driver support. + */ + val = __raw_readl(S3C64XX_NORMAL_CFG); + val &= ~(S3C64XX_NORMALCFG_DOMAIN_G_ON | + S3C64XX_NORMALCFG_DOMAIN_V_ON | + S3C64XX_NORMALCFG_DOMAIN_I_ON | + S3C64XX_NORMALCFG_DOMAIN_P_ON); + __raw_writel(val, S3C64XX_NORMAL_CFG); + #ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK gpio_request(S3C64XX_GPN(12), "DEBUG_LED0"); gpio_request(S3C64XX_GPN(13), "DEBUG_LED1"); @@ -198,5 +376,12 @@ static int s3c64xx_pm_init(void) return 0; } +arch_initcall(s3c64xx_pm_initcall); + +static __init int s3c64xx_pm_late_initcall(void) +{ + pm_genpd_poweroff_unused(); -arch_initcall(s3c64xx_pm_init); + return 0; +} +late_initcall(s3c64xx_pm_late_initcall); diff --git a/arch/arm/mach-s3c64xx/s3c6400.c b/arch/arm/mach-s3c64xx/s3c6400.c index b1e1571f2f6..4869714c6f1 100644 --- a/arch/arm/mach-s3c64xx/s3c6400.c +++ b/arch/arm/mach-s3c64xx/s3c6400.c @@ -17,7 +17,7 @@ #include <linux/init.h> #include <linux/clk.h> #include <linux/io.h> -#include <linux/sysdev.h> +#include <linux/device.h> #include <linux/serial_core.h> #include <linux/platform_device.h> @@ -71,17 +71,18 @@ void __init s3c6400_init_irq(void) s3c64xx_init_irq(~0 & ~(0xf << 5), ~0); } -static struct sysdev_class s3c6400_sysclass = { - .name = "s3c6400-core", +static struct bus_type s3c6400_subsys = { + .name = "s3c6400-core", + .dev_name = "s3c6400-core", }; -static struct sys_device s3c6400_sysdev = { - .cls = &s3c6400_sysclass, +static struct device s3c6400_dev = { + .bus = &s3c6400_subsys, }; static int __init s3c6400_core_init(void) { - return sysdev_class_register(&s3c6400_sysclass); + return subsys_system_register(&s3c6400_subsys, NULL); } core_initcall(s3c6400_core_init); @@ -90,5 +91,5 @@ int __init s3c6400_init(void) { printk("S3C6400: Initialising architecture\n"); - return sysdev_register(&s3c6400_sysdev); + return device_register(&s3c6400_dev); } diff --git a/arch/arm/mach-s3c64xx/s3c6410.c b/arch/arm/mach-s3c64xx/s3c6410.c index fba71bd991c..31c29fdf180 100644 --- a/arch/arm/mach-s3c64xx/s3c6410.c +++ b/arch/arm/mach-s3c64xx/s3c6410.c @@ -18,7 +18,7 @@ #include <linux/init.h> #include <linux/clk.h> #include <linux/io.h> -#include <linux/sysdev.h> +#include <linux/device.h> #include <linux/serial_core.h> #include <linux/platform_device.h> @@ -75,17 +75,18 @@ void __init s3c6410_init_irq(void) s3c64xx_init_irq(~0 & ~(1 << 7), ~0); } -struct sysdev_class s3c6410_sysclass = { - .name = "s3c6410-core", +struct bus_type s3c6410_subsys = { + .name = "s3c6410-core", + .dev_name = "s3c6410-core", }; -static struct sys_device s3c6410_sysdev = { - .cls = &s3c6410_sysclass, +static struct device s3c6410_dev = { + .bus = &s3c6410_subsys, }; static int __init s3c6410_core_init(void) { - return sysdev_class_register(&s3c6410_sysclass); + return subsys_system_register(&s3c6410_subsys, NULL); } core_initcall(s3c6410_core_init); @@ -94,5 +95,5 @@ int __init s3c6410_init(void) { printk("S3C6410: Initialising architecture\n"); - return sysdev_register(&s3c6410_sysdev); + return device_register(&s3c6410_dev); } diff --git a/arch/arm/mach-s3c64xx/setup-sdhci.c b/arch/arm/mach-s3c64xx/setup-sdhci.c deleted file mode 100644 index c75a71b2116..00000000000 --- a/arch/arm/mach-s3c64xx/setup-sdhci.c +++ /dev/null @@ -1,24 +0,0 @@ -/* linux/arch/arm/mach-s3c64xx/setup-sdhci.c - * - * Copyright 2008 Simtec Electronics - * Copyright 2008 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * S3C6400/S3C6410 - Helper functions for settign up SDHCI device(s) (HSMMC) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/types.h> - -/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */ - -char *s3c64xx_hsmmc_clksrcs[4] = { - [0] = "hsmmc", - [1] = "hsmmc", - [2] = "mmc_bus", - /* [3] = "48m", - note not successfully used yet */ -}; diff --git a/arch/arm/mach-s3c64xx/setup-spi.c b/arch/arm/mach-s3c64xx/setup-spi.c new file mode 100644 index 00000000000..d9592ad7a82 --- /dev/null +++ b/arch/arm/mach-s3c64xx/setup-spi.c @@ -0,0 +1,45 @@ +/* linux/arch/arm/mach-s3c64xx/setup-spi.c + * + * Copyright (C) 2011 Samsung Electronics Ltd. + * http://www.samsung.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/gpio.h> +#include <linux/platform_device.h> + +#include <plat/gpio-cfg.h> +#include <plat/s3c64xx-spi.h> + +#ifdef CONFIG_S3C64XX_DEV_SPI0 +struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = { + .fifo_lvl_mask = 0x7f, + .rx_lvl_offset = 13, + .tx_st_done = 21, +}; + +int s3c64xx_spi0_cfg_gpio(struct platform_device *dev) +{ + s3c_gpio_cfgall_range(S3C64XX_GPC(0), 3, + S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); + return 0; +} +#endif + +#ifdef CONFIG_S3C64XX_DEV_SPI1 +struct s3c64xx_spi_info s3c64xx_spi1_pdata __initdata = { + .fifo_lvl_mask = 0x7f, + .rx_lvl_offset = 13, + .tx_st_done = 21, +}; + +int s3c64xx_spi1_cfg_gpio(struct platform_device *dev) +{ + s3c_gpio_cfgall_range(S3C64XX_GPC(4), 3, + S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); + return 0; +} +#endif diff --git a/arch/arm/mach-s5p64x0/Kconfig b/arch/arm/mach-s5p64x0/Kconfig index 18690c5f99e..c87f6108eeb 100644 --- a/arch/arm/mach-s5p64x0/Kconfig +++ b/arch/arm/mach-s5p64x0/Kconfig @@ -36,6 +36,16 @@ config S5P64X0_SETUP_I2C1 help Common setup code for i2c bus 1. +config S5P64X0_SETUP_SPI + bool + help + Common setup code for SPI GPIO configurations + +config S5P64X0_SETUP_SDHCI_GPIO + bool + help + Common setup code for SDHCI gpio. + # machine support config MACH_SMDK6440 @@ -45,13 +55,16 @@ config MACH_SMDK6440 select S3C_DEV_I2C1 select S3C_DEV_RTC select S3C_DEV_WDT - select S3C64XX_DEV_SPI + select S3C_DEV_HSMMC + select S3C_DEV_HSMMC1 + select S3C_DEV_HSMMC2 select SAMSUNG_DEV_ADC select SAMSUNG_DEV_BACKLIGHT select SAMSUNG_DEV_PWM select SAMSUNG_DEV_TS select S5P64X0_SETUP_FB_24BPP select S5P64X0_SETUP_I2C1 + select S5P64X0_SETUP_SDHCI_GPIO help Machine support for the Samsung SMDK6440 @@ -62,14 +75,28 @@ config MACH_SMDK6450 select S3C_DEV_I2C1 select S3C_DEV_RTC select S3C_DEV_WDT - select S3C64XX_DEV_SPI + select S3C_DEV_HSMMC + select S3C_DEV_HSMMC1 + select S3C_DEV_HSMMC2 select SAMSUNG_DEV_ADC select SAMSUNG_DEV_BACKLIGHT select SAMSUNG_DEV_PWM select SAMSUNG_DEV_TS select S5P64X0_SETUP_FB_24BPP select S5P64X0_SETUP_I2C1 + select S5P64X0_SETUP_SDHCI_GPIO help Machine support for the Samsung SMDK6450 +menu "Use 8-bit SDHCI bus width" + +config S5P64X0_SD_CH1_8BIT + bool "SDHCI Channel 1 (Slot 1)" + depends on MACH_SMDK6450 || MACH_SMDK6440 + help + Support SDHCI Channel 1 8-bit bus. + If selected, Channel 2 is disabled. + +endmenu + endif diff --git a/arch/arm/mach-s5p64x0/Makefile b/arch/arm/mach-s5p64x0/Makefile index d3f7409999f..12bb951187a 100644 --- a/arch/arm/mach-s5p64x0/Makefile +++ b/arch/arm/mach-s5p64x0/Makefile @@ -28,8 +28,9 @@ obj-$(CONFIG_MACH_SMDK6450) += mach-smdk6450.o # device support obj-y += dev-audio.o -obj-$(CONFIG_S3C64XX_DEV_SPI) += dev-spi.o obj-y += setup-i2c0.o obj-$(CONFIG_S5P64X0_SETUP_I2C1) += setup-i2c1.o obj-$(CONFIG_S5P64X0_SETUP_FB_24BPP) += setup-fb-24bpp.o +obj-$(CONFIG_S5P64X0_SETUP_SPI) += setup-spi.o +obj-$(CONFIG_S5P64X0_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o diff --git a/arch/arm/mach-s5p64x0/clock-s5p6440.c b/arch/arm/mach-s5p64x0/clock-s5p6440.c index dd2b8daef0c..ee1e8e7f563 100644 --- a/arch/arm/mach-s5p64x0/clock-s5p6440.c +++ b/arch/arm/mach-s5p64x0/clock-s5p6440.c @@ -17,7 +17,7 @@ #include <linux/errno.h> #include <linux/err.h> #include <linux/clk.h> -#include <linux/sysdev.h> +#include <linux/device.h> #include <linux/io.h> #include <mach/hardware.h> @@ -269,18 +269,6 @@ static struct clk init_clocks_off[] = { .enable = s5p64x0_pclk_ctrl, .ctrlbit = (1 << 31), }, { - .name = "sclk_spi_48", - .devname = "s3c64xx-spi.0", - .parent = &clk_48m, - .enable = s5p64x0_sclk_ctrl, - .ctrlbit = (1 << 22), - }, { - .name = "sclk_spi_48", - .devname = "s3c64xx-spi.1", - .parent = &clk_48m, - .enable = s5p64x0_sclk_ctrl, - .ctrlbit = (1 << 23), - }, { .name = "mmc_48m", .devname = "s3c-sdhci.0", .parent = &clk_48m, @@ -392,65 +380,6 @@ static struct clksrc_sources clkset_audio = { static struct clksrc_clk clksrcs[] = { { .clk = { - .name = "sclk_mmc", - .devname = "s3c-sdhci.0", - .ctrlbit = (1 << 24), - .enable = s5p64x0_sclk_ctrl, - }, - .sources = &clkset_group1, - .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 }, - .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 }, - }, { - .clk = { - .name = "sclk_mmc", - .devname = "s3c-sdhci.1", - .ctrlbit = (1 << 25), - .enable = s5p64x0_sclk_ctrl, - }, - .sources = &clkset_group1, - .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 }, - .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 }, - }, { - .clk = { - .name = "sclk_mmc", - .devname = "s3c-sdhci.2", - .ctrlbit = (1 << 26), - .enable = s5p64x0_sclk_ctrl, - }, - .sources = &clkset_group1, - .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 }, - .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 }, - }, { - .clk = { - .name = "uclk1", - .ctrlbit = (1 << 5), - .enable = s5p64x0_sclk_ctrl, - }, - .sources = &clkset_uart, - .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 13, .size = 1 }, - .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 }, - }, { - .clk = { - .name = "sclk_spi", - .devname = "s3c64xx-spi.0", - .ctrlbit = (1 << 20), - .enable = s5p64x0_sclk_ctrl, - }, - .sources = &clkset_group1, - .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 }, - .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 }, - }, { - .clk = { - .name = "sclk_spi", - .devname = "s3c64xx-spi.1", - .ctrlbit = (1 << 21), - .enable = s5p64x0_sclk_ctrl, - }, - .sources = &clkset_group1, - .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 }, - .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 }, - }, { - .clk = { .name = "sclk_post", .ctrlbit = (1 << 10), .enable = s5p64x0_sclk_ctrl, @@ -488,6 +417,77 @@ static struct clksrc_clk clksrcs[] = { }, }; +static struct clksrc_clk clk_sclk_mmc0 = { + .clk = { + .name = "sclk_mmc", + .devname = "s3c-sdhci.0", + .ctrlbit = (1 << 24), + .enable = s5p64x0_sclk_ctrl, + }, + .sources = &clkset_group1, + .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 }, + .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 }, +}; + +static struct clksrc_clk clk_sclk_mmc1 = { + .clk = { + .name = "sclk_mmc", + .devname = "s3c-sdhci.1", + .ctrlbit = (1 << 25), + .enable = s5p64x0_sclk_ctrl, + }, + .sources = &clkset_group1, + .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 }, + .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 }, +}; + +static struct clksrc_clk clk_sclk_mmc2 = { + .clk = { + .name = "sclk_mmc", + .devname = "s3c-sdhci.2", + .ctrlbit = (1 << 26), + .enable = s5p64x0_sclk_ctrl, + }, + .sources = &clkset_group1, + .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 }, + .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 }, +}; + +static struct clksrc_clk clk_sclk_uclk = { + .clk = { + .name = "uclk1", + .ctrlbit = (1 << 5), + .enable = s5p64x0_sclk_ctrl, + }, + .sources = &clkset_uart, + .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 13, .size = 1 }, + .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 }, +}; + +static struct clksrc_clk clk_sclk_spi0 = { + .clk = { + .name = "sclk_spi", + .devname = "s3c64xx-spi.0", + .ctrlbit = (1 << 20), + .enable = s5p64x0_sclk_ctrl, + }, + .sources = &clkset_group1, + .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 }, + .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 }, +}; + +static struct clksrc_clk clk_sclk_spi1 = { + .clk = { + .name = "sclk_spi", + .devname = "s3c64xx-spi.1", + .ctrlbit = (1 << 21), + .enable = s5p64x0_sclk_ctrl, + }, + .sources = &clkset_group1, + .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 }, + .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 }, +}; + /* Clock initialization code */ static struct clksrc_clk *sysclks[] = { &clk_mout_apll, @@ -506,6 +506,26 @@ static struct clk dummy_apb_pclk = { .id = -1, }; +static struct clksrc_clk *clksrc_cdev[] = { + &clk_sclk_uclk, + &clk_sclk_spi0, + &clk_sclk_spi1, + &clk_sclk_mmc0, + &clk_sclk_mmc1, + &clk_sclk_mmc2 +}; + +static struct clk_lookup s5p6440_clk_lookup[] = { + CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_pclk_low.clk), + CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk), + CLKDEV_INIT(NULL, "spi_busclk0", &clk_p), + CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk), + CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk), + CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk), + CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk), + CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk), +}; + void __init_or_cpufreq s5p6440_setup_clocks(void) { struct clk *xtal_clk; @@ -584,9 +604,12 @@ void __init s5p6440_register_clocks(void) s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); + for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++) + s3c_register_clksrc(clksrc_cdev[ptr], 1); s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); + clkdev_add_table(s5p6440_clk_lookup, ARRAY_SIZE(s5p6440_clk_lookup)); s3c24xx_register_clock(&dummy_apb_pclk); diff --git a/arch/arm/mach-s5p64x0/clock-s5p6450.c b/arch/arm/mach-s5p64x0/clock-s5p6450.c index 328a224f007..dae6a13f43b 100644 --- a/arch/arm/mach-s5p64x0/clock-s5p6450.c +++ b/arch/arm/mach-s5p64x0/clock-s5p6450.c @@ -17,7 +17,7 @@ #include <linux/errno.h> #include <linux/err.h> #include <linux/clk.h> -#include <linux/sysdev.h> +#include <linux/device.h> #include <linux/io.h> #include <mach/hardware.h> @@ -414,65 +414,6 @@ static struct clksrc_clk clk_sclk_audio0 = { static struct clksrc_clk clksrcs[] = { { .clk = { - .name = "sclk_mmc", - .devname = "s3c-sdhci.0", - .ctrlbit = (1 << 24), - .enable = s5p64x0_sclk_ctrl, - }, - .sources = &clkset_group2, - .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 }, - .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 }, - }, { - .clk = { - .name = "sclk_mmc", - .devname = "s3c-sdhci.1", - .ctrlbit = (1 << 25), - .enable = s5p64x0_sclk_ctrl, - }, - .sources = &clkset_group2, - .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 }, - .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 }, - }, { - .clk = { - .name = "sclk_mmc", - .devname = "s3c-sdhci.2", - .ctrlbit = (1 << 26), - .enable = s5p64x0_sclk_ctrl, - }, - .sources = &clkset_group2, - .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 }, - .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 }, - }, { - .clk = { - .name = "uclk1", - .ctrlbit = (1 << 5), - .enable = s5p64x0_sclk_ctrl, - }, - .sources = &clkset_uart, - .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 13, .size = 1 }, - .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 }, - }, { - .clk = { - .name = "sclk_spi", - .devname = "s3c64xx-spi.0", - .ctrlbit = (1 << 20), - .enable = s5p64x0_sclk_ctrl, - }, - .sources = &clkset_group2, - .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 }, - .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 }, - }, { - .clk = { - .name = "sclk_spi", - .devname = "s3c64xx-spi.1", - .ctrlbit = (1 << 21), - .enable = s5p64x0_sclk_ctrl, - }, - .sources = &clkset_group2, - .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 }, - .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 }, - }, { - .clk = { .name = "sclk_fimc", .ctrlbit = (1 << 10), .enable = s5p64x0_sclk_ctrl, @@ -537,6 +478,97 @@ static struct clksrc_clk clksrcs[] = { }, }; +static struct clksrc_clk clk_sclk_mmc0 = { + .clk = { + .name = "sclk_mmc", + .devname = "s3c-sdhci.0", + .ctrlbit = (1 << 24), + .enable = s5p64x0_sclk_ctrl, + }, + .sources = &clkset_group2, + .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 }, + .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 }, +}; + +static struct clksrc_clk clk_sclk_mmc1 = { + .clk = { + .name = "sclk_mmc", + .devname = "s3c-sdhci.1", + .ctrlbit = (1 << 25), + .enable = s5p64x0_sclk_ctrl, + }, + .sources = &clkset_group2, + .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 }, + .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 }, +}; + +static struct clksrc_clk clk_sclk_mmc2 = { + .clk = { + .name = "sclk_mmc", + .devname = "s3c-sdhci.2", + .ctrlbit = (1 << 26), + .enable = s5p64x0_sclk_ctrl, + }, + .sources = &clkset_group2, + .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 }, + .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 }, +}; + +static struct clksrc_clk clk_sclk_uclk = { + .clk = { + .name = "uclk1", + .ctrlbit = (1 << 5), + .enable = s5p64x0_sclk_ctrl, + }, + .sources = &clkset_uart, + .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 13, .size = 1 }, + .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 }, +}; + +static struct clksrc_clk clk_sclk_spi0 = { + .clk = { + .name = "sclk_spi", + .devname = "s3c64xx-spi.0", + .ctrlbit = (1 << 20), + .enable = s5p64x0_sclk_ctrl, + }, + .sources = &clkset_group2, + .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 }, + .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 }, +}; + +static struct clksrc_clk clk_sclk_spi1 = { + .clk = { + .name = "sclk_spi", + .devname = "s3c64xx-spi.1", + .ctrlbit = (1 << 21), + .enable = s5p64x0_sclk_ctrl, + }, + .sources = &clkset_group2, + .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 }, + .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 }, +}; + +static struct clksrc_clk *clksrc_cdev[] = { + &clk_sclk_uclk, + &clk_sclk_spi0, + &clk_sclk_spi1, + &clk_sclk_mmc0, + &clk_sclk_mmc1, + &clk_sclk_mmc2, +}; + +static struct clk_lookup s5p6450_clk_lookup[] = { + CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_pclk_low.clk), + CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk), + CLKDEV_INIT(NULL, "spi_busclk0", &clk_p), + CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk), + CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk), + CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk), + CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk), + CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk), +}; + /* Clock initialization code */ static struct clksrc_clk *sysclks[] = { &clk_mout_apll, @@ -635,9 +667,12 @@ void __init s5p6450_register_clocks(void) s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); + for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++) + s3c_register_clksrc(clksrc_cdev[ptr], 1); s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); + clkdev_add_table(s5p6450_clk_lookup, ARRAY_SIZE(s5p6450_clk_lookup)); s3c24xx_register_clock(&dummy_apb_pclk); diff --git a/arch/arm/mach-s5p64x0/clock.c b/arch/arm/mach-s5p64x0/clock.c index b289b726a7d..241d0e645c8 100644 --- a/arch/arm/mach-s5p64x0/clock.c +++ b/arch/arm/mach-s5p64x0/clock.c @@ -17,7 +17,7 @@ #include <linux/errno.h> #include <linux/err.h> #include <linux/clk.h> -#include <linux/sysdev.h> +#include <linux/device.h> #include <linux/io.h> #include <mach/hardware.h> diff --git a/arch/arm/mach-s5p64x0/common.c b/arch/arm/mach-s5p64x0/common.c index b7555a0fb0f..52b89a37644 100644 --- a/arch/arm/mach-s5p64x0/common.c +++ b/arch/arm/mach-s5p64x0/common.c @@ -17,7 +17,7 @@ #include <linux/init.h> #include <linux/clk.h> #include <linux/io.h> -#include <linux/sysdev.h> +#include <linux/device.h> #include <linux/serial_core.h> #include <linux/platform_device.h> #include <linux/sched.h> @@ -40,6 +40,7 @@ #include <plat/clock.h> #include <plat/devs.h> #include <plat/pm.h> +#include <plat/sdhci.h> #include <plat/adc-core.h> #include <plat/fb-core.h> #include <plat/gpio-cfg.h> @@ -181,6 +182,10 @@ void __init s5p6440_map_io(void) s3c_adc_setname("s3c64xx-adc"); s3c_fb_setname("s5p64x0-fb"); + s5p64x0_default_sdhci0(); + s5p64x0_default_sdhci1(); + s5p6440_default_sdhci2(); + iotable_init(s5p6440_iodesc, ARRAY_SIZE(s5p6440_iodesc)); init_consistent_dma_size(SZ_8M); } @@ -191,6 +196,10 @@ void __init s5p6450_map_io(void) s3c_adc_setname("s3c64xx-adc"); s3c_fb_setname("s5p64x0-fb"); + s5p64x0_default_sdhci0(); + s5p64x0_default_sdhci1(); + s5p6450_default_sdhci2(); + iotable_init(s5p6450_iodesc, ARRAY_SIZE(s5p6450_iodesc)); init_consistent_dma_size(SZ_8M); } @@ -257,17 +266,18 @@ void __init s5p6450_init_irq(void) s5p_init_irq(vic, ARRAY_SIZE(vic)); } -struct sysdev_class s5p64x0_sysclass = { - .name = "s5p64x0-core", +struct bus_type s5p64x0_subsys = { + .name = "s5p64x0-core", + .dev_name = "s5p64x0-core", }; -static struct sys_device s5p64x0_sysdev = { - .cls = &s5p64x0_sysclass, +static struct device s5p64x0_dev = { + .bus = &s5p64x0_subsys, }; static int __init s5p64x0_core_init(void) { - return sysdev_class_register(&s5p64x0_sysclass); + return subsys_system_register(&s5p64x0_subsys, NULL); } core_initcall(s5p64x0_core_init); @@ -278,39 +288,10 @@ int __init s5p64x0_init(void) /* set idle function */ pm_idle = s5p64x0_idle; - return sysdev_register(&s5p64x0_sysdev); + return device_register(&s5p64x0_dev); } -static struct s3c24xx_uart_clksrc s5p64x0_serial_clocks[] = { - [0] = { - .name = "pclk_low", - .divisor = 1, - .min_baud = 0, - .max_baud = 0, - }, - [1] = { - .name = "uclk1", - .divisor = 1, - .min_baud = 0, - .max_baud = 0, - }, -}; - /* uart registration process */ - -void __init s5p64x0_common_init_uarts(struct s3c2410_uartcfg *cfg, int no) -{ - struct s3c2410_uartcfg *tcfg = cfg; - u32 ucnt; - - for (ucnt = 0; ucnt < no; ucnt++, tcfg++) { - if (!tcfg->clocks) { - tcfg->clocks = s5p64x0_serial_clocks; - tcfg->clocks_size = ARRAY_SIZE(s5p64x0_serial_clocks); - } - } -} - void __init s5p6440_init_uarts(struct s3c2410_uartcfg *cfg, int no) { int uart; @@ -320,13 +301,11 @@ void __init s5p6440_init_uarts(struct s3c2410_uartcfg *cfg, int no) s5p_uart_resources[uart].resources->end = S5P6440_PA_UART(uart) + S5P_SZ_UART; } - s5p64x0_common_init_uarts(cfg, no); s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no); } void __init s5p6450_init_uarts(struct s3c2410_uartcfg *cfg, int no) { - s5p64x0_common_init_uarts(cfg, no); s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no); } diff --git a/arch/arm/mach-s5p64x0/dev-spi.c b/arch/arm/mach-s5p64x0/dev-spi.c deleted file mode 100644 index 1fd9c79c7db..00000000000 --- a/arch/arm/mach-s5p64x0/dev-spi.c +++ /dev/null @@ -1,224 +0,0 @@ -/* linux/arch/arm/mach-s5p64x0/dev-spi.c - * - * Copyright (c) 2010 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Copyright (C) 2010 Samsung Electronics Co. Ltd. - * Jaswinder Singh <jassi.brar@samsung.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/platform_device.h> -#include <linux/dma-mapping.h> -#include <linux/gpio.h> - -#include <mach/dma.h> -#include <mach/map.h> -#include <mach/irqs.h> -#include <mach/regs-clock.h> -#include <mach/spi-clocks.h> - -#include <plat/cpu.h> -#include <plat/s3c64xx-spi.h> -#include <plat/gpio-cfg.h> - -static char *s5p64x0_spi_src_clks[] = { - [S5P64X0_SPI_SRCCLK_PCLK] = "pclk", - [S5P64X0_SPI_SRCCLK_SCLK] = "sclk_spi", -}; - -/* SPI Controller platform_devices */ - -/* Since we emulate multi-cs capability, we do not touch the CS. - * The emulated CS is toggled by board specific mechanism, as it can - * be either some immediate GPIO or some signal out of some other - * chip in between ... or some yet another way. - * We simply do not assume anything about CS. - */ -static int s5p6440_spi_cfg_gpio(struct platform_device *pdev) -{ - unsigned int base; - - switch (pdev->id) { - case 0: - base = S5P6440_GPC(0); - break; - - case 1: - base = S5P6440_GPC(4); - break; - - default: - dev_err(&pdev->dev, "Invalid SPI Controller number!"); - return -EINVAL; - } - - s3c_gpio_cfgall_range(base, 3, - S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); - - return 0; -} - -static int s5p6450_spi_cfg_gpio(struct platform_device *pdev) -{ - unsigned int base; - - switch (pdev->id) { - case 0: - base = S5P6450_GPC(0); - break; - - case 1: - base = S5P6450_GPC(4); - break; - - default: - dev_err(&pdev->dev, "Invalid SPI Controller number!"); - return -EINVAL; - } - - s3c_gpio_cfgall_range(base, 3, - S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); - - return 0; -} - -static struct resource s5p64x0_spi0_resource[] = { - [0] = { - .start = S5P64X0_PA_SPI0, - .end = S5P64X0_PA_SPI0 + 0x100 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = DMACH_SPI0_TX, - .end = DMACH_SPI0_TX, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = DMACH_SPI0_RX, - .end = DMACH_SPI0_RX, - .flags = IORESOURCE_DMA, - }, - [3] = { - .start = IRQ_SPI0, - .end = IRQ_SPI0, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct s3c64xx_spi_info s5p6440_spi0_pdata = { - .cfg_gpio = s5p6440_spi_cfg_gpio, - .fifo_lvl_mask = 0x1ff, - .rx_lvl_offset = 15, - .tx_st_done = 25, -}; - -static struct s3c64xx_spi_info s5p6450_spi0_pdata = { - .cfg_gpio = s5p6450_spi_cfg_gpio, - .fifo_lvl_mask = 0x1ff, - .rx_lvl_offset = 15, - .tx_st_done = 25, -}; - -static u64 spi_dmamask = DMA_BIT_MASK(32); - -struct platform_device s5p64x0_device_spi0 = { - .name = "s3c64xx-spi", - .id = 0, - .num_resources = ARRAY_SIZE(s5p64x0_spi0_resource), - .resource = s5p64x0_spi0_resource, - .dev = { - .dma_mask = &spi_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - -static struct resource s5p64x0_spi1_resource[] = { - [0] = { - .start = S5P64X0_PA_SPI1, - .end = S5P64X0_PA_SPI1 + 0x100 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = DMACH_SPI1_TX, - .end = DMACH_SPI1_TX, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = DMACH_SPI1_RX, - .end = DMACH_SPI1_RX, - .flags = IORESOURCE_DMA, - }, - [3] = { - .start = IRQ_SPI1, - .end = IRQ_SPI1, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct s3c64xx_spi_info s5p6440_spi1_pdata = { - .cfg_gpio = s5p6440_spi_cfg_gpio, - .fifo_lvl_mask = 0x7f, - .rx_lvl_offset = 15, - .tx_st_done = 25, -}; - -static struct s3c64xx_spi_info s5p6450_spi1_pdata = { - .cfg_gpio = s5p6450_spi_cfg_gpio, - .fifo_lvl_mask = 0x7f, - .rx_lvl_offset = 15, - .tx_st_done = 25, -}; - -struct platform_device s5p64x0_device_spi1 = { - .name = "s3c64xx-spi", - .id = 1, - .num_resources = ARRAY_SIZE(s5p64x0_spi1_resource), - .resource = s5p64x0_spi1_resource, - .dev = { - .dma_mask = &spi_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - -void __init s5p64x0_spi_set_info(int cntrlr, int src_clk_nr, int num_cs) -{ - struct s3c64xx_spi_info *pd; - - /* Reject invalid configuration */ - if (!num_cs || src_clk_nr < 0 - || src_clk_nr > S5P64X0_SPI_SRCCLK_SCLK) { - printk(KERN_ERR "%s: Invalid SPI configuration\n", __func__); - return; - } - - switch (cntrlr) { - case 0: - if (soc_is_s5p6450()) - pd = &s5p6450_spi0_pdata; - else - pd = &s5p6440_spi0_pdata; - - s5p64x0_device_spi0.dev.platform_data = pd; - break; - case 1: - if (soc_is_s5p6450()) - pd = &s5p6450_spi1_pdata; - else - pd = &s5p6440_spi1_pdata; - - s5p64x0_device_spi1.dev.platform_data = pd; - break; - default: - printk(KERN_ERR "%s: Invalid SPI controller(%d)\n", - __func__, cntrlr); - return; - } - - pd->num_cs = num_cs; - pd->src_clk_nr = src_clk_nr; - pd->src_clk_name = s5p64x0_spi_src_clks[src_clk_nr]; -} diff --git a/arch/arm/mach-s5p64x0/dma.c b/arch/arm/mach-s5p64x0/dma.c index 442dd4ad12d..f820c074440 100644 --- a/arch/arm/mach-s5p64x0/dma.c +++ b/arch/arm/mach-s5p64x0/dma.c @@ -38,176 +38,74 @@ static u64 dma_dmamask = DMA_BIT_MASK(32); -struct dma_pl330_peri s5p6440_pdma_peri[22] = { - { - .peri_id = (u8)DMACH_UART0_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_UART0_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_UART1_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_UART1_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_UART2_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_UART2_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_UART3_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_UART3_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = DMACH_MAX, - }, { - .peri_id = DMACH_MAX, - }, { - .peri_id = (u8)DMACH_PCM0_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_PCM0_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_I2S0_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_I2S0_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_SPI0_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_SPI0_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_MAX, - }, { - .peri_id = (u8)DMACH_MAX, - }, { - .peri_id = (u8)DMACH_MAX, - }, { - .peri_id = (u8)DMACH_MAX, - }, { - .peri_id = (u8)DMACH_SPI1_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_SPI1_RX, - .rqtype = DEVTOMEM, - }, +u8 s5p6440_pdma_peri[] = { + DMACH_UART0_RX, + DMACH_UART0_TX, + DMACH_UART1_RX, + DMACH_UART1_TX, + DMACH_UART2_RX, + DMACH_UART2_TX, + DMACH_UART3_RX, + DMACH_UART3_TX, + DMACH_MAX, + DMACH_MAX, + DMACH_PCM0_TX, + DMACH_PCM0_RX, + DMACH_I2S0_TX, + DMACH_I2S0_RX, + DMACH_SPI0_TX, + DMACH_SPI0_RX, + DMACH_MAX, + DMACH_MAX, + DMACH_MAX, + DMACH_MAX, + DMACH_SPI1_TX, + DMACH_SPI1_RX, }; struct dma_pl330_platdata s5p6440_pdma_pdata = { .nr_valid_peri = ARRAY_SIZE(s5p6440_pdma_peri), - .peri = s5p6440_pdma_peri, + .peri_id = s5p6440_pdma_peri, }; -struct dma_pl330_peri s5p6450_pdma_peri[32] = { - { - .peri_id = (u8)DMACH_UART0_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_UART0_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_UART1_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_UART1_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_UART2_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_UART2_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_UART3_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_UART3_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_UART4_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_UART4_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_PCM0_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_PCM0_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_I2S0_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_I2S0_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_SPI0_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_SPI0_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_PCM1_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_PCM1_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_PCM2_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_PCM2_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_SPI1_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_SPI1_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_USI_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_USI_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_MAX, - }, { - .peri_id = (u8)DMACH_I2S1_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_I2S1_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_I2S2_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_I2S2_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_PWM, - }, { - .peri_id = (u8)DMACH_UART5_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_UART5_TX, - .rqtype = MEMTODEV, - }, +u8 s5p6450_pdma_peri[] = { + DMACH_UART0_RX, + DMACH_UART0_TX, + DMACH_UART1_RX, + DMACH_UART1_TX, + DMACH_UART2_RX, + DMACH_UART2_TX, + DMACH_UART3_RX, + DMACH_UART3_TX, + DMACH_UART4_RX, + DMACH_UART4_TX, + DMACH_PCM0_TX, + DMACH_PCM0_RX, + DMACH_I2S0_TX, + DMACH_I2S0_RX, + DMACH_SPI0_TX, + DMACH_SPI0_RX, + DMACH_PCM1_TX, + DMACH_PCM1_RX, + DMACH_PCM2_TX, + DMACH_PCM2_RX, + DMACH_SPI1_TX, + DMACH_SPI1_RX, + DMACH_USI_TX, + DMACH_USI_RX, + DMACH_MAX, + DMACH_I2S1_TX, + DMACH_I2S1_RX, + DMACH_I2S2_TX, + DMACH_I2S2_RX, + DMACH_PWM, + DMACH_UART5_RX, + DMACH_UART5_TX, }; struct dma_pl330_platdata s5p6450_pdma_pdata = { .nr_valid_peri = ARRAY_SIZE(s5p6450_pdma_peri), - .peri = s5p6450_pdma_peri, + .peri_id = s5p6450_pdma_peri, }; struct amba_device s5p64x0_device_pdma = { @@ -227,10 +125,15 @@ struct amba_device s5p64x0_device_pdma = { static int __init s5p64x0_dma_init(void) { - if (soc_is_s5p6450()) + if (soc_is_s5p6450()) { + dma_cap_set(DMA_SLAVE, s5p6450_pdma_pdata.cap_mask); + dma_cap_set(DMA_CYCLIC, s5p6450_pdma_pdata.cap_mask); s5p64x0_device_pdma.dev.platform_data = &s5p6450_pdma_pdata; - else + } else { + dma_cap_set(DMA_SLAVE, s5p6440_pdma_pdata.cap_mask); + dma_cap_set(DMA_CYCLIC, s5p6440_pdma_pdata.cap_mask); s5p64x0_device_pdma.dev.platform_data = &s5p6440_pdma_pdata; + } amba_device_register(&s5p64x0_device_pdma, &iomem_resource); diff --git a/arch/arm/mach-s5p64x0/include/mach/irqs.h b/arch/arm/mach-s5p64x0/include/mach/irqs.h index 53982db9d25..5b845e849b3 100644 --- a/arch/arm/mach-s5p64x0/include/mach/irqs.h +++ b/arch/arm/mach-s5p64x0/include/mach/irqs.h @@ -141,6 +141,8 @@ #define IRQ_EINT_GROUP(grp, x) (IRQ_EINT_GROUP##grp##_BASE + (x)) +#define IRQ_TIMER_BASE (11) + /* Set the default NR_IRQS */ #define NR_IRQS (IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR + 1) diff --git a/arch/arm/mach-s5p64x0/include/mach/map.h b/arch/arm/mach-s5p64x0/include/mach/map.h index 4d3ac8a3709..0c0175dbfa3 100644 --- a/arch/arm/mach-s5p64x0/include/mach/map.h +++ b/arch/arm/mach-s5p64x0/include/mach/map.h @@ -67,6 +67,8 @@ #define S3C_PA_RTC S5P64X0_PA_RTC #define S3C_PA_WDT S5P64X0_PA_WDT #define S3C_PA_FB S5P64X0_PA_FB +#define S3C_PA_SPI0 S5P64X0_PA_SPI0 +#define S3C_PA_SPI1 S5P64X0_PA_SPI1 #define S5P_PA_CHIPID S5P64X0_PA_CHIPID #define S5P_PA_SROMC S5P64X0_PA_SROMC diff --git a/arch/arm/mach-s5p64x0/mach-smdk6440.c b/arch/arm/mach-s5p64x0/mach-smdk6440.c index 34d98a1dae5..a40e325d62c 100644 --- a/arch/arm/mach-s5p64x0/mach-smdk6440.c +++ b/arch/arm/mach-s5p64x0/mach-smdk6440.c @@ -24,6 +24,7 @@ #include <linux/gpio.h> #include <linux/pwm_backlight.h> #include <linux/fb.h> +#include <linux/mmc/host.h> #include <video/platform_lcd.h> @@ -52,6 +53,7 @@ #include <plat/backlight.h> #include <plat/fb.h> #include <plat/regs-fb.h> +#include <plat/sdhci.h> #include "common.h" @@ -163,6 +165,25 @@ static struct platform_device *smdk6440_devices[] __initdata = { &s5p6440_device_iis, &s3c_device_fb, &smdk6440_lcd_lte480wv, + &s3c_device_hsmmc0, + &s3c_device_hsmmc1, + &s3c_device_hsmmc2, +}; + +static struct s3c_sdhci_platdata smdk6440_hsmmc0_pdata __initdata = { + .cd_type = S3C_SDHCI_CD_NONE, +}; + +static struct s3c_sdhci_platdata smdk6440_hsmmc1_pdata __initdata = { + .cd_type = S3C_SDHCI_CD_INTERNAL, +#if defined(CONFIG_S5P64X0_SD_CH1_8BIT) + .max_width = 8, + .host_caps = MMC_CAP_8_BIT_DATA, +#endif +}; + +static struct s3c_sdhci_platdata smdk6440_hsmmc2_pdata __initdata = { + .cd_type = S3C_SDHCI_CD_NONE, }; static struct s3c2410_platform_i2c s5p6440_i2c0_data __initdata = { @@ -236,6 +257,10 @@ static void __init smdk6440_machine_init(void) s5p6440_set_lcd_interface(); s3c_fb_set_platdata(&smdk6440_lcd_pdata); + s3c_sdhci0_set_platdata(&smdk6440_hsmmc0_pdata); + s3c_sdhci1_set_platdata(&smdk6440_hsmmc1_pdata); + s3c_sdhci2_set_platdata(&smdk6440_hsmmc2_pdata); + platform_add_devices(smdk6440_devices, ARRAY_SIZE(smdk6440_devices)); } diff --git a/arch/arm/mach-s5p64x0/mach-smdk6450.c b/arch/arm/mach-s5p64x0/mach-smdk6450.c index 135cf5d8473..efb69e2f2af 100644 --- a/arch/arm/mach-s5p64x0/mach-smdk6450.c +++ b/arch/arm/mach-s5p64x0/mach-smdk6450.c @@ -24,6 +24,7 @@ #include <linux/gpio.h> #include <linux/pwm_backlight.h> #include <linux/fb.h> +#include <linux/mmc/host.h> #include <video/platform_lcd.h> @@ -52,6 +53,7 @@ #include <plat/backlight.h> #include <plat/fb.h> #include <plat/regs-fb.h> +#include <plat/sdhci.h> #include "common.h" @@ -181,10 +183,28 @@ static struct platform_device *smdk6450_devices[] __initdata = { &s5p6450_device_iis0, &s3c_device_fb, &smdk6450_lcd_lte480wv, - + &s3c_device_hsmmc0, + &s3c_device_hsmmc1, + &s3c_device_hsmmc2, /* s5p6450_device_spi0 will be added */ }; +static struct s3c_sdhci_platdata smdk6450_hsmmc0_pdata __initdata = { + .cd_type = S3C_SDHCI_CD_NONE, +}; + +static struct s3c_sdhci_platdata smdk6450_hsmmc1_pdata __initdata = { + .cd_type = S3C_SDHCI_CD_NONE, +#if defined(CONFIG_S5P64X0_SD_CH1_8BIT) + .max_width = 8, + .host_caps = MMC_CAP_8_BIT_DATA, +#endif +}; + +static struct s3c_sdhci_platdata smdk6450_hsmmc2_pdata __initdata = { + .cd_type = S3C_SDHCI_CD_NONE, +}; + static struct s3c2410_platform_i2c s5p6450_i2c0_data __initdata = { .flags = 0, .slave_addr = 0x10, @@ -256,6 +276,10 @@ static void __init smdk6450_machine_init(void) s5p6450_set_lcd_interface(); s3c_fb_set_platdata(&smdk6450_lcd_pdata); + s3c_sdhci0_set_platdata(&smdk6450_hsmmc0_pdata); + s3c_sdhci1_set_platdata(&smdk6450_hsmmc1_pdata); + s3c_sdhci2_set_platdata(&smdk6450_hsmmc2_pdata); + platform_add_devices(smdk6450_devices, ARRAY_SIZE(smdk6450_devices)); } diff --git a/arch/arm/mach-s5p64x0/pm.c b/arch/arm/mach-s5p64x0/pm.c index 69927243d25..23f9b22439c 100644 --- a/arch/arm/mach-s5p64x0/pm.c +++ b/arch/arm/mach-s5p64x0/pm.c @@ -160,7 +160,7 @@ static void s5p64x0_pm_prepare(void) } -static int s5p64x0_pm_add(struct sys_device *sysdev) +static int s5p64x0_pm_add(struct device *dev) { pm_cpu_prep = s5p64x0_pm_prepare; pm_cpu_sleep = s5p64x0_cpu_suspend; @@ -169,15 +169,17 @@ static int s5p64x0_pm_add(struct sys_device *sysdev) return 0; } -static struct sysdev_driver s5p64x0_pm_driver = { - .add = s5p64x0_pm_add, +static struct subsys_interface s5p64x0_pm_interface = { + .name = "s5p64x0_pm", + .subsys = &s5p64x0_subsys, + .add_dev = s5p64x0_pm_add, }; static __init int s5p64x0_pm_drvinit(void) { s3c_pm_init(); - return sysdev_driver_register(&s5p64x0_sysclass, &s5p64x0_pm_driver); + return subsys_interface_register(&s5p64x0_pm_interface); } arch_initcall(s5p64x0_pm_drvinit); diff --git a/arch/arm/mach-s5p64x0/setup-sdhci-gpio.c b/arch/arm/mach-s5p64x0/setup-sdhci-gpio.c new file mode 100644 index 00000000000..8410af0d12b --- /dev/null +++ b/arch/arm/mach-s5p64x0/setup-sdhci-gpio.c @@ -0,0 +1,104 @@ +/* linux/arch/arm/mach-s5p64x0/setup-sdhci-gpio.c + * + * Copyright (c) 2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5P64X0 - Helper functions for setting up SDHCI device(s) GPIO (HSMMC) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/platform_device.h> +#include <linux/io.h> +#include <linux/gpio.h> + +#include <mach/regs-gpio.h> +#include <mach/regs-clock.h> + +#include <plat/gpio-cfg.h> +#include <plat/sdhci.h> +#include <plat/cpu.h> + +void s5p64x0_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width) +{ + struct s3c_sdhci_platdata *pdata = dev->dev.platform_data; + + /* Set all the necessary GPG pins to special-function 2 */ + if (soc_is_s5p6450()) + s3c_gpio_cfgrange_nopull(S5P6450_GPG(0), 2 + width, + S3C_GPIO_SFN(2)); + else + s3c_gpio_cfgrange_nopull(S5P6440_GPG(0), 2 + width, + S3C_GPIO_SFN(2)); + + /* Set GPG[6] pin to special-function 2 - MMC0 CDn */ + if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) { + if (soc_is_s5p6450()) { + s3c_gpio_setpull(S5P6450_GPG(6), S3C_GPIO_PULL_UP); + s3c_gpio_cfgpin(S5P6450_GPG(6), S3C_GPIO_SFN(2)); + } else { + s3c_gpio_setpull(S5P6440_GPG(6), S3C_GPIO_PULL_UP); + s3c_gpio_cfgpin(S5P6440_GPG(6), S3C_GPIO_SFN(2)); + } + } +} + +void s5p64x0_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width) +{ + struct s3c_sdhci_platdata *pdata = dev->dev.platform_data; + + /* Set GPH[0:1] pins to special-function 2 - CLK and CMD */ + if (soc_is_s5p6450()) + s3c_gpio_cfgrange_nopull(S5P6450_GPH(0), 2, S3C_GPIO_SFN(2)); + else + s3c_gpio_cfgrange_nopull(S5P6440_GPH(0), 2 , S3C_GPIO_SFN(2)); + + switch (width) { + case 8: + /* Set data pins GPH[6:9] special-function 2 */ + if (soc_is_s5p6450()) + s3c_gpio_cfgrange_nopull(S5P6450_GPH(6), 4, + S3C_GPIO_SFN(2)); + else + s3c_gpio_cfgrange_nopull(S5P6440_GPH(6), 4, + S3C_GPIO_SFN(2)); + case 4: + /* set data pins GPH[2:5] special-function 2 */ + if (soc_is_s5p6450()) + s3c_gpio_cfgrange_nopull(S5P6450_GPH(2), 4, + S3C_GPIO_SFN(2)); + else + s3c_gpio_cfgrange_nopull(S5P6440_GPH(2), 4, + S3C_GPIO_SFN(2)); + default: + break; + } + + /* Set GPG[6] pin to special-funtion 3 : MMC1 CDn */ + if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) { + if (soc_is_s5p6450()) { + s3c_gpio_setpull(S5P6450_GPG(6), S3C_GPIO_PULL_UP); + s3c_gpio_cfgpin(S5P6450_GPG(6), S3C_GPIO_SFN(3)); + } else { + s3c_gpio_setpull(S5P6440_GPG(6), S3C_GPIO_PULL_UP); + s3c_gpio_cfgpin(S5P6440_GPG(6), S3C_GPIO_SFN(3)); + } + } +} + +void s5p6440_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width) +{ + /* Set GPC[4:5] pins to special-function 3 - CLK and CMD */ + s3c_gpio_cfgrange_nopull(S5P6440_GPC(4), 2, S3C_GPIO_SFN(3)); + + /* Set data pins GPH[6:9] pins to special-function 3 */ + s3c_gpio_cfgrange_nopull(S5P6440_GPH(6), 4, S3C_GPIO_SFN(3)); +} + +void s5p6450_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width) +{ + /* Set all the necessary GPG pins to special-function 3 */ + s3c_gpio_cfgrange_nopull(S5P6450_GPG(7), 2 + width, S3C_GPIO_SFN(3)); +} diff --git a/arch/arm/mach-s5p64x0/setup-spi.c b/arch/arm/mach-s5p64x0/setup-spi.c new file mode 100644 index 00000000000..e9b84124035 --- /dev/null +++ b/arch/arm/mach-s5p64x0/setup-spi.c @@ -0,0 +1,55 @@ +/* linux/arch/arm/mach-s5p64x0/setup-spi.c + * + * Copyright (C) 2011 Samsung Electronics Ltd. + * http://www.samsung.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/gpio.h> +#include <linux/platform_device.h> +#include <linux/io.h> + +#include <plat/gpio-cfg.h> +#include <plat/cpu.h> +#include <plat/s3c64xx-spi.h> + +#ifdef CONFIG_S3C64XX_DEV_SPI0 +struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = { + .fifo_lvl_mask = 0x1ff, + .rx_lvl_offset = 15, + .tx_st_done = 25, +}; + +int s3c64xx_spi0_cfg_gpio(struct platform_device *dev) +{ + if (soc_is_s5p6450()) + s3c_gpio_cfgall_range(S5P6450_GPC(0), 3, + S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); + else + s3c_gpio_cfgall_range(S5P6440_GPC(0), 3, + S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); + return 0; +} +#endif + +#ifdef CONFIG_S3C64XX_DEV_SPI1 +struct s3c64xx_spi_info s3c64xx_spi1_pdata __initdata = { + .fifo_lvl_mask = 0x7f, + .rx_lvl_offset = 15, + .tx_st_done = 25, +}; + +int s3c64xx_spi1_cfg_gpio(struct platform_device *dev) +{ + if (soc_is_s5p6450()) + s3c_gpio_cfgall_range(S5P6450_GPC(4), 3, + S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); + else + s3c_gpio_cfgall_range(S5P6440_GPC(4), 3, + S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); + return 0; +} +#endif diff --git a/arch/arm/mach-s5pc100/Kconfig b/arch/arm/mach-s5pc100/Kconfig index e538a4c67e9..75a26eaf263 100644 --- a/arch/arm/mach-s5pc100/Kconfig +++ b/arch/arm/mach-s5pc100/Kconfig @@ -45,6 +45,11 @@ config S5PC100_SETUP_SDHCI_GPIO help Common setup code for SDHCI gpio. +config S5PC100_SETUP_SPI + bool + help + Common setup code for SPI GPIO configurations. + config MACH_SMDKC100 bool "SMDKC100" select CPU_S5PC100 diff --git a/arch/arm/mach-s5pc100/Makefile b/arch/arm/mach-s5pc100/Makefile index c3166c4d2ac..118c711f74e 100644 --- a/arch/arm/mach-s5pc100/Makefile +++ b/arch/arm/mach-s5pc100/Makefile @@ -22,12 +22,11 @@ obj-$(CONFIG_MACH_SMDKC100) += mach-smdkc100.o # device support obj-y += dev-audio.o -obj-$(CONFIG_S3C64XX_DEV_SPI) += dev-spi.o obj-y += setup-i2c0.o obj-$(CONFIG_S5PC100_SETUP_FB_24BPP) += setup-fb-24bpp.o obj-$(CONFIG_S5PC100_SETUP_I2C1) += setup-i2c1.o obj-$(CONFIG_S5PC100_SETUP_IDE) += setup-ide.o obj-$(CONFIG_S5PC100_SETUP_KEYPAD) += setup-keypad.o -obj-$(CONFIG_S5PC100_SETUP_SDHCI) += setup-sdhci.o obj-$(CONFIG_S5PC100_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o +obj-$(CONFIG_S5PC100_SETUP_SPI) += setup-spi.o diff --git a/arch/arm/mach-s5pc100/clock.c b/arch/arm/mach-s5pc100/clock.c index c4c74893f53..247194dd366 100644 --- a/arch/arm/mach-s5pc100/clock.c +++ b/arch/arm/mach-s5pc100/clock.c @@ -427,24 +427,6 @@ static struct clk init_clocks_off[] = { .enable = s5pc100_d0_2_ctrl, .ctrlbit = (1 << 1), }, { - .name = "hsmmc", - .devname = "s3c-sdhci.2", - .parent = &clk_div_d1_bus.clk, - .enable = s5pc100_d1_0_ctrl, - .ctrlbit = (1 << 7), - }, { - .name = "hsmmc", - .devname = "s3c-sdhci.1", - .parent = &clk_div_d1_bus.clk, - .enable = s5pc100_d1_0_ctrl, - .ctrlbit = (1 << 6), - }, { - .name = "hsmmc", - .devname = "s3c-sdhci.0", - .parent = &clk_div_d1_bus.clk, - .enable = s5pc100_d1_0_ctrl, - .ctrlbit = (1 << 5), - }, { .name = "modemif", .parent = &clk_div_d1_bus.clk, .enable = s5pc100_d1_0_ctrl, @@ -674,24 +656,6 @@ static struct clk init_clocks_off[] = { .enable = s5pc100_d1_5_ctrl, .ctrlbit = (1 << 8), }, { - .name = "spi_48m", - .devname = "s3c64xx-spi.0", - .parent = &clk_mout_48m.clk, - .enable = s5pc100_sclk0_ctrl, - .ctrlbit = (1 << 7), - }, { - .name = "spi_48m", - .devname = "s3c64xx-spi.1", - .parent = &clk_mout_48m.clk, - .enable = s5pc100_sclk0_ctrl, - .ctrlbit = (1 << 8), - }, { - .name = "spi_48m", - .devname = "s3c64xx-spi.2", - .parent = &clk_mout_48m.clk, - .enable = s5pc100_sclk0_ctrl, - .ctrlbit = (1 << 9), - }, { .name = "mmc_48m", .devname = "s3c-sdhci.0", .parent = &clk_mout_48m.clk, @@ -712,6 +676,54 @@ static struct clk init_clocks_off[] = { }, }; +static struct clk clk_hsmmc2 = { + .name = "hsmmc", + .devname = "s3c-sdhci.2", + .parent = &clk_div_d1_bus.clk, + .enable = s5pc100_d1_0_ctrl, + .ctrlbit = (1 << 7), +}; + +static struct clk clk_hsmmc1 = { + .name = "hsmmc", + .devname = "s3c-sdhci.1", + .parent = &clk_div_d1_bus.clk, + .enable = s5pc100_d1_0_ctrl, + .ctrlbit = (1 << 6), +}; + +static struct clk clk_hsmmc0 = { + .name = "hsmmc", + .devname = "s3c-sdhci.0", + .parent = &clk_div_d1_bus.clk, + .enable = s5pc100_d1_0_ctrl, + .ctrlbit = (1 << 5), +}; + +static struct clk clk_48m_spi0 = { + .name = "spi_48m", + .devname = "s3c64xx-spi.0", + .parent = &clk_mout_48m.clk, + .enable = s5pc100_sclk0_ctrl, + .ctrlbit = (1 << 7), +}; + +static struct clk clk_48m_spi1 = { + .name = "spi_48m", + .devname = "s3c64xx-spi.1", + .parent = &clk_mout_48m.clk, + .enable = s5pc100_sclk0_ctrl, + .ctrlbit = (1 << 8), +}; + +static struct clk clk_48m_spi2 = { + .name = "spi_48m", + .devname = "s3c64xx-spi.2", + .parent = &clk_mout_48m.clk, + .enable = s5pc100_sclk0_ctrl, + .ctrlbit = (1 << 9), +}; + static struct clk clk_vclk54m = { .name = "vclk_54m", .rate = 54000000, @@ -930,49 +942,6 @@ static struct clksrc_clk clk_sclk_spdif = { static struct clksrc_clk clksrcs[] = { { .clk = { - .name = "sclk_spi", - .devname = "s3c64xx-spi.0", - .ctrlbit = (1 << 4), - .enable = s5pc100_sclk0_ctrl, - - }, - .sources = &clk_src_group1, - .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 2 }, - .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 }, - }, { - .clk = { - .name = "sclk_spi", - .devname = "s3c64xx-spi.1", - .ctrlbit = (1 << 5), - .enable = s5pc100_sclk0_ctrl, - - }, - .sources = &clk_src_group1, - .reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 2 }, - .reg_div = { .reg = S5P_CLK_DIV2, .shift = 8, .size = 4 }, - }, { - .clk = { - .name = "sclk_spi", - .devname = "s3c64xx-spi.2", - .ctrlbit = (1 << 6), - .enable = s5pc100_sclk0_ctrl, - - }, - .sources = &clk_src_group1, - .reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 2 }, - .reg_div = { .reg = S5P_CLK_DIV2, .shift = 12, .size = 4 }, - }, { - .clk = { - .name = "uclk1", - .ctrlbit = (1 << 3), - .enable = s5pc100_sclk0_ctrl, - - }, - .sources = &clk_src_group2, - .reg_src = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 1 }, - .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 }, - }, { - .clk = { .name = "sclk_mixer", .ctrlbit = (1 << 6), .enable = s5pc100_sclk0_ctrl, @@ -1025,39 +994,6 @@ static struct clksrc_clk clksrcs[] = { .reg_div = { .reg = S5P_CLK_DIV3, .shift = 24, .size = 4 }, }, { .clk = { - .name = "sclk_mmc", - .devname = "s3c-sdhci.0", - .ctrlbit = (1 << 12), - .enable = s5pc100_sclk1_ctrl, - - }, - .sources = &clk_src_mmc0, - .reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 }, - .reg_div = { .reg = S5P_CLK_DIV3, .shift = 0, .size = 4 }, - }, { - .clk = { - .name = "sclk_mmc", - .devname = "s3c-sdhci.1", - .ctrlbit = (1 << 13), - .enable = s5pc100_sclk1_ctrl, - - }, - .sources = &clk_src_mmc12, - .reg_src = { .reg = S5P_CLK_SRC2, .shift = 4, .size = 2 }, - .reg_div = { .reg = S5P_CLK_DIV3, .shift = 4, .size = 4 }, - }, { - .clk = { - .name = "sclk_mmc", - .devname = "s3c-sdhci.2", - .ctrlbit = (1 << 14), - .enable = s5pc100_sclk1_ctrl, - - }, - .sources = &clk_src_mmc12, - .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 }, - .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 }, - }, { - .clk = { .name = "sclk_irda", .ctrlbit = (1 << 10), .enable = s5pc100_sclk0_ctrl, @@ -1099,6 +1035,89 @@ static struct clksrc_clk clksrcs[] = { }, }; +static struct clksrc_clk clk_sclk_uart = { + .clk = { + .name = "uclk1", + .ctrlbit = (1 << 3), + .enable = s5pc100_sclk0_ctrl, + }, + .sources = &clk_src_group2, + .reg_src = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 1 }, + .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 }, +}; + +static struct clksrc_clk clk_sclk_mmc0 = { + .clk = { + .name = "sclk_mmc", + .devname = "s3c-sdhci.0", + .ctrlbit = (1 << 12), + .enable = s5pc100_sclk1_ctrl, + }, + .sources = &clk_src_mmc0, + .reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 }, + .reg_div = { .reg = S5P_CLK_DIV3, .shift = 0, .size = 4 }, +}; + +static struct clksrc_clk clk_sclk_mmc1 = { + .clk = { + .name = "sclk_mmc", + .devname = "s3c-sdhci.1", + .ctrlbit = (1 << 13), + .enable = s5pc100_sclk1_ctrl, + }, + .sources = &clk_src_mmc12, + .reg_src = { .reg = S5P_CLK_SRC2, .shift = 4, .size = 2 }, + .reg_div = { .reg = S5P_CLK_DIV3, .shift = 4, .size = 4 }, +}; + +static struct clksrc_clk clk_sclk_mmc2 = { + .clk = { + .name = "sclk_mmc", + .devname = "s3c-sdhci.2", + .ctrlbit = (1 << 14), + .enable = s5pc100_sclk1_ctrl, + }, + .sources = &clk_src_mmc12, + .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 }, + .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 }, +}; + +static struct clksrc_clk clk_sclk_spi0 = { + .clk = { + .name = "sclk_spi", + .devname = "s3c64xx-spi.0", + .ctrlbit = (1 << 4), + .enable = s5pc100_sclk0_ctrl, + }, + .sources = &clk_src_group1, + .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 2 }, + .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 }, +}; + +static struct clksrc_clk clk_sclk_spi1 = { + .clk = { + .name = "sclk_spi", + .devname = "s3c64xx-spi.1", + .ctrlbit = (1 << 5), + .enable = s5pc100_sclk0_ctrl, + }, + .sources = &clk_src_group1, + .reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 2 }, + .reg_div = { .reg = S5P_CLK_DIV2, .shift = 8, .size = 4 }, +}; + +static struct clksrc_clk clk_sclk_spi2 = { + .clk = { + .name = "sclk_spi", + .devname = "s3c64xx-spi.2", + .ctrlbit = (1 << 6), + .enable = s5pc100_sclk0_ctrl, + }, + .sources = &clk_src_group1, + .reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 2 }, + .reg_div = { .reg = S5P_CLK_DIV2, .shift = 12, .size = 4 }, +}; + /* Clock initialisation code */ static struct clksrc_clk *sysclks[] = { &clk_mout_apll, @@ -1128,6 +1147,25 @@ static struct clksrc_clk *sysclks[] = { &clk_sclk_spdif, }; +static struct clk *clk_cdev[] = { + &clk_hsmmc0, + &clk_hsmmc1, + &clk_hsmmc2, + &clk_48m_spi0, + &clk_48m_spi1, + &clk_48m_spi2, +}; + +static struct clksrc_clk *clksrc_cdev[] = { + &clk_sclk_uart, + &clk_sclk_mmc0, + &clk_sclk_mmc1, + &clk_sclk_mmc2, + &clk_sclk_spi0, + &clk_sclk_spi1, + &clk_sclk_spi2, +}; + void __init_or_cpufreq s5pc100_setup_clocks(void) { unsigned long xtal; @@ -1267,6 +1305,24 @@ static struct clk *clks[] __initdata = { &clk_pcmcdclk1, }; +static struct clk_lookup s5pc100_clk_lookup[] = { + CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p), + CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uart.clk), + CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &clk_hsmmc0), + CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &clk_hsmmc1), + CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.0", &clk_hsmmc2), + CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk), + CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk), + CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk), + CLKDEV_INIT(NULL, "spi_busclk0", &clk_p), + CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_48m_spi0), + CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &clk_sclk_spi0.clk), + CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_48m_spi1), + CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk2", &clk_sclk_spi1.clk), + CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk1", &clk_48m_spi2), + CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk2", &clk_sclk_spi2.clk), +}; + void __init s5pc100_register_clocks(void) { int ptr; @@ -1278,9 +1334,16 @@ void __init s5pc100_register_clocks(void) s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); + for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++) + s3c_register_clksrc(clksrc_cdev[ptr], 1); s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); + clkdev_add_table(s5pc100_clk_lookup, ARRAY_SIZE(s5pc100_clk_lookup)); + + s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev)); + for (ptr = 0; ptr < ARRAY_SIZE(clk_cdev); ptr++) + s3c_disable_clocks(clk_cdev[ptr], 1); s3c24xx_register_clock(&dummy_apb_pclk); diff --git a/arch/arm/mach-s5pc100/common.c b/arch/arm/mach-s5pc100/common.c index 73594a2fcf2..c9095730a7f 100644 --- a/arch/arm/mach-s5pc100/common.c +++ b/arch/arm/mach-s5pc100/common.c @@ -20,7 +20,7 @@ #include <linux/init.h> #include <linux/clk.h> #include <linux/io.h> -#include <linux/sysdev.h> +#include <linux/device.h> #include <linux/serial_core.h> #include <linux/platform_device.h> #include <linux/sched.h> @@ -192,17 +192,18 @@ void __init s5pc100_init_irq(void) s5p_init_irq(vic, ARRAY_SIZE(vic)); } -static struct sysdev_class s5pc100_sysclass = { - .name = "s5pc100-core", +static struct bus_type s5pc100_subsys = { + .name = "s5pc100-core", + .dev_name = "s5pc100-core", }; -static struct sys_device s5pc100_sysdev = { - .cls = &s5pc100_sysclass, +static struct device s5pc100_dev = { + .bus = &s5pc100_subsys, }; static int __init s5pc100_core_init(void) { - return sysdev_class_register(&s5pc100_sysclass); + return subsys_system_register(&s5pc100_subsys, NULL); } core_initcall(s5pc100_core_init); @@ -213,7 +214,7 @@ int __init s5pc100_init(void) /* set idle function */ pm_idle = s5pc100_idle; - return sysdev_register(&s5pc100_sysdev); + return device_register(&s5pc100_dev); } /* uart registration process */ diff --git a/arch/arm/mach-s5pc100/dev-spi.c b/arch/arm/mach-s5pc100/dev-spi.c deleted file mode 100644 index e5d6c4dceb5..00000000000 --- a/arch/arm/mach-s5pc100/dev-spi.c +++ /dev/null @@ -1,227 +0,0 @@ -/* linux/arch/arm/mach-s5pc100/dev-spi.c - * - * Copyright (C) 2010 Samsung Electronics Co. Ltd. - * Jaswinder Singh <jassi.brar@samsung.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/platform_device.h> -#include <linux/dma-mapping.h> -#include <linux/gpio.h> - -#include <mach/dma.h> -#include <mach/map.h> -#include <mach/spi-clocks.h> -#include <mach/irqs.h> - -#include <plat/s3c64xx-spi.h> -#include <plat/gpio-cfg.h> -#include <plat/irqs.h> - -static char *spi_src_clks[] = { - [S5PC100_SPI_SRCCLK_PCLK] = "pclk", - [S5PC100_SPI_SRCCLK_48M] = "spi_48m", - [S5PC100_SPI_SRCCLK_SPIBUS] = "spi_bus", -}; - -/* SPI Controller platform_devices */ - -/* Since we emulate multi-cs capability, we do not touch the CS. - * The emulated CS is toggled by board specific mechanism, as it can - * be either some immediate GPIO or some signal out of some other - * chip in between ... or some yet another way. - * We simply do not assume anything about CS. - */ -static int s5pc100_spi_cfg_gpio(struct platform_device *pdev) -{ - switch (pdev->id) { - case 0: - s3c_gpio_cfgall_range(S5PC100_GPB(0), 3, - S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); - break; - - case 1: - s3c_gpio_cfgall_range(S5PC100_GPB(4), 3, - S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); - break; - - case 2: - s3c_gpio_cfgpin(S5PC100_GPG3(0), S3C_GPIO_SFN(3)); - s3c_gpio_setpull(S5PC100_GPG3(0), S3C_GPIO_PULL_UP); - s3c_gpio_cfgall_range(S5PC100_GPB(2), 2, - S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP); - break; - - default: - dev_err(&pdev->dev, "Invalid SPI Controller number!"); - return -EINVAL; - } - - return 0; -} - -static struct resource s5pc100_spi0_resource[] = { - [0] = { - .start = S5PC100_PA_SPI0, - .end = S5PC100_PA_SPI0 + 0x100 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = DMACH_SPI0_TX, - .end = DMACH_SPI0_TX, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = DMACH_SPI0_RX, - .end = DMACH_SPI0_RX, - .flags = IORESOURCE_DMA, - }, - [3] = { - .start = IRQ_SPI0, - .end = IRQ_SPI0, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct s3c64xx_spi_info s5pc100_spi0_pdata = { - .cfg_gpio = s5pc100_spi_cfg_gpio, - .fifo_lvl_mask = 0x7f, - .rx_lvl_offset = 13, - .high_speed = 1, - .tx_st_done = 21, -}; - -static u64 spi_dmamask = DMA_BIT_MASK(32); - -struct platform_device s5pc100_device_spi0 = { - .name = "s3c64xx-spi", - .id = 0, - .num_resources = ARRAY_SIZE(s5pc100_spi0_resource), - .resource = s5pc100_spi0_resource, - .dev = { - .dma_mask = &spi_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - .platform_data = &s5pc100_spi0_pdata, - }, -}; - -static struct resource s5pc100_spi1_resource[] = { - [0] = { - .start = S5PC100_PA_SPI1, - .end = S5PC100_PA_SPI1 + 0x100 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = DMACH_SPI1_TX, - .end = DMACH_SPI1_TX, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = DMACH_SPI1_RX, - .end = DMACH_SPI1_RX, - .flags = IORESOURCE_DMA, - }, - [3] = { - .start = IRQ_SPI1, - .end = IRQ_SPI1, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct s3c64xx_spi_info s5pc100_spi1_pdata = { - .cfg_gpio = s5pc100_spi_cfg_gpio, - .fifo_lvl_mask = 0x7f, - .rx_lvl_offset = 13, - .high_speed = 1, - .tx_st_done = 21, -}; - -struct platform_device s5pc100_device_spi1 = { - .name = "s3c64xx-spi", - .id = 1, - .num_resources = ARRAY_SIZE(s5pc100_spi1_resource), - .resource = s5pc100_spi1_resource, - .dev = { - .dma_mask = &spi_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - .platform_data = &s5pc100_spi1_pdata, - }, -}; - -static struct resource s5pc100_spi2_resource[] = { - [0] = { - .start = S5PC100_PA_SPI2, - .end = S5PC100_PA_SPI2 + 0x100 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = DMACH_SPI2_TX, - .end = DMACH_SPI2_TX, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = DMACH_SPI2_RX, - .end = DMACH_SPI2_RX, - .flags = IORESOURCE_DMA, - }, - [3] = { - .start = IRQ_SPI2, - .end = IRQ_SPI2, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct s3c64xx_spi_info s5pc100_spi2_pdata = { - .cfg_gpio = s5pc100_spi_cfg_gpio, - .fifo_lvl_mask = 0x7f, - .rx_lvl_offset = 13, - .high_speed = 1, - .tx_st_done = 21, -}; - -struct platform_device s5pc100_device_spi2 = { - .name = "s3c64xx-spi", - .id = 2, - .num_resources = ARRAY_SIZE(s5pc100_spi2_resource), - .resource = s5pc100_spi2_resource, - .dev = { - .dma_mask = &spi_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - .platform_data = &s5pc100_spi2_pdata, - }, -}; - -void __init s5pc100_spi_set_info(int cntrlr, int src_clk_nr, int num_cs) -{ - struct s3c64xx_spi_info *pd; - - /* Reject invalid configuration */ - if (!num_cs || src_clk_nr < 0 - || src_clk_nr > S5PC100_SPI_SRCCLK_SPIBUS) { - printk(KERN_ERR "%s: Invalid SPI configuration\n", __func__); - return; - } - - switch (cntrlr) { - case 0: - pd = &s5pc100_spi0_pdata; - break; - case 1: - pd = &s5pc100_spi1_pdata; - break; - case 2: - pd = &s5pc100_spi2_pdata; - break; - default: - printk(KERN_ERR "%s: Invalid SPI controller(%d)\n", - __func__, cntrlr); - return; - } - - pd->num_cs = num_cs; - pd->src_clk_nr = src_clk_nr; - pd->src_clk_name = spi_src_clks[src_clk_nr]; -} diff --git a/arch/arm/mach-s5pc100/dma.c b/arch/arm/mach-s5pc100/dma.c index 065a087f5a8..c841f4d313f 100644 --- a/arch/arm/mach-s5pc100/dma.c +++ b/arch/arm/mach-s5pc100/dma.c @@ -35,100 +35,42 @@ static u64 dma_dmamask = DMA_BIT_MASK(32); -struct dma_pl330_peri pdma0_peri[30] = { - { - .peri_id = (u8)DMACH_UART0_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_UART0_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_UART1_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_UART1_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_UART2_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_UART2_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_UART3_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_UART3_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = DMACH_IRDA, - }, { - .peri_id = (u8)DMACH_I2S0_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_I2S0_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_I2S0S_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_I2S1_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_I2S1_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_I2S2_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_I2S2_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_SPI0_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_SPI0_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_SPI1_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_SPI1_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_SPI2_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_SPI2_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_AC97_MICIN, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_AC97_PCMIN, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_AC97_PCMOUT, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_EXTERNAL, - }, { - .peri_id = (u8)DMACH_PWM, - }, { - .peri_id = (u8)DMACH_SPDIF, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_HSI_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_HSI_TX, - .rqtype = MEMTODEV, - }, +u8 pdma0_peri[] = { + DMACH_UART0_RX, + DMACH_UART0_TX, + DMACH_UART1_RX, + DMACH_UART1_TX, + DMACH_UART2_RX, + DMACH_UART2_TX, + DMACH_UART3_RX, + DMACH_UART3_TX, + DMACH_IRDA, + DMACH_I2S0_RX, + DMACH_I2S0_TX, + DMACH_I2S0S_TX, + DMACH_I2S1_RX, + DMACH_I2S1_TX, + DMACH_I2S2_RX, + DMACH_I2S2_TX, + DMACH_SPI0_RX, + DMACH_SPI0_TX, + DMACH_SPI1_RX, + DMACH_SPI1_TX, + DMACH_SPI2_RX, + DMACH_SPI2_TX, + DMACH_AC97_MICIN, + DMACH_AC97_PCMIN, + DMACH_AC97_PCMOUT, + DMACH_EXTERNAL, + DMACH_PWM, + DMACH_SPDIF, + DMACH_HSI_RX, + DMACH_HSI_TX, }; struct dma_pl330_platdata s5pc100_pdma0_pdata = { .nr_valid_peri = ARRAY_SIZE(pdma0_peri), - .peri = pdma0_peri, + .peri_id = pdma0_peri, }; struct amba_device s5pc100_device_pdma0 = { @@ -147,98 +89,42 @@ struct amba_device s5pc100_device_pdma0 = { .periphid = 0x00041330, }; -struct dma_pl330_peri pdma1_peri[30] = { - { - .peri_id = (u8)DMACH_UART0_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_UART0_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_UART1_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_UART1_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_UART2_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_UART2_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_UART3_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_UART3_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = DMACH_IRDA, - }, { - .peri_id = (u8)DMACH_I2S0_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_I2S0_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_I2S0S_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_I2S1_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_I2S1_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_I2S2_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_I2S2_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_SPI0_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_SPI0_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_SPI1_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_SPI1_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_SPI2_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_SPI2_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_PCM0_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_PCM1_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_PCM1_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_PCM1_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_MSM_REQ0, - }, { - .peri_id = (u8)DMACH_MSM_REQ1, - }, { - .peri_id = (u8)DMACH_MSM_REQ2, - }, { - .peri_id = (u8)DMACH_MSM_REQ3, - }, +u8 pdma1_peri[] = { + DMACH_UART0_RX, + DMACH_UART0_TX, + DMACH_UART1_RX, + DMACH_UART1_TX, + DMACH_UART2_RX, + DMACH_UART2_TX, + DMACH_UART3_RX, + DMACH_UART3_TX, + DMACH_IRDA, + DMACH_I2S0_RX, + DMACH_I2S0_TX, + DMACH_I2S0S_TX, + DMACH_I2S1_RX, + DMACH_I2S1_TX, + DMACH_I2S2_RX, + DMACH_I2S2_TX, + DMACH_SPI0_RX, + DMACH_SPI0_TX, + DMACH_SPI1_RX, + DMACH_SPI1_TX, + DMACH_SPI2_RX, + DMACH_SPI2_TX, + DMACH_PCM0_RX, + DMACH_PCM0_TX, + DMACH_PCM1_RX, + DMACH_PCM1_TX, + DMACH_MSM_REQ0, + DMACH_MSM_REQ1, + DMACH_MSM_REQ2, + DMACH_MSM_REQ3, }; struct dma_pl330_platdata s5pc100_pdma1_pdata = { .nr_valid_peri = ARRAY_SIZE(pdma1_peri), - .peri = pdma1_peri, + .peri_id = pdma1_peri, }; struct amba_device s5pc100_device_pdma1 = { @@ -259,7 +145,12 @@ struct amba_device s5pc100_device_pdma1 = { static int __init s5pc100_dma_init(void) { + dma_cap_set(DMA_SLAVE, s5pc100_pdma0_pdata.cap_mask); + dma_cap_set(DMA_CYCLIC, s5pc100_pdma0_pdata.cap_mask); amba_device_register(&s5pc100_device_pdma0, &iomem_resource); + + dma_cap_set(DMA_SLAVE, s5pc100_pdma1_pdata.cap_mask); + dma_cap_set(DMA_CYCLIC, s5pc100_pdma1_pdata.cap_mask); amba_device_register(&s5pc100_device_pdma1, &iomem_resource); return 0; diff --git a/arch/arm/mach-s5pc100/include/mach/irqs.h b/arch/arm/mach-s5pc100/include/mach/irqs.h index d2eb4757381..2870f12c792 100644 --- a/arch/arm/mach-s5pc100/include/mach/irqs.h +++ b/arch/arm/mach-s5pc100/include/mach/irqs.h @@ -97,6 +97,8 @@ #define IRQ_SDMFIQ S5P_IRQ_VIC2(31) #define IRQ_VIC_END S5P_IRQ_VIC2(31) +#define IRQ_TIMER_BASE (11) + #define S5P_EINT_BASE1 (S5P_IRQ_VIC0(0)) #define S5P_EINT_BASE2 (IRQ_VIC_END + 1) diff --git a/arch/arm/mach-s5pc100/include/mach/map.h b/arch/arm/mach-s5pc100/include/mach/map.h index ccbe6b767f7..54bc4f82e17 100644 --- a/arch/arm/mach-s5pc100/include/mach/map.h +++ b/arch/arm/mach-s5pc100/include/mach/map.h @@ -100,6 +100,9 @@ #define S3C_PA_USB_HSOTG S5PC100_PA_USB_HSOTG #define S3C_PA_USB_HSPHY S5PC100_PA_USB_HSPHY #define S3C_PA_WDT S5PC100_PA_WATCHDOG +#define S3C_PA_SPI0 S5PC100_PA_SPI0 +#define S3C_PA_SPI1 S5PC100_PA_SPI1 +#define S3C_PA_SPI2 S5PC100_PA_SPI2 #define S5P_PA_CHIPID S5PC100_PA_CHIPID #define S5P_PA_FIMC0 S5PC100_PA_FIMC0 diff --git a/arch/arm/mach-s5pc100/setup-sdhci.c b/arch/arm/mach-s5pc100/setup-sdhci.c deleted file mode 100644 index 6418c6e8a7b..00000000000 --- a/arch/arm/mach-s5pc100/setup-sdhci.c +++ /dev/null @@ -1,23 +0,0 @@ -/* linux/arch/arm/mach-s5pc100/setup-sdhci.c - * - * Copyright 2008 Samsung Electronics - * - * S5PC100 - Helper functions for settign up SDHCI device(s) (HSMMC) - * - * Based on mach-s3c6410/setup-sdhci.c - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/types.h> - -/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */ - -char *s5pc100_hsmmc_clksrcs[4] = { - [0] = "hsmmc", /* HCLK */ - /* [1] = "hsmmc", - duplicate HCLK entry */ - [2] = "sclk_mmc", /* mmc_bus */ - /* [3] = "48m", - note not successfully used yet */ -}; diff --git a/arch/arm/mach-s5pc100/setup-spi.c b/arch/arm/mach-s5pc100/setup-spi.c new file mode 100644 index 00000000000..431a6f747ca --- /dev/null +++ b/arch/arm/mach-s5pc100/setup-spi.c @@ -0,0 +1,65 @@ +/* linux/arch/arm/mach-s5pc100/setup-spi.c + * + * Copyright (C) 2011 Samsung Electronics Ltd. + * http://www.samsung.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/gpio.h> +#include <linux/platform_device.h> + +#include <plat/gpio-cfg.h> +#include <plat/s3c64xx-spi.h> + +#ifdef CONFIG_S3C64XX_DEV_SPI0 +struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = { + .fifo_lvl_mask = 0x7f, + .rx_lvl_offset = 13, + .high_speed = 1, + .tx_st_done = 21, +}; + +int s3c64xx_spi0_cfg_gpio(struct platform_device *dev) +{ + s3c_gpio_cfgall_range(S5PC100_GPB(0), 3, + S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); + return 0; +} +#endif + +#ifdef CONFIG_S3C64XX_DEV_SPI1 +struct s3c64xx_spi_info s3c64xx_spi1_pdata __initdata = { + .fifo_lvl_mask = 0x7f, + .rx_lvl_offset = 13, + .high_speed = 1, + .tx_st_done = 21, +}; + +int s3c64xx_spi1_cfg_gpio(struct platform_device *dev) +{ + s3c_gpio_cfgall_range(S5PC100_GPB(4), 3, + S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); + return 0; +} +#endif + +#ifdef CONFIG_S3C64XX_DEV_SPI2 +struct s3c64xx_spi_info s3c64xx_spi2_pdata __initdata = { + .fifo_lvl_mask = 0x7f, + .rx_lvl_offset = 13, + .high_speed = 1, + .tx_st_done = 21, +}; + +int s3c64xx_spi2_cfg_gpio(struct platform_device *dev) +{ + s3c_gpio_cfgpin(S5PC100_GPG3(0), S3C_GPIO_SFN(3)); + s3c_gpio_setpull(S5PC100_GPG3(0), S3C_GPIO_PULL_UP); + s3c_gpio_cfgall_range(S5PC100_GPB(2), 2, + S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP); + return 0; +} +#endif diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig index 646057ab2e4..2cdc42e838b 100644 --- a/arch/arm/mach-s5pv210/Kconfig +++ b/arch/arm/mach-s5pv210/Kconfig @@ -60,6 +60,11 @@ config S5PV210_SETUP_FIMC help Common setup code for the camera interfaces. +config S5PV210_SETUP_SPI + bool + help + Common setup code for SPI GPIO configurations. + menu "S5PC110 Machines" config MACH_AQUILA diff --git a/arch/arm/mach-s5pv210/Makefile b/arch/arm/mach-s5pv210/Makefile index 4c59186de95..76a121dd52b 100644 --- a/arch/arm/mach-s5pv210/Makefile +++ b/arch/arm/mach-s5pv210/Makefile @@ -29,7 +29,6 @@ obj-$(CONFIG_MACH_TORBRECK) += mach-torbreck.o # device support obj-y += dev-audio.o -obj-$(CONFIG_S3C64XX_DEV_SPI) += dev-spi.o obj-y += setup-i2c0.o obj-$(CONFIG_S5PV210_SETUP_FB_24BPP) += setup-fb-24bpp.o @@ -38,5 +37,5 @@ obj-$(CONFIG_S5PV210_SETUP_I2C1) += setup-i2c1.o obj-$(CONFIG_S5PV210_SETUP_I2C2) += setup-i2c2.o obj-$(CONFIG_S5PV210_SETUP_IDE) += setup-ide.o obj-$(CONFIG_S5PV210_SETUP_KEYPAD) += setup-keypad.o -obj-$(CONFIG_S5PV210_SETUP_SDHCI) += setup-sdhci.o obj-$(CONFIG_S5PV210_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o +obj-$(CONFIG_S5PV210_SETUP_SPI) += setup-spi.o diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c index f2dbf5f75a2..c78dfddd77f 100644 --- a/arch/arm/mach-s5pv210/clock.c +++ b/arch/arm/mach-s5pv210/clock.c @@ -17,7 +17,7 @@ #include <linux/errno.h> #include <linux/err.h> #include <linux/clk.h> -#include <linux/sysdev.h> +#include <linux/device.h> #include <linux/io.h> #include <mach/map.h> @@ -400,30 +400,6 @@ static struct clk init_clocks_off[] = { .enable = s5pv210_clk_ip1_ctrl, .ctrlbit = (1<<25), }, { - .name = "hsmmc", - .devname = "s3c-sdhci.0", - .parent = &clk_hclk_psys.clk, - .enable = s5pv210_clk_ip2_ctrl, - .ctrlbit = (1<<16), - }, { - .name = "hsmmc", - .devname = "s3c-sdhci.1", - .parent = &clk_hclk_psys.clk, - .enable = s5pv210_clk_ip2_ctrl, - .ctrlbit = (1<<17), - }, { - .name = "hsmmc", - .devname = "s3c-sdhci.2", - .parent = &clk_hclk_psys.clk, - .enable = s5pv210_clk_ip2_ctrl, - .ctrlbit = (1<<18), - }, { - .name = "hsmmc", - .devname = "s3c-sdhci.3", - .parent = &clk_hclk_psys.clk, - .enable = s5pv210_clk_ip2_ctrl, - .ctrlbit = (1<<19), - }, { .name = "systimer", .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, @@ -560,6 +536,38 @@ static struct clk init_clocks[] = { }, }; +static struct clk clk_hsmmc0 = { + .name = "hsmmc", + .devname = "s3c-sdhci.0", + .parent = &clk_hclk_psys.clk, + .enable = s5pv210_clk_ip2_ctrl, + .ctrlbit = (1<<16), +}; + +static struct clk clk_hsmmc1 = { + .name = "hsmmc", + .devname = "s3c-sdhci.1", + .parent = &clk_hclk_psys.clk, + .enable = s5pv210_clk_ip2_ctrl, + .ctrlbit = (1<<17), +}; + +static struct clk clk_hsmmc2 = { + .name = "hsmmc", + .devname = "s3c-sdhci.2", + .parent = &clk_hclk_psys.clk, + .enable = s5pv210_clk_ip2_ctrl, + .ctrlbit = (1<<18), +}; + +static struct clk clk_hsmmc3 = { + .name = "hsmmc", + .devname = "s3c-sdhci.3", + .parent = &clk_hclk_psys.clk, + .enable = s5pv210_clk_ip2_ctrl, + .ctrlbit = (1<<19), +}; + static struct clk *clkset_uart_list[] = { [6] = &clk_mout_mpll.clk, [7] = &clk_mout_epll.clk, @@ -810,46 +818,6 @@ static struct clksrc_clk clksrcs[] = { .reg_div = { .reg = S5P_CLK_DIV6, .shift = 12, .size = 3 }, }, { .clk = { - .name = "uclk1", - .devname = "s5pv210-uart.0", - .enable = s5pv210_clk_mask0_ctrl, - .ctrlbit = (1 << 12), - }, - .sources = &clkset_uart, - .reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 }, - .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 }, - }, { - .clk = { - .name = "uclk1", - .devname = "s5pv210-uart.1", - .enable = s5pv210_clk_mask0_ctrl, - .ctrlbit = (1 << 13), - }, - .sources = &clkset_uart, - .reg_src = { .reg = S5P_CLK_SRC4, .shift = 20, .size = 4 }, - .reg_div = { .reg = S5P_CLK_DIV4, .shift = 20, .size = 4 }, - }, { - .clk = { - .name = "uclk1", - .devname = "s5pv210-uart.2", - .enable = s5pv210_clk_mask0_ctrl, - .ctrlbit = (1 << 14), - }, - .sources = &clkset_uart, - .reg_src = { .reg = S5P_CLK_SRC4, .shift = 24, .size = 4 }, - .reg_div = { .reg = S5P_CLK_DIV4, .shift = 24, .size = 4 }, - }, { - .clk = { - .name = "uclk1", - .devname = "s5pv210-uart.3", - .enable = s5pv210_clk_mask0_ctrl, - .ctrlbit = (1 << 15), - }, - .sources = &clkset_uart, - .reg_src = { .reg = S5P_CLK_SRC4, .shift = 28, .size = 4 }, - .reg_div = { .reg = S5P_CLK_DIV4, .shift = 28, .size = 4 }, - }, { - .clk = { .name = "sclk_fimc", .devname = "s5pv210-fimc.0", .enable = s5pv210_clk_mask1_ctrl, @@ -907,46 +875,6 @@ static struct clksrc_clk clksrcs[] = { .reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 4 }, }, { .clk = { - .name = "sclk_mmc", - .devname = "s3c-sdhci.0", - .enable = s5pv210_clk_mask0_ctrl, - .ctrlbit = (1 << 8), - }, - .sources = &clkset_group2, - .reg_src = { .reg = S5P_CLK_SRC4, .shift = 0, .size = 4 }, - .reg_div = { .reg = S5P_CLK_DIV4, .shift = 0, .size = 4 }, - }, { - .clk = { - .name = "sclk_mmc", - .devname = "s3c-sdhci.1", - .enable = s5pv210_clk_mask0_ctrl, - .ctrlbit = (1 << 9), - }, - .sources = &clkset_group2, - .reg_src = { .reg = S5P_CLK_SRC4, .shift = 4, .size = 4 }, - .reg_div = { .reg = S5P_CLK_DIV4, .shift = 4, .size = 4 }, - }, { - .clk = { - .name = "sclk_mmc", - .devname = "s3c-sdhci.2", - .enable = s5pv210_clk_mask0_ctrl, - .ctrlbit = (1 << 10), - }, - .sources = &clkset_group2, - .reg_src = { .reg = S5P_CLK_SRC4, .shift = 8, .size = 4 }, - .reg_div = { .reg = S5P_CLK_DIV4, .shift = 8, .size = 4 }, - }, { - .clk = { - .name = "sclk_mmc", - .devname = "s3c-sdhci.3", - .enable = s5pv210_clk_mask0_ctrl, - .ctrlbit = (1 << 11), - }, - .sources = &clkset_group2, - .reg_src = { .reg = S5P_CLK_SRC4, .shift = 12, .size = 4 }, - .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 }, - }, { - .clk = { .name = "sclk_mfc", .devname = "s5p-mfc", .enable = s5pv210_clk_ip0_ctrl, @@ -984,26 +912,6 @@ static struct clksrc_clk clksrcs[] = { .reg_div = { .reg = S5P_CLK_DIV1, .shift = 28, .size = 4 }, }, { .clk = { - .name = "sclk_spi", - .devname = "s3c64xx-spi.0", - .enable = s5pv210_clk_mask0_ctrl, - .ctrlbit = (1 << 16), - }, - .sources = &clkset_group2, - .reg_src = { .reg = S5P_CLK_SRC5, .shift = 0, .size = 4 }, - .reg_div = { .reg = S5P_CLK_DIV5, .shift = 0, .size = 4 }, - }, { - .clk = { - .name = "sclk_spi", - .devname = "s3c64xx-spi.1", - .enable = s5pv210_clk_mask0_ctrl, - .ctrlbit = (1 << 17), - }, - .sources = &clkset_group2, - .reg_src = { .reg = S5P_CLK_SRC5, .shift = 4, .size = 4 }, - .reg_div = { .reg = S5P_CLK_DIV5, .shift = 4, .size = 4 }, - }, { - .clk = { .name = "sclk_pwi", .enable = s5pv210_clk_mask0_ctrl, .ctrlbit = (1 << 29), @@ -1023,6 +931,147 @@ static struct clksrc_clk clksrcs[] = { }, }; +static struct clksrc_clk clk_sclk_uart0 = { + .clk = { + .name = "uclk1", + .devname = "s5pv210-uart.0", + .enable = s5pv210_clk_mask0_ctrl, + .ctrlbit = (1 << 12), + }, + .sources = &clkset_uart, + .reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 }, + .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 }, +}; + +static struct clksrc_clk clk_sclk_uart1 = { + .clk = { + .name = "uclk1", + .devname = "s5pv210-uart.1", + .enable = s5pv210_clk_mask0_ctrl, + .ctrlbit = (1 << 13), + }, + .sources = &clkset_uart, + .reg_src = { .reg = S5P_CLK_SRC4, .shift = 20, .size = 4 }, + .reg_div = { .reg = S5P_CLK_DIV4, .shift = 20, .size = 4 }, +}; + +static struct clksrc_clk clk_sclk_uart2 = { + .clk = { + .name = "uclk1", + .devname = "s5pv210-uart.2", + .enable = s5pv210_clk_mask0_ctrl, + .ctrlbit = (1 << 14), + }, + .sources = &clkset_uart, + .reg_src = { .reg = S5P_CLK_SRC4, .shift = 24, .size = 4 }, + .reg_div = { .reg = S5P_CLK_DIV4, .shift = 24, .size = 4 }, +}; + +static struct clksrc_clk clk_sclk_uart3 = { + .clk = { + .name = "uclk1", + .devname = "s5pv210-uart.3", + .enable = s5pv210_clk_mask0_ctrl, + .ctrlbit = (1 << 15), + }, + .sources = &clkset_uart, + .reg_src = { .reg = S5P_CLK_SRC4, .shift = 28, .size = 4 }, + .reg_div = { .reg = S5P_CLK_DIV4, .shift = 28, .size = 4 }, +}; + +static struct clksrc_clk clk_sclk_mmc0 = { + .clk = { + .name = "sclk_mmc", + .devname = "s3c-sdhci.0", + .enable = s5pv210_clk_mask0_ctrl, + .ctrlbit = (1 << 8), + }, + .sources = &clkset_group2, + .reg_src = { .reg = S5P_CLK_SRC4, .shift = 0, .size = 4 }, + .reg_div = { .reg = S5P_CLK_DIV4, .shift = 0, .size = 4 }, +}; + +static struct clksrc_clk clk_sclk_mmc1 = { + .clk = { + .name = "sclk_mmc", + .devname = "s3c-sdhci.1", + .enable = s5pv210_clk_mask0_ctrl, + .ctrlbit = (1 << 9), + }, + .sources = &clkset_group2, + .reg_src = { .reg = S5P_CLK_SRC4, .shift = 4, .size = 4 }, + .reg_div = { .reg = S5P_CLK_DIV4, .shift = 4, .size = 4 }, +}; + +static struct clksrc_clk clk_sclk_mmc2 = { + .clk = { + .name = "sclk_mmc", + .devname = "s3c-sdhci.2", + .enable = s5pv210_clk_mask0_ctrl, + .ctrlbit = (1 << 10), + }, + .sources = &clkset_group2, + .reg_src = { .reg = S5P_CLK_SRC4, .shift = 8, .size = 4 }, + .reg_div = { .reg = S5P_CLK_DIV4, .shift = 8, .size = 4 }, +}; + +static struct clksrc_clk clk_sclk_mmc3 = { + .clk = { + .name = "sclk_mmc", + .devname = "s3c-sdhci.3", + .enable = s5pv210_clk_mask0_ctrl, + .ctrlbit = (1 << 11), + }, + .sources = &clkset_group2, + .reg_src = { .reg = S5P_CLK_SRC4, .shift = 12, .size = 4 }, + .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 }, +}; + +static struct clksrc_clk clk_sclk_spi0 = { + .clk = { + .name = "sclk_spi", + .devname = "s3c64xx-spi.0", + .enable = s5pv210_clk_mask0_ctrl, + .ctrlbit = (1 << 16), + }, + .sources = &clkset_group2, + .reg_src = { .reg = S5P_CLK_SRC5, .shift = 0, .size = 4 }, + .reg_div = { .reg = S5P_CLK_DIV5, .shift = 0, .size = 4 }, + }; + +static struct clksrc_clk clk_sclk_spi1 = { + .clk = { + .name = "sclk_spi", + .devname = "s3c64xx-spi.1", + .enable = s5pv210_clk_mask0_ctrl, + .ctrlbit = (1 << 17), + }, + .sources = &clkset_group2, + .reg_src = { .reg = S5P_CLK_SRC5, .shift = 4, .size = 4 }, + .reg_div = { .reg = S5P_CLK_DIV5, .shift = 4, .size = 4 }, + }; + + +static struct clksrc_clk *clksrc_cdev[] = { + &clk_sclk_uart0, + &clk_sclk_uart1, + &clk_sclk_uart2, + &clk_sclk_uart3, + &clk_sclk_mmc0, + &clk_sclk_mmc1, + &clk_sclk_mmc2, + &clk_sclk_mmc3, + &clk_sclk_spi0, + &clk_sclk_spi1, +}; + +static struct clk *clk_cdev[] = { + &clk_hsmmc0, + &clk_hsmmc1, + &clk_hsmmc2, + &clk_hsmmc3, +}; + /* Clock initialisation code */ static struct clksrc_clk *sysclks[] = { &clk_mout_apll, @@ -1262,6 +1311,25 @@ static struct clk *clks[] __initdata = { &clk_pcmcdclk2, }; +static struct clk_lookup s5pv210_clk_lookup[] = { + CLKDEV_INIT(NULL, "clk_uart_baud0", &clk_p), + CLKDEV_INIT("s5pv210-uart.0", "clk_uart_baud1", &clk_sclk_uart0.clk), + CLKDEV_INIT("s5pv210-uart.1", "clk_uart_baud1", &clk_sclk_uart1.clk), + CLKDEV_INIT("s5pv210-uart.2", "clk_uart_baud1", &clk_sclk_uart2.clk), + CLKDEV_INIT("s5pv210-uart.3", "clk_uart_baud1", &clk_sclk_uart3.clk), + CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &clk_hsmmc0), + CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &clk_hsmmc1), + CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.0", &clk_hsmmc2), + CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.0", &clk_hsmmc3), + CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk), + CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk), + CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk), + CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &clk_sclk_mmc3.clk), + CLKDEV_INIT(NULL, "spi_busclk0", &clk_p), + CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk), + CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk), +}; + void __init s5pv210_register_clocks(void) { int ptr; @@ -1274,11 +1342,19 @@ void __init s5pv210_register_clocks(void) for (ptr = 0; ptr < ARRAY_SIZE(sclk_tv); ptr++) s3c_register_clksrc(sclk_tv[ptr], 1); + for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++) + s3c_register_clksrc(clksrc_cdev[ptr], 1); + s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); + clkdev_add_table(s5pv210_clk_lookup, ARRAY_SIZE(s5pv210_clk_lookup)); + + s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev)); + for (ptr = 0; ptr < ARRAY_SIZE(clk_cdev); ptr++) + s3c_disable_clocks(clk_cdev[ptr], 1); s3c24xx_register_clock(&dummy_apb_pclk); s3c_pwmclk_init(); diff --git a/arch/arm/mach-s5pv210/common.c b/arch/arm/mach-s5pv210/common.c index a4921bc9f1d..9c1bcdcc12c 100644 --- a/arch/arm/mach-s5pv210/common.c +++ b/arch/arm/mach-s5pv210/common.c @@ -18,7 +18,7 @@ #include <linux/module.h> #include <linux/clk.h> #include <linux/io.h> -#include <linux/sysdev.h> +#include <linux/device.h> #include <linux/platform_device.h> #include <linux/sched.h> #include <linux/dma-mapping.h> @@ -229,17 +229,18 @@ void __init s5pv210_init_irq(void) s5p_init_irq(vic, ARRAY_SIZE(vic)); } -struct sysdev_class s5pv210_sysclass = { - .name = "s5pv210-core", +struct bus_type s5pv210_subsys = { + .name = "s5pv210-core", + .dev_name = "s5pv210-core", }; -static struct sys_device s5pv210_sysdev = { - .cls = &s5pv210_sysclass, +static struct device s5pv210_dev = { + .bus = &s5pv210_subsys, }; static int __init s5pv210_core_init(void) { - return sysdev_class_register(&s5pv210_sysclass); + return subsys_system_register(&s5pv210_subsys, NULL); } core_initcall(s5pv210_core_init); @@ -250,31 +251,12 @@ int __init s5pv210_init(void) /* set idle function */ pm_idle = s5pv210_idle; - return sysdev_register(&s5pv210_sysdev); + return device_register(&s5pv210_dev); } -static struct s3c24xx_uart_clksrc s5pv210_serial_clocks[] = { - [0] = { - .name = "pclk", - .divisor = 1, - .min_baud = 0, - .max_baud = 0, - }, -}; - /* uart registration process */ void __init s5pv210_init_uarts(struct s3c2410_uartcfg *cfg, int no) { - struct s3c2410_uartcfg *tcfg = cfg; - u32 ucnt; - - for (ucnt = 0; ucnt < no; ucnt++, tcfg++) { - if (!tcfg->clocks) { - tcfg->clocks = s5pv210_serial_clocks; - tcfg->clocks_size = ARRAY_SIZE(s5pv210_serial_clocks); - } - } - s3c24xx_init_uartdevs("s5pv210-uart", s5p_uart_resources, cfg, no); } diff --git a/arch/arm/mach-s5pv210/dev-spi.c b/arch/arm/mach-s5pv210/dev-spi.c deleted file mode 100644 index eaf9a7bff7a..00000000000 --- a/arch/arm/mach-s5pv210/dev-spi.c +++ /dev/null @@ -1,175 +0,0 @@ -/* linux/arch/arm/mach-s5pv210/dev-spi.c - * - * Copyright (C) 2010 Samsung Electronics Co. Ltd. - * Jaswinder Singh <jassi.brar@samsung.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/platform_device.h> -#include <linux/dma-mapping.h> -#include <linux/gpio.h> - -#include <mach/dma.h> -#include <mach/map.h> -#include <mach/irqs.h> -#include <mach/spi-clocks.h> - -#include <plat/s3c64xx-spi.h> -#include <plat/gpio-cfg.h> - -static char *spi_src_clks[] = { - [S5PV210_SPI_SRCCLK_PCLK] = "pclk", - [S5PV210_SPI_SRCCLK_SCLK] = "sclk_spi", -}; - -/* SPI Controller platform_devices */ - -/* Since we emulate multi-cs capability, we do not touch the CS. - * The emulated CS is toggled by board specific mechanism, as it can - * be either some immediate GPIO or some signal out of some other - * chip in between ... or some yet another way. - * We simply do not assume anything about CS. - */ -static int s5pv210_spi_cfg_gpio(struct platform_device *pdev) -{ - unsigned int base; - - switch (pdev->id) { - case 0: - base = S5PV210_GPB(0); - break; - - case 1: - base = S5PV210_GPB(4); - break; - - default: - dev_err(&pdev->dev, "Invalid SPI Controller number!"); - return -EINVAL; - } - - s3c_gpio_cfgall_range(base, 3, - S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); - - return 0; -} - -static struct resource s5pv210_spi0_resource[] = { - [0] = { - .start = S5PV210_PA_SPI0, - .end = S5PV210_PA_SPI0 + 0x100 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = DMACH_SPI0_TX, - .end = DMACH_SPI0_TX, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = DMACH_SPI0_RX, - .end = DMACH_SPI0_RX, - .flags = IORESOURCE_DMA, - }, - [3] = { - .start = IRQ_SPI0, - .end = IRQ_SPI0, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct s3c64xx_spi_info s5pv210_spi0_pdata = { - .cfg_gpio = s5pv210_spi_cfg_gpio, - .fifo_lvl_mask = 0x1ff, - .rx_lvl_offset = 15, - .high_speed = 1, - .tx_st_done = 25, -}; - -static u64 spi_dmamask = DMA_BIT_MASK(32); - -struct platform_device s5pv210_device_spi0 = { - .name = "s3c64xx-spi", - .id = 0, - .num_resources = ARRAY_SIZE(s5pv210_spi0_resource), - .resource = s5pv210_spi0_resource, - .dev = { - .dma_mask = &spi_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - .platform_data = &s5pv210_spi0_pdata, - }, -}; - -static struct resource s5pv210_spi1_resource[] = { - [0] = { - .start = S5PV210_PA_SPI1, - .end = S5PV210_PA_SPI1 + 0x100 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = DMACH_SPI1_TX, - .end = DMACH_SPI1_TX, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = DMACH_SPI1_RX, - .end = DMACH_SPI1_RX, - .flags = IORESOURCE_DMA, - }, - [3] = { - .start = IRQ_SPI1, - .end = IRQ_SPI1, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct s3c64xx_spi_info s5pv210_spi1_pdata = { - .cfg_gpio = s5pv210_spi_cfg_gpio, - .fifo_lvl_mask = 0x7f, - .rx_lvl_offset = 15, - .high_speed = 1, - .tx_st_done = 25, -}; - -struct platform_device s5pv210_device_spi1 = { - .name = "s3c64xx-spi", - .id = 1, - .num_resources = ARRAY_SIZE(s5pv210_spi1_resource), - .resource = s5pv210_spi1_resource, - .dev = { - .dma_mask = &spi_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - .platform_data = &s5pv210_spi1_pdata, - }, -}; - -void __init s5pv210_spi_set_info(int cntrlr, int src_clk_nr, int num_cs) -{ - struct s3c64xx_spi_info *pd; - - /* Reject invalid configuration */ - if (!num_cs || src_clk_nr < 0 - || src_clk_nr > S5PV210_SPI_SRCCLK_SCLK) { - printk(KERN_ERR "%s: Invalid SPI configuration\n", __func__); - return; - } - - switch (cntrlr) { - case 0: - pd = &s5pv210_spi0_pdata; - break; - case 1: - pd = &s5pv210_spi1_pdata; - break; - default: - printk(KERN_ERR "%s: Invalid SPI controller(%d)\n", - __func__, cntrlr); - return; - } - - pd->num_cs = num_cs; - pd->src_clk_nr = src_clk_nr; - pd->src_clk_name = spi_src_clks[src_clk_nr]; -} diff --git a/arch/arm/mach-s5pv210/dma.c b/arch/arm/mach-s5pv210/dma.c index 86b749c18b7..a6113e0267f 100644 --- a/arch/arm/mach-s5pv210/dma.c +++ b/arch/arm/mach-s5pv210/dma.c @@ -35,90 +35,40 @@ static u64 dma_dmamask = DMA_BIT_MASK(32); -struct dma_pl330_peri pdma0_peri[28] = { - { - .peri_id = (u8)DMACH_UART0_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_UART0_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_UART1_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_UART1_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_UART2_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_UART2_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_UART3_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_UART3_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = DMACH_MAX, - }, { - .peri_id = (u8)DMACH_I2S0_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_I2S0_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_I2S0S_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_I2S1_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_I2S1_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_MAX, - }, { - .peri_id = (u8)DMACH_MAX, - }, { - .peri_id = (u8)DMACH_SPI0_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_SPI0_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_SPI1_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_SPI1_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_MAX, - }, { - .peri_id = (u8)DMACH_MAX, - }, { - .peri_id = (u8)DMACH_AC97_MICIN, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_AC97_PCMIN, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_AC97_PCMOUT, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_MAX, - }, { - .peri_id = (u8)DMACH_PWM, - }, { - .peri_id = (u8)DMACH_SPDIF, - .rqtype = MEMTODEV, - }, +u8 pdma0_peri[] = { + DMACH_UART0_RX, + DMACH_UART0_TX, + DMACH_UART1_RX, + DMACH_UART1_TX, + DMACH_UART2_RX, + DMACH_UART2_TX, + DMACH_UART3_RX, + DMACH_UART3_TX, + DMACH_MAX, + DMACH_I2S0_RX, + DMACH_I2S0_TX, + DMACH_I2S0S_TX, + DMACH_I2S1_RX, + DMACH_I2S1_TX, + DMACH_MAX, + DMACH_MAX, + DMACH_SPI0_RX, + DMACH_SPI0_TX, + DMACH_SPI1_RX, + DMACH_SPI1_TX, + DMACH_MAX, + DMACH_MAX, + DMACH_AC97_MICIN, + DMACH_AC97_PCMIN, + DMACH_AC97_PCMOUT, + DMACH_MAX, + DMACH_PWM, + DMACH_SPDIF, }; struct dma_pl330_platdata s5pv210_pdma0_pdata = { .nr_valid_peri = ARRAY_SIZE(pdma0_peri), - .peri = pdma0_peri, + .peri_id = pdma0_peri, }; struct amba_device s5pv210_device_pdma0 = { @@ -137,102 +87,44 @@ struct amba_device s5pv210_device_pdma0 = { .periphid = 0x00041330, }; -struct dma_pl330_peri pdma1_peri[32] = { - { - .peri_id = (u8)DMACH_UART0_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_UART0_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_UART1_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_UART1_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_UART2_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_UART2_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_UART3_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_UART3_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = DMACH_MAX, - }, { - .peri_id = (u8)DMACH_I2S0_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_I2S0_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_I2S0S_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_I2S1_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_I2S1_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_I2S2_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_I2S2_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_SPI0_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_SPI0_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_SPI1_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_SPI1_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_MAX, - }, { - .peri_id = (u8)DMACH_MAX, - }, { - .peri_id = (u8)DMACH_PCM0_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_PCM0_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_PCM1_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_PCM1_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_MSM_REQ0, - }, { - .peri_id = (u8)DMACH_MSM_REQ1, - }, { - .peri_id = (u8)DMACH_MSM_REQ2, - }, { - .peri_id = (u8)DMACH_MSM_REQ3, - }, { - .peri_id = (u8)DMACH_PCM2_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_PCM2_TX, - .rqtype = MEMTODEV, - }, +u8 pdma1_peri[] = { + DMACH_UART0_RX, + DMACH_UART0_TX, + DMACH_UART1_RX, + DMACH_UART1_TX, + DMACH_UART2_RX, + DMACH_UART2_TX, + DMACH_UART3_RX, + DMACH_UART3_TX, + DMACH_MAX, + DMACH_I2S0_RX, + DMACH_I2S0_TX, + DMACH_I2S0S_TX, + DMACH_I2S1_RX, + DMACH_I2S1_TX, + DMACH_I2S2_RX, + DMACH_I2S2_TX, + DMACH_SPI0_RX, + DMACH_SPI0_TX, + DMACH_SPI1_RX, + DMACH_SPI1_TX, + DMACH_MAX, + DMACH_MAX, + DMACH_PCM0_RX, + DMACH_PCM0_TX, + DMACH_PCM1_RX, + DMACH_PCM1_TX, + DMACH_MSM_REQ0, + DMACH_MSM_REQ1, + DMACH_MSM_REQ2, + DMACH_MSM_REQ3, + DMACH_PCM2_RX, + DMACH_PCM2_TX, }; struct dma_pl330_platdata s5pv210_pdma1_pdata = { .nr_valid_peri = ARRAY_SIZE(pdma1_peri), - .peri = pdma1_peri, + .peri_id = pdma1_peri, }; struct amba_device s5pv210_device_pdma1 = { @@ -253,7 +145,12 @@ struct amba_device s5pv210_device_pdma1 = { static int __init s5pv210_dma_init(void) { + dma_cap_set(DMA_SLAVE, s5pv210_pdma0_pdata.cap_mask); + dma_cap_set(DMA_CYCLIC, s5pv210_pdma0_pdata.cap_mask); amba_device_register(&s5pv210_device_pdma0, &iomem_resource); + + dma_cap_set(DMA_SLAVE, s5pv210_pdma1_pdata.cap_mask); + dma_cap_set(DMA_CYCLIC, s5pv210_pdma1_pdata.cap_mask); amba_device_register(&s5pv210_device_pdma1, &iomem_resource); return 0; diff --git a/arch/arm/mach-s5pv210/include/mach/irqs.h b/arch/arm/mach-s5pv210/include/mach/irqs.h index 5e0de3a31f3..e777e010ed2 100644 --- a/arch/arm/mach-s5pv210/include/mach/irqs.h +++ b/arch/arm/mach-s5pv210/include/mach/irqs.h @@ -118,6 +118,8 @@ #define IRQ_MDNIE3 S5P_IRQ_VIC3(8) #define IRQ_VIC_END S5P_IRQ_VIC3(31) +#define IRQ_TIMER_BASE (11) + #define S5P_EINT_BASE1 (S5P_IRQ_VIC0(0)) #define S5P_EINT_BASE2 (IRQ_VIC_END + 1) diff --git a/arch/arm/mach-s5pv210/include/mach/map.h b/arch/arm/mach-s5pv210/include/mach/map.h index 7ff609f1568..89c34b8f73b 100644 --- a/arch/arm/mach-s5pv210/include/mach/map.h +++ b/arch/arm/mach-s5pv210/include/mach/map.h @@ -109,6 +109,8 @@ #define S3C_PA_RTC S5PV210_PA_RTC #define S3C_PA_USB_HSOTG S5PV210_PA_HSOTG #define S3C_PA_WDT S5PV210_PA_WATCHDOG +#define S3C_PA_SPI0 S5PV210_PA_SPI0 +#define S3C_PA_SPI1 S5PV210_PA_SPI1 #define S5P_PA_CHIPID S5PV210_PA_CHIPID #define S5P_PA_FIMC0 S5PV210_PA_FIMC0 diff --git a/arch/arm/mach-s5pv210/mach-aquila.c b/arch/arm/mach-s5pv210/mach-aquila.c index 6f7dfe993c1..5e734d025a6 100644 --- a/arch/arm/mach-s5pv210/mach-aquila.c +++ b/arch/arm/mach-s5pv210/mach-aquila.c @@ -597,8 +597,7 @@ static struct s3c_sdhci_platdata aquila_hsmmc2_data __initdata = { static void aquila_setup_sdhci(void) { - gpio_request(AQUILA_EXT_FLASH_EN, "FLASH_EN"); - gpio_direction_output(AQUILA_EXT_FLASH_EN, 1); + gpio_request_one(AQUILA_EXT_FLASH_EN, GPIOF_OUT_INIT_HIGH, "FLASH_EN"); s3c_sdhci0_set_platdata(&aquila_hsmmc0_data); s3c_sdhci1_set_platdata(&aquila_hsmmc1_data); diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c index 12c69371739..ff915261043 100644 --- a/arch/arm/mach-s5pv210/mach-goni.c +++ b/arch/arm/mach-s5pv210/mach-goni.c @@ -229,8 +229,7 @@ static void __init goni_radio_init(void) i2c1_devs[0].irq = gpio_to_irq(gpio); gpio = S5PV210_GPJ2(5); /* XMSMDATA_5 */ - gpio_request(gpio, "FM_RST"); - gpio_direction_output(gpio, 1); + gpio_request_one(gpio, GPIOF_OUT_INIT_HIGH, "FM_RST"); } /* TSP */ @@ -266,8 +265,7 @@ static void __init goni_tsp_init(void) int gpio; gpio = S5PV210_GPJ1(3); /* XMSMADDR_11 */ - gpio_request(gpio, "TSP_LDO_ON"); - gpio_direction_output(gpio, 1); + gpio_request_one(gpio, GPIOF_OUT_INIT_HIGH, "TSP_LDO_ON"); gpio_export(gpio, 0); gpio = S5PV210_GPJ0(5); /* XMSMADDR_5 */ diff --git a/arch/arm/mach-s5pv210/mach-smdkc110.c b/arch/arm/mach-s5pv210/mach-smdkc110.c index 9405da4ae3a..b323983b2c5 100644 --- a/arch/arm/mach-s5pv210/mach-smdkc110.c +++ b/arch/arm/mach-s5pv210/mach-smdkc110.c @@ -13,7 +13,7 @@ #include <linux/init.h> #include <linux/serial_core.h> #include <linux/i2c.h> -#include <linux/sysdev.h> +#include <linux/device.h> #include <asm/hardware/vic.h> #include <asm/mach/arch.h> diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c index cf4da739382..dff9ea7b5bb 100644 --- a/arch/arm/mach-s5pv210/mach-smdkv210.c +++ b/arch/arm/mach-s5pv210/mach-smdkv210.c @@ -13,7 +13,7 @@ #include <linux/i2c.h> #include <linux/init.h> #include <linux/serial_core.h> -#include <linux/sysdev.h> +#include <linux/device.h> #include <linux/dm9000.h> #include <linux/fb.h> #include <linux/gpio.h> @@ -155,15 +155,12 @@ static void smdkv210_lte480wv_set_power(struct plat_lcd_data *pd, { if (power) { #if !defined(CONFIG_BACKLIGHT_PWM) - gpio_request(S5PV210_GPD0(3), "GPD0"); - gpio_direction_output(S5PV210_GPD0(3), 1); + gpio_request_one(S5PV210_GPD0(3), GPIOF_OUT_INIT_HIGH, "GPD0"); gpio_free(S5PV210_GPD0(3)); #endif /* fire nRESET on power up */ - gpio_request(S5PV210_GPH0(6), "GPH0"); - - gpio_direction_output(S5PV210_GPH0(6), 1); + gpio_request_one(S5PV210_GPH0(6), GPIOF_OUT_INIT_HIGH, "GPH0"); gpio_set_value(S5PV210_GPH0(6), 0); mdelay(10); @@ -174,8 +171,7 @@ static void smdkv210_lte480wv_set_power(struct plat_lcd_data *pd, gpio_free(S5PV210_GPH0(6)); } else { #if !defined(CONFIG_BACKLIGHT_PWM) - gpio_request(S5PV210_GPD0(3), "GPD0"); - gpio_direction_output(S5PV210_GPD0(3), 0); + gpio_request_one(S5PV210_GPD0(3), GPIOF_OUT_INIT_LOW, "GPD0"); gpio_free(S5PV210_GPD0(3)); #endif } diff --git a/arch/arm/mach-s5pv210/pm.c b/arch/arm/mach-s5pv210/pm.c index f149d278377..677c71c41e5 100644 --- a/arch/arm/mach-s5pv210/pm.c +++ b/arch/arm/mach-s5pv210/pm.c @@ -133,7 +133,7 @@ static void s5pv210_pm_prepare(void) s3c_pm_do_save(s5pv210_core_save, ARRAY_SIZE(s5pv210_core_save)); } -static int s5pv210_pm_add(struct sys_device *sysdev) +static int s5pv210_pm_add(struct device *dev) { pm_cpu_prep = s5pv210_pm_prepare; pm_cpu_sleep = s5pv210_cpu_suspend; @@ -141,13 +141,15 @@ static int s5pv210_pm_add(struct sys_device *sysdev) return 0; } -static struct sysdev_driver s5pv210_pm_driver = { - .add = s5pv210_pm_add, +static struct subsys_interface s5pv210_pm_interface = { + .name = "s5pv210_pm", + .subsys = &s5pv210_subsys, + .add_dev = s5pv210_pm_add, }; static __init int s5pv210_pm_drvinit(void) { - return sysdev_driver_register(&s5pv210_sysclass, &s5pv210_pm_driver); + return subsys_interface_register(&s5pv210_pm_interface); } arch_initcall(s5pv210_pm_drvinit); diff --git a/arch/arm/mach-s5pv210/setup-sdhci.c b/arch/arm/mach-s5pv210/setup-sdhci.c deleted file mode 100644 index 6b8ccc4d35f..00000000000 --- a/arch/arm/mach-s5pv210/setup-sdhci.c +++ /dev/null @@ -1,22 +0,0 @@ -/* linux/arch/arm/mach-s5pv210/setup-sdhci.c - * - * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd. - * http://www.samsung.com/ - * - * S5PV210 - Helper functions for settign up SDHCI device(s) (HSMMC) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/types.h> - -/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */ - -char *s5pv210_hsmmc_clksrcs[4] = { - [0] = "hsmmc", /* HCLK */ - /* [1] = "hsmmc", - duplicate HCLK entry */ - [2] = "sclk_mmc", /* mmc_bus */ - /* [3] = NULL, - reserved */ -}; diff --git a/arch/arm/mach-s5pv210/setup-spi.c b/arch/arm/mach-s5pv210/setup-spi.c new file mode 100644 index 00000000000..f43c5048a37 --- /dev/null +++ b/arch/arm/mach-s5pv210/setup-spi.c @@ -0,0 +1,51 @@ +/* linux/arch/arm/mach-s5pv210/setup-spi.c + * + * Copyright (C) 2011 Samsung Electronics Ltd. + * http://www.samsung.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/gpio.h> +#include <linux/platform_device.h> + +#include <plat/gpio-cfg.h> +#include <plat/s3c64xx-spi.h> + +#ifdef CONFIG_S3C64XX_DEV_SPI0 +struct s3c64xx_spi_info s3c64xx_spi0_pdata = { + .fifo_lvl_mask = 0x1ff, + .rx_lvl_offset = 15, + .high_speed = 1, + .tx_st_done = 25, +}; + +int s3c64xx_spi0_cfg_gpio(struct platform_device *dev) +{ + s3c_gpio_cfgpin(S5PV210_GPB(0), S3C_GPIO_SFN(2)); + s3c_gpio_setpull(S5PV210_GPB(0), S3C_GPIO_PULL_UP); + s3c_gpio_cfgall_range(S5PV210_GPB(2), 2, + S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); + return 0; +} +#endif + +#ifdef CONFIG_S3C64XX_DEV_SPI1 +struct s3c64xx_spi_info s3c64xx_spi1_pdata = { + .fifo_lvl_mask = 0x7f, + .rx_lvl_offset = 15, + .high_speed = 1, + .tx_st_done = 25, +}; + +int s3c64xx_spi1_cfg_gpio(struct platform_device *dev) +{ + s3c_gpio_cfgpin(S5PV210_GPB(4), S3C_GPIO_SFN(2)); + s3c_gpio_setpull(S5PV210_GPB(4), S3C_GPIO_PULL_UP); + s3c_gpio_cfgall_range(S5PV210_GPB(6), 2, + S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); + return 0; +} +#endif diff --git a/arch/arm/mach-sa1100/clock.c b/arch/arm/mach-sa1100/clock.c index dab3c6347a8..d6df9f6c9f7 100644 --- a/arch/arm/mach-sa1100/clock.c +++ b/arch/arm/mach-sa1100/clock.c @@ -11,17 +11,39 @@ #include <linux/clk.h> #include <linux/spinlock.h> #include <linux/mutex.h> +#include <linux/io.h> +#include <linux/clkdev.h> #include <mach/hardware.h> -/* - * Very simple clock implementation - we only have one clock to deal with. - */ +struct clkops { + void (*enable)(struct clk *); + void (*disable)(struct clk *); + unsigned long (*getrate)(struct clk *); +}; + struct clk { + const struct clkops *ops; + unsigned long rate; unsigned int enabled; }; -static void clk_gpio27_enable(void) +#define INIT_CLKREG(_clk, _devname, _conname) \ + { \ + .clk = _clk, \ + .dev_id = _devname, \ + .con_id = _conname, \ + } + +#define DEFINE_CLK(_name, _ops, _rate) \ +struct clk clk_##_name = { \ + .ops = _ops, \ + .rate = _rate, \ + } + +static DEFINE_SPINLOCK(clocks_lock); + +static void clk_gpio27_enable(struct clk *clk) { /* * First, set up the 3.6864MHz clock on GPIO 27 for the SA-1111: @@ -32,38 +54,22 @@ static void clk_gpio27_enable(void) TUCR = TUCR_3_6864MHz; } -static void clk_gpio27_disable(void) +static void clk_gpio27_disable(struct clk *clk) { TUCR = 0; GPDR &= ~GPIO_32_768kHz; GAFR &= ~GPIO_32_768kHz; } -static struct clk clk_gpio27; - -static DEFINE_SPINLOCK(clocks_lock); - -struct clk *clk_get(struct device *dev, const char *id) -{ - const char *devname = dev_name(dev); - - return strcmp(devname, "sa1111.0") ? ERR_PTR(-ENOENT) : &clk_gpio27; -} -EXPORT_SYMBOL(clk_get); - -void clk_put(struct clk *clk) -{ -} -EXPORT_SYMBOL(clk_put); - int clk_enable(struct clk *clk) { unsigned long flags; spin_lock_irqsave(&clocks_lock, flags); if (clk->enabled++ == 0) - clk_gpio27_enable(); + clk->ops->enable(clk); spin_unlock_irqrestore(&clocks_lock, flags); + return 0; } EXPORT_SYMBOL(clk_enable); @@ -76,13 +82,48 @@ void clk_disable(struct clk *clk) spin_lock_irqsave(&clocks_lock, flags); if (--clk->enabled == 0) - clk_gpio27_disable(); + clk->ops->disable(clk); spin_unlock_irqrestore(&clocks_lock, flags); } EXPORT_SYMBOL(clk_disable); unsigned long clk_get_rate(struct clk *clk) { - return 3686400; + unsigned long rate; + + rate = clk->rate; + if (clk->ops->getrate) + rate = clk->ops->getrate(clk); + + return rate; } EXPORT_SYMBOL(clk_get_rate); + +const struct clkops clk_gpio27_ops = { + .enable = clk_gpio27_enable, + .disable = clk_gpio27_disable, +}; + +static void clk_dummy_enable(struct clk *clk) { } +static void clk_dummy_disable(struct clk *clk) { } + +const struct clkops clk_dummy_ops = { + .enable = clk_dummy_enable, + .disable = clk_dummy_disable, +}; + +static DEFINE_CLK(gpio27, &clk_gpio27_ops, 3686400); +static DEFINE_CLK(dummy, &clk_dummy_ops, 0); + +static struct clk_lookup sa11xx_clkregs[] = { + INIT_CLKREG(&clk_gpio27, "sa1111.0", NULL), + INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL), +}; + +static int __init sa11xx_clk_init(void) +{ + clkdev_add_table(sa11xx_clkregs, ARRAY_SIZE(sa11xx_clkregs)); + return 0; +} + +postcore_initcall(sa11xx_clk_init); diff --git a/arch/arm/mach-sa1100/generic.c b/arch/arm/mach-sa1100/generic.c index bb10ee2cb89..480d2ea46b0 100644 --- a/arch/arm/mach-sa1100/generic.c +++ b/arch/arm/mach-sa1100/generic.c @@ -345,9 +345,29 @@ void sa11x0_register_irda(struct irda_platform_data *irda) sa11x0_register_device(&sa11x0ir_device, irda); } +static struct resource sa11x0rtc_resources[] = { + [0] = { + .start = 0x90010000, + .end = 0x900100ff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_RTC1Hz, + .end = IRQ_RTC1Hz, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = IRQ_RTCAlrm, + .end = IRQ_RTCAlrm, + .flags = IORESOURCE_IRQ, + }, +}; + static struct platform_device sa11x0rtc_device = { .name = "sa1100-rtc", .id = -1, + .resource = sa11x0rtc_resources, + .num_resources = ARRAY_SIZE(sa11x0rtc_resources), }; static struct platform_device *sa11x0_devices[] __initdata = { diff --git a/arch/arm/mach-sa1100/pci-nanoengine.c b/arch/arm/mach-sa1100/pci-nanoengine.c index dd39fee5954..0d01ca78892 100644 --- a/arch/arm/mach-sa1100/pci-nanoengine.c +++ b/arch/arm/mach-sa1100/pci-nanoengine.c @@ -131,7 +131,8 @@ static int __init pci_nanoengine_map_irq(const struct pci_dev *dev, u8 slot, struct pci_bus * __init pci_nanoengine_scan_bus(int nr, struct pci_sys_data *sys) { - return pci_scan_bus(sys->busnr, &pci_nano_ops, sys); + return pci_scan_root_bus(NULL, sys->busnr, &pci_nano_ops, sys, + &sys->resources); } static struct resource pci_io_ports = { @@ -226,7 +227,7 @@ static struct resource pci_prefetchable_memory = { .flags = IORESOURCE_MEM | IORESOURCE_PREFETCH, }; -static int __init pci_nanoengine_setup_resources(struct resource **resource) +static int __init pci_nanoengine_setup_resources(struct pci_sys_data *sys) { if (request_resource(&ioport_resource, &pci_io_ports)) { printk(KERN_ERR "PCI: unable to allocate io port region\n"); @@ -243,9 +244,9 @@ static int __init pci_nanoengine_setup_resources(struct resource **resource) printk(KERN_ERR "PCI: unable to allocate prefetchable\n"); return -EBUSY; } - resource[0] = &pci_io_ports; - resource[1] = &pci_non_prefetchable_memory; - resource[2] = &pci_prefetchable_memory; + pci_add_resource(&sys->resources, &pci_io_ports); + pci_add_resource(&sys->resources, &pci_non_prefetchable_memory); + pci_add_resource(&sys->resources, &pci_prefetchable_memory); return 1; } @@ -260,7 +261,7 @@ int __init pci_nanoengine_setup(int nr, struct pci_sys_data *sys) if (nr == 0) { sys->mem_offset = NANO_PCI_MEM_RW_PHYS; sys->io_offset = 0x400; - ret = pci_nanoengine_setup_resources(sys->resource); + ret = pci_nanoengine_setup_resources(sys); /* Enable alternate memory bus master mode, see * "Intel StrongARM SA1110 Developer's Manual", * section 10.8, "Alternate Memory Bus Master Mode". */ diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig index 0828fab2b65..060e5644c49 100644 --- a/arch/arm/mach-shmobile/Kconfig +++ b/arch/arm/mach-shmobile/Kconfig @@ -28,6 +28,19 @@ config ARCH_SH73A0 select ARM_GIC select I2C +config ARCH_R8A7740 + bool "R-Mobile A1 (R8A77400)" + select CPU_V7 + select SH_CLK_CPG + select ARCH_WANT_OPTIONAL_GPIOLIB + +config ARCH_R8A7779 + bool "R-Car H1 (R8A77790)" + select CPU_V7 + select SH_CLK_CPG + select ARM_GIC + select ARCH_WANT_OPTIONAL_GPIOLIB + comment "SH-Mobile Board Type" config MACH_G3EVM @@ -75,6 +88,16 @@ config MACH_KOTA2 select ARCH_REQUIRE_GPIOLIB depends on ARCH_SH73A0 +config MACH_BONITO + bool "bonito board" + select ARCH_REQUIRE_GPIOLIB + depends on ARCH_R8A7740 + +config MACH_MARZEN + bool "MARZEN board" + depends on ARCH_R8A7779 + select ARCH_REQUIRE_GPIOLIB + comment "SH-Mobile System Configuration" menu "Memory configuration" @@ -83,7 +106,7 @@ config MEMORY_START hex "Physical memory start address" default "0x50000000" if MACH_G3EVM default "0x40000000" if MACH_G4EVM || MACH_AP4EVB || MACH_AG5EVM || \ - MACH_MACKEREL + MACH_MACKEREL || MACH_BONITO default "0x41000000" if MACH_KOTA2 default "0x00000000" ---help--- @@ -95,7 +118,7 @@ config MEMORY_SIZE hex "Physical memory size" default "0x08000000" if MACH_G3EVM default "0x08000000" if MACH_G4EVM - default "0x20000000" if MACH_AG5EVM + default "0x20000000" if MACH_AG5EVM || MACH_BONITO default "0x1e000000" if MACH_KOTA2 default "0x10000000" if MACH_AP4EVB || MACH_MACKEREL default "0x04000000" diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile index 5ca1f9d6699..7ad6954c46c 100644 --- a/arch/arm/mach-shmobile/Makefile +++ b/arch/arm/mach-shmobile/Makefile @@ -10,12 +10,15 @@ obj-$(CONFIG_ARCH_SH7367) += setup-sh7367.o clock-sh7367.o intc-sh7367.o obj-$(CONFIG_ARCH_SH7377) += setup-sh7377.o clock-sh7377.o intc-sh7377.o obj-$(CONFIG_ARCH_SH7372) += setup-sh7372.o clock-sh7372.o intc-sh7372.o obj-$(CONFIG_ARCH_SH73A0) += setup-sh73a0.o clock-sh73a0.o intc-sh73a0.o +obj-$(CONFIG_ARCH_R8A7740) += setup-r8a7740.o clock-r8a7740.o intc-r8a7740.o +obj-$(CONFIG_ARCH_R8A7779) += setup-r8a7779.o clock-r8a7779.o intc-r8a7779.o # SMP objects smp-y := platsmp.o headsmp.o smp-$(CONFIG_HOTPLUG_CPU) += hotplug.o smp-$(CONFIG_LOCAL_TIMERS) += localtimer.o smp-$(CONFIG_ARCH_SH73A0) += smp-sh73a0.o +smp-$(CONFIG_ARCH_R8A7779) += smp-r8a7779.o # Pinmux setup pfc-y := @@ -23,16 +26,20 @@ pfc-$(CONFIG_ARCH_SH7367) += pfc-sh7367.o pfc-$(CONFIG_ARCH_SH7377) += pfc-sh7377.o pfc-$(CONFIG_ARCH_SH7372) += pfc-sh7372.o pfc-$(CONFIG_ARCH_SH73A0) += pfc-sh73a0.o +pfc-$(CONFIG_ARCH_R8A7740) += pfc-r8a7740.o +pfc-$(CONFIG_ARCH_R8A7779) += pfc-r8a7779.o # IRQ objects obj-$(CONFIG_ARCH_SH7367) += entry-intc.o obj-$(CONFIG_ARCH_SH7377) += entry-intc.o obj-$(CONFIG_ARCH_SH7372) += entry-intc.o +obj-$(CONFIG_ARCH_R8A7740) += entry-intc.o # PM objects obj-$(CONFIG_SUSPEND) += suspend.o obj-$(CONFIG_CPU_IDLE) += cpuidle.o obj-$(CONFIG_ARCH_SH7372) += pm-sh7372.o sleep-sh7372.o +obj-$(CONFIG_ARCH_R8A7779) += pm-r8a7779.o # Board objects obj-$(CONFIG_MACH_G3EVM) += board-g3evm.o @@ -41,6 +48,8 @@ obj-$(CONFIG_MACH_AP4EVB) += board-ap4evb.o obj-$(CONFIG_MACH_AG5EVM) += board-ag5evm.o obj-$(CONFIG_MACH_MACKEREL) += board-mackerel.o obj-$(CONFIG_MACH_KOTA2) += board-kota2.o +obj-$(CONFIG_MACH_BONITO) += board-bonito.o +obj-$(CONFIG_MACH_MARZEN) += board-marzen.o # Framework support obj-$(CONFIG_SMP) += $(smp-y) diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c index 6a6f9f7568c..d2e7b73aa9b 100644 --- a/arch/arm/mach-shmobile/board-ap4evb.c +++ b/arch/arm/mach-shmobile/board-ap4evb.c @@ -762,9 +762,22 @@ static struct platform_device fsi_device = { }, }; +static struct fsi_ak4642_info fsi2_ak4643_info = { + .name = "AK4643", + .card = "FSI2A-AK4643", + .cpu_dai = "fsia-dai", + .codec = "ak4642-codec.0-0013", + .platform = "sh_fsi2", + .id = FSI_PORT_A, +}; + static struct platform_device fsi_ak4643_device = { - .name = "sh_fsi2_a_ak4643", + .name = "fsi-ak4642-audio", + .dev = { + .platform_data = &fsi_info, + }, }; + static struct sh_mobile_meram_cfg hdmi_meram_cfg = { .icb[0] = { .marker_icb = 30, diff --git a/arch/arm/mach-shmobile/board-bonito.c b/arch/arm/mach-shmobile/board-bonito.c new file mode 100644 index 00000000000..4d220162232 --- /dev/null +++ b/arch/arm/mach-shmobile/board-bonito.c @@ -0,0 +1,522 @@ +/* + * bonito board support + * + * Copyright (C) 2011 Renesas Solutions Corp. + * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +#include <linux/kernel.h> +#include <linux/i2c.h> +#include <linux/init.h> +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/platform_device.h> +#include <linux/gpio.h> +#include <linux/smsc911x.h> +#include <mach/common.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/map.h> +#include <asm/mach/time.h> +#include <asm/hardware/cache-l2x0.h> +#include <mach/r8a7740.h> +#include <video/sh_mobile_lcdc.h> + +/* + * CS Address device note + *---------------------------------------------------------------- + * 0 0x0000_0000 NOR Flash (64MB) SW12 : bit3 = OFF + * 2 0x0800_0000 ExtNOR (64MB) SW12 : bit3 = OFF + * 4 - + * 5A - + * 5B 0x1600_0000 SRAM (8MB) + * 6 0x1800_0000 FPGA (64K) + * 0x1801_0000 Ether (4KB) + * 0x1801_1000 USB (4KB) + */ + +/* + * SW12 + * + * bit1 bit2 bit3 + *---------------------------------------------------------------------------- + * ON NOR WriteProtect NAND WriteProtect CS0 ExtNOR / CS2 NOR + * OFF NOR Not WriteProtect NAND Not WriteProtect CS0 NOR / CS2 ExtNOR + */ + +/* + * SCIFA5 (CN42) + * + * S38.3 = ON + * S39.6 = ON + * S43.1 = ON + */ + +/* + * LCDC0 (CN3/CN4/CN7) + * + * S38.1 = OFF + * S38.2 = OFF + */ + +/* + * FPGA + */ +#define IRQSR0 0x0020 +#define IRQSR1 0x0022 +#define IRQMR0 0x0030 +#define IRQMR1 0x0032 +#define BUSSWMR1 0x0070 +#define BUSSWMR2 0x0072 +#define BUSSWMR3 0x0074 +#define BUSSWMR4 0x0076 + +#define LCDCR 0x10B4 +#define DEVRSTCR1 0x10D0 +#define DEVRSTCR2 0x10D2 +#define A1MDSR 0x10E0 +#define BVERR 0x1100 + +/* FPGA IRQ */ +#define FPGA_IRQ_BASE (512) +#define FPGA_IRQ0 (FPGA_IRQ_BASE) +#define FPGA_IRQ1 (FPGA_IRQ_BASE + 16) +#define FPGA_ETH_IRQ (FPGA_IRQ0 + 15) +static u16 bonito_fpga_read(u32 offset) +{ + return __raw_readw(0xf0003000 + offset); +} + +static void bonito_fpga_write(u32 offset, u16 val) +{ + __raw_writew(val, 0xf0003000 + offset); +} + +static void bonito_fpga_irq_disable(struct irq_data *data) +{ + unsigned int irq = data->irq; + u32 addr = (irq < 1016) ? IRQMR0 : IRQMR1; + int shift = irq % 16; + + bonito_fpga_write(addr, bonito_fpga_read(addr) | (1 << shift)); +} + +static void bonito_fpga_irq_enable(struct irq_data *data) +{ + unsigned int irq = data->irq; + u32 addr = (irq < 1016) ? IRQMR0 : IRQMR1; + int shift = irq % 16; + + bonito_fpga_write(addr, bonito_fpga_read(addr) & ~(1 << shift)); +} + +static struct irq_chip bonito_fpga_irq_chip __read_mostly = { + .name = "bonito FPGA", + .irq_mask = bonito_fpga_irq_disable, + .irq_unmask = bonito_fpga_irq_enable, +}; + +static void bonito_fpga_irq_demux(unsigned int irq, struct irq_desc *desc) +{ + u32 val = bonito_fpga_read(IRQSR1) << 16 | + bonito_fpga_read(IRQSR0); + u32 mask = bonito_fpga_read(IRQMR1) << 16 | + bonito_fpga_read(IRQMR0); + + int i; + + val &= ~mask; + + for (i = 0; i < 32; i++) { + if (!(val & (1 << i))) + continue; + + generic_handle_irq(FPGA_IRQ_BASE + i); + } +} + +static void bonito_fpga_init(void) +{ + int i; + + bonito_fpga_write(IRQMR0, 0xffff); /* mask all */ + bonito_fpga_write(IRQMR1, 0xffff); /* mask all */ + + /* Device reset */ + bonito_fpga_write(DEVRSTCR1, + (1 << 2)); /* Eth */ + + /* FPGA irq require special handling */ + for (i = FPGA_IRQ_BASE; i < FPGA_IRQ_BASE + 32; i++) { + irq_set_chip_and_handler_name(i, &bonito_fpga_irq_chip, + handle_level_irq, "level"); + set_irq_flags(i, IRQF_VALID); /* yuck */ + } + + irq_set_chained_handler(evt2irq(0x0340), bonito_fpga_irq_demux); + irq_set_irq_type(evt2irq(0x0340), IRQ_TYPE_LEVEL_LOW); +} + +/* +* PMIC settings +* +* FIXME +* +* bonito board needs some settings by pmic which use i2c access. +* pmic settings use device_initcall() here for use it. +*/ +static __u8 *pmic_settings = NULL; +static __u8 pmic_do_2A[] = { + 0x1C, 0x09, + 0x1A, 0x80, + 0xff, 0xff, +}; + +static int __init pmic_init(void) +{ + struct i2c_adapter *a = i2c_get_adapter(0); + struct i2c_msg msg; + __u8 buf[2]; + int i, ret; + + if (!pmic_settings) + return 0; + if (!a) + return 0; + + msg.addr = 0x46; + msg.buf = buf; + msg.len = 2; + msg.flags = 0; + + for (i = 0; ; i += 2) { + buf[0] = pmic_settings[i + 0]; + buf[1] = pmic_settings[i + 1]; + + if ((0xff == buf[0]) && (0xff == buf[1])) + break; + + ret = i2c_transfer(a, &msg, 1); + if (ret < 0) { + pr_err("i2c transfer fail\n"); + break; + } + } + + return 0; +} +device_initcall(pmic_init); + +/* + * LCDC0 + */ +static const struct fb_videomode lcdc0_mode = { + .name = "WVGA Panel", + .xres = 800, + .yres = 480, + .left_margin = 88, + .right_margin = 40, + .hsync_len = 128, + .upper_margin = 20, + .lower_margin = 5, + .vsync_len = 5, + .sync = 0, +}; + +static struct sh_mobile_lcdc_info lcdc0_info = { + .clock_source = LCDC_CLK_BUS, + .ch[0] = { + .chan = LCDC_CHAN_MAINLCD, + .bpp = 16, + .interface_type = RGB24, + .clock_divider = 5, + .flags = 0, + .lcd_cfg = &lcdc0_mode, + .num_cfg = 1, + .lcd_size_cfg = { + .width = 152, + .height = 91, + }, + }, +}; + +static struct resource lcdc0_resources[] = { + [0] = { + .name = "LCDC0", + .start = 0xfe940000, + .end = 0xfe943fff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = intcs_evt2irq(0x0580), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device lcdc0_device = { + .name = "sh_mobile_lcdc_fb", + .id = 0, + .resource = lcdc0_resources, + .num_resources = ARRAY_SIZE(lcdc0_resources), + .dev = { + .platform_data = &lcdc0_info, + .coherent_dma_mask = ~0, + }, +}; + +/* + * SMSC 9221 + */ +static struct resource smsc_resources[] = { + [0] = { + .start = 0x18010000, + .end = 0x18011000 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = FPGA_ETH_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct smsc911x_platform_config smsc_platdata = { + .flags = SMSC911X_USE_16BIT, + .phy_interface = PHY_INTERFACE_MODE_MII, + .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, + .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, +}; + +static struct platform_device smsc_device = { + .name = "smsc911x", + .dev = { + .platform_data = &smsc_platdata, + }, + .resource = smsc_resources, + .num_resources = ARRAY_SIZE(smsc_resources), +}; + +/* + * core board devices + */ +static struct platform_device *bonito_core_devices[] __initdata = { +}; + +/* + * base board devices + */ +static struct platform_device *bonito_base_devices[] __initdata = { + &lcdc0_device, + &smsc_device, +}; + +/* + * map I/O + */ +static struct map_desc bonito_io_desc[] __initdata = { + /* + * for CPGA/INTC/PFC + * 0xe6000000-0xefffffff -> 0xe6000000-0xefffffff + */ + { + .virtual = 0xe6000000, + .pfn = __phys_to_pfn(0xe6000000), + .length = 160 << 20, + .type = MT_DEVICE_NONSHARED + }, +#ifdef CONFIG_CACHE_L2X0 + /* + * for l2x0_init() + * 0xf0100000-0xf0101000 -> 0xf0002000-0xf0003000 + */ + { + .virtual = 0xf0002000, + .pfn = __phys_to_pfn(0xf0100000), + .length = PAGE_SIZE, + .type = MT_DEVICE_NONSHARED + }, +#endif + /* + * for FPGA (0x1800000-0x19ffffff) + * 0x18000000-0x18002000 -> 0xf0003000-0xf0005000 + */ + { + .virtual = 0xf0003000, + .pfn = __phys_to_pfn(0x18000000), + .length = PAGE_SIZE * 2, + .type = MT_DEVICE_NONSHARED + } +}; + +static void __init bonito_map_io(void) +{ + iotable_init(bonito_io_desc, ARRAY_SIZE(bonito_io_desc)); + + /* setup early devices and console here as well */ + r8a7740_add_early_devices(); + shmobile_setup_console(); +} + +/* + * board init + */ +#define BIT_ON(sw, bit) (sw & (1 << bit)) +#define BIT_OFF(sw, bit) (!(sw & (1 << bit))) + +#define VCCQ1CR 0xE6058140 +#define VCCQ1LCDCR 0xE6058186 + +static void __init bonito_init(void) +{ + u16 val; + + r8a7740_pinmux_init(); + bonito_fpga_init(); + + pmic_settings = pmic_do_2A; + + /* + * core board settings + */ + +#ifdef CONFIG_CACHE_L2X0 + /* Early BRESP enable, Shared attribute override enable, 32K*8way */ + l2x0_init(__io(0xf0002000), 0x40440000, 0x82000fff); +#endif + + r8a7740_add_standard_devices(); + + platform_add_devices(bonito_core_devices, + ARRAY_SIZE(bonito_core_devices)); + + /* + * base board settings + */ + gpio_request(GPIO_PORT176, NULL); + gpio_direction_input(GPIO_PORT176); + if (!gpio_get_value(GPIO_PORT176)) { + u16 bsw2; + u16 bsw3; + u16 bsw4; + + /* + * FPGA + */ + gpio_request(GPIO_FN_CS5B, NULL); + gpio_request(GPIO_FN_CS6A, NULL); + gpio_request(GPIO_FN_CS5A_PORT105, NULL); + gpio_request(GPIO_FN_IRQ10, NULL); + + val = bonito_fpga_read(BVERR); + pr_info("bonito version: cpu %02x, base %02x\n", + ((val >> 8) & 0xFF), + ((val >> 0) & 0xFF)); + + bsw2 = bonito_fpga_read(BUSSWMR2); + bsw3 = bonito_fpga_read(BUSSWMR3); + bsw4 = bonito_fpga_read(BUSSWMR4); + + /* + * SCIFA5 (CN42) + */ + if (BIT_OFF(bsw2, 1) && /* S38.3 = ON */ + BIT_OFF(bsw3, 9) && /* S39.6 = ON */ + BIT_OFF(bsw4, 4)) { /* S43.1 = ON */ + gpio_request(GPIO_FN_SCIFA5_TXD_PORT91, NULL); + gpio_request(GPIO_FN_SCIFA5_RXD_PORT92, NULL); + } + + /* + * LCDC0 (CN3) + */ + if (BIT_ON(bsw2, 3) && /* S38.1 = OFF */ + BIT_ON(bsw2, 2)) { /* S38.2 = OFF */ + gpio_request(GPIO_FN_LCDC0_SELECT, NULL); + gpio_request(GPIO_FN_LCD0_D0, NULL); + gpio_request(GPIO_FN_LCD0_D1, NULL); + gpio_request(GPIO_FN_LCD0_D2, NULL); + gpio_request(GPIO_FN_LCD0_D3, NULL); + gpio_request(GPIO_FN_LCD0_D4, NULL); + gpio_request(GPIO_FN_LCD0_D5, NULL); + gpio_request(GPIO_FN_LCD0_D6, NULL); + gpio_request(GPIO_FN_LCD0_D7, NULL); + gpio_request(GPIO_FN_LCD0_D8, NULL); + gpio_request(GPIO_FN_LCD0_D9, NULL); + gpio_request(GPIO_FN_LCD0_D10, NULL); + gpio_request(GPIO_FN_LCD0_D11, NULL); + gpio_request(GPIO_FN_LCD0_D12, NULL); + gpio_request(GPIO_FN_LCD0_D13, NULL); + gpio_request(GPIO_FN_LCD0_D14, NULL); + gpio_request(GPIO_FN_LCD0_D15, NULL); + gpio_request(GPIO_FN_LCD0_D16, NULL); + gpio_request(GPIO_FN_LCD0_D17, NULL); + gpio_request(GPIO_FN_LCD0_D18_PORT163, NULL); + gpio_request(GPIO_FN_LCD0_D19_PORT162, NULL); + gpio_request(GPIO_FN_LCD0_D20_PORT161, NULL); + gpio_request(GPIO_FN_LCD0_D21_PORT158, NULL); + gpio_request(GPIO_FN_LCD0_D22_PORT160, NULL); + gpio_request(GPIO_FN_LCD0_D23_PORT159, NULL); + gpio_request(GPIO_FN_LCD0_DCK, NULL); + gpio_request(GPIO_FN_LCD0_VSYN, NULL); + gpio_request(GPIO_FN_LCD0_HSYN, NULL); + gpio_request(GPIO_FN_LCD0_DISP, NULL); + gpio_request(GPIO_FN_LCD0_LCLK_PORT165, NULL); + + gpio_request(GPIO_PORT61, NULL); /* LCDDON */ + gpio_direction_output(GPIO_PORT61, 1); + + /* backlight on */ + bonito_fpga_write(LCDCR, 1); + + /* drivability Max */ + __raw_writew(0x00FF , VCCQ1LCDCR); + __raw_writew(0xFFFF , VCCQ1CR); + } + + platform_add_devices(bonito_base_devices, + ARRAY_SIZE(bonito_base_devices)); + } +} + +static void __init bonito_timer_init(void) +{ + u16 val; + u8 md_ck = 0; + + /* read MD_CK value */ + val = bonito_fpga_read(A1MDSR); + if (val & (1 << 10)) + md_ck |= MD_CK2; + if (val & (1 << 9)) + md_ck |= MD_CK1; + if (val & (1 << 8)) + md_ck |= MD_CK0; + + r8a7740_clock_init(md_ck); + shmobile_timer.init(); +} + +struct sys_timer bonito_timer = { + .init = bonito_timer_init, +}; + +MACHINE_START(BONITO, "bonito") + .map_io = bonito_map_io, + .init_irq = r8a7740_init_irq, + .handle_irq = shmobile_handle_irq_intc, + .init_machine = bonito_init, + .timer = &bonito_timer, +MACHINE_END diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c index ed525668739..cbc5934ae03 100644 --- a/arch/arm/mach-shmobile/board-mackerel.c +++ b/arch/arm/mach-shmobile/board-mackerel.c @@ -990,8 +990,20 @@ static struct platform_device fsi_device = { }, }; +static struct fsi_ak4642_info fsi2_ak4643_info = { + .name = "AK4643", + .card = "FSI2A-AK4643", + .cpu_dai = "fsia-dai", + .codec = "ak4642-codec.0-0013", + .platform = "sh_fsi2", + .id = FSI_PORT_A, +}; + static struct platform_device fsi_ak4643_device = { - .name = "sh_fsi2_a_ak4643", + .name = "fsi-ak4642-audio", + .dev = { + .platform_data = &fsi2_ak4643_info, + }, }; /* diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c new file mode 100644 index 00000000000..f0e02c0ce99 --- /dev/null +++ b/arch/arm/mach-shmobile/board-marzen.c @@ -0,0 +1,157 @@ +/* + * marzen board support + * + * Copyright (C) 2011 Renesas Solutions Corp. + * Copyright (C) 2011 Magnus Damm + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/platform_device.h> +#include <linux/delay.h> +#include <linux/io.h> +#include <linux/gpio.h> +#include <linux/dma-mapping.h> +#include <linux/smsc911x.h> +#include <mach/hardware.h> +#include <mach/r8a7779.h> +#include <mach/common.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/map.h> +#include <asm/mach/time.h> +#include <asm/hardware/gic.h> +#include <asm/traps.h> + +/* SMSC LAN89218 */ +static struct resource smsc911x_resources[] = { + [0] = { + .start = 0x18000000, /* ExCS0 */ + .end = 0x180000ff, /* A1->A7 */ + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = gic_spi(28), /* IRQ 1 */ + .flags = IORESOURCE_IRQ, + }, +}; + +static struct smsc911x_platform_config smsc911x_platdata = { + .flags = SMSC911X_USE_32BIT, /* 32-bit SW on 16-bit HW bus */ + .phy_interface = PHY_INTERFACE_MODE_MII, + .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, + .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, +}; + +static struct platform_device eth_device = { + .name = "smsc911x", + .id = 0, + .dev = { + .platform_data = &smsc911x_platdata, + }, + .resource = smsc911x_resources, + .num_resources = ARRAY_SIZE(smsc911x_resources), +}; + +static struct platform_device *marzen_devices[] __initdata = { + ð_device, +}; + +static struct map_desc marzen_io_desc[] __initdata = { + /* 2M entity map for 0xf0000000 (MPCORE) */ + { + .virtual = 0xf0000000, + .pfn = __phys_to_pfn(0xf0000000), + .length = SZ_2M, + .type = MT_DEVICE_NONSHARED + }, + /* 16M entity map for 0xfexxxxxx (DMAC-S/HPBREG/INTC2/LRAM/DBSC) */ + { + .virtual = 0xfe000000, + .pfn = __phys_to_pfn(0xfe000000), + .length = SZ_16M, + .type = MT_DEVICE_NONSHARED + }, +}; + +static void __init marzen_map_io(void) +{ + iotable_init(marzen_io_desc, ARRAY_SIZE(marzen_io_desc)); +} + +static void __init marzen_init_early(void) +{ + r8a7779_add_early_devices(); + + /* Early serial console setup is not included here due to + * memory map collisions. The SCIF serial ports in r8a7779 + * are difficult to entity map 1:1 due to collision with the + * virtual memory range used by the coherent DMA code on ARM. + * + * Anyone wanting to debug early can remove UPF_IOREMAP from + * the sh-sci serial console platform data, adjust mapbase + * to a static M:N virt:phys mapping that needs to be added to + * the mappings passed with iotable_init() above. + * + * Then add a call to shmobile_setup_console() from this function. + * + * As a final step pass earlyprint=sh-sci.2,115200 on the kernel + * command line. + */ +} + +static void __init marzen_init(void) +{ + r8a7779_pinmux_init(); + + /* SCIF2 (CN18: DEBUG0) */ + gpio_request(GPIO_FN_TX2_C, NULL); + gpio_request(GPIO_FN_RX2_C, NULL); + + /* SCIF4 (CN19: DEBUG1) */ + gpio_request(GPIO_FN_TX4, NULL); + gpio_request(GPIO_FN_RX4, NULL); + + /* LAN89218 */ + gpio_request(GPIO_FN_EX_CS0, NULL); /* nCS */ + gpio_request(GPIO_FN_IRQ1_B, NULL); /* IRQ + PME */ + + r8a7779_add_standard_devices(); + platform_add_devices(marzen_devices, ARRAY_SIZE(marzen_devices)); +} + +static void __init marzen_timer_init(void) +{ + r8a7779_clock_init(); + shmobile_timer.init(); + return; +} + +struct sys_timer marzen_timer = { + .init = marzen_timer_init, +}; + +MACHINE_START(MARZEN, "marzen") + .map_io = marzen_map_io, + .init_early = marzen_init_early, + .nr_irqs = NR_IRQS_LEGACY, + .init_irq = r8a7779_init_irq, + .handle_irq = gic_handle_irq, + .init_machine = marzen_init, + .timer = &marzen_timer, +MACHINE_END diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c new file mode 100644 index 00000000000..3b35b9afc00 --- /dev/null +++ b/arch/arm/mach-shmobile/clock-r8a7740.c @@ -0,0 +1,382 @@ +/* + * R8A7740 processor support + * + * Copyright (C) 2011 Renesas Solutions Corp. + * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/io.h> +#include <linux/sh_clk.h> +#include <linux/clkdev.h> +#include <mach/common.h> +#include <mach/r8a7740.h> + +/* + * | MDx | XTAL1/EXTAL1 | System | EXTALR | + * Clock |-------+-----------------+ clock | 32.768 | RCLK + * Mode | 2/1/0 | src MHz | source | KHz | source + * -------+-------+-----------------+-----------+--------+---------- + * 0 | 0 0 0 | External 20~50 | XTAL1 | O | EXTALR + * 1 | 0 0 1 | Crystal 20~30 | XTAL1 | O | EXTALR + * 2 | 0 1 0 | External 40~50 | XTAL1 / 2 | O | EXTALR + * 3 | 0 1 1 | Crystal 40~50 | XTAL1 / 2 | O | EXTALR + * 4 | 1 0 0 | External 20~50 | XTAL1 | x | XTAL1 / 1024 + * 5 | 1 0 1 | Crystal 20~30 | XTAL1 | x | XTAL1 / 1024 + * 6 | 1 1 0 | External 40~50 | XTAL1 / 2 | x | XTAL1 / 2048 + * 7 | 1 1 1 | Crystal 40~50 | XTAL1 / 2 | x | XTAL1 / 2048 + */ + +/* CPG registers */ +#define FRQCRA 0xe6150000 +#define FRQCRB 0xe6150004 +#define FRQCRC 0xe61500e0 +#define PLLC01CR 0xe6150028 + +#define SUBCKCR 0xe6150080 + +#define MSTPSR0 0xe6150030 +#define MSTPSR1 0xe6150038 +#define MSTPSR2 0xe6150040 +#define MSTPSR3 0xe6150048 +#define MSTPSR4 0xe615004c +#define SMSTPCR0 0xe6150130 +#define SMSTPCR1 0xe6150134 +#define SMSTPCR2 0xe6150138 +#define SMSTPCR3 0xe615013c +#define SMSTPCR4 0xe6150140 + +/* Fixed 32 KHz root clock from EXTALR pin */ +static struct clk extalr_clk = { + .rate = 32768, +}; + +/* + * 25MHz default rate for the EXTAL1 root input clock. + * If needed, reset this with clk_set_rate() from the platform code. + */ +static struct clk extal1_clk = { + .rate = 25000000, +}; + +/* + * 48MHz default rate for the EXTAL2 root input clock. + * If needed, reset this with clk_set_rate() from the platform code. + */ +static struct clk extal2_clk = { + .rate = 48000000, +}; + +/* + * 27MHz default rate for the DV_CLKI root input clock. + * If needed, reset this with clk_set_rate() from the platform code. + */ +static struct clk dv_clk = { + .rate = 27000000, +}; + +static unsigned long div_recalc(struct clk *clk) +{ + return clk->parent->rate / (int)(clk->priv); +} + +static struct clk_ops div_clk_ops = { + .recalc = div_recalc, +}; + +/* extal1 / 2 */ +static struct clk extal1_div2_clk = { + .ops = &div_clk_ops, + .priv = (void *)2, + .parent = &extal1_clk, +}; + +/* extal1 / 1024 */ +static struct clk extal1_div1024_clk = { + .ops = &div_clk_ops, + .priv = (void *)1024, + .parent = &extal1_clk, +}; + +/* extal1 / 2 / 1024 */ +static struct clk extal1_div2048_clk = { + .ops = &div_clk_ops, + .priv = (void *)1024, + .parent = &extal1_div2_clk, +}; + +/* extal2 / 2 */ +static struct clk extal2_div2_clk = { + .ops = &div_clk_ops, + .priv = (void *)2, + .parent = &extal2_clk, +}; + +static struct clk_ops followparent_clk_ops = { + .recalc = followparent_recalc, +}; + +/* Main clock */ +static struct clk system_clk = { + .ops = &followparent_clk_ops, +}; + +static struct clk system_div2_clk = { + .ops = &div_clk_ops, + .priv = (void *)2, + .parent = &system_clk, +}; + +/* r_clk */ +static struct clk r_clk = { + .ops = &followparent_clk_ops, +}; + +/* PLLC0/PLLC1 */ +static unsigned long pllc01_recalc(struct clk *clk) +{ + unsigned long mult = 1; + + if (__raw_readl(PLLC01CR) & (1 << 14)) + mult = ((__raw_readl(clk->enable_reg) >> 24) & 0x7f) + 1; + + return clk->parent->rate * mult; +} + +static struct clk_ops pllc01_clk_ops = { + .recalc = pllc01_recalc, +}; + +static struct clk pllc0_clk = { + .ops = &pllc01_clk_ops, + .flags = CLK_ENABLE_ON_INIT, + .parent = &system_clk, + .enable_reg = (void __iomem *)FRQCRC, +}; + +static struct clk pllc1_clk = { + .ops = &pllc01_clk_ops, + .flags = CLK_ENABLE_ON_INIT, + .parent = &system_div2_clk, + .enable_reg = (void __iomem *)FRQCRA, +}; + +/* PLLC1 / 2 */ +static struct clk pllc1_div2_clk = { + .ops = &div_clk_ops, + .priv = (void *)2, + .parent = &pllc1_clk, +}; + +struct clk *main_clks[] = { + &extalr_clk, + &extal1_clk, + &extal2_clk, + &extal1_div2_clk, + &extal1_div1024_clk, + &extal1_div2048_clk, + &extal2_div2_clk, + &dv_clk, + &system_clk, + &system_div2_clk, + &r_clk, + &pllc0_clk, + &pllc1_clk, + &pllc1_div2_clk, +}; + +static void div4_kick(struct clk *clk) +{ + unsigned long value; + + /* set KICK bit in FRQCRB to update hardware setting */ + value = __raw_readl(FRQCRB); + value |= (1 << 31); + __raw_writel(value, FRQCRB); +} + +static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18, + 24, 32, 36, 48, 0, 72, 96, 0 }; + +static struct clk_div_mult_table div4_div_mult_table = { + .divisors = divisors, + .nr_divisors = ARRAY_SIZE(divisors), +}; + +static struct clk_div4_table div4_table = { + .div_mult_table = &div4_div_mult_table, + .kick = div4_kick, +}; + +enum { + DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_HP, + DIV4_HPP, DIV4_S, DIV4_ZB, DIV4_M3, DIV4_CP, + DIV4_NR +}; + +struct clk div4_clks[DIV4_NR] = { + [DIV4_I] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 20, 0x6fff, CLK_ENABLE_ON_INIT), + [DIV4_ZG] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 16, 0x6fff, CLK_ENABLE_ON_INIT), + [DIV4_B] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 8, 0x6fff, CLK_ENABLE_ON_INIT), + [DIV4_M1] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 4, 0x6fff, CLK_ENABLE_ON_INIT), + [DIV4_HP] = SH_CLK_DIV4(&pllc1_clk, FRQCRB, 4, 0x6fff, 0), + [DIV4_HPP] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 20, 0x6fff, 0), + [DIV4_S] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 12, 0x6fff, 0), + [DIV4_ZB] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 8, 0x6fff, 0), + [DIV4_M3] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 4, 0x6fff, 0), + [DIV4_CP] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 0, 0x6fff, 0), +}; + +enum { + DIV6_SUB, + DIV6_NR +}; + +static struct clk div6_clks[DIV6_NR] = { + [DIV6_SUB] = SH_CLK_DIV6(&pllc1_div2_clk, SUBCKCR, 0), +}; + +enum { + MSTP125, + MSTP116, MSTP111, MSTP100, MSTP117, + + MSTP230, + MSTP222, + MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200, + + MSTP329, MSTP323, + + MSTP_NR +}; + +static struct clk mstp_clks[MSTP_NR] = { + [MSTP125] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR1, 25, 0), /* TMU0 */ + [MSTP117] = SH_CLK_MSTP32(&div4_clks[DIV4_B], SMSTPCR1, 17, 0), /* LCDC1 */ + [MSTP116] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR1, 16, 0), /* IIC0 */ + [MSTP111] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR1, 11, 0), /* TMU1 */ + [MSTP100] = SH_CLK_MSTP32(&div4_clks[DIV4_B], SMSTPCR1, 0, 0), /* LCDC0 */ + + [MSTP230] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 30, 0), /* SCIFA6 */ + [MSTP222] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 22, 0), /* SCIFA7 */ + [MSTP207] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 7, 0), /* SCIFA5 */ + [MSTP206] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 6, 0), /* SCIFB */ + [MSTP204] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 4, 0), /* SCIFA0 */ + [MSTP203] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 3, 0), /* SCIFA1 */ + [MSTP202] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 2, 0), /* SCIFA2 */ + [MSTP201] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 1, 0), /* SCIFA3 */ + [MSTP200] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 0, 0), /* SCIFA4 */ + + [MSTP329] = SH_CLK_MSTP32(&r_clk, SMSTPCR3, 29, 0), /* CMT10 */ + [MSTP323] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR3, 23, 0), /* IIC1 */ +}; + +static struct clk_lookup lookups[] = { + /* main clocks */ + CLKDEV_CON_ID("extalr", &extalr_clk), + CLKDEV_CON_ID("extal1", &extal1_clk), + CLKDEV_CON_ID("extal2", &extal2_clk), + CLKDEV_CON_ID("extal1_div2", &extal1_div2_clk), + CLKDEV_CON_ID("extal1_div1024", &extal1_div1024_clk), + CLKDEV_CON_ID("extal1_div2048", &extal1_div2048_clk), + CLKDEV_CON_ID("extal2_div2", &extal2_div2_clk), + CLKDEV_CON_ID("dv_clk", &dv_clk), + CLKDEV_CON_ID("system_clk", &system_clk), + CLKDEV_CON_ID("system_div2_clk", &system_div2_clk), + CLKDEV_CON_ID("r_clk", &r_clk), + CLKDEV_CON_ID("pllc0_clk", &pllc0_clk), + CLKDEV_CON_ID("pllc1_clk", &pllc1_clk), + CLKDEV_CON_ID("pllc1_div2_clk", &pllc1_div2_clk), + + /* DIV4 clocks */ + CLKDEV_CON_ID("i_clk", &div4_clks[DIV4_I]), + CLKDEV_CON_ID("zg_clk", &div4_clks[DIV4_ZG]), + CLKDEV_CON_ID("b_clk", &div4_clks[DIV4_B]), + CLKDEV_CON_ID("m1_clk", &div4_clks[DIV4_M1]), + CLKDEV_CON_ID("hp_clk", &div4_clks[DIV4_HP]), + CLKDEV_CON_ID("hpp_clk", &div4_clks[DIV4_HPP]), + CLKDEV_CON_ID("s_clk", &div4_clks[DIV4_S]), + CLKDEV_CON_ID("zb_clk", &div4_clks[DIV4_ZB]), + CLKDEV_CON_ID("m3_clk", &div4_clks[DIV4_M3]), + CLKDEV_CON_ID("cp_clk", &div4_clks[DIV4_CP]), + + /* DIV6 clocks */ + CLKDEV_CON_ID("sub_clk", &div6_clks[DIV6_SUB]), + + /* MSTP32 clocks */ + CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &mstp_clks[MSTP100]), + CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP111]), + CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), + CLKDEV_DEV_ID("sh_mobile_lcdc_fb.1", &mstp_clks[MSTP117]), + CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP125]), + + CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]), + CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP201]), + CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP202]), + CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), + CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), + CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP206]), + CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]), + + CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP222]), + CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP230]), + + CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]), + CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), +}; + +void __init r8a7740_clock_init(u8 md_ck) +{ + int k, ret = 0; + + /* detect system clock parent */ + if (md_ck & MD_CK1) + system_clk.parent = &extal1_div2_clk; + else + system_clk.parent = &extal1_clk; + + /* detect RCLK parent */ + switch (md_ck & (MD_CK2 | MD_CK1)) { + case MD_CK2 | MD_CK1: + r_clk.parent = &extal1_div2048_clk; + break; + case MD_CK2: + r_clk.parent = &extal1_div1024_clk; + break; + case MD_CK1: + default: + r_clk.parent = &extalr_clk; + break; + } + + for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) + ret = clk_register(main_clks[k]); + + if (!ret) + ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); + + if (!ret) + ret = sh_clk_div6_register(div6_clks, DIV6_NR); + + if (!ret) + ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR); + + clkdev_add_table(lookups, ARRAY_SIZE(lookups)); + + if (!ret) + clk_init(); + else + panic("failed to setup r8a7740 clocks\n"); +} diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c new file mode 100644 index 00000000000..b4b0e8cd096 --- /dev/null +++ b/arch/arm/mach-shmobile/clock-r8a7779.c @@ -0,0 +1,176 @@ +/* + * r8a7779 clock framework support + * + * Copyright (C) 2011 Renesas Solutions Corp. + * Copyright (C) 2011 Magnus Damm + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/io.h> +#include <linux/sh_clk.h> +#include <linux/clkdev.h> +#include <mach/common.h> + +#define FRQMR 0xffc80014 +#define MSTPCR0 0xffc80030 +#define MSTPCR1 0xffc80034 +#define MSTPCR3 0xffc8003c +#define MSTPSR1 0xffc80044 +#define MSTPSR4 0xffc80048 +#define MSTPSR6 0xffc8004c +#define MSTPCR4 0xffc80050 +#define MSTPCR5 0xffc80054 +#define MSTPCR6 0xffc80058 +#define MSTPCR7 0xffc80040 + +/* ioremap() through clock mapping mandatory to avoid + * collision with ARM coherent DMA virtual memory range. + */ + +static struct clk_mapping cpg_mapping = { + .phys = 0xffc80000, + .len = 0x80, +}; + +/* + * Default rate for the root input clock, reset this with clk_set_rate() + * from the platform code. + */ +static struct clk plla_clk = { + .rate = 1500000000, + .mapping = &cpg_mapping, +}; + +static struct clk *main_clks[] = { + &plla_clk, +}; + +static int divisors[] = { 0, 0, 0, 6, 8, 12, 16, 0, 24, 32, 36, 0, 0, 0, 0, 0 }; + +static struct clk_div_mult_table div4_div_mult_table = { + .divisors = divisors, + .nr_divisors = ARRAY_SIZE(divisors), +}; + +static struct clk_div4_table div4_table = { + .div_mult_table = &div4_div_mult_table, +}; + +enum { DIV4_S, DIV4_OUT, DIV4_S4, DIV4_S3, DIV4_S1, DIV4_P, DIV4_NR }; + +static struct clk div4_clks[DIV4_NR] = { + [DIV4_S] = SH_CLK_DIV4(&plla_clk, FRQMR, 20, + 0x0018, CLK_ENABLE_ON_INIT), + [DIV4_OUT] = SH_CLK_DIV4(&plla_clk, FRQMR, 16, + 0x0700, CLK_ENABLE_ON_INIT), + [DIV4_S4] = SH_CLK_DIV4(&plla_clk, FRQMR, 12, + 0x0040, CLK_ENABLE_ON_INIT), + [DIV4_S3] = SH_CLK_DIV4(&plla_clk, FRQMR, 8, + 0x0010, CLK_ENABLE_ON_INIT), + [DIV4_S1] = SH_CLK_DIV4(&plla_clk, FRQMR, 4, + 0x0060, CLK_ENABLE_ON_INIT), + [DIV4_P] = SH_CLK_DIV4(&plla_clk, FRQMR, 0, + 0x0300, CLK_ENABLE_ON_INIT), +}; + +enum { MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021, + MSTP016, MSTP015, MSTP014, + MSTP_NR }; + +static struct clk mstp_clks[MSTP_NR] = { + [MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0), /* SCIF0 */ + [MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0), /* SCIF1 */ + [MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0), /* SCIF2 */ + [MSTP023] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 23, 0), /* SCIF3 */ + [MSTP022] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 22, 0), /* SCIF4 */ + [MSTP021] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 21, 0), /* SCIF5 */ + [MSTP016] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 16, 0), /* TMU0 */ + [MSTP015] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0), /* TMU1 */ + [MSTP014] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 14, 0), /* TMU2 */ +}; + +static unsigned long mul4_recalc(struct clk *clk) +{ + return clk->parent->rate * 4; +} + +static struct clk_ops mul4_clk_ops = { + .recalc = mul4_recalc, +}; + +struct clk clkz_clk = { + .ops = &mul4_clk_ops, + .parent = &div4_clks[DIV4_S], +}; + +struct clk clkzs_clk = { + /* clks x 4 / 4 = clks */ + .parent = &div4_clks[DIV4_S], +}; + +static struct clk *late_main_clks[] = { + &clkz_clk, + &clkzs_clk, +}; + +static struct clk_lookup lookups[] = { + /* main clocks */ + CLKDEV_CON_ID("plla_clk", &plla_clk), + CLKDEV_CON_ID("clkz_clk", &clkz_clk), + CLKDEV_CON_ID("clkzs_clk", &clkzs_clk), + + /* DIV4 clocks */ + CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_S]), + CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_OUT]), + CLKDEV_CON_ID("shyway4_clk", &div4_clks[DIV4_S4]), + CLKDEV_CON_ID("shyway3_clk", &div4_clks[DIV4_S3]), + CLKDEV_CON_ID("shyway1_clk", &div4_clks[DIV4_S1]), + CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]), + + /* MSTP32 clocks */ + CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP016]), /* TMU00 */ + CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP016]), /* TMU01 */ + CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP026]), /* SCIF0 */ + CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP025]), /* SCIF1 */ + CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP024]), /* SCIF2 */ + CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP023]), /* SCIF3 */ + CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP022]), /* SCIF4 */ + CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP021]), /* SCIF6 */ +}; + +void __init r8a7779_clock_init(void) +{ + int k, ret = 0; + + for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) + ret = clk_register(main_clks[k]); + + if (!ret) + ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); + + if (!ret) + ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR); + + for (k = 0; !ret && (k < ARRAY_SIZE(late_main_clks)); k++) + ret = clk_register(late_main_clks[k]); + + clkdev_add_table(lookups, ARRAY_SIZE(lookups)); + + if (!ret) + clk_init(); + else + panic("failed to setup r8a7779 clocks\n"); +} diff --git a/arch/arm/mach-shmobile/clock-sh7372.c b/arch/arm/mach-shmobile/clock-sh7372.c index 995a9c3aec8..e349c22a0d7 100644 --- a/arch/arm/mach-shmobile/clock-sh7372.c +++ b/arch/arm/mach-shmobile/clock-sh7372.c @@ -411,11 +411,11 @@ static struct clk *fsibckcr_parent[] = { }; static struct clk div6_reparent_clks[DIV6_REPARENT_NR] = { - [DIV6_HDMI] = SH_CLK_DIV6_EXT(&pllc1_div2_clk, HDMICKCR, 0, + [DIV6_HDMI] = SH_CLK_DIV6_EXT(HDMICKCR, 0, hdmi_parent, ARRAY_SIZE(hdmi_parent), 6, 2), - [DIV6_FSIA] = SH_CLK_DIV6_EXT(&pllc1_div2_clk, FSIACKCR, 0, + [DIV6_FSIA] = SH_CLK_DIV6_EXT(FSIACKCR, 0, fsiackcr_parent, ARRAY_SIZE(fsiackcr_parent), 6, 2), - [DIV6_FSIB] = SH_CLK_DIV6_EXT(&pllc1_div2_clk, FSIBCKCR, 0, + [DIV6_FSIB] = SH_CLK_DIV6_EXT(FSIBCKCR, 0, fsibckcr_parent, ARRAY_SIZE(fsibckcr_parent), 6, 2), }; diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c index 1370a89ca35..34944d01bf1 100644 --- a/arch/arm/mach-shmobile/clock-sh73a0.c +++ b/arch/arm/mach-shmobile/clock-sh73a0.c @@ -92,6 +92,24 @@ static struct clk_ops div2_clk_ops = { .recalc = div2_recalc, }; +static unsigned long div7_recalc(struct clk *clk) +{ + return clk->parent->rate / 7; +} + +static struct clk_ops div7_clk_ops = { + .recalc = div7_recalc, +}; + +static unsigned long div13_recalc(struct clk *clk) +{ + return clk->parent->rate / 13; +} + +static struct clk_ops div13_clk_ops = { + .recalc = div13_recalc, +}; + /* Divide extal1 by two */ static struct clk extal1_div2_clk = { .ops = &div2_clk_ops, @@ -174,12 +192,29 @@ static struct clk pll3_clk = { .enable_bit = 3, }; -/* Divide PLL1 by two */ +/* Divide PLL */ static struct clk pll1_div2_clk = { .ops = &div2_clk_ops, .parent = &pll1_clk, }; +static struct clk pll1_div7_clk = { + .ops = &div7_clk_ops, + .parent = &pll1_clk, +}; + +static struct clk pll1_div13_clk = { + .ops = &div13_clk_ops, + .parent = &pll1_clk, +}; + +/* External input clock */ +struct clk sh73a0_extcki_clk = { +}; + +struct clk sh73a0_extalr_clk = { +}; + static struct clk *main_clks[] = { &r_clk, &sh73a0_extal1_clk, @@ -193,6 +228,10 @@ static struct clk *main_clks[] = { &pll2_clk, &pll3_clk, &pll1_div2_clk, + &pll1_div7_clk, + &pll1_div13_clk, + &sh73a0_extcki_clk, + &sh73a0_extalr_clk, }; static void div4_kick(struct clk *clk) @@ -246,27 +285,84 @@ enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_ZB1, DIV6_DSIT, DIV6_DSI0P, DIV6_DSI1P, DIV6_NR }; +static struct clk *vck_parent[8] = { + [0] = &pll1_div2_clk, + [1] = &pll2_clk, + [2] = &sh73a0_extcki_clk, + [3] = &sh73a0_extal2_clk, + [4] = &main_div2_clk, + [5] = &sh73a0_extalr_clk, + [6] = &main_clk, +}; + +static struct clk *pll_parent[4] = { + [0] = &pll1_div2_clk, + [1] = &pll2_clk, + [2] = &pll1_div13_clk, +}; + +static struct clk *hsi_parent[4] = { + [0] = &pll1_div2_clk, + [1] = &pll2_clk, + [2] = &pll1_div7_clk, +}; + +static struct clk *pll_extal2_parent[] = { + [0] = &pll1_div2_clk, + [1] = &pll2_clk, + [2] = &sh73a0_extal2_clk, + [3] = &sh73a0_extal2_clk, +}; + +static struct clk *dsi_parent[8] = { + [0] = &pll1_div2_clk, + [1] = &pll2_clk, + [2] = &main_clk, + [3] = &sh73a0_extal2_clk, + [4] = &sh73a0_extcki_clk, +}; + static struct clk div6_clks[DIV6_NR] = { - [DIV6_VCK1] = SH_CLK_DIV6(&pll1_div2_clk, VCLKCR1, 0), - [DIV6_VCK2] = SH_CLK_DIV6(&pll1_div2_clk, VCLKCR2, 0), - [DIV6_VCK3] = SH_CLK_DIV6(&pll1_div2_clk, VCLKCR3, 0), - [DIV6_ZB1] = SH_CLK_DIV6(&pll1_div2_clk, ZBCKCR, CLK_ENABLE_ON_INIT), - [DIV6_FLCTL] = SH_CLK_DIV6(&pll1_div2_clk, FLCKCR, 0), - [DIV6_SDHI0] = SH_CLK_DIV6(&pll1_div2_clk, SD0CKCR, 0), - [DIV6_SDHI1] = SH_CLK_DIV6(&pll1_div2_clk, SD1CKCR, 0), - [DIV6_SDHI2] = SH_CLK_DIV6(&pll1_div2_clk, SD2CKCR, 0), - [DIV6_FSIA] = SH_CLK_DIV6(&pll1_div2_clk, FSIACKCR, 0), - [DIV6_FSIB] = SH_CLK_DIV6(&pll1_div2_clk, FSIBCKCR, 0), - [DIV6_SUB] = SH_CLK_DIV6(&sh73a0_extal2_clk, SUBCKCR, 0), - [DIV6_SPUA] = SH_CLK_DIV6(&pll1_div2_clk, SPUACKCR, 0), - [DIV6_SPUV] = SH_CLK_DIV6(&pll1_div2_clk, SPUVCKCR, 0), - [DIV6_MSU] = SH_CLK_DIV6(&pll1_div2_clk, MSUCKCR, 0), - [DIV6_HSI] = SH_CLK_DIV6(&pll1_div2_clk, HSICKCR, 0), - [DIV6_MFG1] = SH_CLK_DIV6(&pll1_div2_clk, MFCK1CR, 0), - [DIV6_MFG2] = SH_CLK_DIV6(&pll1_div2_clk, MFCK2CR, 0), - [DIV6_DSIT] = SH_CLK_DIV6(&pll1_div2_clk, DSITCKCR, 0), - [DIV6_DSI0P] = SH_CLK_DIV6(&pll1_div2_clk, DSI0PCKCR, 0), - [DIV6_DSI1P] = SH_CLK_DIV6(&pll1_div2_clk, DSI1PCKCR, 0), + [DIV6_VCK1] = SH_CLK_DIV6_EXT(VCLKCR1, 0, + vck_parent, ARRAY_SIZE(vck_parent), 12, 3), + [DIV6_VCK2] = SH_CLK_DIV6_EXT(VCLKCR2, 0, + vck_parent, ARRAY_SIZE(vck_parent), 12, 3), + [DIV6_VCK3] = SH_CLK_DIV6_EXT(VCLKCR3, 0, + vck_parent, ARRAY_SIZE(vck_parent), 12, 3), + [DIV6_ZB1] = SH_CLK_DIV6_EXT(ZBCKCR, CLK_ENABLE_ON_INIT, + pll_parent, ARRAY_SIZE(pll_parent), 7, 1), + [DIV6_FLCTL] = SH_CLK_DIV6_EXT(FLCKCR, 0, + pll_parent, ARRAY_SIZE(pll_parent), 7, 1), + [DIV6_SDHI0] = SH_CLK_DIV6_EXT(SD0CKCR, 0, + pll_parent, ARRAY_SIZE(pll_parent), 6, 2), + [DIV6_SDHI1] = SH_CLK_DIV6_EXT(SD1CKCR, 0, + pll_parent, ARRAY_SIZE(pll_parent), 6, 2), + [DIV6_SDHI2] = SH_CLK_DIV6_EXT(SD2CKCR, 0, + pll_parent, ARRAY_SIZE(pll_parent), 6, 2), + [DIV6_FSIA] = SH_CLK_DIV6_EXT(FSIACKCR, 0, + pll_parent, ARRAY_SIZE(pll_parent), 6, 1), + [DIV6_FSIB] = SH_CLK_DIV6_EXT(FSIBCKCR, 0, + pll_parent, ARRAY_SIZE(pll_parent), 6, 1), + [DIV6_SUB] = SH_CLK_DIV6_EXT(SUBCKCR, 0, + pll_extal2_parent, ARRAY_SIZE(pll_extal2_parent), 6, 2), + [DIV6_SPUA] = SH_CLK_DIV6_EXT(SPUACKCR, 0, + pll_extal2_parent, ARRAY_SIZE(pll_extal2_parent), 6, 2), + [DIV6_SPUV] = SH_CLK_DIV6_EXT(SPUVCKCR, 0, + pll_extal2_parent, ARRAY_SIZE(pll_extal2_parent), 6, 2), + [DIV6_MSU] = SH_CLK_DIV6_EXT(MSUCKCR, 0, + pll_parent, ARRAY_SIZE(pll_parent), 7, 1), + [DIV6_HSI] = SH_CLK_DIV6_EXT(HSICKCR, 0, + hsi_parent, ARRAY_SIZE(hsi_parent), 6, 2), + [DIV6_MFG1] = SH_CLK_DIV6_EXT(MFCK1CR, 0, + pll_parent, ARRAY_SIZE(pll_parent), 7, 1), + [DIV6_MFG2] = SH_CLK_DIV6_EXT(MFCK2CR, 0, + pll_parent, ARRAY_SIZE(pll_parent), 7, 1), + [DIV6_DSIT] = SH_CLK_DIV6_EXT(DSITCKCR, 0, + pll_parent, ARRAY_SIZE(pll_parent), 7, 1), + [DIV6_DSI0P] = SH_CLK_DIV6_EXT(DSI0PCKCR, 0, + dsi_parent, ARRAY_SIZE(dsi_parent), 12, 3), + [DIV6_DSI1P] = SH_CLK_DIV6_EXT(DSI1PCKCR, 0, + dsi_parent, ARRAY_SIZE(dsi_parent), 12, 3), }; enum { MSTP001, @@ -403,7 +499,7 @@ void __init sh73a0_clock_init(void) ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); if (!ret) - ret = sh_clk_div6_register(div6_clks, DIV6_NR); + ret = sh_clk_div6_reparent_register(div6_clks, DIV6_NR); if (!ret) ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR); diff --git a/arch/arm/mach-shmobile/headsmp.S b/arch/arm/mach-shmobile/headsmp.S index 26079d933d9..6ac015c8920 100644 --- a/arch/arm/mach-shmobile/headsmp.S +++ b/arch/arm/mach-shmobile/headsmp.S @@ -14,7 +14,7 @@ #include <linux/init.h> #include <asm/memory.h> - __INIT + __CPUINIT /* * Reset vector for secondary CPUs. diff --git a/arch/arm/mach-shmobile/hotplug.c b/arch/arm/mach-shmobile/hotplug.c index 238a0d97d2d..828d22f3af5 100644 --- a/arch/arm/mach-shmobile/hotplug.c +++ b/arch/arm/mach-shmobile/hotplug.c @@ -12,14 +12,43 @@ #include <linux/kernel.h> #include <linux/errno.h> #include <linux/smp.h> +#include <linux/cpumask.h> +#include <linux/delay.h> +#include <mach/common.h> +#include <asm/cacheflush.h> + +static cpumask_t dead_cpus; int platform_cpu_kill(unsigned int cpu) { - return 1; + int k; + + /* this function is running on another CPU than the offline target, + * here we need wait for shutdown code in platform_cpu_die() to + * finish before asking SoC-specific code to power off the CPU core. + */ + for (k = 0; k < 1000; k++) { + if (cpumask_test_cpu(cpu, &dead_cpus)) + return shmobile_platform_cpu_kill(cpu); + + mdelay(1); + } + + return 0; } void platform_cpu_die(unsigned int cpu) { + /* hardware shutdown code running on the CPU that is being offlined */ + flush_cache_all(); + dsb(); + + /* notify platform_cpu_kill() that hardware shutdown is finished */ + cpumask_set_cpu(cpu, &dead_cpus); + + /* wait for SoC code in platform_cpu_kill() to shut off CPU core + * power. CPU bring up starts from the reset vector. + */ while (1) { /* * here's the WFI @@ -33,6 +62,7 @@ void platform_cpu_die(unsigned int cpu) int platform_cpu_disable(unsigned int cpu) { + cpumask_clear_cpu(cpu, &dead_cpus); /* * we don't allow CPU 0 to be shutdown (it is still too special * e.g. clock tick interrupts) diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h index 4bf82c15677..e4b945e271e 100644 --- a/arch/arm/mach-shmobile/include/mach/common.h +++ b/arch/arm/mach-shmobile/include/mach/common.h @@ -4,6 +4,7 @@ extern struct sys_timer shmobile_timer; extern void shmobile_setup_console(void); extern void shmobile_secondary_vector(void); +extern int shmobile_platform_cpu_kill(unsigned int cpu); struct clk; extern int clk_init(void); extern void shmobile_handle_irq_intc(struct pt_regs *); @@ -34,8 +35,8 @@ extern void sh7372_add_standard_devices(void); extern void sh7372_clock_init(void); extern void sh7372_pinmux_init(void); extern void sh7372_pm_init(void); -extern void sh7372_resume_core_standby_a3sm(void); -extern int sh7372_do_idle_a3sm(unsigned long unused); +extern void sh7372_resume_core_standby_sysc(void); +extern int sh7372_do_idle_sysc(unsigned long sleep_mode); extern struct clk sh7372_extal1_clk; extern struct clk sh7372_extal2_clk; @@ -46,10 +47,31 @@ extern void sh73a0_clock_init(void); extern void sh73a0_pinmux_init(void); extern struct clk sh73a0_extal1_clk; extern struct clk sh73a0_extal2_clk; +extern struct clk sh73a0_extcki_clk; +extern struct clk sh73a0_extalr_clk; extern unsigned int sh73a0_get_core_count(void); extern void sh73a0_secondary_init(unsigned int cpu); extern int sh73a0_boot_secondary(unsigned int cpu); extern void sh73a0_smp_prepare_cpus(void); +extern void r8a7740_init_irq(void); +extern void r8a7740_add_early_devices(void); +extern void r8a7740_add_standard_devices(void); +extern void r8a7740_clock_init(u8 md_ck); +extern void r8a7740_pinmux_init(void); + +extern void r8a7779_init_irq(void); +extern void r8a7779_add_early_devices(void); +extern void r8a7779_add_standard_devices(void); +extern void r8a7779_clock_init(void); +extern void r8a7779_pinmux_init(void); +extern void r8a7779_pm_init(void); + +extern unsigned int r8a7779_get_core_count(void); +extern int r8a7779_platform_cpu_kill(unsigned int cpu); +extern void r8a7779_secondary_init(unsigned int cpu); +extern int r8a7779_boot_secondary(unsigned int cpu); +extern void r8a7779_smp_prepare_cpus(void); + #endif /* __ARCH_MACH_COMMON_H */ diff --git a/arch/arm/mach-shmobile/include/mach/r8a7740.h b/arch/arm/mach-shmobile/include/mach/r8a7740.h new file mode 100644 index 00000000000..9d447abb969 --- /dev/null +++ b/arch/arm/mach-shmobile/include/mach/r8a7740.h @@ -0,0 +1,584 @@ +/* + * Copyright (C) 2011 Renesas Solutions Corp. + * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __ASM_R8A7740_H__ +#define __ASM_R8A7740_H__ + +/* + * MD_CKx pin + */ +#define MD_CK2 (1 << 2) +#define MD_CK1 (1 << 1) +#define MD_CK0 (1 << 0) + +/* + * Pin Function Controller: + * GPIO_FN_xx - GPIO used to select pin function + * GPIO_PORTxx - GPIO mapped to real I/O pin on CPU + */ +enum { + /* PORT */ + GPIO_PORT0, GPIO_PORT1, GPIO_PORT2, GPIO_PORT3, GPIO_PORT4, + GPIO_PORT5, GPIO_PORT6, GPIO_PORT7, GPIO_PORT8, GPIO_PORT9, + + GPIO_PORT10, GPIO_PORT11, GPIO_PORT12, GPIO_PORT13, GPIO_PORT14, + GPIO_PORT15, GPIO_PORT16, GPIO_PORT17, GPIO_PORT18, GPIO_PORT19, + + GPIO_PORT20, GPIO_PORT21, GPIO_PORT22, GPIO_PORT23, GPIO_PORT24, + GPIO_PORT25, GPIO_PORT26, GPIO_PORT27, GPIO_PORT28, GPIO_PORT29, + + GPIO_PORT30, GPIO_PORT31, GPIO_PORT32, GPIO_PORT33, GPIO_PORT34, + GPIO_PORT35, GPIO_PORT36, GPIO_PORT37, GPIO_PORT38, GPIO_PORT39, + + GPIO_PORT40, GPIO_PORT41, GPIO_PORT42, GPIO_PORT43, GPIO_PORT44, + GPIO_PORT45, GPIO_PORT46, GPIO_PORT47, GPIO_PORT48, GPIO_PORT49, + + GPIO_PORT50, GPIO_PORT51, GPIO_PORT52, GPIO_PORT53, GPIO_PORT54, + GPIO_PORT55, GPIO_PORT56, GPIO_PORT57, GPIO_PORT58, GPIO_PORT59, + + GPIO_PORT60, GPIO_PORT61, GPIO_PORT62, GPIO_PORT63, GPIO_PORT64, + GPIO_PORT65, GPIO_PORT66, GPIO_PORT67, GPIO_PORT68, GPIO_PORT69, + + GPIO_PORT70, GPIO_PORT71, GPIO_PORT72, GPIO_PORT73, GPIO_PORT74, + GPIO_PORT75, GPIO_PORT76, GPIO_PORT77, GPIO_PORT78, GPIO_PORT79, + + GPIO_PORT80, GPIO_PORT81, GPIO_PORT82, GPIO_PORT83, GPIO_PORT84, + GPIO_PORT85, GPIO_PORT86, GPIO_PORT87, GPIO_PORT88, GPIO_PORT89, + + GPIO_PORT90, GPIO_PORT91, GPIO_PORT92, GPIO_PORT93, GPIO_PORT94, + GPIO_PORT95, GPIO_PORT96, GPIO_PORT97, GPIO_PORT98, GPIO_PORT99, + + GPIO_PORT100, GPIO_PORT101, GPIO_PORT102, GPIO_PORT103, GPIO_PORT104, + GPIO_PORT105, GPIO_PORT106, GPIO_PORT107, GPIO_PORT108, GPIO_PORT109, + + GPIO_PORT110, GPIO_PORT111, GPIO_PORT112, GPIO_PORT113, GPIO_PORT114, + GPIO_PORT115, GPIO_PORT116, GPIO_PORT117, GPIO_PORT118, GPIO_PORT119, + + GPIO_PORT120, GPIO_PORT121, GPIO_PORT122, GPIO_PORT123, GPIO_PORT124, + GPIO_PORT125, GPIO_PORT126, GPIO_PORT127, GPIO_PORT128, GPIO_PORT129, + + GPIO_PORT130, GPIO_PORT131, GPIO_PORT132, GPIO_PORT133, GPIO_PORT134, + GPIO_PORT135, GPIO_PORT136, GPIO_PORT137, GPIO_PORT138, GPIO_PORT139, + + GPIO_PORT140, GPIO_PORT141, GPIO_PORT142, GPIO_PORT143, GPIO_PORT144, + GPIO_PORT145, GPIO_PORT146, GPIO_PORT147, GPIO_PORT148, GPIO_PORT149, + + GPIO_PORT150, GPIO_PORT151, GPIO_PORT152, GPIO_PORT153, GPIO_PORT154, + GPIO_PORT155, GPIO_PORT156, GPIO_PORT157, GPIO_PORT158, GPIO_PORT159, + + GPIO_PORT160, GPIO_PORT161, GPIO_PORT162, GPIO_PORT163, GPIO_PORT164, + GPIO_PORT165, GPIO_PORT166, GPIO_PORT167, GPIO_PORT168, GPIO_PORT169, + + GPIO_PORT170, GPIO_PORT171, GPIO_PORT172, GPIO_PORT173, GPIO_PORT174, + GPIO_PORT175, GPIO_PORT176, GPIO_PORT177, GPIO_PORT178, GPIO_PORT179, + + GPIO_PORT180, GPIO_PORT181, GPIO_PORT182, GPIO_PORT183, GPIO_PORT184, + GPIO_PORT185, GPIO_PORT186, GPIO_PORT187, GPIO_PORT188, GPIO_PORT189, + + GPIO_PORT190, GPIO_PORT191, GPIO_PORT192, GPIO_PORT193, GPIO_PORT194, + GPIO_PORT195, GPIO_PORT196, GPIO_PORT197, GPIO_PORT198, GPIO_PORT199, + + GPIO_PORT200, GPIO_PORT201, GPIO_PORT202, GPIO_PORT203, GPIO_PORT204, + GPIO_PORT205, GPIO_PORT206, GPIO_PORT207, GPIO_PORT208, GPIO_PORT209, + + GPIO_PORT210, GPIO_PORT211, + + /* IRQ */ + GPIO_FN_IRQ0_PORT2, GPIO_FN_IRQ0_PORT13, + GPIO_FN_IRQ1, + GPIO_FN_IRQ2_PORT11, GPIO_FN_IRQ2_PORT12, + GPIO_FN_IRQ3_PORT10, GPIO_FN_IRQ3_PORT14, + GPIO_FN_IRQ4_PORT15, GPIO_FN_IRQ4_PORT172, + GPIO_FN_IRQ5_PORT0, GPIO_FN_IRQ5_PORT1, + GPIO_FN_IRQ6_PORT121, GPIO_FN_IRQ6_PORT173, + GPIO_FN_IRQ7_PORT120, GPIO_FN_IRQ7_PORT209, + GPIO_FN_IRQ8, + GPIO_FN_IRQ9_PORT118, GPIO_FN_IRQ9_PORT210, + GPIO_FN_IRQ10, + GPIO_FN_IRQ11, + GPIO_FN_IRQ12_PORT42, GPIO_FN_IRQ12_PORT97, + GPIO_FN_IRQ13_PORT64, GPIO_FN_IRQ13_PORT98, + GPIO_FN_IRQ14_PORT63, GPIO_FN_IRQ14_PORT99, + GPIO_FN_IRQ15_PORT62, GPIO_FN_IRQ15_PORT100, + GPIO_FN_IRQ16_PORT68, GPIO_FN_IRQ16_PORT211, + GPIO_FN_IRQ17, + GPIO_FN_IRQ18, + GPIO_FN_IRQ19, + GPIO_FN_IRQ20, + GPIO_FN_IRQ21, + GPIO_FN_IRQ22, + GPIO_FN_IRQ23, + GPIO_FN_IRQ24, + GPIO_FN_IRQ25, + GPIO_FN_IRQ26_PORT58, GPIO_FN_IRQ26_PORT81, + GPIO_FN_IRQ27_PORT57, GPIO_FN_IRQ27_PORT168, + GPIO_FN_IRQ28_PORT56, GPIO_FN_IRQ28_PORT169, + GPIO_FN_IRQ29_PORT50, GPIO_FN_IRQ29_PORT170, + GPIO_FN_IRQ30_PORT49, GPIO_FN_IRQ30_PORT171, + GPIO_FN_IRQ31_PORT41, GPIO_FN_IRQ31_PORT167, + + /* Function */ + + /* DBGT */ + GPIO_FN_DBGMDT2, GPIO_FN_DBGMDT1, GPIO_FN_DBGMDT0, + GPIO_FN_DBGMD10, GPIO_FN_DBGMD11, GPIO_FN_DBGMD20, + GPIO_FN_DBGMD21, + + /* FSI */ + GPIO_FN_FSIAISLD_PORT0, /* FSIAISLD Port 0/5 */ + GPIO_FN_FSIAISLD_PORT5, + GPIO_FN_FSIASPDIF_PORT9, /* FSIASPDIF Port 9/18 */ + GPIO_FN_FSIASPDIF_PORT18, + GPIO_FN_FSIAOSLD1, GPIO_FN_FSIAOSLD2, + GPIO_FN_FSIAOLR, GPIO_FN_FSIAOBT, + GPIO_FN_FSIAOSLD, GPIO_FN_FSIAOMC, + GPIO_FN_FSIACK, GPIO_FN_FSIAILR, + GPIO_FN_FSIAIBT, + + /* FMSI */ + GPIO_FN_FMSISLD_PORT1, /* FMSISLD Port 1/6 */ + GPIO_FN_FMSISLD_PORT6, + GPIO_FN_FMSIILR, GPIO_FN_FMSIIBT, + GPIO_FN_FMSIOLR, GPIO_FN_FMSIOBT, + GPIO_FN_FMSICK, GPIO_FN_FMSOILR, + GPIO_FN_FMSOIBT, GPIO_FN_FMSOOLR, + GPIO_FN_FMSOOBT, GPIO_FN_FMSOSLD, + GPIO_FN_FMSOCK, + + /* SCIFA0 */ + GPIO_FN_SCIFA0_SCK, GPIO_FN_SCIFA0_CTS, + GPIO_FN_SCIFA0_RTS, GPIO_FN_SCIFA0_RXD, + GPIO_FN_SCIFA0_TXD, + + /* SCIFA1 */ + GPIO_FN_SCIFA1_CTS, GPIO_FN_SCIFA1_SCK, + GPIO_FN_SCIFA1_RXD, GPIO_FN_SCIFA1_TXD, + GPIO_FN_SCIFA1_RTS, + + /* SCIFA2 */ + GPIO_FN_SCIFA2_SCK_PORT22, /* SCIFA2_SCK Port 22/199 */ + GPIO_FN_SCIFA2_SCK_PORT199, + GPIO_FN_SCIFA2_RXD, GPIO_FN_SCIFA2_TXD, + GPIO_FN_SCIFA2_CTS, GPIO_FN_SCIFA2_RTS, + + /* SCIFA3 */ + GPIO_FN_SCIFA3_RTS_PORT105, /* MSEL5CR_8_0 */ + GPIO_FN_SCIFA3_SCK_PORT116, + GPIO_FN_SCIFA3_CTS_PORT117, + GPIO_FN_SCIFA3_RXD_PORT174, + GPIO_FN_SCIFA3_TXD_PORT175, + + GPIO_FN_SCIFA3_RTS_PORT161, /* MSEL5CR_8_1 */ + GPIO_FN_SCIFA3_SCK_PORT158, + GPIO_FN_SCIFA3_CTS_PORT162, + GPIO_FN_SCIFA3_RXD_PORT159, + GPIO_FN_SCIFA3_TXD_PORT160, + + /* SCIFA4 */ + GPIO_FN_SCIFA4_RXD_PORT12, /* MSEL5CR[12:11] = 00 */ + GPIO_FN_SCIFA4_TXD_PORT13, + + GPIO_FN_SCIFA4_RXD_PORT204, /* MSEL5CR[12:11] = 01 */ + GPIO_FN_SCIFA4_TXD_PORT203, + + GPIO_FN_SCIFA4_RXD_PORT94, /* MSEL5CR[12:11] = 10 */ + GPIO_FN_SCIFA4_TXD_PORT93, + + GPIO_FN_SCIFA4_SCK_PORT21, /* SCIFA4_SCK Port 21/205 */ + GPIO_FN_SCIFA4_SCK_PORT205, + + /* SCIFA5 */ + GPIO_FN_SCIFA5_TXD_PORT20, /* MSEL5CR[15:14] = 00 */ + GPIO_FN_SCIFA5_RXD_PORT10, + + GPIO_FN_SCIFA5_RXD_PORT207, /* MSEL5CR[15:14] = 01 */ + GPIO_FN_SCIFA5_TXD_PORT208, + + GPIO_FN_SCIFA5_TXD_PORT91, /* MSEL5CR[15:14] = 10 */ + GPIO_FN_SCIFA5_RXD_PORT92, + + GPIO_FN_SCIFA5_SCK_PORT23, /* SCIFA5_SCK Port 23/206 */ + GPIO_FN_SCIFA5_SCK_PORT206, + + /* SCIFA6 */ + GPIO_FN_SCIFA6_SCK, GPIO_FN_SCIFA6_RXD, GPIO_FN_SCIFA6_TXD, + + /* SCIFA7 */ + GPIO_FN_SCIFA7_TXD, GPIO_FN_SCIFA7_RXD, + + /* SCIFAB */ + GPIO_FN_SCIFB_SCK_PORT190, /* MSEL5CR_17_0 */ + GPIO_FN_SCIFB_RXD_PORT191, + GPIO_FN_SCIFB_TXD_PORT192, + GPIO_FN_SCIFB_RTS_PORT186, + GPIO_FN_SCIFB_CTS_PORT187, + + GPIO_FN_SCIFB_SCK_PORT2, /* MSEL5CR_17_1 */ + GPIO_FN_SCIFB_RXD_PORT3, + GPIO_FN_SCIFB_TXD_PORT4, + GPIO_FN_SCIFB_RTS_PORT172, + GPIO_FN_SCIFB_CTS_PORT173, + + /* LCD0 */ + GPIO_FN_LCDC0_SELECT, + GPIO_FN_LCD0_D0, GPIO_FN_LCD0_D1, GPIO_FN_LCD0_D2, + GPIO_FN_LCD0_D3, GPIO_FN_LCD0_D4, GPIO_FN_LCD0_D5, + GPIO_FN_LCD0_D6, GPIO_FN_LCD0_D7, GPIO_FN_LCD0_D8, + GPIO_FN_LCD0_D9, GPIO_FN_LCD0_D10, GPIO_FN_LCD0_D11, + GPIO_FN_LCD0_D12, GPIO_FN_LCD0_D13, GPIO_FN_LCD0_D14, + GPIO_FN_LCD0_D15, GPIO_FN_LCD0_D16, GPIO_FN_LCD0_D17, + GPIO_FN_LCD0_DON, GPIO_FN_LCD0_VCPWC, GPIO_FN_LCD0_VEPWC, + + GPIO_FN_LCD0_DCK, GPIO_FN_LCD0_VSYN, /* for RGB */ + GPIO_FN_LCD0_HSYN, GPIO_FN_LCD0_DISP, /* for RGB */ + + GPIO_FN_LCD0_WR, GPIO_FN_LCD0_RD, /* for SYS */ + GPIO_FN_LCD0_CS, GPIO_FN_LCD0_RS, /* for SYS */ + + GPIO_FN_LCD0_D18_PORT163, GPIO_FN_LCD0_D19_PORT162, + GPIO_FN_LCD0_D20_PORT161, GPIO_FN_LCD0_D21_PORT158, + GPIO_FN_LCD0_D22_PORT160, GPIO_FN_LCD0_D23_PORT159, + GPIO_FN_LCD0_LCLK_PORT165, /* MSEL5CR_6_1 */ + + GPIO_FN_LCD0_D18_PORT40, GPIO_FN_LCD0_D19_PORT4, + GPIO_FN_LCD0_D20_PORT3, GPIO_FN_LCD0_D21_PORT2, + GPIO_FN_LCD0_D22_PORT0, GPIO_FN_LCD0_D23_PORT1, + GPIO_FN_LCD0_LCLK_PORT102, /* MSEL5CR_6_0 */ + + /* LCD1 */ + GPIO_FN_LCDC1_SELECT, + GPIO_FN_LCD1_D0, GPIO_FN_LCD1_D1, GPIO_FN_LCD1_D2, + GPIO_FN_LCD1_D3, GPIO_FN_LCD1_D4, GPIO_FN_LCD1_D5, + GPIO_FN_LCD1_D6, GPIO_FN_LCD1_D7, GPIO_FN_LCD1_D8, + GPIO_FN_LCD1_D9, GPIO_FN_LCD1_D10, GPIO_FN_LCD1_D11, + GPIO_FN_LCD1_D12, GPIO_FN_LCD1_D13, GPIO_FN_LCD1_D14, + GPIO_FN_LCD1_D15, GPIO_FN_LCD1_D16, GPIO_FN_LCD1_D17, + GPIO_FN_LCD1_D18, GPIO_FN_LCD1_D19, GPIO_FN_LCD1_D20, + GPIO_FN_LCD1_D21, GPIO_FN_LCD1_D22, GPIO_FN_LCD1_D23, + GPIO_FN_LCD1_DON, GPIO_FN_LCD1_VCPWC, + GPIO_FN_LCD1_LCLK, GPIO_FN_LCD1_VEPWC, + + GPIO_FN_LCD1_DCK, GPIO_FN_LCD1_VSYN, /* for RGB */ + GPIO_FN_LCD1_HSYN, GPIO_FN_LCD1_DISP, /* for RGB */ + + GPIO_FN_LCD1_WR, GPIO_FN_LCD1_RD, /* for SYS */ + GPIO_FN_LCD1_CS, GPIO_FN_LCD1_RS, /* for SYS */ + + /* RSPI */ + GPIO_FN_RSPI_SSL0_A, GPIO_FN_RSPI_SSL1_A, + GPIO_FN_RSPI_SSL2_A, GPIO_FN_RSPI_SSL3_A, + GPIO_FN_RSPI_MOSI_A, GPIO_FN_RSPI_MISO_A, + GPIO_FN_RSPI_CK_A, + + /* VIO CKO */ + GPIO_FN_VIO_CKO1, + GPIO_FN_VIO_CKO2, + GPIO_FN_VIO_CKO_1, + GPIO_FN_VIO_CKO, + + /* VIO0 */ + GPIO_FN_VIO0_D0, GPIO_FN_VIO0_D1, GPIO_FN_VIO0_D2, + GPIO_FN_VIO0_D3, GPIO_FN_VIO0_D4, GPIO_FN_VIO0_D5, + GPIO_FN_VIO0_D6, GPIO_FN_VIO0_D7, GPIO_FN_VIO0_D8, + GPIO_FN_VIO0_D9, GPIO_FN_VIO0_D10, GPIO_FN_VIO0_D11, + GPIO_FN_VIO0_D12, GPIO_FN_VIO0_VD, GPIO_FN_VIO0_HD, + GPIO_FN_VIO0_CLK, GPIO_FN_VIO0_FIELD, + + GPIO_FN_VIO0_D13_PORT26, /* MSEL5CR_27_0 */ + GPIO_FN_VIO0_D14_PORT25, + GPIO_FN_VIO0_D15_PORT24, + + GPIO_FN_VIO0_D13_PORT22, /* MSEL5CR_27_1 */ + GPIO_FN_VIO0_D14_PORT95, + GPIO_FN_VIO0_D15_PORT96, + + /* VIO1 */ + GPIO_FN_VIO1_D0, GPIO_FN_VIO1_D1, GPIO_FN_VIO1_D2, + GPIO_FN_VIO1_D3, GPIO_FN_VIO1_D4, GPIO_FN_VIO1_D5, + GPIO_FN_VIO1_D6, GPIO_FN_VIO1_D7, GPIO_FN_VIO1_VD, + GPIO_FN_VIO1_HD, GPIO_FN_VIO1_CLK, GPIO_FN_VIO1_FIELD, + + /* TPU0 */ + GPIO_FN_TPU0TO0, GPIO_FN_TPU0TO1, + GPIO_FN_TPU0TO3, + GPIO_FN_TPU0TO2_PORT66, /* TPU0TO2 Port 66/202 */ + GPIO_FN_TPU0TO2_PORT202, + + /* SSP1 0 */ + GPIO_FN_STP0_IPD0, GPIO_FN_STP0_IPD1, GPIO_FN_STP0_IPD2, + GPIO_FN_STP0_IPD3, GPIO_FN_STP0_IPD4, GPIO_FN_STP0_IPD5, + GPIO_FN_STP0_IPD6, GPIO_FN_STP0_IPD7, GPIO_FN_STP0_IPEN, + GPIO_FN_STP0_IPCLK, GPIO_FN_STP0_IPSYNC, + + /* SSP1 1 */ + GPIO_FN_STP1_IPD1, GPIO_FN_STP1_IPD2, GPIO_FN_STP1_IPD3, + GPIO_FN_STP1_IPD4, GPIO_FN_STP1_IPD5, GPIO_FN_STP1_IPD6, + GPIO_FN_STP1_IPD7, GPIO_FN_STP1_IPCLK, GPIO_FN_STP1_IPSYNC, + + GPIO_FN_STP1_IPD0_PORT186, /* MSEL5CR_23_0 */ + GPIO_FN_STP1_IPEN_PORT187, + + GPIO_FN_STP1_IPD0_PORT194, /* MSEL5CR_23_1 */ + GPIO_FN_STP1_IPEN_PORT193, + + /* SIM */ + GPIO_FN_SIM_RST, GPIO_FN_SIM_CLK, + GPIO_FN_SIM_D_PORT22, /* SIM_D Port 22/199 */ + GPIO_FN_SIM_D_PORT199, + + /* SDHI0 */ + GPIO_FN_SDHI0_D0, GPIO_FN_SDHI0_D1, GPIO_FN_SDHI0_D2, + GPIO_FN_SDHI0_D3, GPIO_FN_SDHI0_CD, GPIO_FN_SDHI0_WP, + GPIO_FN_SDHI0_CMD, GPIO_FN_SDHI0_CLK, + + /* SDHI1 */ + GPIO_FN_SDHI1_D0, GPIO_FN_SDHI1_D1, GPIO_FN_SDHI1_D2, + GPIO_FN_SDHI1_D3, GPIO_FN_SDHI1_CD, GPIO_FN_SDHI1_WP, + GPIO_FN_SDHI1_CMD, GPIO_FN_SDHI1_CLK, + + /* SDHI2 */ + GPIO_FN_SDHI2_D0, GPIO_FN_SDHI2_D1, GPIO_FN_SDHI2_D2, + GPIO_FN_SDHI2_D3, GPIO_FN_SDHI2_CLK, GPIO_FN_SDHI2_CMD, + + GPIO_FN_SDHI2_CD_PORT24, /* MSEL5CR_19_0 */ + GPIO_FN_SDHI2_WP_PORT25, + + GPIO_FN_SDHI2_WP_PORT177, /* MSEL5CR_19_1 */ + GPIO_FN_SDHI2_CD_PORT202, + + /* MSIOF2 */ + GPIO_FN_MSIOF2_TXD, GPIO_FN_MSIOF2_RXD, GPIO_FN_MSIOF2_TSCK, + GPIO_FN_MSIOF2_SS2, GPIO_FN_MSIOF2_TSYNC, GPIO_FN_MSIOF2_SS1, + GPIO_FN_MSIOF2_MCK1, GPIO_FN_MSIOF2_MCK0, GPIO_FN_MSIOF2_RSYNC, + GPIO_FN_MSIOF2_RSCK, + + /* KEYSC */ + GPIO_FN_KEYIN4, GPIO_FN_KEYIN5, + GPIO_FN_KEYIN6, GPIO_FN_KEYIN7, + GPIO_FN_KEYOUT0, GPIO_FN_KEYOUT1, GPIO_FN_KEYOUT2, + GPIO_FN_KEYOUT3, GPIO_FN_KEYOUT4, GPIO_FN_KEYOUT5, + GPIO_FN_KEYOUT6, GPIO_FN_KEYOUT7, + + GPIO_FN_KEYIN0_PORT43, /* MSEL4CR_18_0 */ + GPIO_FN_KEYIN1_PORT44, + GPIO_FN_KEYIN2_PORT45, + GPIO_FN_KEYIN3_PORT46, + + GPIO_FN_KEYIN0_PORT58, /* MSEL4CR_18_1 */ + GPIO_FN_KEYIN1_PORT57, + GPIO_FN_KEYIN2_PORT56, + GPIO_FN_KEYIN3_PORT55, + + /* VOU */ + GPIO_FN_DV_D0, GPIO_FN_DV_D1, GPIO_FN_DV_D2, GPIO_FN_DV_D3, + GPIO_FN_DV_D4, GPIO_FN_DV_D5, GPIO_FN_DV_D6, GPIO_FN_DV_D7, + GPIO_FN_DV_D8, GPIO_FN_DV_D9, GPIO_FN_DV_D10, GPIO_FN_DV_D11, + GPIO_FN_DV_D12, GPIO_FN_DV_D13, GPIO_FN_DV_D14, GPIO_FN_DV_D15, + GPIO_FN_DV_CLK, + GPIO_FN_DV_VSYNC, + GPIO_FN_DV_HSYNC, + + /* MEMC */ + GPIO_FN_MEMC_AD0, GPIO_FN_MEMC_AD1, GPIO_FN_MEMC_AD2, + GPIO_FN_MEMC_AD3, GPIO_FN_MEMC_AD4, GPIO_FN_MEMC_AD5, + GPIO_FN_MEMC_AD6, GPIO_FN_MEMC_AD7, GPIO_FN_MEMC_AD8, + GPIO_FN_MEMC_AD9, GPIO_FN_MEMC_AD10, GPIO_FN_MEMC_AD11, + GPIO_FN_MEMC_AD12, GPIO_FN_MEMC_AD13, GPIO_FN_MEMC_AD14, + GPIO_FN_MEMC_AD15, GPIO_FN_MEMC_CS0, GPIO_FN_MEMC_INT, + GPIO_FN_MEMC_NWE, GPIO_FN_MEMC_NOE, + + GPIO_FN_MEMC_CS1, /* MSEL4CR_6_0 */ + GPIO_FN_MEMC_ADV, + GPIO_FN_MEMC_WAIT, + GPIO_FN_MEMC_BUSCLK, + + GPIO_FN_MEMC_A1, /* MSEL4CR_6_1 */ + GPIO_FN_MEMC_DREQ0, + GPIO_FN_MEMC_DREQ1, + GPIO_FN_MEMC_A0, + + /* MMC */ + GPIO_FN_MMC0_D0_PORT68, GPIO_FN_MMC0_D1_PORT69, + GPIO_FN_MMC0_D2_PORT70, GPIO_FN_MMC0_D3_PORT71, + GPIO_FN_MMC0_D4_PORT72, GPIO_FN_MMC0_D5_PORT73, + GPIO_FN_MMC0_D6_PORT74, GPIO_FN_MMC0_D7_PORT75, + GPIO_FN_MMC0_CLK_PORT66, + GPIO_FN_MMC0_CMD_PORT67, /* MSEL4CR_15_0 */ + + GPIO_FN_MMC1_D0_PORT149, GPIO_FN_MMC1_D1_PORT148, + GPIO_FN_MMC1_D2_PORT147, GPIO_FN_MMC1_D3_PORT146, + GPIO_FN_MMC1_D4_PORT145, GPIO_FN_MMC1_D5_PORT144, + GPIO_FN_MMC1_D6_PORT143, GPIO_FN_MMC1_D7_PORT142, + GPIO_FN_MMC1_CLK_PORT103, + GPIO_FN_MMC1_CMD_PORT104, /* MSEL4CR_15_1 */ + + /* MSIOF0 */ + GPIO_FN_MSIOF0_SS1, GPIO_FN_MSIOF0_SS2, + GPIO_FN_MSIOF0_RXD, GPIO_FN_MSIOF0_TXD, + GPIO_FN_MSIOF0_MCK0, GPIO_FN_MSIOF0_MCK1, + GPIO_FN_MSIOF0_RSYNC, GPIO_FN_MSIOF0_RSCK, + GPIO_FN_MSIOF0_TSCK, GPIO_FN_MSIOF0_TSYNC, + + /* MSIOF1 */ + GPIO_FN_MSIOF1_RSCK, GPIO_FN_MSIOF1_RSYNC, + GPIO_FN_MSIOF1_MCK0, GPIO_FN_MSIOF1_MCK1, + + GPIO_FN_MSIOF1_SS2_PORT116, GPIO_FN_MSIOF1_SS1_PORT117, + GPIO_FN_MSIOF1_RXD_PORT118, GPIO_FN_MSIOF1_TXD_PORT119, + GPIO_FN_MSIOF1_TSYNC_PORT120, + GPIO_FN_MSIOF1_TSCK_PORT121, /* MSEL4CR_10_0 */ + + GPIO_FN_MSIOF1_SS1_PORT67, GPIO_FN_MSIOF1_TSCK_PORT72, + GPIO_FN_MSIOF1_TSYNC_PORT73, GPIO_FN_MSIOF1_TXD_PORT74, + GPIO_FN_MSIOF1_RXD_PORT75, + GPIO_FN_MSIOF1_SS2_PORT202, /* MSEL4CR_10_1 */ + + /* GPIO */ + GPIO_FN_GPO0, GPIO_FN_GPI0, + GPIO_FN_GPO1, GPIO_FN_GPI1, + + /* USB0 */ + GPIO_FN_USB0_OCI, GPIO_FN_USB0_PPON, GPIO_FN_VBUS, + + /* USB1 */ + GPIO_FN_USB1_OCI, GPIO_FN_USB1_PPON, + + /* BBIF1 */ + GPIO_FN_BBIF1_RXD, GPIO_FN_BBIF1_TXD, GPIO_FN_BBIF1_TSYNC, + GPIO_FN_BBIF1_TSCK, GPIO_FN_BBIF1_RSCK, GPIO_FN_BBIF1_RSYNC, + GPIO_FN_BBIF1_FLOW, GPIO_FN_BBIF1_RX_FLOW_N, + + /* BBIF2 */ + GPIO_FN_BBIF2_TXD2_PORT5, /* MSEL5CR_0_0 */ + GPIO_FN_BBIF2_RXD2_PORT60, + GPIO_FN_BBIF2_TSYNC2_PORT6, + GPIO_FN_BBIF2_TSCK2_PORT59, + + GPIO_FN_BBIF2_RXD2_PORT90, /* MSEL5CR_0_1 */ + GPIO_FN_BBIF2_TXD2_PORT183, + GPIO_FN_BBIF2_TSCK2_PORT89, + GPIO_FN_BBIF2_TSYNC2_PORT184, + + /* BSC / FLCTL / PCMCIA */ + GPIO_FN_CS0, GPIO_FN_CS2, GPIO_FN_CS4, + GPIO_FN_CS5B, GPIO_FN_CS6A, + GPIO_FN_CS5A_PORT105, /* CS5A PORT 19/105 */ + GPIO_FN_CS5A_PORT19, + GPIO_FN_IOIS16, /* ? */ + + GPIO_FN_A0, GPIO_FN_A1, GPIO_FN_A2, GPIO_FN_A3, + GPIO_FN_A4_FOE, /* share with FLCTL */ + GPIO_FN_A5_FCDE, /* share with FLCTL */ + GPIO_FN_A6, GPIO_FN_A7, GPIO_FN_A8, GPIO_FN_A9, + GPIO_FN_A10, GPIO_FN_A11, GPIO_FN_A12, GPIO_FN_A13, + GPIO_FN_A14, GPIO_FN_A15, GPIO_FN_A16, GPIO_FN_A17, + GPIO_FN_A18, GPIO_FN_A19, GPIO_FN_A20, GPIO_FN_A21, + GPIO_FN_A22, GPIO_FN_A23, GPIO_FN_A24, GPIO_FN_A25, + GPIO_FN_A26, + + GPIO_FN_D0_NAF0, GPIO_FN_D1_NAF1, /* share with FLCTL */ + GPIO_FN_D2_NAF2, GPIO_FN_D3_NAF3, /* share with FLCTL */ + GPIO_FN_D4_NAF4, GPIO_FN_D5_NAF5, /* share with FLCTL */ + GPIO_FN_D6_NAF6, GPIO_FN_D7_NAF7, /* share with FLCTL */ + GPIO_FN_D8_NAF8, GPIO_FN_D9_NAF9, /* share with FLCTL */ + GPIO_FN_D10_NAF10, GPIO_FN_D11_NAF11, /* share with FLCTL */ + GPIO_FN_D12_NAF12, GPIO_FN_D13_NAF13, /* share with FLCTL */ + GPIO_FN_D14_NAF14, GPIO_FN_D15_NAF15, /* share with FLCTL */ + + GPIO_FN_D16, GPIO_FN_D17, GPIO_FN_D18, GPIO_FN_D19, + GPIO_FN_D20, GPIO_FN_D21, GPIO_FN_D22, GPIO_FN_D23, + GPIO_FN_D24, GPIO_FN_D25, GPIO_FN_D26, GPIO_FN_D27, + GPIO_FN_D28, GPIO_FN_D29, GPIO_FN_D30, GPIO_FN_D31, + + GPIO_FN_WE0_FWE, /* share with FLCTL */ + GPIO_FN_WE1, + GPIO_FN_WE2_ICIORD, /* share with PCMCIA */ + GPIO_FN_WE3_ICIOWR, /* share with PCMCIA */ + GPIO_FN_CKO, GPIO_FN_BS, GPIO_FN_RDWR, + GPIO_FN_RD_FSC, /* share with FLCTL */ + GPIO_FN_WAIT_PORT177, /* WAIT Port 90/177 */ + GPIO_FN_WAIT_PORT90, + + GPIO_FN_FCE0, GPIO_FN_FCE1, GPIO_FN_FRB, /* FLCTL */ + + /* IRDA */ + GPIO_FN_IRDA_FIRSEL, GPIO_FN_IRDA_IN, GPIO_FN_IRDA_OUT, + + /* ATAPI */ + GPIO_FN_IDE_D0, GPIO_FN_IDE_D1, GPIO_FN_IDE_D2, + GPIO_FN_IDE_D3, GPIO_FN_IDE_D4, GPIO_FN_IDE_D5, + GPIO_FN_IDE_D6, GPIO_FN_IDE_D7, GPIO_FN_IDE_D8, + GPIO_FN_IDE_D9, GPIO_FN_IDE_D10, GPIO_FN_IDE_D11, + GPIO_FN_IDE_D12, GPIO_FN_IDE_D13, GPIO_FN_IDE_D14, + GPIO_FN_IDE_D15, GPIO_FN_IDE_A0, GPIO_FN_IDE_A1, + GPIO_FN_IDE_A2, GPIO_FN_IDE_CS0, GPIO_FN_IDE_CS1, + GPIO_FN_IDE_IOWR, GPIO_FN_IDE_IORD, GPIO_FN_IDE_IORDY, + GPIO_FN_IDE_INT, GPIO_FN_IDE_RST, GPIO_FN_IDE_DIRECTION, + GPIO_FN_IDE_EXBUF_ENB, GPIO_FN_IDE_IODACK, GPIO_FN_IDE_IODREQ, + + /* RMII */ + GPIO_FN_RMII_CRS_DV, GPIO_FN_RMII_RX_ER, GPIO_FN_RMII_RXD0, + GPIO_FN_RMII_RXD1, GPIO_FN_RMII_TX_EN, GPIO_FN_RMII_TXD0, + GPIO_FN_RMII_MDC, GPIO_FN_RMII_TXD1, GPIO_FN_RMII_MDIO, + GPIO_FN_RMII_REF50CK, /* for RMII */ + GPIO_FN_RMII_REF125CK, /* for GMII */ + + /* GEther */ + GPIO_FN_ET_TX_CLK, GPIO_FN_ET_TX_EN, GPIO_FN_ET_ETXD0, + GPIO_FN_ET_ETXD1, GPIO_FN_ET_ETXD2, GPIO_FN_ET_ETXD3, + GPIO_FN_ET_ETXD4, GPIO_FN_ET_ETXD5, /* for GEther */ + GPIO_FN_ET_ETXD6, GPIO_FN_ET_ETXD7, /* for GEther */ + GPIO_FN_ET_COL, GPIO_FN_ET_TX_ER, + GPIO_FN_ET_RX_CLK, GPIO_FN_ET_RX_DV, + GPIO_FN_ET_ERXD0, GPIO_FN_ET_ERXD1, + GPIO_FN_ET_ERXD2, GPIO_FN_ET_ERXD3, + GPIO_FN_ET_ERXD4, GPIO_FN_ET_ERXD5, /* for GEther */ + GPIO_FN_ET_ERXD6, GPIO_FN_ET_ERXD7, /* for GEther */ + GPIO_FN_ET_RX_ER, GPIO_FN_ET_CRS, + GPIO_FN_ET_MDC, GPIO_FN_ET_MDIO, + GPIO_FN_ET_LINK, GPIO_FN_ET_PHY_INT, + GPIO_FN_ET_WOL, GPIO_FN_ET_GTX_CLK, + + /* DMA0 */ + GPIO_FN_DREQ0, GPIO_FN_DACK0, + + /* DMA1 */ + GPIO_FN_DREQ1, GPIO_FN_DACK1, + + /* SYSC */ + GPIO_FN_RESETOUTS, + GPIO_FN_RESETP_PULLUP, + GPIO_FN_RESETP_PLAIN, + + /* SDENC */ + GPIO_FN_SDENC_CPG, + GPIO_FN_SDENC_DV_CLKI, + + /* IRREM */ + GPIO_FN_IROUT, + + /* DEBUG */ + GPIO_FN_EDEBGREQ_PULLDOWN, + GPIO_FN_EDEBGREQ_PULLUP, + + GPIO_FN_TRACEAUD_FROM_VIO, + GPIO_FN_TRACEAUD_FROM_LCDC0, + GPIO_FN_TRACEAUD_FROM_MEMC, +}; + +#endif /* __ASM_R8A7740_H__ */ diff --git a/arch/arm/mach-shmobile/include/mach/r8a7779.h b/arch/arm/mach-shmobile/include/mach/r8a7779.h new file mode 100644 index 00000000000..b07ad318eb2 --- /dev/null +++ b/arch/arm/mach-shmobile/include/mach/r8a7779.h @@ -0,0 +1,363 @@ +#ifndef __ASM_R8A7779_H__ +#define __ASM_R8A7779_H__ + +#include <linux/sh_clk.h> +#include <linux/pm_domain.h> + +/* Pin Function Controller: + * GPIO_FN_xx - GPIO used to select pin function + * GPIO_GP_x_x - GPIO mapped to real I/O pin on CPU + */ +enum { + GPIO_GP_0_0, GPIO_GP_0_1, GPIO_GP_0_2, GPIO_GP_0_3, + GPIO_GP_0_4, GPIO_GP_0_5, GPIO_GP_0_6, GPIO_GP_0_7, + GPIO_GP_0_8, GPIO_GP_0_9, GPIO_GP_0_10, GPIO_GP_0_11, + GPIO_GP_0_12, GPIO_GP_0_13, GPIO_GP_0_14, GPIO_GP_0_15, + GPIO_GP_0_16, GPIO_GP_0_17, GPIO_GP_0_18, GPIO_GP_0_19, + GPIO_GP_0_20, GPIO_GP_0_21, GPIO_GP_0_22, GPIO_GP_0_23, + GPIO_GP_0_24, GPIO_GP_0_25, GPIO_GP_0_26, GPIO_GP_0_27, + GPIO_GP_0_28, GPIO_GP_0_29, GPIO_GP_0_30, GPIO_GP_0_31, + + GPIO_GP_1_0, GPIO_GP_1_1, GPIO_GP_1_2, GPIO_GP_1_3, + GPIO_GP_1_4, GPIO_GP_1_5, GPIO_GP_1_6, GPIO_GP_1_7, + GPIO_GP_1_8, GPIO_GP_1_9, GPIO_GP_1_10, GPIO_GP_1_11, + GPIO_GP_1_12, GPIO_GP_1_13, GPIO_GP_1_14, GPIO_GP_1_15, + GPIO_GP_1_16, GPIO_GP_1_17, GPIO_GP_1_18, GPIO_GP_1_19, + GPIO_GP_1_20, GPIO_GP_1_21, GPIO_GP_1_22, GPIO_GP_1_23, + GPIO_GP_1_24, GPIO_GP_1_25, GPIO_GP_1_26, GPIO_GP_1_27, + GPIO_GP_1_28, GPIO_GP_1_29, GPIO_GP_1_30, GPIO_GP_1_31, + + GPIO_GP_2_0, GPIO_GP_2_1, GPIO_GP_2_2, GPIO_GP_2_3, + GPIO_GP_2_4, GPIO_GP_2_5, GPIO_GP_2_6, GPIO_GP_2_7, + GPIO_GP_2_8, GPIO_GP_2_9, GPIO_GP_2_10, GPIO_GP_2_11, + GPIO_GP_2_12, GPIO_GP_2_13, GPIO_GP_2_14, GPIO_GP_2_15, + GPIO_GP_2_16, GPIO_GP_2_17, GPIO_GP_2_18, GPIO_GP_2_19, + GPIO_GP_2_20, GPIO_GP_2_21, GPIO_GP_2_22, GPIO_GP_2_23, + GPIO_GP_2_24, GPIO_GP_2_25, GPIO_GP_2_26, GPIO_GP_2_27, + GPIO_GP_2_28, GPIO_GP_2_29, GPIO_GP_2_30, GPIO_GP_2_31, + + GPIO_GP_3_0, GPIO_GP_3_1, GPIO_GP_3_2, GPIO_GP_3_3, + GPIO_GP_3_4, GPIO_GP_3_5, GPIO_GP_3_6, GPIO_GP_3_7, + GPIO_GP_3_8, GPIO_GP_3_9, GPIO_GP_3_10, GPIO_GP_3_11, + GPIO_GP_3_12, GPIO_GP_3_13, GPIO_GP_3_14, GPIO_GP_3_15, + GPIO_GP_3_16, GPIO_GP_3_17, GPIO_GP_3_18, GPIO_GP_3_19, + GPIO_GP_3_20, GPIO_GP_3_21, GPIO_GP_3_22, GPIO_GP_3_23, + GPIO_GP_3_24, GPIO_GP_3_25, GPIO_GP_3_26, GPIO_GP_3_27, + GPIO_GP_3_28, GPIO_GP_3_29, GPIO_GP_3_30, GPIO_GP_3_31, + + GPIO_GP_4_0, GPIO_GP_4_1, GPIO_GP_4_2, GPIO_GP_4_3, + GPIO_GP_4_4, GPIO_GP_4_5, GPIO_GP_4_6, GPIO_GP_4_7, + GPIO_GP_4_8, GPIO_GP_4_9, GPIO_GP_4_10, GPIO_GP_4_11, + GPIO_GP_4_12, GPIO_GP_4_13, GPIO_GP_4_14, GPIO_GP_4_15, + GPIO_GP_4_16, GPIO_GP_4_17, GPIO_GP_4_18, GPIO_GP_4_19, + GPIO_GP_4_20, GPIO_GP_4_21, GPIO_GP_4_22, GPIO_GP_4_23, + GPIO_GP_4_24, GPIO_GP_4_25, GPIO_GP_4_26, GPIO_GP_4_27, + GPIO_GP_4_28, GPIO_GP_4_29, GPIO_GP_4_30, GPIO_GP_4_31, + + GPIO_GP_5_0, GPIO_GP_5_1, GPIO_GP_5_2, GPIO_GP_5_3, + GPIO_GP_5_4, GPIO_GP_5_5, GPIO_GP_5_6, GPIO_GP_5_7, + GPIO_GP_5_8, GPIO_GP_5_9, GPIO_GP_5_10, GPIO_GP_5_11, + GPIO_GP_5_12, GPIO_GP_5_13, GPIO_GP_5_14, GPIO_GP_5_15, + GPIO_GP_5_16, GPIO_GP_5_17, GPIO_GP_5_18, GPIO_GP_5_19, + GPIO_GP_5_20, GPIO_GP_5_21, GPIO_GP_5_22, GPIO_GP_5_23, + GPIO_GP_5_24, GPIO_GP_5_25, GPIO_GP_5_26, GPIO_GP_5_27, + GPIO_GP_5_28, GPIO_GP_5_29, GPIO_GP_5_30, GPIO_GP_5_31, + + GPIO_GP_6_0, GPIO_GP_6_1, GPIO_GP_6_2, GPIO_GP_6_3, + GPIO_GP_6_4, GPIO_GP_6_5, GPIO_GP_6_6, GPIO_GP_6_7, + GPIO_GP_6_8, + + GPIO_FN_AVS1, GPIO_FN_AVS2, GPIO_FN_A17, GPIO_FN_A18, + GPIO_FN_A19, + + /* IPSR0 */ + GPIO_FN_PENC2, GPIO_FN_SCK0, GPIO_FN_PWM1, GPIO_FN_PWMFSW0, + GPIO_FN_SCIF_CLK, GPIO_FN_TCLK0_C, GPIO_FN_BS, GPIO_FN_SD1_DAT2, + GPIO_FN_MMC0_D2, GPIO_FN_FD2, GPIO_FN_ATADIR0, GPIO_FN_SDSELF, + GPIO_FN_HCTS1, GPIO_FN_TX4_C, GPIO_FN_A0, GPIO_FN_SD1_DAT3, + GPIO_FN_MMC0_D3, GPIO_FN_FD3, GPIO_FN_A20, GPIO_FN_TX5_D, + GPIO_FN_HSPI_TX2_B, GPIO_FN_A21, GPIO_FN_SCK5_D, GPIO_FN_HSPI_CLK2_B, + GPIO_FN_A22, GPIO_FN_RX5_D, GPIO_FN_HSPI_RX2_B, GPIO_FN_VI1_R0, + GPIO_FN_A23, GPIO_FN_FCLE, GPIO_FN_HSPI_CLK2, GPIO_FN_VI1_R1, + GPIO_FN_A24, GPIO_FN_SD1_CD, GPIO_FN_MMC0_D4, GPIO_FN_FD4, + GPIO_FN_HSPI_CS2, GPIO_FN_VI1_R2, GPIO_FN_SSI_WS78_B, GPIO_FN_A25, + GPIO_FN_SD1_WP, GPIO_FN_MMC0_D5, GPIO_FN_FD5, GPIO_FN_HSPI_RX2, + GPIO_FN_VI1_R3, GPIO_FN_TX5_B, GPIO_FN_SSI_SDATA7_B, GPIO_FN_CTS0_B, + GPIO_FN_CLKOUT, GPIO_FN_TX3C_IRDA_TX_C, GPIO_FN_PWM0_B, GPIO_FN_CS0, + GPIO_FN_HSPI_CS2_B, GPIO_FN_CS1_A26, GPIO_FN_HSPI_TX2, + GPIO_FN_SDSELF_B, GPIO_FN_RD_WR, GPIO_FN_FWE, GPIO_FN_ATAG0, + GPIO_FN_VI1_R7, GPIO_FN_HRTS1, GPIO_FN_RX4_C, + + /* IPSR1 */ + GPIO_FN_EX_CS0, GPIO_FN_RX3_C_IRDA_RX_C, GPIO_FN_MMC0_D6, + GPIO_FN_FD6, GPIO_FN_EX_CS1, GPIO_FN_MMC0_D7, GPIO_FN_FD7, + GPIO_FN_EX_CS2, GPIO_FN_SD1_CLK, GPIO_FN_MMC0_CLK, GPIO_FN_FALE, + GPIO_FN_ATACS00, GPIO_FN_EX_CS3, GPIO_FN_SD1_CMD, GPIO_FN_MMC0_CMD, + GPIO_FN_FRE, GPIO_FN_ATACS10, GPIO_FN_VI1_R4, GPIO_FN_RX5_B, + GPIO_FN_HSCK1, GPIO_FN_SSI_SDATA8_B, GPIO_FN_RTS0_B_TANS_B, + GPIO_FN_SSI_SDATA9, GPIO_FN_EX_CS4, GPIO_FN_SD1_DAT0, GPIO_FN_MMC0_D0, + GPIO_FN_FD0, GPIO_FN_ATARD0, GPIO_FN_VI1_R5, GPIO_FN_SCK5_B, + GPIO_FN_HTX1, GPIO_FN_TX2_E, GPIO_FN_TX0_B, GPIO_FN_SSI_SCK9, + GPIO_FN_EX_CS5, GPIO_FN_SD1_DAT1, GPIO_FN_MMC0_D1, GPIO_FN_FD1, + GPIO_FN_ATAWR0, GPIO_FN_VI1_R6, GPIO_FN_HRX1, GPIO_FN_RX2_E, + GPIO_FN_RX0_B, GPIO_FN_SSI_WS9, GPIO_FN_MLB_CLK, GPIO_FN_PWM2, + GPIO_FN_SCK4, GPIO_FN_MLB_SIG, GPIO_FN_PWM3, GPIO_FN_TX4, + GPIO_FN_MLB_DAT, GPIO_FN_PWM4, GPIO_FN_RX4, GPIO_FN_HTX0, + GPIO_FN_TX1, GPIO_FN_SDATA, GPIO_FN_CTS0_C, GPIO_FN_SUB_TCK, + GPIO_FN_CC5_STATE2, GPIO_FN_CC5_STATE10, GPIO_FN_CC5_STATE18, + GPIO_FN_CC5_STATE26, GPIO_FN_CC5_STATE34, + + /* IPSR2 */ + GPIO_FN_HRX0, GPIO_FN_RX1, GPIO_FN_SCKZ, GPIO_FN_RTS0_C_TANS_C, + GPIO_FN_SUB_TDI, GPIO_FN_CC5_STATE3, GPIO_FN_CC5_STATE11, + GPIO_FN_CC5_STATE19, GPIO_FN_CC5_STATE27, GPIO_FN_CC5_STATE35, + GPIO_FN_HSCK0, GPIO_FN_SCK1, GPIO_FN_MTS, GPIO_FN_PWM5, + GPIO_FN_SCK0_C, GPIO_FN_SSI_SDATA9_B, GPIO_FN_SUB_TDO, + GPIO_FN_CC5_STATE0, GPIO_FN_CC5_STATE8, GPIO_FN_CC5_STATE16, + GPIO_FN_CC5_STATE24, GPIO_FN_CC5_STATE32, GPIO_FN_HCTS0, GPIO_FN_CTS1, + GPIO_FN_STM, GPIO_FN_PWM0_D, GPIO_FN_RX0_C, GPIO_FN_SCIF_CLK_C, + GPIO_FN_SUB_TRST, GPIO_FN_TCLK1_B, GPIO_FN_CC5_OSCOUT, GPIO_FN_HRTS0, + GPIO_FN_RTS1_TANS, GPIO_FN_MDATA, GPIO_FN_TX0_C, GPIO_FN_SUB_TMS, + GPIO_FN_CC5_STATE1, GPIO_FN_CC5_STATE9, GPIO_FN_CC5_STATE17, + GPIO_FN_CC5_STATE25, GPIO_FN_CC5_STATE33, GPIO_FN_DU0_DR0, + GPIO_FN_LCDOUT0, GPIO_FN_DREQ0, GPIO_FN_GPS_CLK_B, GPIO_FN_AUDATA0, + GPIO_FN_TX5_C, GPIO_FN_DU0_DR1, GPIO_FN_LCDOUT1, GPIO_FN_DACK0, + GPIO_FN_DRACK0, GPIO_FN_GPS_SIGN_B, GPIO_FN_AUDATA1, GPIO_FN_RX5_C, + GPIO_FN_DU0_DR2, GPIO_FN_LCDOUT2, GPIO_FN_DU0_DR3, GPIO_FN_LCDOUT3, + GPIO_FN_DU0_DR4, GPIO_FN_LCDOUT4, GPIO_FN_DU0_DR5, GPIO_FN_LCDOUT5, + GPIO_FN_DU0_DR6, GPIO_FN_LCDOUT6, GPIO_FN_DU0_DR7, GPIO_FN_LCDOUT7, + GPIO_FN_DU0_DG0, GPIO_FN_LCDOUT8, GPIO_FN_DREQ1, GPIO_FN_SCL2, + GPIO_FN_AUDATA2, + + /* IPSR3 */ + GPIO_FN_DU0_DG1, GPIO_FN_LCDOUT9, GPIO_FN_DACK1, GPIO_FN_SDA2, + GPIO_FN_AUDATA3, GPIO_FN_DU0_DG2, GPIO_FN_LCDOUT10, GPIO_FN_DU0_DG3, + GPIO_FN_LCDOUT11, GPIO_FN_DU0_DG4, GPIO_FN_LCDOUT12, GPIO_FN_DU0_DG5, + GPIO_FN_LCDOUT13, GPIO_FN_DU0_DG6, GPIO_FN_LCDOUT14, GPIO_FN_DU0_DG7, + GPIO_FN_LCDOUT15, GPIO_FN_DU0_DB0, GPIO_FN_LCDOUT16, GPIO_FN_EX_WAIT1, + GPIO_FN_SCL1, GPIO_FN_TCLK1, GPIO_FN_AUDATA4, GPIO_FN_DU0_DB1, + GPIO_FN_LCDOUT17, GPIO_FN_EX_WAIT2, GPIO_FN_SDA1, GPIO_FN_GPS_MAG_B, + GPIO_FN_AUDATA5, GPIO_FN_SCK5_C, GPIO_FN_DU0_DB2, GPIO_FN_LCDOUT18, + GPIO_FN_DU0_DB3, GPIO_FN_LCDOUT19, GPIO_FN_DU0_DB4, GPIO_FN_LCDOUT20, + GPIO_FN_DU0_DB5, GPIO_FN_LCDOUT21, GPIO_FN_DU0_DB6, GPIO_FN_LCDOUT22, + GPIO_FN_DU0_DB7, GPIO_FN_LCDOUT23, GPIO_FN_DU0_DOTCLKIN, + GPIO_FN_QSTVA_QVS, GPIO_FN_TX3_D_IRDA_TX_D, GPIO_FN_SCL3_B, + GPIO_FN_DU0_DOTCLKOUT0, GPIO_FN_QCLK, GPIO_FN_DU0_DOTCLKOUT1, + GPIO_FN_QSTVB_QVE, GPIO_FN_RX3_D_IRDA_RX_D, GPIO_FN_SDA3_B, + GPIO_FN_SDA2_C, GPIO_FN_DACK0_B, GPIO_FN_DRACK0_B, + GPIO_FN_DU0_EXHSYNC_DU0_HSYNC, GPIO_FN_QSTH_QHS, + GPIO_FN_DU0_EXVSYNC_DU0_VSYNC, GPIO_FN_QSTB_QHE, + GPIO_FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, GPIO_FN_QCPV_QDE, + GPIO_FN_CAN1_TX, GPIO_FN_TX2_C, GPIO_FN_SCL2_C, GPIO_FN_REMOCON, + + /* IPSR4 */ + GPIO_FN_DU0_DISP, GPIO_FN_QPOLA, GPIO_FN_CAN_CLK_C, GPIO_FN_SCK2_C, + GPIO_FN_DU0_CDE, GPIO_FN_QPOLB, GPIO_FN_CAN1_RX, GPIO_FN_RX2_C, + GPIO_FN_DREQ0_B, GPIO_FN_SSI_SCK78_B, GPIO_FN_SCK0_B, GPIO_FN_DU1_DR0, + GPIO_FN_VI2_DATA0_VI2_B0, GPIO_FN_PWM6, GPIO_FN_SD3_CLK, + GPIO_FN_TX3_E_IRDA_TX_E, GPIO_FN_AUDCK, GPIO_FN_PWMFSW0_B, + GPIO_FN_DU1_DR1, GPIO_FN_VI2_DATA1_VI2_B1, GPIO_FN_PWM0, + GPIO_FN_SD3_CMD, GPIO_FN_RX3_E_IRDA_RX_E, GPIO_FN_AUDSYNC, + GPIO_FN_CTS0_D, GPIO_FN_DU1_DR2, GPIO_FN_VI2_G0, GPIO_FN_DU1_DR3, + GPIO_FN_VI2_G1, GPIO_FN_DU1_DR4, GPIO_FN_VI2_G2, GPIO_FN_DU1_DR5, + GPIO_FN_VI2_G3, GPIO_FN_DU1_DR6, GPIO_FN_VI2_G4, GPIO_FN_DU1_DR7, + GPIO_FN_VI2_G5, GPIO_FN_DU1_DG0, GPIO_FN_VI2_DATA2_VI2_B2, + GPIO_FN_SCL1_B, GPIO_FN_SD3_DAT2, GPIO_FN_SCK3_E, GPIO_FN_AUDATA6, + GPIO_FN_TX0_D, GPIO_FN_DU1_DG1, GPIO_FN_VI2_DATA3_VI2_B3, + GPIO_FN_SDA1_B, GPIO_FN_SD3_DAT3, GPIO_FN_SCK5, GPIO_FN_AUDATA7, + GPIO_FN_RX0_D, GPIO_FN_DU1_DG2, GPIO_FN_VI2_G6, GPIO_FN_DU1_DG3, + GPIO_FN_VI2_G7, GPIO_FN_DU1_DG4, GPIO_FN_VI2_R0, GPIO_FN_DU1_DG5, + GPIO_FN_VI2_R1, GPIO_FN_DU1_DG6, GPIO_FN_VI2_R2, GPIO_FN_DU1_DG7, + GPIO_FN_VI2_R3, GPIO_FN_DU1_DB0, GPIO_FN_VI2_DATA4_VI2_B4, + GPIO_FN_SCL2_B, GPIO_FN_SD3_DAT0, GPIO_FN_TX5, GPIO_FN_SCK0_D, + + /* IPSR5 */ + GPIO_FN_DU1_DB1, GPIO_FN_VI2_DATA5_VI2_B5, GPIO_FN_SDA2_B, + GPIO_FN_SD3_DAT1, GPIO_FN_RX5, GPIO_FN_RTS0_D_TANS_D, + GPIO_FN_DU1_DB2, GPIO_FN_VI2_R4, GPIO_FN_DU1_DB3, GPIO_FN_VI2_R5, + GPIO_FN_DU1_DB4, GPIO_FN_VI2_R6, GPIO_FN_DU1_DB5, GPIO_FN_VI2_R7, + GPIO_FN_DU1_DB6, GPIO_FN_SCL2_D, GPIO_FN_DU1_DB7, GPIO_FN_SDA2_D, + GPIO_FN_DU1_DOTCLKIN, GPIO_FN_VI2_CLKENB, GPIO_FN_HSPI_CS1, + GPIO_FN_SCL1_D, GPIO_FN_DU1_DOTCLKOUT, GPIO_FN_VI2_FIELD, + GPIO_FN_SDA1_D, GPIO_FN_DU1_EXHSYNC_DU1_HSYNC, GPIO_FN_VI2_HSYNC, + GPIO_FN_VI3_HSYNC, GPIO_FN_DU1_EXVSYNC_DU1_VSYNC, GPIO_FN_VI2_VSYNC, + GPIO_FN_VI3_VSYNC, GPIO_FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, + GPIO_FN_VI2_CLK, GPIO_FN_TX3_B_IRDA_TX_B, GPIO_FN_SD3_CD, + GPIO_FN_HSPI_TX1, GPIO_FN_VI1_CLKENB, GPIO_FN_VI3_CLKENB, + GPIO_FN_AUDIO_CLKC, GPIO_FN_TX2_D, GPIO_FN_SPEEDIN, + GPIO_FN_GPS_SIGN_D, GPIO_FN_DU1_DISP, GPIO_FN_VI2_DATA6_VI2_B6, + GPIO_FN_TCLK0, GPIO_FN_QSTVA_B_QVS_B, GPIO_FN_HSPI_CLK1, + GPIO_FN_SCK2_D, GPIO_FN_AUDIO_CLKOUT_B, GPIO_FN_GPS_MAG_D, + GPIO_FN_DU1_CDE, GPIO_FN_VI2_DATA7_VI2_B7, GPIO_FN_RX3_B_IRDA_RX_B, + GPIO_FN_SD3_WP, GPIO_FN_HSPI_RX1, GPIO_FN_VI1_FIELD, GPIO_FN_VI3_FIELD, + GPIO_FN_AUDIO_CLKOUT, GPIO_FN_RX2_D, GPIO_FN_GPS_CLK_C, + GPIO_FN_GPS_CLK_D, GPIO_FN_AUDIO_CLKA, GPIO_FN_CAN_TXCLK, + GPIO_FN_AUDIO_CLKB, GPIO_FN_USB_OVC2, GPIO_FN_CAN_DEBUGOUT0, + GPIO_FN_MOUT0, + + /* IPSR6 */ + GPIO_FN_SSI_SCK0129, GPIO_FN_CAN_DEBUGOUT1, GPIO_FN_MOUT1, + GPIO_FN_SSI_WS0129, GPIO_FN_CAN_DEBUGOUT2, GPIO_FN_MOUT2, + GPIO_FN_SSI_SDATA0, GPIO_FN_CAN_DEBUGOUT3, GPIO_FN_MOUT5, + GPIO_FN_SSI_SDATA1, GPIO_FN_CAN_DEBUGOUT4, GPIO_FN_MOUT6, + GPIO_FN_SSI_SDATA2, GPIO_FN_CAN_DEBUGOUT5, GPIO_FN_SSI_SCK34, + GPIO_FN_CAN_DEBUGOUT6, GPIO_FN_CAN0_TX_B, GPIO_FN_IERX, + GPIO_FN_SSI_SCK9_C, GPIO_FN_SSI_WS34, GPIO_FN_CAN_DEBUGOUT7, + GPIO_FN_CAN0_RX_B, GPIO_FN_IETX, GPIO_FN_SSI_WS9_C, + GPIO_FN_SSI_SDATA3, GPIO_FN_PWM0_C, GPIO_FN_CAN_DEBUGOUT8, + GPIO_FN_CAN_CLK_B, GPIO_FN_IECLK, GPIO_FN_SCIF_CLK_B, GPIO_FN_TCLK0_B, + GPIO_FN_SSI_SDATA4, GPIO_FN_CAN_DEBUGOUT9, GPIO_FN_SSI_SDATA9_C, + GPIO_FN_SSI_SCK5, GPIO_FN_ADICLK, GPIO_FN_CAN_DEBUGOUT10, + GPIO_FN_SCK3, GPIO_FN_TCLK0_D, GPIO_FN_SSI_WS5, GPIO_FN_ADICS_SAMP, + GPIO_FN_CAN_DEBUGOUT11, GPIO_FN_TX3_IRDA_TX, GPIO_FN_SSI_SDATA5, + GPIO_FN_ADIDATA, GPIO_FN_CAN_DEBUGOUT12, GPIO_FN_RX3_IRDA_RX, + GPIO_FN_SSI_SCK6, GPIO_FN_ADICHS0, GPIO_FN_CAN0_TX, GPIO_FN_IERX_B, + + /* IPSR7 */ + GPIO_FN_SSI_WS6, GPIO_FN_ADICHS1, GPIO_FN_CAN0_RX, GPIO_FN_IETX_B, + GPIO_FN_SSI_SDATA6, GPIO_FN_ADICHS2, GPIO_FN_CAN_CLK, GPIO_FN_IECLK_B, + GPIO_FN_SSI_SCK78, GPIO_FN_CAN_DEBUGOUT13, GPIO_FN_IRQ0_B, + GPIO_FN_SSI_SCK9_B, GPIO_FN_HSPI_CLK1_C, GPIO_FN_SSI_WS78, + GPIO_FN_CAN_DEBUGOUT14, GPIO_FN_IRQ1_B, GPIO_FN_SSI_WS9_B, + GPIO_FN_HSPI_CS1_C, GPIO_FN_SSI_SDATA7, GPIO_FN_CAN_DEBUGOUT15, + GPIO_FN_IRQ2_B, GPIO_FN_TCLK1_C, GPIO_FN_HSPI_TX1_C, + GPIO_FN_SSI_SDATA8, GPIO_FN_VSP, GPIO_FN_IRQ3_B, GPIO_FN_HSPI_RX1_C, + GPIO_FN_SD0_CLK, GPIO_FN_ATACS01, GPIO_FN_SCK1_B, GPIO_FN_SD0_CMD, + GPIO_FN_ATACS11, GPIO_FN_TX1_B, GPIO_FN_CC5_TDO, GPIO_FN_SD0_DAT0, + GPIO_FN_ATADIR1, GPIO_FN_RX1_B, GPIO_FN_CC5_TRST, GPIO_FN_SD0_DAT1, + GPIO_FN_ATAG1, GPIO_FN_SCK2_B, GPIO_FN_CC5_TMS, GPIO_FN_SD0_DAT2, + GPIO_FN_ATARD1, GPIO_FN_TX2_B, GPIO_FN_CC5_TCK, GPIO_FN_SD0_DAT3, + GPIO_FN_ATAWR1, GPIO_FN_RX2_B, GPIO_FN_CC5_TDI, GPIO_FN_SD0_CD, + GPIO_FN_DREQ2, GPIO_FN_RTS1_B_TANS_B, GPIO_FN_SD0_WP, GPIO_FN_DACK2, + GPIO_FN_CTS1_B, + + /* IPSR8 */ + GPIO_FN_HSPI_CLK0, GPIO_FN_CTS0, GPIO_FN_USB_OVC0, GPIO_FN_AD_CLK, + GPIO_FN_CC5_STATE4, GPIO_FN_CC5_STATE12, GPIO_FN_CC5_STATE20, + GPIO_FN_CC5_STATE28, GPIO_FN_CC5_STATE36, GPIO_FN_HSPI_CS0, + GPIO_FN_RTS0_TANS, GPIO_FN_USB_OVC1, GPIO_FN_AD_DI, + GPIO_FN_CC5_STATE5, GPIO_FN_CC5_STATE13, GPIO_FN_CC5_STATE21, + GPIO_FN_CC5_STATE29, GPIO_FN_CC5_STATE37, GPIO_FN_HSPI_TX0, + GPIO_FN_TX0, GPIO_FN_CAN_DEBUG_HW_TRIGGER, GPIO_FN_AD_DO, + GPIO_FN_CC5_STATE6, GPIO_FN_CC5_STATE14, GPIO_FN_CC5_STATE22, + GPIO_FN_CC5_STATE30, GPIO_FN_CC5_STATE38, GPIO_FN_HSPI_RX0, + GPIO_FN_RX0, GPIO_FN_CAN_STEP0, GPIO_FN_AD_NCS, GPIO_FN_CC5_STATE7, + GPIO_FN_CC5_STATE15, GPIO_FN_CC5_STATE23, GPIO_FN_CC5_STATE31, + GPIO_FN_CC5_STATE39, GPIO_FN_FMCLK, GPIO_FN_RDS_CLK, GPIO_FN_PCMOE, + GPIO_FN_BPFCLK, GPIO_FN_PCMWE, GPIO_FN_FMIN, GPIO_FN_RDS_DATA, + GPIO_FN_VI0_CLK, GPIO_FN_MMC1_CLK, GPIO_FN_VI0_CLKENB, GPIO_FN_TX1_C, + GPIO_FN_HTX1_B, GPIO_FN_MT1_SYNC, GPIO_FN_VI0_FIELD, GPIO_FN_RX1_C, + GPIO_FN_HRX1_B, GPIO_FN_VI0_HSYNC, GPIO_FN_VI0_DATA0_B_VI0_B0_B, + GPIO_FN_CTS1_C, GPIO_FN_TX4_D, GPIO_FN_MMC1_CMD, GPIO_FN_HSCK1_B, + GPIO_FN_VI0_VSYNC, GPIO_FN_VI0_DATA1_B_VI0_B1_B, + GPIO_FN_RTS1_C_TANS_C, GPIO_FN_RX4_D, GPIO_FN_PWMFSW0_C, + + /* IPSR9 */ + GPIO_FN_VI0_DATA0_VI0_B0, GPIO_FN_HRTS1_B, GPIO_FN_MT1_VCXO, + GPIO_FN_VI0_DATA1_VI0_B1, GPIO_FN_HCTS1_B, GPIO_FN_MT1_PWM, + GPIO_FN_VI0_DATA2_VI0_B2, GPIO_FN_MMC1_D0, GPIO_FN_VI0_DATA3_VI0_B3, + GPIO_FN_MMC1_D1, GPIO_FN_VI0_DATA4_VI0_B4, GPIO_FN_MMC1_D2, + GPIO_FN_VI0_DATA5_VI0_B5, GPIO_FN_MMC1_D3, GPIO_FN_VI0_DATA6_VI0_B6, + GPIO_FN_MMC1_D4, GPIO_FN_ARM_TRACEDATA_0, GPIO_FN_VI0_DATA7_VI0_B7, + GPIO_FN_MMC1_D5, GPIO_FN_ARM_TRACEDATA_1, GPIO_FN_VI0_G0, + GPIO_FN_SSI_SCK78_C, GPIO_FN_IRQ0, GPIO_FN_ARM_TRACEDATA_2, + GPIO_FN_VI0_G1, GPIO_FN_SSI_WS78_C, GPIO_FN_IRQ1, + GPIO_FN_ARM_TRACEDATA_3, GPIO_FN_VI0_G2, GPIO_FN_ETH_TXD1, + GPIO_FN_MMC1_D6, GPIO_FN_ARM_TRACEDATA_4, GPIO_FN_TS_SPSYNC0, + GPIO_FN_VI0_G3, GPIO_FN_ETH_CRS_DV, GPIO_FN_MMC1_D7, + GPIO_FN_ARM_TRACEDATA_5, GPIO_FN_TS_SDAT0, GPIO_FN_VI0_G4, + GPIO_FN_ETH_TX_EN, GPIO_FN_SD2_DAT0_B, GPIO_FN_ARM_TRACEDATA_6, + GPIO_FN_VI0_G5, GPIO_FN_ETH_RX_ER, GPIO_FN_SD2_DAT1_B, + GPIO_FN_ARM_TRACEDATA_7, GPIO_FN_VI0_G6, GPIO_FN_ETH_RXD0, + GPIO_FN_SD2_DAT2_B, GPIO_FN_ARM_TRACEDATA_8, GPIO_FN_VI0_G7, + GPIO_FN_ETH_RXD1, GPIO_FN_SD2_DAT3_B, GPIO_FN_ARM_TRACEDATA_9, + + /* IPSR10 */ + GPIO_FN_VI0_R0, GPIO_FN_SSI_SDATA7_C, GPIO_FN_SCK1_C, GPIO_FN_DREQ1_B, + GPIO_FN_ARM_TRACEDATA_10, GPIO_FN_DREQ0_C, GPIO_FN_VI0_R1, + GPIO_FN_SSI_SDATA8_C, GPIO_FN_DACK1_B, GPIO_FN_ARM_TRACEDATA_11, + GPIO_FN_DACK0_C, GPIO_FN_DRACK0_C, GPIO_FN_VI0_R2, GPIO_FN_ETH_LINK, + GPIO_FN_SD2_CLK_B, GPIO_FN_IRQ2, GPIO_FN_ARM_TRACEDATA_12, + GPIO_FN_VI0_R3, GPIO_FN_ETH_MAGIC, GPIO_FN_SD2_CMD_B, GPIO_FN_IRQ3, + GPIO_FN_ARM_TRACEDATA_13, GPIO_FN_VI0_R4, GPIO_FN_ETH_REFCLK, + GPIO_FN_SD2_CD_B, GPIO_FN_HSPI_CLK1_B, GPIO_FN_ARM_TRACEDATA_14, + GPIO_FN_MT1_CLK, GPIO_FN_TS_SCK0, GPIO_FN_VI0_R5, GPIO_FN_ETH_TXD0, + GPIO_FN_SD2_WP_B, GPIO_FN_HSPI_CS1_B, GPIO_FN_ARM_TRACEDATA_15, + GPIO_FN_MT1_D, GPIO_FN_TS_SDEN0, GPIO_FN_VI0_R6, GPIO_FN_ETH_MDC, + GPIO_FN_DREQ2_C, GPIO_FN_HSPI_TX1_B, GPIO_FN_TRACECLK, + GPIO_FN_MT1_BEN, GPIO_FN_PWMFSW0_D, GPIO_FN_VI0_R7, GPIO_FN_ETH_MDIO, + GPIO_FN_DACK2_C, GPIO_FN_HSPI_RX1_B, GPIO_FN_SCIF_CLK_D, + GPIO_FN_TRACECTL, GPIO_FN_MT1_PEN, GPIO_FN_VI1_CLK, GPIO_FN_SIM_D, + GPIO_FN_SDA3, GPIO_FN_VI1_HSYNC, GPIO_FN_VI3_CLK, GPIO_FN_SSI_SCK4, + GPIO_FN_GPS_SIGN_C, GPIO_FN_PWMFSW0_E, GPIO_FN_VI1_VSYNC, + GPIO_FN_AUDIO_CLKOUT_C, GPIO_FN_SSI_WS4, GPIO_FN_SIM_CLK, + GPIO_FN_GPS_MAG_C, GPIO_FN_SPV_TRST, GPIO_FN_SCL3, + + /* IPSR11 */ + GPIO_FN_VI1_DATA0_VI1_B0, GPIO_FN_SD2_DAT0, GPIO_FN_SIM_RST, + GPIO_FN_SPV_TCK, GPIO_FN_ADICLK_B, GPIO_FN_VI1_DATA1_VI1_B1, + GPIO_FN_SD2_DAT1, GPIO_FN_MT0_CLK, GPIO_FN_SPV_TMS, + GPIO_FN_ADICS_B_SAMP_B, GPIO_FN_VI1_DATA2_VI1_B2, GPIO_FN_SD2_DAT2, + GPIO_FN_MT0_D, GPIO_FN_SPVTDI, GPIO_FN_ADIDATA_B, + GPIO_FN_VI1_DATA3_VI1_B3, GPIO_FN_SD2_DAT3, GPIO_FN_MT0_BEN, + GPIO_FN_SPV_TDO, GPIO_FN_ADICHS0_B, GPIO_FN_VI1_DATA4_VI1_B4, + GPIO_FN_SD2_CLK, GPIO_FN_MT0_PEN, GPIO_FN_SPA_TRST, + GPIO_FN_HSPI_CLK1_D, GPIO_FN_ADICHS1_B, GPIO_FN_VI1_DATA5_VI1_B5, + GPIO_FN_SD2_CMD, GPIO_FN_MT0_SYNC, GPIO_FN_SPA_TCK, + GPIO_FN_HSPI_CS1_D, GPIO_FN_ADICHS2_B, GPIO_FN_VI1_DATA6_VI1_B6, + GPIO_FN_SD2_CD, GPIO_FN_MT0_VCXO, GPIO_FN_SPA_TMS, GPIO_FN_HSPI_TX1_D, + GPIO_FN_VI1_DATA7_VI1_B7, GPIO_FN_SD2_WP, GPIO_FN_MT0_PWM, + GPIO_FN_SPA_TDI, GPIO_FN_HSPI_RX1_D, GPIO_FN_VI1_G0, GPIO_FN_VI3_DATA0, + GPIO_FN_DU1_DOTCLKOUT1, GPIO_FN_TS_SCK1, GPIO_FN_DREQ2_B, GPIO_FN_TX2, + GPIO_FN_SPA_TDO, GPIO_FN_HCTS0_B, GPIO_FN_VI1_G1, GPIO_FN_VI3_DATA1, + GPIO_FN_SSI_SCK1, GPIO_FN_TS_SDEN1, GPIO_FN_DACK2_B, GPIO_FN_RX2, + GPIO_FN_HRTS0_B, + + /* IPSR12 */ + GPIO_FN_VI1_G2, GPIO_FN_VI3_DATA2, GPIO_FN_SSI_WS1, GPIO_FN_TS_SPSYNC1, + GPIO_FN_SCK2, GPIO_FN_HSCK0_B, GPIO_FN_VI1_G3, GPIO_FN_VI3_DATA3, + GPIO_FN_SSI_SCK2, GPIO_FN_TS_SDAT1, GPIO_FN_SCL1_C, GPIO_FN_HTX0_B, + GPIO_FN_VI1_G4, GPIO_FN_VI3_DATA4, GPIO_FN_SSI_WS2, GPIO_FN_SDA1_C, + GPIO_FN_SIM_RST_B, GPIO_FN_HRX0_B, GPIO_FN_VI1_G5, GPIO_FN_VI3_DATA5, + GPIO_FN_GPS_CLK, GPIO_FN_FSE, GPIO_FN_TX4_B, GPIO_FN_SIM_D_B, + GPIO_FN_VI1_G6, GPIO_FN_VI3_DATA6, GPIO_FN_GPS_SIGN, GPIO_FN_FRB, + GPIO_FN_RX4_B, GPIO_FN_SIM_CLK_B, GPIO_FN_VI1_G7, GPIO_FN_VI3_DATA7, + GPIO_FN_GPS_MAG, GPIO_FN_FCE, GPIO_FN_SCK4_B, +}; + +struct platform_device; + +struct r8a7779_pm_ch { + unsigned long chan_offs; + unsigned int chan_bit; + unsigned int isr_bit; +}; + +struct r8a7779_pm_domain { + struct generic_pm_domain genpd; + struct r8a7779_pm_ch ch; +}; + +static inline struct r8a7779_pm_ch *to_r8a7779_ch(struct generic_pm_domain *d) +{ + return &container_of(d, struct r8a7779_pm_domain, genpd)->ch; +} + +extern int r8a7779_sysc_power_down(struct r8a7779_pm_ch *r8a7779_ch); +extern int r8a7779_sysc_power_up(struct r8a7779_pm_ch *r8a7779_ch); + +#ifdef CONFIG_PM +extern struct r8a7779_pm_domain r8a7779_sh4a; +extern struct r8a7779_pm_domain r8a7779_sgx; +extern struct r8a7779_pm_domain r8a7779_vdp1; +extern struct r8a7779_pm_domain r8a7779_impx3; + +extern void r8a7779_init_pm_domain(struct r8a7779_pm_domain *r8a7779_pd); +extern void r8a7779_add_device_to_domain(struct r8a7779_pm_domain *r8a7779_pd, + struct platform_device *pdev); +#else +#define r8a7779_init_pm_domain(pd) do { } while (0) +#define r8a7779_add_device_to_domain(pd, pdev) do { } while (0) +#endif /* CONFIG_PM */ + +#endif /* __ASM_R8A7779_H__ */ diff --git a/arch/arm/mach-shmobile/include/mach/sh7372.h b/arch/arm/mach-shmobile/include/mach/sh7372.h index 84532f9629b..8254ab86f6c 100644 --- a/arch/arm/mach-shmobile/include/mach/sh7372.h +++ b/arch/arm/mach-shmobile/include/mach/sh7372.h @@ -480,11 +480,10 @@ struct platform_device; struct sh7372_pm_domain { struct generic_pm_domain genpd; struct dev_power_governor *gov; - void (*suspend)(void); + int (*suspend)(void); void (*resume)(void); unsigned int bit_shift; bool no_debug; - bool stay_on; }; static inline struct sh7372_pm_domain *to_sh7372_pd(struct generic_pm_domain *d) @@ -499,6 +498,7 @@ extern struct sh7372_pm_domain sh7372_d4; extern struct sh7372_pm_domain sh7372_a4r; extern struct sh7372_pm_domain sh7372_a3rv; extern struct sh7372_pm_domain sh7372_a3ri; +extern struct sh7372_pm_domain sh7372_a4s; extern struct sh7372_pm_domain sh7372_a3sp; extern struct sh7372_pm_domain sh7372_a3sg; @@ -515,5 +515,7 @@ extern void sh7372_pm_add_subdomain(struct sh7372_pm_domain *sh7372_pd, extern void sh7372_intcs_suspend(void); extern void sh7372_intcs_resume(void); +extern void sh7372_intca_suspend(void); +extern void sh7372_intca_resume(void); #endif /* __ASM_SH7372_H__ */ diff --git a/arch/arm/mach-shmobile/intc-r8a7740.c b/arch/arm/mach-shmobile/intc-r8a7740.c new file mode 100644 index 00000000000..272c84c20c8 --- /dev/null +++ b/arch/arm/mach-shmobile/intc-r8a7740.c @@ -0,0 +1,631 @@ +/* + * R8A7740 processor support + * + * Copyright (C) 2011 Renesas Solutions Corp. + * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/io.h> +#include <linux/sh_intc.h> +#include <mach/intc.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> + +/* + * INTCA + */ +enum { + UNUSED_INTCA = 0, + + /* interrupt sources INTCA */ + DIRC, + ATAPI, + IIC1_ALI, IIC1_TACKI, IIC1_WAITI, IIC1_DTEI, + AP_ARM_COMMTX, AP_ARM_COMMRX, + MFI, MFIS, + BBIF1, BBIF2, + USBHSDMAC, + USBF_OUL_SOF, USBF_IXL_INT, + SGX540, + CMT1_0, CMT1_1, CMT1_2, CMT1_3, + CMT2, + CMT3, + KEYSC, + SCIFA0, SCIFA1, SCIFA2, SCIFA3, + MSIOF2, MSIOF1, + SCIFA4, SCIFA5, SCIFB, + FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I, + SDHI0_0, SDHI0_1, SDHI0_2, SDHI0_3, + SDHI1_0, SDHI1_1, SDHI1_2, SDHI1_3, + AP_ARM_L2CINT, + IRDA, + TPU0, + SCIFA6, SCIFA7, + GbEther, + ICBS0, + DDM, + SDHI2_0, SDHI2_1, SDHI2_2, SDHI2_3, + RWDT0, + DMAC1_1_DEI0, DMAC1_1_DEI1, DMAC1_1_DEI2, DMAC1_1_DEI3, + DMAC1_2_DEI4, DMAC1_2_DEI5, DMAC1_2_DADERR, + DMAC2_1_DEI0, DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3, + DMAC2_2_DEI4, DMAC2_2_DEI5, DMAC2_2_DADERR, + DMAC3_1_DEI0, DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3, + DMAC3_2_DEI4, DMAC3_2_DEI5, DMAC3_2_DADERR, + SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM, + USBH_INT, USBH_OHCI, USBH_EHCI, USBH_PME, USBH_BIND, + RSPI_OVRF, RSPI_SPTEF, RSPI_SPRF, + SPU2_0, SPU2_1, + FSI, FMSI, + IPMMU, + AP_ARM_CTIIRQ, AP_ARM_PMURQ, + MFIS2, + CPORTR2S, + CMT14, CMT15, + MMCIF_0, MMCIF_1, MMCIF_2, + SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI, + STPRO_0, STPRO_1, STPRO_2, STPRO_3, STPRO_4, + + /* interrupt groups INTCA */ + DMAC1_1, DMAC1_2, + DMAC2_1, DMAC2_2, + DMAC3_1, DMAC3_2, + AP_ARM1, AP_ARM2, + SDHI0, SDHI1, SDHI2, + SHWYSTAT, + USBF, USBH1, USBH2, + RSPI, SPU2, FLCTL, IIC1, +}; + +static struct intc_vect intca_vectors[] __initdata = { + INTC_VECT(DIRC, 0x0560), + INTC_VECT(ATAPI, 0x05E0), + INTC_VECT(IIC1_ALI, 0x0780), + INTC_VECT(IIC1_TACKI, 0x07A0), + INTC_VECT(IIC1_WAITI, 0x07C0), + INTC_VECT(IIC1_DTEI, 0x07E0), + INTC_VECT(AP_ARM_COMMTX, 0x0840), + INTC_VECT(AP_ARM_COMMRX, 0x0860), + INTC_VECT(MFI, 0x0900), + INTC_VECT(MFIS, 0x0920), + INTC_VECT(BBIF1, 0x0940), + INTC_VECT(BBIF2, 0x0960), + INTC_VECT(USBHSDMAC, 0x0A00), + INTC_VECT(USBF_OUL_SOF, 0x0A20), + INTC_VECT(USBF_IXL_INT, 0x0A40), + INTC_VECT(SGX540, 0x0A60), + INTC_VECT(CMT1_0, 0x0B00), + INTC_VECT(CMT1_1, 0x0B20), + INTC_VECT(CMT1_2, 0x0B40), + INTC_VECT(CMT1_3, 0x0B60), + INTC_VECT(CMT2, 0x0B80), + INTC_VECT(CMT3, 0x0BA0), + INTC_VECT(KEYSC, 0x0BE0), + INTC_VECT(SCIFA0, 0x0C00), + INTC_VECT(SCIFA1, 0x0C20), + INTC_VECT(SCIFA2, 0x0C40), + INTC_VECT(SCIFA3, 0x0C60), + INTC_VECT(MSIOF2, 0x0C80), + INTC_VECT(MSIOF1, 0x0D00), + INTC_VECT(SCIFA4, 0x0D20), + INTC_VECT(SCIFA5, 0x0D40), + INTC_VECT(SCIFB, 0x0D60), + INTC_VECT(FLCTL_FLSTEI, 0x0D80), + INTC_VECT(FLCTL_FLTENDI, 0x0DA0), + INTC_VECT(FLCTL_FLTREQ0I, 0x0DC0), + INTC_VECT(FLCTL_FLTREQ1I, 0x0DE0), + INTC_VECT(SDHI0_0, 0x0E00), + INTC_VECT(SDHI0_1, 0x0E20), + INTC_VECT(SDHI0_2, 0x0E40), + INTC_VECT(SDHI0_3, 0x0E60), + INTC_VECT(SDHI1_0, 0x0E80), + INTC_VECT(SDHI1_1, 0x0EA0), + INTC_VECT(SDHI1_2, 0x0EC0), + INTC_VECT(SDHI1_3, 0x0EE0), + INTC_VECT(AP_ARM_L2CINT, 0x0FA0), + INTC_VECT(IRDA, 0x0480), + INTC_VECT(TPU0, 0x04A0), + INTC_VECT(SCIFA6, 0x04C0), + INTC_VECT(SCIFA7, 0x04E0), + INTC_VECT(GbEther, 0x0500), + INTC_VECT(ICBS0, 0x0540), + INTC_VECT(DDM, 0x1140), + INTC_VECT(SDHI2_0, 0x1200), + INTC_VECT(SDHI2_1, 0x1220), + INTC_VECT(SDHI2_2, 0x1240), + INTC_VECT(SDHI2_3, 0x1260), + INTC_VECT(RWDT0, 0x1280), + INTC_VECT(DMAC1_1_DEI0, 0x2000), + INTC_VECT(DMAC1_1_DEI1, 0x2020), + INTC_VECT(DMAC1_1_DEI2, 0x2040), + INTC_VECT(DMAC1_1_DEI3, 0x2060), + INTC_VECT(DMAC1_2_DEI4, 0x2080), + INTC_VECT(DMAC1_2_DEI5, 0x20A0), + INTC_VECT(DMAC1_2_DADERR, 0x20C0), + INTC_VECT(DMAC2_1_DEI0, 0x2100), + INTC_VECT(DMAC2_1_DEI1, 0x2120), + INTC_VECT(DMAC2_1_DEI2, 0x2140), + INTC_VECT(DMAC2_1_DEI3, 0x2160), + INTC_VECT(DMAC2_2_DEI4, 0x2180), + INTC_VECT(DMAC2_2_DEI5, 0x21A0), + INTC_VECT(DMAC2_2_DADERR, 0x21C0), + INTC_VECT(DMAC3_1_DEI0, 0x2200), + INTC_VECT(DMAC3_1_DEI1, 0x2220), + INTC_VECT(DMAC3_1_DEI2, 0x2240), + INTC_VECT(DMAC3_1_DEI3, 0x2260), + INTC_VECT(DMAC3_2_DEI4, 0x2280), + INTC_VECT(DMAC3_2_DEI5, 0x22A0), + INTC_VECT(DMAC3_2_DADERR, 0x22C0), + INTC_VECT(SHWYSTAT_RT, 0x1300), + INTC_VECT(SHWYSTAT_HS, 0x1320), + INTC_VECT(SHWYSTAT_COM, 0x1340), + INTC_VECT(USBH_INT, 0x1540), + INTC_VECT(USBH_OHCI, 0x1560), + INTC_VECT(USBH_EHCI, 0x1580), + INTC_VECT(USBH_PME, 0x15A0), + INTC_VECT(USBH_BIND, 0x15C0), + INTC_VECT(RSPI_OVRF, 0x1780), + INTC_VECT(RSPI_SPTEF, 0x17A0), + INTC_VECT(RSPI_SPRF, 0x17C0), + INTC_VECT(SPU2_0, 0x1800), + INTC_VECT(SPU2_1, 0x1820), + INTC_VECT(FSI, 0x1840), + INTC_VECT(FMSI, 0x1860), + INTC_VECT(IPMMU, 0x1920), + INTC_VECT(AP_ARM_CTIIRQ, 0x1980), + INTC_VECT(AP_ARM_PMURQ, 0x19A0), + INTC_VECT(MFIS2, 0x1A00), + INTC_VECT(CPORTR2S, 0x1A20), + INTC_VECT(CMT14, 0x1A40), + INTC_VECT(CMT15, 0x1A60), + INTC_VECT(MMCIF_0, 0x1AA0), + INTC_VECT(MMCIF_1, 0x1AC0), + INTC_VECT(MMCIF_2, 0x1AE0), + INTC_VECT(SIM_ERI, 0x1C00), + INTC_VECT(SIM_RXI, 0x1C20), + INTC_VECT(SIM_TXI, 0x1C40), + INTC_VECT(SIM_TEI, 0x1C60), + INTC_VECT(STPRO_0, 0x1C80), + INTC_VECT(STPRO_1, 0x1CA0), + INTC_VECT(STPRO_2, 0x1CC0), + INTC_VECT(STPRO_3, 0x1CE0), + INTC_VECT(STPRO_4, 0x1D00), +}; + +static struct intc_group intca_groups[] __initdata = { + INTC_GROUP(DMAC1_1, + DMAC1_1_DEI0, DMAC1_1_DEI1, DMAC1_1_DEI2, DMAC1_1_DEI3), + INTC_GROUP(DMAC1_2, + DMAC1_2_DEI4, DMAC1_2_DEI5, DMAC1_2_DADERR), + INTC_GROUP(DMAC2_1, + DMAC2_1_DEI0, DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3), + INTC_GROUP(DMAC2_2, + DMAC2_2_DEI4, DMAC2_2_DEI5, DMAC2_2_DADERR), + INTC_GROUP(DMAC3_1, + DMAC3_1_DEI0, DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3), + INTC_GROUP(DMAC3_2, + DMAC3_2_DEI4, DMAC3_2_DEI5, DMAC3_2_DADERR), + INTC_GROUP(AP_ARM1, + AP_ARM_COMMTX, AP_ARM_COMMRX), + INTC_GROUP(AP_ARM2, + AP_ARM_CTIIRQ, AP_ARM_PMURQ), + INTC_GROUP(USBF, + USBF_OUL_SOF, USBF_IXL_INT), + INTC_GROUP(SDHI0, + SDHI0_0, SDHI0_1, SDHI0_2, SDHI0_3), + INTC_GROUP(SDHI1, + SDHI1_0, SDHI1_1, SDHI1_2, SDHI1_3), + INTC_GROUP(SDHI2, + SDHI2_0, SDHI2_1, SDHI2_2, SDHI2_3), + INTC_GROUP(SHWYSTAT, + SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM), + INTC_GROUP(USBH1, /* FIXME */ + USBH_INT, USBH_OHCI), + INTC_GROUP(USBH2, /* FIXME */ + USBH_EHCI, + USBH_PME, USBH_BIND), + INTC_GROUP(RSPI, + RSPI_OVRF, RSPI_SPTEF, RSPI_SPRF), + INTC_GROUP(SPU2, + SPU2_0, SPU2_1), + INTC_GROUP(FLCTL, + FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I), + INTC_GROUP(IIC1, + IIC1_ALI, IIC1_TACKI, IIC1_WAITI, IIC1_DTEI), +}; + +static struct intc_mask_reg intca_mask_registers[] __initdata = { + { /* IMR0A / IMCR0A */ 0xe6940080, 0xe69400c0, 8, + { DMAC2_1_DEI3, DMAC2_1_DEI2, DMAC2_1_DEI1, DMAC2_1_DEI0, + 0, 0, AP_ARM_COMMTX, AP_ARM_COMMRX } }, + { /* IMR1A / IMCR1A */ 0xe6940084, 0xe69400c4, 8, + { ATAPI, 0, DIRC, 0, + DMAC1_1_DEI3, DMAC1_1_DEI2, DMAC1_1_DEI1, DMAC1_1_DEI0 } }, + { /* IMR2A / IMCR2A */ 0xe6940088, 0xe69400c8, 8, + { 0, 0, 0, 0, + BBIF1, BBIF2, MFIS, MFI } }, + { /* IMR3A / IMCR3A */ 0xe694008c, 0xe69400cc, 8, + { DMAC3_1_DEI3, DMAC3_1_DEI2, DMAC3_1_DEI1, DMAC3_1_DEI0, + DMAC3_2_DADERR, DMAC3_2_DEI5, DMAC3_2_DEI4, IRDA } }, + { /* IMR4A / IMCR4A */ 0xe6940090, 0xe69400d0, 8, + { DDM, 0, 0, 0, + 0, 0, 0, 0 } }, + { /* IMR5A / IMCR5A */ 0xe6940094, 0xe69400d4, 8, + { KEYSC, DMAC1_2_DADERR, DMAC1_2_DEI5, DMAC1_2_DEI4, + SCIFA3, SCIFA2, SCIFA1, SCIFA0 } }, + { /* IMR6A / IMCR6A */ 0xe6940098, 0xe69400d8, 8, + { SCIFB, SCIFA5, SCIFA4, MSIOF1, + 0, 0, MSIOF2, 0 } }, + { /* IMR7A / IMCR7A */ 0xe694009c, 0xe69400dc, 8, + { SDHI0_3, SDHI0_2, SDHI0_1, SDHI0_0, + FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } }, + { /* IMR8A / IMCR8A */ 0xe69400a0, 0xe69400e0, 8, + { SDHI1_3, SDHI1_2, SDHI1_1, SDHI1_0, + 0, USBHSDMAC, 0, AP_ARM_L2CINT } }, + { /* IMR9A / IMCR9A */ 0xe69400a4, 0xe69400e4, 8, + { CMT1_3, CMT1_2, CMT1_1, CMT1_0, + CMT2, USBF_IXL_INT, USBF_OUL_SOF, SGX540 } }, + { /* IMR10A / IMCR10A */ 0xe69400a8, 0xe69400e8, 8, + { 0, DMAC2_2_DADERR, DMAC2_2_DEI5, DMAC2_2_DEI4, + 0, 0, 0, 0 } }, + { /* IMR11A / IMCR11A */ 0xe69400ac, 0xe69400ec, 8, + { IIC1_DTEI, IIC1_WAITI, IIC1_TACKI, IIC1_ALI, + ICBS0, 0, 0, 0 } }, + { /* IMR12A / IMCR12A */ 0xe69400b0, 0xe69400f0, 8, + { 0, 0, TPU0, SCIFA6, + SCIFA7, GbEther, 0, 0 } }, + { /* IMR13A / IMCR13A */ 0xe69400b4, 0xe69400f4, 8, + { SDHI2_3, SDHI2_2, SDHI2_1, SDHI2_0, + 0, CMT3, 0, RWDT0 } }, + { /* IMR0A3 / IMCR0A3 */ 0xe6950080, 0xe69500c0, 8, + { SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM, 0, + 0, 0, 0, 0 } }, + /* IMR1A3 / IMCR1A3 */ + { /* IMR2A3 / IMCR2A3 */ 0xe6950088, 0xe69500c8, 8, + { 0, 0, USBH_INT, USBH_OHCI, + USBH_EHCI, USBH_PME, USBH_BIND, 0 } }, + /* IMR3A3 / IMCR3A3 */ + { /* IMR4A3 / IMCR4A3 */ 0xe6950090, 0xe69500d0, 8, + { 0, 0, 0, 0, + RSPI_OVRF, RSPI_SPTEF, RSPI_SPRF, 0 } }, + { /* IMR5A3 / IMCR5A3 */ 0xe6950094, 0xe69500d4, 8, + { SPU2_0, SPU2_1, FSI, FMSI, + 0, 0, 0, 0 } }, + { /* IMR6A3 / IMCR6A3 */ 0xe6950098, 0xe69500d8, 8, + { 0, IPMMU, 0, 0, + AP_ARM_CTIIRQ, AP_ARM_PMURQ, 0, 0 } }, + { /* IMR7A3 / IMCR7A3 */ 0xe695009c, 0xe69500dc, 8, + { MFIS2, CPORTR2S, CMT14, CMT15, + 0, MMCIF_0, MMCIF_1, MMCIF_2 } }, + /* IMR8A3 / IMCR8A3 */ + { /* IMR9A3 / IMCR9A3 */ 0xe69500a4, 0xe69500e4, 8, + { SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI, + STPRO_0, STPRO_1, STPRO_2, STPRO_3 } }, + { /* IMR10A3 / IMCR10A3 */ 0xe69500a8, 0xe69500e8, 8, + { STPRO_4, 0, 0, 0, + 0, 0, 0, 0 } }, +}; + +static struct intc_prio_reg intca_prio_registers[] __initdata = { + { 0xe6940000, 0, 16, 4, /* IPRAA */ { DMAC3_1, DMAC3_2, CMT2, ICBS0 } }, + { 0xe6940004, 0, 16, 4, /* IPRBA */ { IRDA, 0, BBIF1, BBIF2 } }, + { 0xe6940008, 0, 16, 4, /* IPRCA */ { ATAPI, 0, CMT1_1, AP_ARM1 } }, + { 0xe694000c, 0, 16, 4, /* IPRDA */ { 0, 0, CMT1_2, 0 } }, + { 0xe6940010, 0, 16, 4, /* IPREA */ { DMAC1_1, MFIS, MFI, USBF } }, + { 0xe6940014, 0, 16, 4, /* IPRFA */ { KEYSC, DMAC1_2, + SGX540, CMT1_0 } }, + { 0xe6940018, 0, 16, 4, /* IPRGA */ { SCIFA0, SCIFA1, + SCIFA2, SCIFA3 } }, + { 0xe694001c, 0, 16, 4, /* IPRGH */ { MSIOF2, USBHSDMAC, + FLCTL, SDHI0 } }, + { 0xe6940020, 0, 16, 4, /* IPRIA */ { MSIOF1, SCIFA4, 0, IIC1 } }, + { 0xe6940024, 0, 16, 4, /* IPRJA */ { DMAC2_1, DMAC2_2, + AP_ARM_L2CINT, 0 } }, + { 0xe6940028, 0, 16, 4, /* IPRKA */ { 0, CMT1_3, 0, SDHI1 } }, + { 0xe694002c, 0, 16, 4, /* IPRLA */ { TPU0, SCIFA6, + SCIFA7, GbEther } }, + { 0xe6940030, 0, 16, 4, /* IPRMA */ { 0, CMT3, 0, RWDT0 } }, + { 0xe6940034, 0, 16, 4, /* IPRNA */ { SCIFB, SCIFA5, 0, DDM } }, + { 0xe6940038, 0, 16, 4, /* IPROA */ { 0, 0, DIRC, SDHI2 } }, + { 0xe6950000, 0, 16, 4, /* IPRAA3 */ { SHWYSTAT, 0, 0, 0 } }, + /* IPRBA3 */ + /* IPRCA3 */ + /* IPRDA3 */ + { 0xe6950010, 0, 16, 4, /* IPREA3 */ { USBH1, 0, 0, 0 } }, + { 0xe6950014, 0, 16, 4, /* IPRFA3 */ { USBH2, 0, 0, 0 } }, + /* IPRGA3 */ + /* IPRHA3 */ + /* IPRIA3 */ + { 0xe6950024, 0, 16, 4, /* IPRJA3 */ { RSPI, 0, 0, 0 } }, + { 0xe6950028, 0, 16, 4, /* IPRKA3 */ { SPU2, 0, FSI, FMSI } }, + /* IPRLA3 */ + { 0xe6950030, 0, 16, 4, /* IPRMA3 */ { IPMMU, 0, 0, 0 } }, + { 0xe6950034, 0, 16, 4, /* IPRNA3 */ { AP_ARM2, 0, 0, 0 } }, + { 0xe6950038, 0, 16, 4, /* IPROA3 */ { MFIS2, CPORTR2S, + CMT14, CMT15 } }, + { 0xe695003c, 0, 16, 4, /* IPRPA3 */ { 0, MMCIF_0, MMCIF_1, MMCIF_2 } }, + /* IPRQA3 */ + /* IPRRA3 */ + { 0xe6950048, 0, 16, 4, /* IPRSA3 */ { SIM_ERI, SIM_RXI, + SIM_TXI, SIM_TEI } }, + { 0xe695004c, 0, 16, 4, /* IPRTA3 */ { STPRO_0, STPRO_1, + STPRO_2, STPRO_3 } }, + { 0xe6950050, 0, 16, 4, /* IPRUA3 */ { STPRO_4, 0, 0, 0 } }, +}; + +static DECLARE_INTC_DESC(intca_desc, "r8a7740-intca", + intca_vectors, intca_groups, + intca_mask_registers, intca_prio_registers, + NULL); + +INTC_IRQ_PINS_32(intca_irq_pins, 0xe6900000, + INTC_VECT, "r8a7740-intca-irq-pins"); + + +/* + * INTCS + */ +enum { + UNUSED_INTCS = 0, + + INTCS, + + /* interrupt sources INTCS */ + + /* HUDI */ + /* STPRO */ + /* RTDMAC(1) */ + VPU5HA2, + _2DG_TRAP, _2DG_GPM_INT, _2DG_CER_INT, + /* MFI */ + /* BBIF2 */ + VPU5F, + _2DG_BRK_INT, + /* SGX540 */ + /* 2DDMAC */ + /* IPMMU */ + /* RTDMAC 2 */ + /* KEYSC */ + /* MSIOF */ + IIC0_ALI, IIC0_TACKI, IIC0_WAITI, IIC0_DTEI, + TMU0_0, TMU0_1, TMU0_2, + CMT0, + /* CMT2 */ + LMB, + CTI, + VOU, + /* RWDT0 */ + ICB, + VIO6C, + CEU20, CEU21, + JPU, + LCDC0, + LCRC, + /* RTDMAC2(1) */ + /* RTDMAC2(2) */ + LCDC1, + /* SPU2 */ + /* FSI */ + /* FMSI */ + TMU1_0, TMU1_1, TMU1_2, + CMT4, + DISP, + DSRV, + /* MFIS2 */ + CPORTS2R, + + /* interrupt groups INTCS */ + _2DG1, + IIC0, TMU1, +}; + +static struct intc_vect intcs_vectors[] = { + /* HUDI */ + /* STPRO */ + /* RTDMAC(1) */ + INTCS_VECT(VPU5HA2, 0x0880), + INTCS_VECT(_2DG_TRAP, 0x08A0), + INTCS_VECT(_2DG_GPM_INT, 0x08C0), + INTCS_VECT(_2DG_CER_INT, 0x08E0), + /* MFI */ + /* BBIF2 */ + INTCS_VECT(VPU5F, 0x0980), + INTCS_VECT(_2DG_BRK_INT, 0x09A0), + /* SGX540 */ + /* 2DDMAC */ + /* IPMMU */ + /* RTDMAC(2) */ + /* KEYSC */ + /* MSIOF */ + INTCS_VECT(IIC0_ALI, 0x0E00), + INTCS_VECT(IIC0_TACKI, 0x0E20), + INTCS_VECT(IIC0_WAITI, 0x0E40), + INTCS_VECT(IIC0_DTEI, 0x0E60), + INTCS_VECT(TMU0_0, 0x0E80), + INTCS_VECT(TMU0_1, 0x0EA0), + INTCS_VECT(TMU0_2, 0x0EC0), + INTCS_VECT(CMT0, 0x0F00), + /* CMT2 */ + INTCS_VECT(LMB, 0x0F60), + INTCS_VECT(CTI, 0x0400), + INTCS_VECT(VOU, 0x0420), + /* RWDT0 */ + INTCS_VECT(ICB, 0x0480), + INTCS_VECT(VIO6C, 0x04E0), + INTCS_VECT(CEU20, 0x0500), + INTCS_VECT(CEU21, 0x0520), + INTCS_VECT(JPU, 0x0560), + INTCS_VECT(LCDC0, 0x0580), + INTCS_VECT(LCRC, 0x05A0), + /* RTDMAC2(1) */ + /* RTDMAC2(2) */ + INTCS_VECT(LCDC1, 0x1780), + /* SPU2 */ + /* FSI */ + /* FMSI */ + INTCS_VECT(TMU1_0, 0x1900), + INTCS_VECT(TMU1_1, 0x1920), + INTCS_VECT(TMU1_2, 0x1940), + INTCS_VECT(CMT4, 0x1980), + INTCS_VECT(DISP, 0x19A0), + INTCS_VECT(DSRV, 0x19C0), + /* MFIS2 */ + INTCS_VECT(CPORTS2R, 0x1A20), + + INTC_VECT(INTCS, 0xf80), +}; + +static struct intc_group intcs_groups[] __initdata = { + INTC_GROUP(_2DG1, /*FIXME*/ + _2DG_CER_INT, _2DG_GPM_INT, _2DG_TRAP), + INTC_GROUP(IIC0, + IIC0_DTEI, IIC0_WAITI, IIC0_TACKI, IIC0_ALI), + INTC_GROUP(TMU1, + TMU1_0, TMU1_1, TMU1_2), +}; + +static struct intc_mask_reg intcs_mask_registers[] = { + /* IMR0SA / IMCR0SA */ /* all 0 */ + { /* IMR1SA / IMCR1SA */ 0xffd20184, 0xffd201c4, 8, + { _2DG_CER_INT, _2DG_GPM_INT, _2DG_TRAP, VPU5HA2, + 0, 0, 0, 0 /*STPRO*/ } }, + { /* IMR2SA / IMCR2SA */ 0xffd20188, 0xffd201c8, 8, + { 0/*STPRO*/, 0, CEU21, VPU5F, + 0/*BBIF2*/, 0, 0, 0/*MFI*/ } }, + { /* IMR3SA / IMCR3SA */ 0xffd2018c, 0xffd201cc, 8, + { 0, 0, 0, 0, /*2DDMAC*/ + VIO6C, 0, 0, ICB } }, + { /* IMR4SA / IMCR4SA */ 0xffd20190, 0xffd201d0, 8, + { 0, 0, VOU, CTI, + JPU, 0, LCRC, LCDC0 } }, + /* IMR5SA / IMCR5SA */ /*KEYSC/RTDMAC2/RTDMAC1*/ + /* IMR6SA / IMCR6SA */ /*MSIOF/SGX540*/ + { /* IMR7SA / IMCR7SA */ 0xffd2019c, 0xffd201dc, 8, + { 0, TMU0_2, TMU0_1, TMU0_0, + 0, 0, 0, 0 } }, + { /* IMR8SA / IMCR8SA */ 0xffd201a0, 0xffd201e0, 8, + { 0, 0, 0, 0, + CEU20, 0, 0, 0 } }, + { /* IMR9SA / IMCR9SA */ 0xffd201a4, 0xffd201e4, 8, + { 0, 0/*RWDT0*/, 0/*CMT2*/, CMT0, + 0, 0, 0, 0 } }, + /* IMR10SA / IMCR10SA */ /*IPMMU*/ + { /* IMR11SA / IMCR11SA */ 0xffd201ac, 0xffd201ec, 8, + { IIC0_DTEI, IIC0_WAITI, IIC0_TACKI, IIC0_ALI, + 0, _2DG_BRK_INT, LMB, 0 } }, + /* IMR12SA / IMCR12SA */ + /* IMR13SA / IMCR13SA */ + /* IMR0SA3 / IMCR0SA3 */ /*RTDMAC2(1)/RTDMAC2(2)*/ + /* IMR1SA3 / IMCR1SA3 */ + /* IMR2SA3 / IMCR2SA3 */ + /* IMR3SA3 / IMCR3SA3 */ + { /* IMR4SA3 / IMCR4SA3 */ 0xffd50190, 0xffd501d0, 8, + { 0, 0, 0, 0, + LCDC1, 0, 0, 0 } }, + /* IMR5SA3 / IMCR5SA3 */ /* SPU2/FSI/FMSI */ + { /* IMR6SA3 / IMCR6SA3 */ 0xffd50198, 0xffd501d8, 8, + { TMU1_0, TMU1_1, TMU1_2, 0, + CMT4, DISP, DSRV, 0 } }, + { /* IMR7SA3 / IMCR7SA3 */ 0xffd5019c, 0xffd501dc, 8, + { 0/*MFIS2*/, CPORTS2R, 0, 0, + 0, 0, 0, 0 } }, + { /* INTAMASK */ 0xffd20104, 0, 16, + { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, INTCS } }, +}; + +/* Priority is needed for INTCA to receive the INTCS interrupt */ +static struct intc_prio_reg intcs_prio_registers[] = { + { 0xffd20000, 0, 16, 4, /* IPRAS */ { CTI, VOU, 0/*2DDMAC*/, ICB } }, + { 0xffd20004, 0, 16, 4, /* IPRBS */ { JPU, LCDC0, 0, LCRC } }, + /* IPRCS */ /*BBIF2*/ + /* IPRDS */ + { 0xffd20010, 0, 16, 4, /* IPRES */ { 0/*RTDMAC(1)*/, VPU5HA2, + 0/*MFI*/, VPU5F } }, + { 0xffd20014, 0, 16, 4, /* IPRFS */ { 0/*KEYSC*/, 0/*RTDMAC(2)*/, + 0/*CMT2*/, CMT0 } }, + { 0xffd20018, 0, 16, 4, /* IPRGS */ { TMU0_0, TMU0_1, + TMU0_2, _2DG1 } }, + { 0xffd2001c, 0, 16, 4, /* IPRHS */ { 0, 0/*STPRO*/, 0/*STPRO*/, + _2DG_BRK_INT/*FIXME*/ } }, + { 0xffd20020, 0, 16, 4, /* IPRIS */ { 0, 0/*MSIOF*/, 0, IIC0 } }, + { 0xffd20024, 0, 16, 4, /* IPRJS */ { CEU20, 0/*SGX540*/, 0, 0 } }, + { 0xffd20028, 0, 16, 4, /* IPRKS */ { VIO6C, 0, LMB, 0 } }, + { 0xffd2002c, 0, 16, 4, /* IPRLS */ { 0/*IPMMU*/, 0, CEU21, 0 } }, + /* IPRMS */ /*RWDT0*/ + /* IPRAS3 */ /*RTDMAC2(1)*/ + /* IPRBS3 */ /*RTDMAC2(2)*/ + /* IPRCS3 */ + /* IPRDS3 */ + /* IPRES3 */ + /* IPRFS3 */ + /* IPRGS3 */ + /* IPRHS3 */ + /* IPRIS3 */ + { 0xffd50024, 0, 16, 4, /* IPRJS3 */ { LCDC1, 0, 0, 0 } }, + /* IPRKS3 */ /*SPU2/FSI/FMSi*/ + /* IPRLS3 */ + { 0xffd50030, 0, 16, 4, /* IPRMS3 */ { TMU1, 0, 0, 0 } }, + { 0xffd50034, 0, 16, 4, /* IPRNS3 */ { CMT4, DISP, DSRV, 0 } }, + { 0xffd50038, 0, 16, 4, /* IPROS3 */ { 0/*MFIS2*/, CPORTS2R, 0, 0 } }, + /* IPRPS3 */ +}; + +static struct resource intcs_resources[] __initdata = { + [0] = { + .start = 0xffd20000, + .end = 0xffd201ff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = 0xffd50000, + .end = 0xffd501ff, + .flags = IORESOURCE_MEM, + } +}; + +static struct intc_desc intcs_desc __initdata = { + .name = "r8a7740-intcs", + .resource = intcs_resources, + .num_resources = ARRAY_SIZE(intcs_resources), + .hw = INTC_HW_DESC(intcs_vectors, intcs_groups, intcs_mask_registers, + intcs_prio_registers, NULL, NULL), +}; + +static void intcs_demux(unsigned int irq, struct irq_desc *desc) +{ + void __iomem *reg = (void *)irq_get_handler_data(irq); + unsigned int evtcodeas = ioread32(reg); + + generic_handle_irq(intcs_evt2irq(evtcodeas)); +} + +void __init r8a7740_init_irq(void) +{ + void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE); + + register_intc_controller(&intca_desc); + register_intc_controller(&intca_irq_pins_desc); + register_intc_controller(&intcs_desc); + + /* demux using INTEVTSA */ + irq_set_handler_data(evt2irq(0xf80), (void *)intevtsa); + irq_set_chained_handler(evt2irq(0xf80), intcs_demux); +} diff --git a/arch/arm/mach-shmobile/intc-r8a7779.c b/arch/arm/mach-shmobile/intc-r8a7779.c new file mode 100644 index 00000000000..5d92fcde2bc --- /dev/null +++ b/arch/arm/mach-shmobile/intc-r8a7779.c @@ -0,0 +1,58 @@ +/* + * r8a7779 processor support - INTC hardware block + * + * Copyright (C) 2011 Renesas Solutions Corp. + * Copyright (C) 2011 Magnus Damm + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/io.h> +#include <mach/common.h> +#include <mach/intc.h> +#include <mach/r8a7779.h> +#include <asm/hardware/gic.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> + +#define INT2SMSKCR0 0xfe7822a0 +#define INT2SMSKCR1 0xfe7822a4 +#define INT2SMSKCR2 0xfe7822a8 +#define INT2SMSKCR3 0xfe7822ac +#define INT2SMSKCR4 0xfe7822b0 + +static int r8a7779_set_wake(struct irq_data *data, unsigned int on) +{ + return 0; /* always allow wakeup */ +} + +void __init r8a7779_init_irq(void) +{ + void __iomem *gic_dist_base = __io(0xf0001000); + void __iomem *gic_cpu_base = __io(0xf0000100); + + /* use GIC to handle interrupts */ + gic_init(0, 29, gic_dist_base, gic_cpu_base); + gic_arch_extn.irq_set_wake = r8a7779_set_wake; + + /* unmask all known interrupts in INTCS2 */ + __raw_writel(0xfffffff0, INT2SMSKCR0); + __raw_writel(0xfff7ffff, INT2SMSKCR1); + __raw_writel(0xfffbffdf, INT2SMSKCR2); + __raw_writel(0xbffffffc, INT2SMSKCR3); + __raw_writel(0x003fee3f, INT2SMSKCR4); +} diff --git a/arch/arm/mach-shmobile/intc-sh7372.c b/arch/arm/mach-shmobile/intc-sh7372.c index 2d8856df80e..89afcaba99a 100644 --- a/arch/arm/mach-shmobile/intc-sh7372.c +++ b/arch/arm/mach-shmobile/intc-sh7372.c @@ -535,6 +535,7 @@ static struct resource intcs_resources[] __initdata = { static struct intc_desc intcs_desc __initdata = { .name = "sh7372-intcs", .force_enable = ENABLED_INTCS, + .skip_syscore_suspend = true, .resource = intcs_resources, .num_resources = ARRAY_SIZE(intcs_resources), .hw = INTC_HW_DESC(intcs_vectors, intcs_groups, intcs_mask_registers, @@ -611,3 +612,52 @@ void sh7372_intcs_resume(void) for (k = 0x80; k <= 0x9c; k += 4) __raw_writeb(ffd5[k], intcs_ffd5 + k); } + +static unsigned short e694[0x200]; +static unsigned short e695[0x200]; + +void sh7372_intca_suspend(void) +{ + int k; + + for (k = 0x00; k <= 0x38; k += 4) + e694[k] = __raw_readw(0xe6940000 + k); + + for (k = 0x80; k <= 0xb4; k += 4) + e694[k] = __raw_readb(0xe6940000 + k); + + for (k = 0x180; k <= 0x1b4; k += 4) + e694[k] = __raw_readb(0xe6940000 + k); + + for (k = 0x00; k <= 0x50; k += 4) + e695[k] = __raw_readw(0xe6950000 + k); + + for (k = 0x80; k <= 0xa8; k += 4) + e695[k] = __raw_readb(0xe6950000 + k); + + for (k = 0x180; k <= 0x1a8; k += 4) + e695[k] = __raw_readb(0xe6950000 + k); +} + +void sh7372_intca_resume(void) +{ + int k; + + for (k = 0x00; k <= 0x38; k += 4) + __raw_writew(e694[k], 0xe6940000 + k); + + for (k = 0x80; k <= 0xb4; k += 4) + __raw_writeb(e694[k], 0xe6940000 + k); + + for (k = 0x180; k <= 0x1b4; k += 4) + __raw_writeb(e694[k], 0xe6940000 + k); + + for (k = 0x00; k <= 0x50; k += 4) + __raw_writew(e695[k], 0xe6950000 + k); + + for (k = 0x80; k <= 0xa8; k += 4) + __raw_writeb(e695[k], 0xe6950000 + k); + + for (k = 0x180; k <= 0x1a8; k += 4) + __raw_writeb(e695[k], 0xe6950000 + k); +} diff --git a/arch/arm/mach-shmobile/pfc-r8a7740.c b/arch/arm/mach-shmobile/pfc-r8a7740.c new file mode 100644 index 00000000000..a4fff6950b0 --- /dev/null +++ b/arch/arm/mach-shmobile/pfc-r8a7740.c @@ -0,0 +1,2562 @@ +/* + * R8A7740 processor support + * + * Copyright (C) 2011 Renesas Solutions Corp. + * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the + * License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/gpio.h> +#include <mach/r8a7740.h> + +#define CPU_ALL_PORT(fn, pfx, sfx) \ + PORT_10(fn, pfx, sfx), PORT_90(fn, pfx, sfx), \ + PORT_10(fn, pfx##10, sfx), PORT_90(fn, pfx##1, sfx), \ + PORT_10(fn, pfx##20, sfx), \ + PORT_1(fn, pfx##210, sfx), PORT_1(fn, pfx##211, sfx) + +enum { + PINMUX_RESERVED = 0, + + /* PORT0_DATA -> PORT211_DATA */ + PINMUX_DATA_BEGIN, + PORT_ALL(DATA), + PINMUX_DATA_END, + + /* PORT0_IN -> PORT211_IN */ + PINMUX_INPUT_BEGIN, + PORT_ALL(IN), + PINMUX_INPUT_END, + + /* PORT0_IN_PU -> PORT211_IN_PU */ + PINMUX_INPUT_PULLUP_BEGIN, + PORT_ALL(IN_PU), + PINMUX_INPUT_PULLUP_END, + + /* PORT0_IN_PD -> PORT211_IN_PD */ + PINMUX_INPUT_PULLDOWN_BEGIN, + PORT_ALL(IN_PD), + PINMUX_INPUT_PULLDOWN_END, + + /* PORT0_OUT -> PORT211_OUT */ + PINMUX_OUTPUT_BEGIN, + PORT_ALL(OUT), + PINMUX_OUTPUT_END, + + PINMUX_FUNCTION_BEGIN, + PORT_ALL(FN_IN), /* PORT0_FN_IN -> PORT211_FN_IN */ + PORT_ALL(FN_OUT), /* PORT0_FN_OUT -> PORT211_FN_OUT */ + PORT_ALL(FN0), /* PORT0_FN0 -> PORT211_FN0 */ + PORT_ALL(FN1), /* PORT0_FN1 -> PORT211_FN1 */ + PORT_ALL(FN2), /* PORT0_FN2 -> PORT211_FN2 */ + PORT_ALL(FN3), /* PORT0_FN3 -> PORT211_FN3 */ + PORT_ALL(FN4), /* PORT0_FN4 -> PORT211_FN4 */ + PORT_ALL(FN5), /* PORT0_FN5 -> PORT211_FN5 */ + PORT_ALL(FN6), /* PORT0_FN6 -> PORT211_FN6 */ + PORT_ALL(FN7), /* PORT0_FN7 -> PORT211_FN7 */ + + MSEL1CR_31_0, MSEL1CR_31_1, + MSEL1CR_30_0, MSEL1CR_30_1, + MSEL1CR_29_0, MSEL1CR_29_1, + MSEL1CR_28_0, MSEL1CR_28_1, + MSEL1CR_27_0, MSEL1CR_27_1, + MSEL1CR_26_0, MSEL1CR_26_1, + MSEL1CR_16_0, MSEL1CR_16_1, + MSEL1CR_15_0, MSEL1CR_15_1, + MSEL1CR_14_0, MSEL1CR_14_1, + MSEL1CR_13_0, MSEL1CR_13_1, + MSEL1CR_12_0, MSEL1CR_12_1, + MSEL1CR_9_0, MSEL1CR_9_1, + MSEL1CR_7_0, MSEL1CR_7_1, + MSEL1CR_6_0, MSEL1CR_6_1, + MSEL1CR_5_0, MSEL1CR_5_1, + MSEL1CR_4_0, MSEL1CR_4_1, + MSEL1CR_3_0, MSEL1CR_3_1, + MSEL1CR_2_0, MSEL1CR_2_1, + MSEL1CR_0_0, MSEL1CR_0_1, + + MSEL3CR_15_0, MSEL3CR_15_1, /* Trace / Debug ? */ + MSEL3CR_6_0, MSEL3CR_6_1, + + MSEL4CR_19_0, MSEL4CR_19_1, + MSEL4CR_18_0, MSEL4CR_18_1, + MSEL4CR_15_0, MSEL4CR_15_1, + MSEL4CR_10_0, MSEL4CR_10_1, + MSEL4CR_6_0, MSEL4CR_6_1, + MSEL4CR_4_0, MSEL4CR_4_1, + MSEL4CR_1_0, MSEL4CR_1_1, + + MSEL5CR_31_0, MSEL5CR_31_1, /* irq/fiq output */ + MSEL5CR_30_0, MSEL5CR_30_1, + MSEL5CR_29_0, MSEL5CR_29_1, + MSEL5CR_27_0, MSEL5CR_27_1, + MSEL5CR_25_0, MSEL5CR_25_1, + MSEL5CR_23_0, MSEL5CR_23_1, + MSEL5CR_21_0, MSEL5CR_21_1, + MSEL5CR_19_0, MSEL5CR_19_1, + MSEL5CR_17_0, MSEL5CR_17_1, + MSEL5CR_15_0, MSEL5CR_15_1, + MSEL5CR_14_0, MSEL5CR_14_1, + MSEL5CR_13_0, MSEL5CR_13_1, + MSEL5CR_12_0, MSEL5CR_12_1, + MSEL5CR_11_0, MSEL5CR_11_1, + MSEL5CR_10_0, MSEL5CR_10_1, + MSEL5CR_8_0, MSEL5CR_8_1, + MSEL5CR_7_0, MSEL5CR_7_1, + MSEL5CR_6_0, MSEL5CR_6_1, + MSEL5CR_5_0, MSEL5CR_5_1, + MSEL5CR_4_0, MSEL5CR_4_1, + MSEL5CR_3_0, MSEL5CR_3_1, + MSEL5CR_2_0, MSEL5CR_2_1, + MSEL5CR_0_0, MSEL5CR_0_1, + PINMUX_FUNCTION_END, + + PINMUX_MARK_BEGIN, + + /* IRQ */ + IRQ0_PORT2_MARK, IRQ0_PORT13_MARK, + IRQ1_MARK, + IRQ2_PORT11_MARK, IRQ2_PORT12_MARK, + IRQ3_PORT10_MARK, IRQ3_PORT14_MARK, + IRQ4_PORT15_MARK, IRQ4_PORT172_MARK, + IRQ5_PORT0_MARK, IRQ5_PORT1_MARK, + IRQ6_PORT121_MARK, IRQ6_PORT173_MARK, + IRQ7_PORT120_MARK, IRQ7_PORT209_MARK, + IRQ8_MARK, + IRQ9_PORT118_MARK, IRQ9_PORT210_MARK, + IRQ10_MARK, + IRQ11_MARK, + IRQ12_PORT42_MARK, IRQ12_PORT97_MARK, + IRQ13_PORT64_MARK, IRQ13_PORT98_MARK, + IRQ14_PORT63_MARK, IRQ14_PORT99_MARK, + IRQ15_PORT62_MARK, IRQ15_PORT100_MARK, + IRQ16_PORT68_MARK, IRQ16_PORT211_MARK, + IRQ17_MARK, + IRQ18_MARK, + IRQ19_MARK, + IRQ20_MARK, + IRQ21_MARK, + IRQ22_MARK, + IRQ23_MARK, + IRQ24_MARK, + IRQ25_MARK, + IRQ26_PORT58_MARK, IRQ26_PORT81_MARK, + IRQ27_PORT57_MARK, IRQ27_PORT168_MARK, + IRQ28_PORT56_MARK, IRQ28_PORT169_MARK, + IRQ29_PORT50_MARK, IRQ29_PORT170_MARK, + IRQ30_PORT49_MARK, IRQ30_PORT171_MARK, + IRQ31_PORT41_MARK, IRQ31_PORT167_MARK, + + /* Function */ + + /* DBGT */ + DBGMDT2_MARK, DBGMDT1_MARK, DBGMDT0_MARK, + DBGMD10_MARK, DBGMD11_MARK, DBGMD20_MARK, + DBGMD21_MARK, + + /* FSI */ + FSIAISLD_PORT0_MARK, /* FSIAISLD Port 0/5 */ + FSIAISLD_PORT5_MARK, + FSIASPDIF_PORT9_MARK, /* FSIASPDIF Port 9/18 */ + FSIASPDIF_PORT18_MARK, + FSIAOSLD1_MARK, FSIAOSLD2_MARK, FSIAOLR_MARK, + FSIAOBT_MARK, FSIAOSLD_MARK, FSIAOMC_MARK, + FSIACK_MARK, FSIAILR_MARK, FSIAIBT_MARK, + + /* FMSI */ + FMSISLD_PORT1_MARK, /* FMSISLD Port 1/6 */ + FMSISLD_PORT6_MARK, + FMSIILR_MARK, FMSIIBT_MARK, FMSIOLR_MARK, FMSIOBT_MARK, + FMSICK_MARK, FMSOILR_MARK, FMSOIBT_MARK, FMSOOLR_MARK, + FMSOOBT_MARK, FMSOSLD_MARK, FMSOCK_MARK, + + /* SCIFA0 */ + SCIFA0_SCK_MARK, SCIFA0_CTS_MARK, SCIFA0_RTS_MARK, + SCIFA0_RXD_MARK, SCIFA0_TXD_MARK, + + /* SCIFA1 */ + SCIFA1_CTS_MARK, SCIFA1_SCK_MARK, SCIFA1_RXD_MARK, + SCIFA1_TXD_MARK, SCIFA1_RTS_MARK, + + /* SCIFA2 */ + SCIFA2_SCK_PORT22_MARK, /* SCIFA2_SCK Port 22/199 */ + SCIFA2_SCK_PORT199_MARK, + SCIFA2_RXD_MARK, SCIFA2_TXD_MARK, + SCIFA2_CTS_MARK, SCIFA2_RTS_MARK, + + /* SCIFA3 */ + SCIFA3_RTS_PORT105_MARK, /* MSEL5CR_8_0 */ + SCIFA3_SCK_PORT116_MARK, + SCIFA3_CTS_PORT117_MARK, + SCIFA3_RXD_PORT174_MARK, + SCIFA3_TXD_PORT175_MARK, + + SCIFA3_RTS_PORT161_MARK, /* MSEL5CR_8_1 */ + SCIFA3_SCK_PORT158_MARK, + SCIFA3_CTS_PORT162_MARK, + SCIFA3_RXD_PORT159_MARK, + SCIFA3_TXD_PORT160_MARK, + + /* SCIFA4 */ + SCIFA4_RXD_PORT12_MARK, /* MSEL5CR[12:11] = 00 */ + SCIFA4_TXD_PORT13_MARK, + + SCIFA4_RXD_PORT204_MARK, /* MSEL5CR[12:11] = 01 */ + SCIFA4_TXD_PORT203_MARK, + + SCIFA4_RXD_PORT94_MARK, /* MSEL5CR[12:11] = 10 */ + SCIFA4_TXD_PORT93_MARK, + + SCIFA4_SCK_PORT21_MARK, /* SCIFA4_SCK Port 21/205 */ + SCIFA4_SCK_PORT205_MARK, + + /* SCIFA5 */ + SCIFA5_TXD_PORT20_MARK, /* MSEL5CR[15:14] = 00 */ + SCIFA5_RXD_PORT10_MARK, + + SCIFA5_RXD_PORT207_MARK, /* MSEL5CR[15:14] = 01 */ + SCIFA5_TXD_PORT208_MARK, + + SCIFA5_TXD_PORT91_MARK, /* MSEL5CR[15:14] = 10 */ + SCIFA5_RXD_PORT92_MARK, + + SCIFA5_SCK_PORT23_MARK, /* SCIFA5_SCK Port 23/206 */ + SCIFA5_SCK_PORT206_MARK, + + /* SCIFA6 */ + SCIFA6_SCK_MARK, SCIFA6_RXD_MARK, SCIFA6_TXD_MARK, + + /* SCIFA7 */ + SCIFA7_TXD_MARK, SCIFA7_RXD_MARK, + + /* SCIFAB */ + SCIFB_SCK_PORT190_MARK, /* MSEL5CR_17_0 */ + SCIFB_RXD_PORT191_MARK, + SCIFB_TXD_PORT192_MARK, + SCIFB_RTS_PORT186_MARK, + SCIFB_CTS_PORT187_MARK, + + SCIFB_SCK_PORT2_MARK, /* MSEL5CR_17_1 */ + SCIFB_RXD_PORT3_MARK, + SCIFB_TXD_PORT4_MARK, + SCIFB_RTS_PORT172_MARK, + SCIFB_CTS_PORT173_MARK, + + /* LCD0 */ + LCDC0_SELECT_MARK, + + LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK, + LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK, + LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK, + LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK, + LCD0_D16_MARK, LCD0_D17_MARK, + LCD0_DON_MARK, LCD0_VCPWC_MARK, LCD0_VEPWC_MARK, + LCD0_DCK_MARK, LCD0_VSYN_MARK, /* for RGB */ + LCD0_HSYN_MARK, LCD0_DISP_MARK, /* for RGB */ + LCD0_WR_MARK, LCD0_RD_MARK, /* for SYS */ + LCD0_CS_MARK, LCD0_RS_MARK, /* for SYS */ + + LCD0_D21_PORT158_MARK, LCD0_D23_PORT159_MARK, /* MSEL5CR_6_1 */ + LCD0_D22_PORT160_MARK, LCD0_D20_PORT161_MARK, + LCD0_D19_PORT162_MARK, LCD0_D18_PORT163_MARK, + LCD0_LCLK_PORT165_MARK, + + LCD0_D18_PORT40_MARK, LCD0_D22_PORT0_MARK, /* MSEL5CR_6_0 */ + LCD0_D23_PORT1_MARK, LCD0_D21_PORT2_MARK, + LCD0_D20_PORT3_MARK, LCD0_D19_PORT4_MARK, + LCD0_LCLK_PORT102_MARK, + + /* LCD1 */ + LCDC1_SELECT_MARK, + + LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK, + LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK, + LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK, + LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK, + LCD1_D16_MARK, LCD1_D17_MARK, LCD1_D18_MARK, LCD1_D19_MARK, + LCD1_D20_MARK, LCD1_D21_MARK, LCD1_D22_MARK, LCD1_D23_MARK, + LCD1_DON_MARK, LCD1_VCPWC_MARK, + LCD1_LCLK_MARK, LCD1_VEPWC_MARK, + + LCD1_DCK_MARK, LCD1_VSYN_MARK, /* for RGB */ + LCD1_HSYN_MARK, LCD1_DISP_MARK, /* for RGB */ + LCD1_RS_MARK, LCD1_CS_MARK, /* for SYS */ + LCD1_RD_MARK, LCD1_WR_MARK, /* for SYS */ + + /* RSPI */ + RSPI_SSL0_A_MARK, RSPI_SSL1_A_MARK, RSPI_SSL2_A_MARK, + RSPI_SSL3_A_MARK, RSPI_CK_A_MARK, RSPI_MOSI_A_MARK, + RSPI_MISO_A_MARK, + + /* VIO CKO */ + VIO_CKO1_MARK, /* needs fixup */ + VIO_CKO2_MARK, + VIO_CKO_1_MARK, + VIO_CKO_MARK, + + /* VIO0 */ + VIO0_D0_MARK, VIO0_D1_MARK, VIO0_D2_MARK, VIO0_D3_MARK, + VIO0_D4_MARK, VIO0_D5_MARK, VIO0_D6_MARK, VIO0_D7_MARK, + VIO0_D8_MARK, VIO0_D9_MARK, VIO0_D10_MARK, VIO0_D11_MARK, + VIO0_D12_MARK, VIO0_VD_MARK, VIO0_HD_MARK, VIO0_CLK_MARK, + VIO0_FIELD_MARK, + + VIO0_D13_PORT26_MARK, /* MSEL5CR_27_0 */ + VIO0_D14_PORT25_MARK, + VIO0_D15_PORT24_MARK, + + VIO0_D13_PORT22_MARK, /* MSEL5CR_27_1 */ + VIO0_D14_PORT95_MARK, + VIO0_D15_PORT96_MARK, + + /* VIO1 */ + VIO1_D0_MARK, VIO1_D1_MARK, VIO1_D2_MARK, VIO1_D3_MARK, + VIO1_D4_MARK, VIO1_D5_MARK, VIO1_D6_MARK, VIO1_D7_MARK, + VIO1_VD_MARK, VIO1_HD_MARK, VIO1_CLK_MARK, VIO1_FIELD_MARK, + + /* TPU0 */ + TPU0TO0_MARK, TPU0TO1_MARK, TPU0TO3_MARK, + TPU0TO2_PORT66_MARK, /* TPU0TO2 Port 66/202 */ + TPU0TO2_PORT202_MARK, + + /* SSP1 0 */ + STP0_IPD0_MARK, STP0_IPD1_MARK, STP0_IPD2_MARK, STP0_IPD3_MARK, + STP0_IPD4_MARK, STP0_IPD5_MARK, STP0_IPD6_MARK, STP0_IPD7_MARK, + STP0_IPEN_MARK, STP0_IPCLK_MARK, STP0_IPSYNC_MARK, + + /* SSP1 1 */ + STP1_IPD1_MARK, STP1_IPD2_MARK, STP1_IPD3_MARK, STP1_IPD4_MARK, + STP1_IPD5_MARK, STP1_IPD6_MARK, STP1_IPD7_MARK, STP1_IPCLK_MARK, + STP1_IPSYNC_MARK, + + STP1_IPD0_PORT186_MARK, /* MSEL5CR_23_0 */ + STP1_IPEN_PORT187_MARK, + + STP1_IPD0_PORT194_MARK, /* MSEL5CR_23_1 */ + STP1_IPEN_PORT193_MARK, + + /* SIM */ + SIM_RST_MARK, SIM_CLK_MARK, + SIM_D_PORT22_MARK, /* SIM_D Port 22/199 */ + SIM_D_PORT199_MARK, + + /* SDHI0 */ + SDHI0_D0_MARK, SDHI0_D1_MARK, SDHI0_D2_MARK, SDHI0_D3_MARK, + SDHI0_CD_MARK, SDHI0_WP_MARK, SDHI0_CMD_MARK, SDHI0_CLK_MARK, + + /* SDHI1 */ + SDHI1_D0_MARK, SDHI1_D1_MARK, SDHI1_D2_MARK, SDHI1_D3_MARK, + SDHI1_CD_MARK, SDHI1_WP_MARK, SDHI1_CMD_MARK, SDHI1_CLK_MARK, + + /* SDHI2 */ + SDHI2_D0_MARK, SDHI2_D1_MARK, SDHI2_D2_MARK, SDHI2_D3_MARK, + SDHI2_CLK_MARK, SDHI2_CMD_MARK, + + SDHI2_CD_PORT24_MARK, /* MSEL5CR_19_0 */ + SDHI2_WP_PORT25_MARK, + + SDHI2_WP_PORT177_MARK, /* MSEL5CR_19_1 */ + SDHI2_CD_PORT202_MARK, + + /* MSIOF2 */ + MSIOF2_TXD_MARK, MSIOF2_RXD_MARK, MSIOF2_TSCK_MARK, + MSIOF2_SS2_MARK, MSIOF2_TSYNC_MARK, MSIOF2_SS1_MARK, + MSIOF2_MCK1_MARK, MSIOF2_MCK0_MARK, MSIOF2_RSYNC_MARK, + MSIOF2_RSCK_MARK, + + /* KEYSC */ + KEYIN4_MARK, KEYIN5_MARK, KEYIN6_MARK, KEYIN7_MARK, + KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK, + KEYOUT4_MARK, KEYOUT5_MARK, KEYOUT6_MARK, KEYOUT7_MARK, + + KEYIN0_PORT43_MARK, /* MSEL4CR_18_0 */ + KEYIN1_PORT44_MARK, + KEYIN2_PORT45_MARK, + KEYIN3_PORT46_MARK, + + KEYIN0_PORT58_MARK, /* MSEL4CR_18_1 */ + KEYIN1_PORT57_MARK, + KEYIN2_PORT56_MARK, + KEYIN3_PORT55_MARK, + + /* VOU */ + DV_D0_MARK, DV_D1_MARK, DV_D2_MARK, DV_D3_MARK, + DV_D4_MARK, DV_D5_MARK, DV_D6_MARK, DV_D7_MARK, + DV_D8_MARK, DV_D9_MARK, DV_D10_MARK, DV_D11_MARK, + DV_D12_MARK, DV_D13_MARK, DV_D14_MARK, DV_D15_MARK, + DV_CLK_MARK, DV_VSYNC_MARK, DV_HSYNC_MARK, + + /* MEMC */ + MEMC_AD0_MARK, MEMC_AD1_MARK, MEMC_AD2_MARK, MEMC_AD3_MARK, + MEMC_AD4_MARK, MEMC_AD5_MARK, MEMC_AD6_MARK, MEMC_AD7_MARK, + MEMC_AD8_MARK, MEMC_AD9_MARK, MEMC_AD10_MARK, MEMC_AD11_MARK, + MEMC_AD12_MARK, MEMC_AD13_MARK, MEMC_AD14_MARK, MEMC_AD15_MARK, + MEMC_CS0_MARK, MEMC_INT_MARK, MEMC_NWE_MARK, MEMC_NOE_MARK, + + MEMC_CS1_MARK, /* MSEL4CR_6_0 */ + MEMC_ADV_MARK, + MEMC_WAIT_MARK, + MEMC_BUSCLK_MARK, + + MEMC_A1_MARK, /* MSEL4CR_6_1 */ + MEMC_DREQ0_MARK, + MEMC_DREQ1_MARK, + MEMC_A0_MARK, + + /* MMC */ + MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK, + MMC0_D3_PORT71_MARK, MMC0_D4_PORT72_MARK, MMC0_D5_PORT73_MARK, + MMC0_D6_PORT74_MARK, MMC0_D7_PORT75_MARK, MMC0_CLK_PORT66_MARK, + MMC0_CMD_PORT67_MARK, /* MSEL4CR_15_0 */ + + MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK, + MMC1_D3_PORT146_MARK, MMC1_D4_PORT145_MARK, MMC1_D5_PORT144_MARK, + MMC1_D6_PORT143_MARK, MMC1_D7_PORT142_MARK, MMC1_CLK_PORT103_MARK, + MMC1_CMD_PORT104_MARK, /* MSEL4CR_15_1 */ + + /* MSIOF0 */ + MSIOF0_SS1_MARK, MSIOF0_SS2_MARK, MSIOF0_RXD_MARK, + MSIOF0_TXD_MARK, MSIOF0_MCK0_MARK, MSIOF0_MCK1_MARK, + MSIOF0_RSYNC_MARK, MSIOF0_RSCK_MARK, MSIOF0_TSCK_MARK, + MSIOF0_TSYNC_MARK, + + /* MSIOF1 */ + MSIOF1_RSCK_MARK, MSIOF1_RSYNC_MARK, + MSIOF1_MCK0_MARK, MSIOF1_MCK1_MARK, + + MSIOF1_SS2_PORT116_MARK, MSIOF1_SS1_PORT117_MARK, + MSIOF1_RXD_PORT118_MARK, MSIOF1_TXD_PORT119_MARK, + MSIOF1_TSYNC_PORT120_MARK, + MSIOF1_TSCK_PORT121_MARK, /* MSEL4CR_10_0 */ + + MSIOF1_SS1_PORT67_MARK, MSIOF1_TSCK_PORT72_MARK, + MSIOF1_TSYNC_PORT73_MARK, MSIOF1_TXD_PORT74_MARK, + MSIOF1_RXD_PORT75_MARK, + MSIOF1_SS2_PORT202_MARK, /* MSEL4CR_10_1 */ + + /* GPIO */ + GPO0_MARK, GPI0_MARK, GPO1_MARK, GPI1_MARK, + + /* USB0 */ + USB0_OCI_MARK, USB0_PPON_MARK, VBUS_MARK, + + /* USB1 */ + USB1_OCI_MARK, USB1_PPON_MARK, + + /* BBIF1 */ + BBIF1_RXD_MARK, BBIF1_TXD_MARK, BBIF1_TSYNC_MARK, + BBIF1_TSCK_MARK, BBIF1_RSCK_MARK, BBIF1_RSYNC_MARK, + BBIF1_FLOW_MARK, BBIF1_RX_FLOW_N_MARK, + + /* BBIF2 */ + BBIF2_TXD2_PORT5_MARK, /* MSEL5CR_0_0 */ + BBIF2_RXD2_PORT60_MARK, + BBIF2_TSYNC2_PORT6_MARK, + BBIF2_TSCK2_PORT59_MARK, + + BBIF2_RXD2_PORT90_MARK, /* MSEL5CR_0_1 */ + BBIF2_TXD2_PORT183_MARK, + BBIF2_TSCK2_PORT89_MARK, + BBIF2_TSYNC2_PORT184_MARK, + + /* BSC / FLCTL / PCMCIA */ + CS0_MARK, CS2_MARK, CS4_MARK, + CS5B_MARK, CS6A_MARK, + CS5A_PORT105_MARK, /* CS5A PORT 19/105 */ + CS5A_PORT19_MARK, + IOIS16_MARK, /* ? */ + + A0_MARK, A1_MARK, A2_MARK, A3_MARK, + A4_FOE_MARK, /* share with FLCTL */ + A5_FCDE_MARK, /* share with FLCTL */ + A6_MARK, A7_MARK, A8_MARK, A9_MARK, + A10_MARK, A11_MARK, A12_MARK, A13_MARK, + A14_MARK, A15_MARK, A16_MARK, A17_MARK, + A18_MARK, A19_MARK, A20_MARK, A21_MARK, + A22_MARK, A23_MARK, A24_MARK, A25_MARK, + A26_MARK, + + D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, /* share with FLCTL */ + D3_NAF3_MARK, D4_NAF4_MARK, D5_NAF5_MARK, /* share with FLCTL */ + D6_NAF6_MARK, D7_NAF7_MARK, D8_NAF8_MARK, /* share with FLCTL */ + D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK, /* share with FLCTL */ + D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, /* share with FLCTL */ + D15_NAF15_MARK, /* share with FLCTL */ + D16_MARK, D17_MARK, D18_MARK, D19_MARK, + D20_MARK, D21_MARK, D22_MARK, D23_MARK, + D24_MARK, D25_MARK, D26_MARK, D27_MARK, + D28_MARK, D29_MARK, D30_MARK, D31_MARK, + + WE0_FWE_MARK, /* share with FLCTL */ + WE1_MARK, + WE2_ICIORD_MARK, /* share with PCMCIA */ + WE3_ICIOWR_MARK, /* share with PCMCIA */ + CKO_MARK, BS_MARK, RDWR_MARK, + RD_FSC_MARK, /* share with FLCTL */ + WAIT_PORT177_MARK, /* WAIT Port 90/177 */ + WAIT_PORT90_MARK, + + FCE0_MARK, FCE1_MARK, FRB_MARK, /* FLCTL */ + + /* IRDA */ + IRDA_FIRSEL_MARK, IRDA_IN_MARK, IRDA_OUT_MARK, + + /* ATAPI */ + IDE_D0_MARK, IDE_D1_MARK, IDE_D2_MARK, IDE_D3_MARK, + IDE_D4_MARK, IDE_D5_MARK, IDE_D6_MARK, IDE_D7_MARK, + IDE_D8_MARK, IDE_D9_MARK, IDE_D10_MARK, IDE_D11_MARK, + IDE_D12_MARK, IDE_D13_MARK, IDE_D14_MARK, IDE_D15_MARK, + IDE_A0_MARK, IDE_A1_MARK, IDE_A2_MARK, IDE_CS0_MARK, + IDE_CS1_MARK, IDE_IOWR_MARK, IDE_IORD_MARK, IDE_IORDY_MARK, + IDE_INT_MARK, IDE_RST_MARK, IDE_DIRECTION_MARK, + IDE_EXBUF_ENB_MARK, IDE_IODACK_MARK, IDE_IODREQ_MARK, + + /* RMII */ + RMII_CRS_DV_MARK, RMII_RX_ER_MARK, RMII_RXD0_MARK, + RMII_RXD1_MARK, RMII_TX_EN_MARK, RMII_TXD0_MARK, + RMII_MDC_MARK, RMII_TXD1_MARK, RMII_MDIO_MARK, + RMII_REF50CK_MARK, /* for RMII */ + RMII_REF125CK_MARK, /* for GMII */ + + /* GEther */ + ET_TX_CLK_MARK, ET_TX_EN_MARK, ET_ETXD0_MARK, ET_ETXD1_MARK, + ET_ETXD2_MARK, ET_ETXD3_MARK, + ET_ETXD4_MARK, ET_ETXD5_MARK, /* for GEther */ + ET_ETXD6_MARK, ET_ETXD7_MARK, /* for GEther */ + ET_COL_MARK, ET_TX_ER_MARK, ET_RX_CLK_MARK, ET_RX_DV_MARK, + ET_ERXD0_MARK, ET_ERXD1_MARK, ET_ERXD2_MARK, ET_ERXD3_MARK, + ET_ERXD4_MARK, ET_ERXD5_MARK, /* for GEther */ + ET_ERXD6_MARK, ET_ERXD7_MARK, /* for GEther */ + ET_RX_ER_MARK, ET_CRS_MARK, ET_MDC_MARK, ET_MDIO_MARK, + ET_LINK_MARK, ET_PHY_INT_MARK, ET_WOL_MARK, ET_GTX_CLK_MARK, + + /* DMA0 */ + DREQ0_MARK, DACK0_MARK, + + /* DMA1 */ + DREQ1_MARK, DACK1_MARK, + + /* SYSC */ + RESETOUTS_MARK, RESETP_PULLUP_MARK, RESETP_PLAIN_MARK, + + /* IRREM */ + IROUT_MARK, + + /* SDENC */ + SDENC_CPG_MARK, SDENC_DV_CLKI_MARK, + + /* DEBUG */ + EDEBGREQ_PULLUP_MARK, /* for JTAG */ + EDEBGREQ_PULLDOWN_MARK, + + TRACEAUD_FROM_VIO_MARK, /* for TRACE/AUD */ + TRACEAUD_FROM_LCDC0_MARK, + TRACEAUD_FROM_MEMC_MARK, + + PINMUX_MARK_END, +}; + +static pinmux_enum_t pinmux_data[] = { + /* specify valid pin states for each pin in GPIO mode */ + + /* I/O and Pull U/D */ + PORT_DATA_IO_PD(0), PORT_DATA_IO_PD(1), + PORT_DATA_IO_PD(2), PORT_DATA_IO_PD(3), + PORT_DATA_IO_PD(4), PORT_DATA_IO_PD(5), + PORT_DATA_IO_PD(6), PORT_DATA_IO(7), + PORT_DATA_IO(8), PORT_DATA_IO(9), + + PORT_DATA_IO_PD(10), PORT_DATA_IO_PD(11), + PORT_DATA_IO_PD(12), PORT_DATA_IO_PU_PD(13), + PORT_DATA_IO_PD(14), PORT_DATA_IO_PD(15), + PORT_DATA_IO_PD(16), PORT_DATA_IO_PD(17), + PORT_DATA_IO(18), PORT_DATA_IO_PU(19), + + PORT_DATA_IO_PU_PD(20), PORT_DATA_IO_PD(21), + PORT_DATA_IO_PU_PD(22), PORT_DATA_IO(23), + PORT_DATA_IO_PU(24), PORT_DATA_IO_PU(25), + PORT_DATA_IO_PU(26), PORT_DATA_IO_PU(27), + PORT_DATA_IO_PU(28), PORT_DATA_IO_PU(29), + + PORT_DATA_IO_PU(30), PORT_DATA_IO_PD(31), + PORT_DATA_IO_PD(32), PORT_DATA_IO_PD(33), + PORT_DATA_IO_PD(34), PORT_DATA_IO_PU(35), + PORT_DATA_IO_PU(36), PORT_DATA_IO_PD(37), + PORT_DATA_IO_PU(38), PORT_DATA_IO_PD(39), + + PORT_DATA_IO_PU_PD(40), PORT_DATA_IO_PD(41), + PORT_DATA_IO_PD(42), PORT_DATA_IO_PU_PD(43), + PORT_DATA_IO_PU_PD(44), PORT_DATA_IO_PU_PD(45), + PORT_DATA_IO_PU_PD(46), PORT_DATA_IO_PU_PD(47), + PORT_DATA_IO_PU_PD(48), PORT_DATA_IO_PU_PD(49), + + PORT_DATA_IO_PU_PD(50), PORT_DATA_IO_PD(51), + PORT_DATA_IO_PD(52), PORT_DATA_IO_PD(53), + PORT_DATA_IO_PD(54), PORT_DATA_IO_PU_PD(55), + PORT_DATA_IO_PU_PD(56), PORT_DATA_IO_PU_PD(57), + PORT_DATA_IO_PU_PD(58), PORT_DATA_IO_PU_PD(59), + + PORT_DATA_IO_PU_PD(60), PORT_DATA_IO_PD(61), + PORT_DATA_IO_PD(62), PORT_DATA_IO_PD(63), + PORT_DATA_IO_PD(64), PORT_DATA_IO_PD(65), + PORT_DATA_IO_PU_PD(66), PORT_DATA_IO_PU_PD(67), + PORT_DATA_IO_PU_PD(68), PORT_DATA_IO_PU_PD(69), + + PORT_DATA_IO_PU_PD(70), PORT_DATA_IO_PU_PD(71), + PORT_DATA_IO_PU_PD(72), PORT_DATA_IO_PU_PD(73), + PORT_DATA_IO_PU_PD(74), PORT_DATA_IO_PU_PD(75), + PORT_DATA_IO_PU_PD(76), PORT_DATA_IO_PU_PD(77), + PORT_DATA_IO_PU_PD(78), PORT_DATA_IO_PU_PD(79), + + PORT_DATA_IO_PU_PD(80), PORT_DATA_IO_PU_PD(81), + PORT_DATA_IO(82), PORT_DATA_IO_PU_PD(83), + PORT_DATA_IO(84), PORT_DATA_IO_PD(85), + PORT_DATA_IO_PD(86), PORT_DATA_IO_PD(87), + PORT_DATA_IO_PD(88), PORT_DATA_IO_PD(89), + + PORT_DATA_IO_PD(90), PORT_DATA_IO_PU_PD(91), + PORT_DATA_IO_PU_PD(92), PORT_DATA_IO_PU_PD(93), + PORT_DATA_IO_PU_PD(94), PORT_DATA_IO_PU_PD(95), + PORT_DATA_IO_PU_PD(96), PORT_DATA_IO_PU_PD(97), + PORT_DATA_IO_PU_PD(98), PORT_DATA_IO_PU_PD(99), + + PORT_DATA_IO_PU_PD(100), PORT_DATA_IO(101), + PORT_DATA_IO_PU(102), PORT_DATA_IO_PU_PD(103), + PORT_DATA_IO_PU(104), PORT_DATA_IO_PU(105), + PORT_DATA_IO_PU_PD(106), PORT_DATA_IO(107), + PORT_DATA_IO(108), PORT_DATA_IO(109), + + PORT_DATA_IO(110), PORT_DATA_IO(111), + PORT_DATA_IO(112), PORT_DATA_IO(113), + PORT_DATA_IO_PU_PD(114), PORT_DATA_IO(115), + PORT_DATA_IO_PD(116), PORT_DATA_IO_PD(117), + PORT_DATA_IO_PD(118), PORT_DATA_IO_PD(119), + + PORT_DATA_IO_PD(120), PORT_DATA_IO_PD(121), + PORT_DATA_IO_PD(122), PORT_DATA_IO_PD(123), + PORT_DATA_IO_PD(124), PORT_DATA_IO(125), + PORT_DATA_IO(126), PORT_DATA_IO(127), + PORT_DATA_IO(128), PORT_DATA_IO(129), + + PORT_DATA_IO(130), PORT_DATA_IO(131), + PORT_DATA_IO(132), PORT_DATA_IO(133), + PORT_DATA_IO(134), PORT_DATA_IO(135), + PORT_DATA_IO(136), PORT_DATA_IO(137), + PORT_DATA_IO(138), PORT_DATA_IO(139), + + PORT_DATA_IO(140), PORT_DATA_IO(141), + PORT_DATA_IO_PU(142), PORT_DATA_IO_PU(143), + PORT_DATA_IO_PU(144), PORT_DATA_IO_PU(145), + PORT_DATA_IO_PU(146), PORT_DATA_IO_PU(147), + PORT_DATA_IO_PU(148), PORT_DATA_IO_PU(149), + + PORT_DATA_IO_PU(150), PORT_DATA_IO_PU(151), + PORT_DATA_IO_PU(152), PORT_DATA_IO_PU(153), + PORT_DATA_IO_PU(154), PORT_DATA_IO_PU(155), + PORT_DATA_IO_PU(156), PORT_DATA_IO_PU(157), + PORT_DATA_IO_PD(158), PORT_DATA_IO_PD(159), + + PORT_DATA_IO_PU_PD(160), PORT_DATA_IO_PD(161), + PORT_DATA_IO_PD(162), PORT_DATA_IO_PD(163), + PORT_DATA_IO_PD(164), PORT_DATA_IO_PD(165), + PORT_DATA_IO_PU(166), PORT_DATA_IO_PU(167), + PORT_DATA_IO_PU(168), PORT_DATA_IO_PU(169), + + PORT_DATA_IO_PU(170), PORT_DATA_IO_PU(171), + PORT_DATA_IO_PD(172), PORT_DATA_IO_PD(173), + PORT_DATA_IO_PD(174), PORT_DATA_IO_PD(175), + PORT_DATA_IO_PU(176), PORT_DATA_IO_PU_PD(177), + PORT_DATA_IO_PU(178), PORT_DATA_IO_PD(179), + + PORT_DATA_IO_PD(180), PORT_DATA_IO_PU(181), + PORT_DATA_IO_PU(182), PORT_DATA_IO(183), + PORT_DATA_IO_PD(184), PORT_DATA_IO_PD(185), + PORT_DATA_IO_PD(186), PORT_DATA_IO_PD(187), + PORT_DATA_IO_PD(188), PORT_DATA_IO_PD(189), + + PORT_DATA_IO_PD(190), PORT_DATA_IO_PD(191), + PORT_DATA_IO_PD(192), PORT_DATA_IO_PU_PD(193), + PORT_DATA_IO_PU_PD(194), PORT_DATA_IO_PD(195), + PORT_DATA_IO_PU_PD(196), PORT_DATA_IO_PD(197), + PORT_DATA_IO_PU_PD(198), PORT_DATA_IO_PU_PD(199), + + PORT_DATA_IO_PU_PD(200), PORT_DATA_IO_PU(201), + PORT_DATA_IO_PU_PD(202), PORT_DATA_IO(203), + PORT_DATA_IO_PU_PD(204), PORT_DATA_IO_PU_PD(205), + PORT_DATA_IO_PU_PD(206), PORT_DATA_IO_PU_PD(207), + PORT_DATA_IO_PU_PD(208), PORT_DATA_IO_PD(209), + + PORT_DATA_IO_PD(210), PORT_DATA_IO_PD(211), + + /* Port0 */ + PINMUX_DATA(DBGMDT2_MARK, PORT0_FN1), + PINMUX_DATA(FSIAISLD_PORT0_MARK, PORT0_FN2, MSEL5CR_3_0), + PINMUX_DATA(FSIAOSLD1_MARK, PORT0_FN3), + PINMUX_DATA(LCD0_D22_PORT0_MARK, PORT0_FN4, MSEL5CR_6_0), + PINMUX_DATA(SCIFA7_RXD_MARK, PORT0_FN6), + PINMUX_DATA(LCD1_D4_MARK, PORT0_FN7), + PINMUX_DATA(IRQ5_PORT0_MARK, PORT0_FN0, MSEL1CR_5_0), + + /* Port1 */ + PINMUX_DATA(DBGMDT1_MARK, PORT1_FN1), + PINMUX_DATA(FMSISLD_PORT1_MARK, PORT1_FN2, MSEL5CR_5_0), + PINMUX_DATA(FSIAOSLD2_MARK, PORT1_FN3), + PINMUX_DATA(LCD0_D23_PORT1_MARK, PORT1_FN4, MSEL5CR_6_0), + PINMUX_DATA(SCIFA7_TXD_MARK, PORT1_FN6), + PINMUX_DATA(LCD1_D3_MARK, PORT1_FN7), + PINMUX_DATA(IRQ5_PORT1_MARK, PORT1_FN0, MSEL1CR_5_1), + + /* Port2 */ + PINMUX_DATA(DBGMDT0_MARK, PORT2_FN1), + PINMUX_DATA(SCIFB_SCK_PORT2_MARK, PORT2_FN2, MSEL5CR_17_1), + PINMUX_DATA(LCD0_D21_PORT2_MARK, PORT2_FN4, MSEL5CR_6_0), + PINMUX_DATA(LCD1_D2_MARK, PORT2_FN7), + PINMUX_DATA(IRQ0_PORT2_MARK, PORT2_FN0, MSEL1CR_0_1), + + /* Port3 */ + PINMUX_DATA(DBGMD21_MARK, PORT3_FN1), + PINMUX_DATA(SCIFB_RXD_PORT3_MARK, PORT3_FN2, MSEL5CR_17_1), + PINMUX_DATA(LCD0_D20_PORT3_MARK, PORT3_FN4, MSEL5CR_6_0), + PINMUX_DATA(LCD1_D1_MARK, PORT3_FN7), + + /* Port4 */ + PINMUX_DATA(DBGMD20_MARK, PORT4_FN1), + PINMUX_DATA(SCIFB_TXD_PORT4_MARK, PORT4_FN2, MSEL5CR_17_1), + PINMUX_DATA(LCD0_D19_PORT4_MARK, PORT4_FN4, MSEL5CR_6_0), + PINMUX_DATA(LCD1_D0_MARK, PORT4_FN7), + + /* Port5 */ + PINMUX_DATA(DBGMD11_MARK, PORT5_FN1), + PINMUX_DATA(BBIF2_TXD2_PORT5_MARK, PORT5_FN2, MSEL5CR_0_0), + PINMUX_DATA(FSIAISLD_PORT5_MARK, PORT5_FN4, MSEL5CR_3_1), + PINMUX_DATA(RSPI_SSL0_A_MARK, PORT5_FN6), + PINMUX_DATA(LCD1_VCPWC_MARK, PORT5_FN7), + + /* Port6 */ + PINMUX_DATA(DBGMD10_MARK, PORT6_FN1), + PINMUX_DATA(BBIF2_TSYNC2_PORT6_MARK, PORT6_FN2, MSEL5CR_0_0), + PINMUX_DATA(FMSISLD_PORT6_MARK, PORT6_FN4, MSEL5CR_5_1), + PINMUX_DATA(RSPI_SSL1_A_MARK, PORT6_FN6), + PINMUX_DATA(LCD1_VEPWC_MARK, PORT6_FN7), + + /* Port7 */ + PINMUX_DATA(FSIAOLR_MARK, PORT7_FN1), + + /* Port8 */ + PINMUX_DATA(FSIAOBT_MARK, PORT8_FN1), + + /* Port9 */ + PINMUX_DATA(FSIAOSLD_MARK, PORT9_FN1), + PINMUX_DATA(FSIASPDIF_PORT9_MARK, PORT9_FN2, MSEL5CR_4_0), + + /* Port10 */ + PINMUX_DATA(FSIAOMC_MARK, PORT10_FN1), + PINMUX_DATA(SCIFA5_RXD_PORT10_MARK, PORT10_FN3, MSEL5CR_14_0, MSEL5CR_15_0), + PINMUX_DATA(IRQ3_PORT10_MARK, PORT10_FN0, MSEL1CR_3_0), + + /* Port11 */ + PINMUX_DATA(FSIACK_MARK, PORT11_FN1), + PINMUX_DATA(IRQ2_PORT11_MARK, PORT11_FN0, MSEL1CR_2_0), + + /* Port12 */ + PINMUX_DATA(FSIAILR_MARK, PORT12_FN1), + PINMUX_DATA(SCIFA4_RXD_PORT12_MARK, PORT12_FN2, MSEL5CR_12_0, MSEL5CR_11_0), + PINMUX_DATA(LCD1_RS_MARK, PORT12_FN6), + PINMUX_DATA(LCD1_DISP_MARK, PORT12_FN7), + PINMUX_DATA(IRQ2_PORT12_MARK, PORT12_FN0, MSEL1CR_2_1), + + /* Port13 */ + PINMUX_DATA(FSIAIBT_MARK, PORT13_FN1), + PINMUX_DATA(SCIFA4_TXD_PORT13_MARK, PORT13_FN2, MSEL5CR_12_0, MSEL5CR_11_0), + PINMUX_DATA(LCD1_RD_MARK, PORT13_FN7), + PINMUX_DATA(IRQ0_PORT13_MARK, PORT13_FN0, MSEL1CR_0_0), + + /* Port14 */ + PINMUX_DATA(FMSOILR_MARK, PORT14_FN1), + PINMUX_DATA(FMSIILR_MARK, PORT14_FN2), + PINMUX_DATA(VIO_CKO1_MARK, PORT14_FN3), + PINMUX_DATA(LCD1_D23_MARK, PORT14_FN7), + PINMUX_DATA(IRQ3_PORT14_MARK, PORT14_FN0, MSEL1CR_3_1), + + /* Port15 */ + PINMUX_DATA(FMSOIBT_MARK, PORT15_FN1), + PINMUX_DATA(FMSIIBT_MARK, PORT15_FN2), + PINMUX_DATA(VIO_CKO2_MARK, PORT15_FN3), + PINMUX_DATA(LCD1_D22_MARK, PORT15_FN7), + PINMUX_DATA(IRQ4_PORT15_MARK, PORT15_FN0, MSEL1CR_4_0), + + /* Port16 */ + PINMUX_DATA(FMSOOLR_MARK, PORT16_FN1), + PINMUX_DATA(FMSIOLR_MARK, PORT16_FN2), + + /* Port17 */ + PINMUX_DATA(FMSOOBT_MARK, PORT17_FN1), + PINMUX_DATA(FMSIOBT_MARK, PORT17_FN2), + + /* Port18 */ + PINMUX_DATA(FMSOSLD_MARK, PORT18_FN1), + PINMUX_DATA(FSIASPDIF_PORT18_MARK, PORT18_FN2, MSEL5CR_4_1), + + /* Port19 */ + PINMUX_DATA(FMSICK_MARK, PORT19_FN1), + PINMUX_DATA(CS5A_PORT19_MARK, PORT19_FN7, MSEL5CR_2_1), + PINMUX_DATA(IRQ10_MARK, PORT19_FN0), + + /* Port20 */ + PINMUX_DATA(FMSOCK_MARK, PORT20_FN1), + PINMUX_DATA(SCIFA5_TXD_PORT20_MARK, PORT20_FN3, MSEL5CR_15_0, MSEL5CR_14_0), + PINMUX_DATA(IRQ1_MARK, PORT20_FN0), + + /* Port21 */ + PINMUX_DATA(SCIFA1_CTS_MARK, PORT21_FN1), + PINMUX_DATA(SCIFA4_SCK_PORT21_MARK, PORT21_FN2, MSEL5CR_10_0), + PINMUX_DATA(TPU0TO1_MARK, PORT21_FN4), + PINMUX_DATA(VIO1_FIELD_MARK, PORT21_FN5), + PINMUX_DATA(STP0_IPD5_MARK, PORT21_FN6), + PINMUX_DATA(LCD1_D10_MARK, PORT21_FN7), + + /* Port22 */ + PINMUX_DATA(SCIFA2_SCK_PORT22_MARK, PORT22_FN1, MSEL5CR_7_0), + PINMUX_DATA(SIM_D_PORT22_MARK, PORT22_FN4, MSEL5CR_21_0), + PINMUX_DATA(VIO0_D13_PORT22_MARK, PORT22_FN7, MSEL5CR_27_1), + + /* Port23 */ + PINMUX_DATA(SCIFA1_RTS_MARK, PORT23_FN1), + PINMUX_DATA(SCIFA5_SCK_PORT23_MARK, PORT23_FN3, MSEL5CR_13_0), + PINMUX_DATA(TPU0TO0_MARK, PORT23_FN4), + PINMUX_DATA(VIO_CKO_1_MARK, PORT23_FN5), + PINMUX_DATA(STP0_IPD2_MARK, PORT23_FN6), + PINMUX_DATA(LCD1_D7_MARK, PORT23_FN7), + + /* Port24 */ + PINMUX_DATA(VIO0_D15_PORT24_MARK, PORT24_FN1, MSEL5CR_27_0), + PINMUX_DATA(VIO1_D7_MARK, PORT24_FN5), + PINMUX_DATA(SCIFA6_SCK_MARK, PORT24_FN6), + PINMUX_DATA(SDHI2_CD_PORT24_MARK, PORT24_FN7, MSEL5CR_19_0), + + /* Port25 */ + PINMUX_DATA(VIO0_D14_PORT25_MARK, PORT25_FN1, MSEL5CR_27_0), + PINMUX_DATA(VIO1_D6_MARK, PORT25_FN5), + PINMUX_DATA(SCIFA6_RXD_MARK, PORT25_FN6), + PINMUX_DATA(SDHI2_WP_PORT25_MARK, PORT25_FN7, MSEL5CR_19_0), + + /* Port26 */ + PINMUX_DATA(VIO0_D13_PORT26_MARK, PORT26_FN1, MSEL5CR_27_0), + PINMUX_DATA(VIO1_D5_MARK, PORT26_FN5), + PINMUX_DATA(SCIFA6_TXD_MARK, PORT26_FN6), + + /* Port27 - Port39 Function */ + PINMUX_DATA(VIO0_D7_MARK, PORT27_FN1), + PINMUX_DATA(VIO0_D6_MARK, PORT28_FN1), + PINMUX_DATA(VIO0_D5_MARK, PORT29_FN1), + PINMUX_DATA(VIO0_D4_MARK, PORT30_FN1), + PINMUX_DATA(VIO0_D3_MARK, PORT31_FN1), + PINMUX_DATA(VIO0_D2_MARK, PORT32_FN1), + PINMUX_DATA(VIO0_D1_MARK, PORT33_FN1), + PINMUX_DATA(VIO0_D0_MARK, PORT34_FN1), + PINMUX_DATA(VIO0_CLK_MARK, PORT35_FN1), + PINMUX_DATA(VIO_CKO_MARK, PORT36_FN1), + PINMUX_DATA(VIO0_HD_MARK, PORT37_FN1), + PINMUX_DATA(VIO0_FIELD_MARK, PORT38_FN1), + PINMUX_DATA(VIO0_VD_MARK, PORT39_FN1), + + /* Port38 IRQ */ + PINMUX_DATA(IRQ25_MARK, PORT38_FN0), + + /* Port40 */ + PINMUX_DATA(LCD0_D18_PORT40_MARK, PORT40_FN4, MSEL5CR_6_0), + PINMUX_DATA(RSPI_CK_A_MARK, PORT40_FN6), + PINMUX_DATA(LCD1_LCLK_MARK, PORT40_FN7), + + /* Port41 */ + PINMUX_DATA(LCD0_D17_MARK, PORT41_FN1), + PINMUX_DATA(MSIOF2_SS1_MARK, PORT41_FN2), + PINMUX_DATA(IRQ31_PORT41_MARK, PORT41_FN0, MSEL1CR_31_1), + + /* Port42 */ + PINMUX_DATA(LCD0_D16_MARK, PORT42_FN1), + PINMUX_DATA(MSIOF2_MCK1_MARK, PORT42_FN2), + PINMUX_DATA(IRQ12_PORT42_MARK, PORT42_FN0, MSEL1CR_12_1), + + /* Port43 */ + PINMUX_DATA(LCD0_D15_MARK, PORT43_FN1), + PINMUX_DATA(MSIOF2_MCK0_MARK, PORT43_FN2), + PINMUX_DATA(KEYIN0_PORT43_MARK, PORT43_FN3, MSEL4CR_18_0), + PINMUX_DATA(DV_D15_MARK, PORT43_FN6), + + /* Port44 */ + PINMUX_DATA(LCD0_D14_MARK, PORT44_FN1), + PINMUX_DATA(MSIOF2_RSYNC_MARK, PORT44_FN2), + PINMUX_DATA(KEYIN1_PORT44_MARK, PORT44_FN3, MSEL4CR_18_0), + PINMUX_DATA(DV_D14_MARK, PORT44_FN6), + + /* Port45 */ + PINMUX_DATA(LCD0_D13_MARK, PORT45_FN1), + PINMUX_DATA(MSIOF2_RSCK_MARK, PORT45_FN2), + PINMUX_DATA(KEYIN2_PORT45_MARK, PORT45_FN3, MSEL4CR_18_0), + PINMUX_DATA(DV_D13_MARK, PORT45_FN6), + + /* Port46 */ + PINMUX_DATA(LCD0_D12_MARK, PORT46_FN1), + PINMUX_DATA(KEYIN3_PORT46_MARK, PORT46_FN3, MSEL4CR_18_0), + PINMUX_DATA(DV_D12_MARK, PORT46_FN6), + + /* Port47 */ + PINMUX_DATA(LCD0_D11_MARK, PORT47_FN1), + PINMUX_DATA(KEYIN4_MARK, PORT47_FN3), + PINMUX_DATA(DV_D11_MARK, PORT47_FN6), + + /* Port48 */ + PINMUX_DATA(LCD0_D10_MARK, PORT48_FN1), + PINMUX_DATA(KEYIN5_MARK, PORT48_FN3), + PINMUX_DATA(DV_D10_MARK, PORT48_FN6), + + /* Port49 */ + PINMUX_DATA(LCD0_D9_MARK, PORT49_FN1), + PINMUX_DATA(KEYIN6_MARK, PORT49_FN3), + PINMUX_DATA(DV_D9_MARK, PORT49_FN6), + PINMUX_DATA(IRQ30_PORT49_MARK, PORT49_FN0, MSEL1CR_30_1), + + /* Port50 */ + PINMUX_DATA(LCD0_D8_MARK, PORT50_FN1), + PINMUX_DATA(KEYIN7_MARK, PORT50_FN3), + PINMUX_DATA(DV_D8_MARK, PORT50_FN6), + PINMUX_DATA(IRQ29_PORT50_MARK, PORT50_FN0, MSEL1CR_29_1), + + /* Port51 */ + PINMUX_DATA(LCD0_D7_MARK, PORT51_FN1), + PINMUX_DATA(KEYOUT0_MARK, PORT51_FN3), + PINMUX_DATA(DV_D7_MARK, PORT51_FN6), + + /* Port52 */ + PINMUX_DATA(LCD0_D6_MARK, PORT52_FN1), + PINMUX_DATA(KEYOUT1_MARK, PORT52_FN3), + PINMUX_DATA(DV_D6_MARK, PORT52_FN6), + + /* Port53 */ + PINMUX_DATA(LCD0_D5_MARK, PORT53_FN1), + PINMUX_DATA(KEYOUT2_MARK, PORT53_FN3), + PINMUX_DATA(DV_D5_MARK, PORT53_FN6), + + /* Port54 */ + PINMUX_DATA(LCD0_D4_MARK, PORT54_FN1), + PINMUX_DATA(KEYOUT3_MARK, PORT54_FN3), + PINMUX_DATA(DV_D4_MARK, PORT54_FN6), + + /* Port55 */ + PINMUX_DATA(LCD0_D3_MARK, PORT55_FN1), + PINMUX_DATA(KEYOUT4_MARK, PORT55_FN3), + PINMUX_DATA(KEYIN3_PORT55_MARK, PORT55_FN4, MSEL4CR_18_1), + PINMUX_DATA(DV_D3_MARK, PORT55_FN6), + + /* Port56 */ + PINMUX_DATA(LCD0_D2_MARK, PORT56_FN1), + PINMUX_DATA(KEYOUT5_MARK, PORT56_FN3), + PINMUX_DATA(KEYIN2_PORT56_MARK, PORT56_FN4, MSEL4CR_18_1), + PINMUX_DATA(DV_D2_MARK, PORT56_FN6), + PINMUX_DATA(IRQ28_PORT56_MARK, PORT56_FN0, MSEL1CR_28_1), + + /* Port57 */ + PINMUX_DATA(LCD0_D1_MARK, PORT57_FN1), + PINMUX_DATA(KEYOUT6_MARK, PORT57_FN3), + PINMUX_DATA(KEYIN1_PORT57_MARK, PORT57_FN4, MSEL4CR_18_1), + PINMUX_DATA(DV_D1_MARK, PORT57_FN6), + PINMUX_DATA(IRQ27_PORT57_MARK, PORT57_FN0, MSEL1CR_27_1), + + /* Port58 */ + PINMUX_DATA(LCD0_D0_MARK, PORT58_FN1), + PINMUX_DATA(KEYOUT7_MARK, PORT58_FN3), + PINMUX_DATA(KEYIN0_PORT58_MARK, PORT58_FN4, MSEL4CR_18_1), + PINMUX_DATA(DV_D0_MARK, PORT58_FN6), + PINMUX_DATA(IRQ26_PORT58_MARK, PORT58_FN0, MSEL1CR_26_1), + + /* Port59 */ + PINMUX_DATA(LCD0_VCPWC_MARK, PORT59_FN1), + PINMUX_DATA(BBIF2_TSCK2_PORT59_MARK, PORT59_FN2, MSEL5CR_0_0), + PINMUX_DATA(RSPI_MOSI_A_MARK, PORT59_FN6), + + /* Port60 */ + PINMUX_DATA(LCD0_VEPWC_MARK, PORT60_FN1), + PINMUX_DATA(BBIF2_RXD2_PORT60_MARK, PORT60_FN2, MSEL5CR_0_0), + PINMUX_DATA(RSPI_MISO_A_MARK, PORT60_FN6), + + /* Port61 */ + PINMUX_DATA(LCD0_DON_MARK, PORT61_FN1), + PINMUX_DATA(MSIOF2_TXD_MARK, PORT61_FN2), + + /* Port62 */ + PINMUX_DATA(LCD0_DCK_MARK, PORT62_FN1), + PINMUX_DATA(LCD0_WR_MARK, PORT62_FN4), + PINMUX_DATA(DV_CLK_MARK, PORT62_FN6), + PINMUX_DATA(IRQ15_PORT62_MARK, PORT62_FN0, MSEL1CR_15_1), + + /* Port63 */ + PINMUX_DATA(LCD0_VSYN_MARK, PORT63_FN1), + PINMUX_DATA(DV_VSYNC_MARK, PORT63_FN6), + PINMUX_DATA(IRQ14_PORT63_MARK, PORT63_FN0, MSEL1CR_14_1), + + /* Port64 */ + PINMUX_DATA(LCD0_HSYN_MARK, PORT64_FN1), + PINMUX_DATA(LCD0_CS_MARK, PORT64_FN4), + PINMUX_DATA(DV_HSYNC_MARK, PORT64_FN6), + PINMUX_DATA(IRQ13_PORT64_MARK, PORT64_FN0, MSEL1CR_13_1), + + /* Port65 */ + PINMUX_DATA(LCD0_DISP_MARK, PORT65_FN1), + PINMUX_DATA(MSIOF2_TSCK_MARK, PORT65_FN2), + PINMUX_DATA(LCD0_RS_MARK, PORT65_FN4), + + /* Port66 */ + PINMUX_DATA(MEMC_INT_MARK, PORT66_FN1), + PINMUX_DATA(TPU0TO2_PORT66_MARK, PORT66_FN3, MSEL5CR_25_0), + PINMUX_DATA(MMC0_CLK_PORT66_MARK, PORT66_FN4, MSEL4CR_15_0), + PINMUX_DATA(SDHI1_CLK_MARK, PORT66_FN6), + + /* Port67 - Port73 Function1 */ + PINMUX_DATA(MEMC_CS0_MARK, PORT67_FN1), + PINMUX_DATA(MEMC_AD8_MARK, PORT68_FN1), + PINMUX_DATA(MEMC_AD9_MARK, PORT69_FN1), + PINMUX_DATA(MEMC_AD10_MARK, PORT70_FN1), + PINMUX_DATA(MEMC_AD11_MARK, PORT71_FN1), + PINMUX_DATA(MEMC_AD12_MARK, PORT72_FN1), + PINMUX_DATA(MEMC_AD13_MARK, PORT73_FN1), + + /* Port67 - Port73 Function2 */ + PINMUX_DATA(MSIOF1_SS1_PORT67_MARK, PORT67_FN2, MSEL4CR_10_1), + PINMUX_DATA(MSIOF1_RSCK_MARK, PORT68_FN2), + PINMUX_DATA(MSIOF1_RSYNC_MARK, PORT69_FN2), + PINMUX_DATA(MSIOF1_MCK0_MARK, PORT70_FN2), + PINMUX_DATA(MSIOF1_MCK1_MARK, PORT71_FN2), + PINMUX_DATA(MSIOF1_TSCK_PORT72_MARK, PORT72_FN2, MSEL4CR_10_1), + PINMUX_DATA(MSIOF1_TSYNC_PORT73_MARK, PORT73_FN2, MSEL4CR_10_1), + + /* Port67 - Port73 Function4 */ + PINMUX_DATA(MMC0_CMD_PORT67_MARK, PORT67_FN4, MSEL4CR_15_0), + PINMUX_DATA(MMC0_D0_PORT68_MARK, PORT68_FN4, MSEL4CR_15_0), + PINMUX_DATA(MMC0_D1_PORT69_MARK, PORT69_FN4, MSEL4CR_15_0), + PINMUX_DATA(MMC0_D2_PORT70_MARK, PORT70_FN4, MSEL4CR_15_0), + PINMUX_DATA(MMC0_D3_PORT71_MARK, PORT71_FN4, MSEL4CR_15_0), + PINMUX_DATA(MMC0_D4_PORT72_MARK, PORT72_FN4, MSEL4CR_15_0), + PINMUX_DATA(MMC0_D5_PORT73_MARK, PORT73_FN4, MSEL4CR_15_0), + + /* Port67 - Port73 Function6 */ + PINMUX_DATA(SDHI1_CMD_MARK, PORT67_FN6), + PINMUX_DATA(SDHI1_D0_MARK, PORT68_FN6), + PINMUX_DATA(SDHI1_D1_MARK, PORT69_FN6), + PINMUX_DATA(SDHI1_D2_MARK, PORT70_FN6), + PINMUX_DATA(SDHI1_D3_MARK, PORT71_FN6), + PINMUX_DATA(SDHI1_CD_MARK, PORT72_FN6), + PINMUX_DATA(SDHI1_WP_MARK, PORT73_FN6), + + /* Port67 - Port71 IRQ */ + PINMUX_DATA(IRQ20_MARK, PORT67_FN0), + PINMUX_DATA(IRQ16_PORT68_MARK, PORT68_FN0, MSEL1CR_16_0), + PINMUX_DATA(IRQ17_MARK, PORT69_FN0), + PINMUX_DATA(IRQ18_MARK, PORT70_FN0), + PINMUX_DATA(IRQ19_MARK, PORT71_FN0), + + /* Port74 */ + PINMUX_DATA(MEMC_AD14_MARK, PORT74_FN1), + PINMUX_DATA(MSIOF1_TXD_PORT74_MARK, PORT74_FN2, MSEL4CR_10_1), + PINMUX_DATA(MMC0_D6_PORT74_MARK, PORT74_FN4, MSEL4CR_15_0), + PINMUX_DATA(STP1_IPD7_MARK, PORT74_FN6), + PINMUX_DATA(LCD1_D21_MARK, PORT74_FN7), + + /* Port75 */ + PINMUX_DATA(MEMC_AD15_MARK, PORT75_FN1), + PINMUX_DATA(MSIOF1_RXD_PORT75_MARK, PORT75_FN2, MSEL4CR_10_1), + PINMUX_DATA(MMC0_D7_PORT75_MARK, PORT75_FN4, MSEL4CR_15_0), + PINMUX_DATA(STP1_IPD6_MARK, PORT75_FN6), + PINMUX_DATA(LCD1_D20_MARK, PORT75_FN7), + + /* Port76 - Port80 Function */ + PINMUX_DATA(SDHI0_CMD_MARK, PORT76_FN1), + PINMUX_DATA(SDHI0_D0_MARK, PORT77_FN1), + PINMUX_DATA(SDHI0_D1_MARK, PORT78_FN1), + PINMUX_DATA(SDHI0_D2_MARK, PORT79_FN1), + PINMUX_DATA(SDHI0_D3_MARK, PORT80_FN1), + + /* Port81 */ + PINMUX_DATA(SDHI0_CD_MARK, PORT81_FN1), + PINMUX_DATA(IRQ26_PORT81_MARK, PORT81_FN0, MSEL1CR_26_0), + + /* Port82 - Port88 Function */ + PINMUX_DATA(SDHI0_CLK_MARK, PORT82_FN1), + PINMUX_DATA(SDHI0_WP_MARK, PORT83_FN1), + PINMUX_DATA(RESETOUTS_MARK, PORT84_FN1), + PINMUX_DATA(USB0_PPON_MARK, PORT85_FN1), + PINMUX_DATA(USB0_OCI_MARK, PORT86_FN1), + PINMUX_DATA(USB1_PPON_MARK, PORT87_FN1), + PINMUX_DATA(USB1_OCI_MARK, PORT88_FN1), + + /* Port89 */ + PINMUX_DATA(DREQ0_MARK, PORT89_FN1), + PINMUX_DATA(BBIF2_TSCK2_PORT89_MARK, PORT89_FN2, MSEL5CR_0_1), + PINMUX_DATA(RSPI_SSL3_A_MARK, PORT89_FN6), + + /* Port90 */ + PINMUX_DATA(DACK0_MARK, PORT90_FN1), + PINMUX_DATA(BBIF2_RXD2_PORT90_MARK, PORT90_FN2, MSEL5CR_0_1), + PINMUX_DATA(RSPI_SSL2_A_MARK, PORT90_FN6), + PINMUX_DATA(WAIT_PORT90_MARK, PORT90_FN7, MSEL5CR_2_1), + + /* Port91 */ + PINMUX_DATA(MEMC_AD0_MARK, PORT91_FN1), + PINMUX_DATA(BBIF1_RXD_MARK, PORT91_FN2), + PINMUX_DATA(SCIFA5_TXD_PORT91_MARK, PORT91_FN3, MSEL5CR_15_1, MSEL5CR_14_0), + PINMUX_DATA(LCD1_D5_MARK, PORT91_FN7), + + /* Port92 */ + PINMUX_DATA(MEMC_AD1_MARK, PORT92_FN1), + PINMUX_DATA(BBIF1_TSYNC_MARK, PORT92_FN2), + PINMUX_DATA(SCIFA5_RXD_PORT92_MARK, PORT92_FN3, MSEL5CR_15_1, MSEL5CR_14_0), + PINMUX_DATA(STP0_IPD1_MARK, PORT92_FN6), + PINMUX_DATA(LCD1_D6_MARK, PORT92_FN7), + + /* Port93 */ + PINMUX_DATA(MEMC_AD2_MARK, PORT93_FN1), + PINMUX_DATA(BBIF1_TSCK_MARK, PORT93_FN2), + PINMUX_DATA(SCIFA4_TXD_PORT93_MARK, PORT93_FN3, MSEL5CR_12_1, MSEL5CR_11_0), + PINMUX_DATA(STP0_IPD3_MARK, PORT93_FN6), + PINMUX_DATA(LCD1_D8_MARK, PORT93_FN7), + + /* Port94 */ + PINMUX_DATA(MEMC_AD3_MARK, PORT94_FN1), + PINMUX_DATA(BBIF1_TXD_MARK, PORT94_FN2), + PINMUX_DATA(SCIFA4_RXD_PORT94_MARK, PORT94_FN3, MSEL5CR_12_1, MSEL5CR_11_0), + PINMUX_DATA(STP0_IPD4_MARK, PORT94_FN6), + PINMUX_DATA(LCD1_D9_MARK, PORT94_FN7), + + /* Port95 */ + PINMUX_DATA(MEMC_CS1_MARK, PORT95_FN1, MSEL4CR_6_0), + PINMUX_DATA(MEMC_A1_MARK, PORT95_FN1, MSEL4CR_6_1), + + PINMUX_DATA(SCIFA2_CTS_MARK, PORT95_FN2), + PINMUX_DATA(SIM_RST_MARK, PORT95_FN4), + PINMUX_DATA(VIO0_D14_PORT95_MARK, PORT95_FN7, MSEL5CR_27_1), + PINMUX_DATA(IRQ22_MARK, PORT95_FN0), + + /* Port96 */ + PINMUX_DATA(MEMC_ADV_MARK, PORT96_FN1, MSEL4CR_6_0), + PINMUX_DATA(MEMC_DREQ0_MARK, PORT96_FN1, MSEL4CR_6_1), + + PINMUX_DATA(SCIFA2_RTS_MARK, PORT96_FN2), + PINMUX_DATA(SIM_CLK_MARK, PORT96_FN4), + PINMUX_DATA(VIO0_D15_PORT96_MARK, PORT96_FN7, MSEL5CR_27_1), + PINMUX_DATA(IRQ23_MARK, PORT96_FN0), + + /* Port97 */ + PINMUX_DATA(MEMC_AD4_MARK, PORT97_FN1), + PINMUX_DATA(BBIF1_RSCK_MARK, PORT97_FN2), + PINMUX_DATA(LCD1_CS_MARK, PORT97_FN6), + PINMUX_DATA(LCD1_HSYN_MARK, PORT97_FN7), + PINMUX_DATA(IRQ12_PORT97_MARK, PORT97_FN0, MSEL1CR_12_0), + + /* Port98 */ + PINMUX_DATA(MEMC_AD5_MARK, PORT98_FN1), + PINMUX_DATA(BBIF1_RSYNC_MARK, PORT98_FN2), + PINMUX_DATA(LCD1_VSYN_MARK, PORT98_FN7), + PINMUX_DATA(IRQ13_PORT98_MARK, PORT98_FN0, MSEL1CR_13_0), + + /* Port99 */ + PINMUX_DATA(MEMC_AD6_MARK, PORT99_FN1), + PINMUX_DATA(BBIF1_FLOW_MARK, PORT99_FN2), + PINMUX_DATA(LCD1_WR_MARK, PORT99_FN6), + PINMUX_DATA(LCD1_DCK_MARK, PORT99_FN7), + PINMUX_DATA(IRQ14_PORT99_MARK, PORT99_FN0, MSEL1CR_14_0), + + /* Port100 */ + PINMUX_DATA(MEMC_AD7_MARK, PORT100_FN1), + PINMUX_DATA(BBIF1_RX_FLOW_N_MARK, PORT100_FN2), + PINMUX_DATA(LCD1_DON_MARK, PORT100_FN7), + PINMUX_DATA(IRQ15_PORT100_MARK, PORT100_FN0, MSEL1CR_15_0), + + /* Port101 */ + PINMUX_DATA(FCE0_MARK, PORT101_FN1), + + /* Port102 */ + PINMUX_DATA(FRB_MARK, PORT102_FN1), + PINMUX_DATA(LCD0_LCLK_PORT102_MARK, PORT102_FN4, MSEL5CR_6_0), + + /* Port103 */ + PINMUX_DATA(CS5B_MARK, PORT103_FN1), + PINMUX_DATA(FCE1_MARK, PORT103_FN2), + PINMUX_DATA(MMC1_CLK_PORT103_MARK, PORT103_FN3, MSEL4CR_15_1), + + /* Port104 */ + PINMUX_DATA(CS6A_MARK, PORT104_FN1), + PINMUX_DATA(MMC1_CMD_PORT104_MARK, PORT104_FN3, MSEL4CR_15_1), + PINMUX_DATA(IRQ11_MARK, PORT104_FN0), + + /* Port105 */ + PINMUX_DATA(CS5A_PORT105_MARK, PORT105_FN1, MSEL5CR_2_0), + PINMUX_DATA(SCIFA3_RTS_PORT105_MARK, PORT105_FN4, MSEL5CR_8_0), + + /* Port106 */ + PINMUX_DATA(IOIS16_MARK, PORT106_FN1), + PINMUX_DATA(IDE_EXBUF_ENB_MARK, PORT106_FN6), + + /* Port107 - Port115 Function */ + PINMUX_DATA(WE3_ICIOWR_MARK, PORT107_FN1), + PINMUX_DATA(WE2_ICIORD_MARK, PORT108_FN1), + PINMUX_DATA(CS0_MARK, PORT109_FN1), + PINMUX_DATA(CS2_MARK, PORT110_FN1), + PINMUX_DATA(CS4_MARK, PORT111_FN1), + PINMUX_DATA(WE1_MARK, PORT112_FN1), + PINMUX_DATA(WE0_FWE_MARK, PORT113_FN1), + PINMUX_DATA(RDWR_MARK, PORT114_FN1), + PINMUX_DATA(RD_FSC_MARK, PORT115_FN1), + + /* Port116 */ + PINMUX_DATA(A25_MARK, PORT116_FN1), + PINMUX_DATA(MSIOF0_SS2_MARK, PORT116_FN2), + PINMUX_DATA(MSIOF1_SS2_PORT116_MARK, PORT116_FN3, MSEL4CR_10_0), + PINMUX_DATA(SCIFA3_SCK_PORT116_MARK, PORT116_FN4, MSEL5CR_8_0), + PINMUX_DATA(GPO1_MARK, PORT116_FN5), + + /* Port117 */ + PINMUX_DATA(A24_MARK, PORT117_FN1), + PINMUX_DATA(MSIOF0_SS1_MARK, PORT117_FN2), + PINMUX_DATA(MSIOF1_SS1_PORT117_MARK, PORT117_FN3, MSEL4CR_10_0), + PINMUX_DATA(SCIFA3_CTS_PORT117_MARK, PORT117_FN4, MSEL5CR_8_0), + PINMUX_DATA(GPO0_MARK, PORT117_FN5), + + /* Port118 */ + PINMUX_DATA(A23_MARK, PORT118_FN1), + PINMUX_DATA(MSIOF0_MCK1_MARK, PORT118_FN2), + PINMUX_DATA(MSIOF1_RXD_PORT118_MARK, PORT118_FN3, MSEL4CR_10_0), + PINMUX_DATA(GPI1_MARK, PORT118_FN5), + PINMUX_DATA(IRQ9_PORT118_MARK, PORT118_FN0, MSEL1CR_9_0), + + /* Port119 */ + PINMUX_DATA(A22_MARK, PORT119_FN1), + PINMUX_DATA(MSIOF0_MCK0_MARK, PORT119_FN2), + PINMUX_DATA(MSIOF1_TXD_PORT119_MARK, PORT119_FN3, MSEL4CR_10_0), + PINMUX_DATA(GPI0_MARK, PORT119_FN5), + PINMUX_DATA(IRQ8_MARK, PORT119_FN0), + + /* Port120 */ + PINMUX_DATA(A21_MARK, PORT120_FN1), + PINMUX_DATA(MSIOF0_RSYNC_MARK, PORT120_FN2), + PINMUX_DATA(MSIOF1_TSYNC_PORT120_MARK, PORT120_FN3, MSEL4CR_10_0), + PINMUX_DATA(IRQ7_PORT120_MARK, PORT120_FN0, MSEL1CR_7_0), + + /* Port121 */ + PINMUX_DATA(A20_MARK, PORT121_FN1), + PINMUX_DATA(MSIOF0_RSCK_MARK, PORT121_FN2), + PINMUX_DATA(MSIOF1_TSCK_PORT121_MARK, PORT121_FN3, MSEL4CR_10_0), + PINMUX_DATA(IRQ6_PORT121_MARK, PORT121_FN0, MSEL1CR_6_0), + + /* Port122 */ + PINMUX_DATA(A19_MARK, PORT122_FN1), + PINMUX_DATA(MSIOF0_RXD_MARK, PORT122_FN2), + + /* Port123 */ + PINMUX_DATA(A18_MARK, PORT123_FN1), + PINMUX_DATA(MSIOF0_TSCK_MARK, PORT123_FN2), + + /* Port124 */ + PINMUX_DATA(A17_MARK, PORT124_FN1), + PINMUX_DATA(MSIOF0_TSYNC_MARK, PORT124_FN2), + + /* Port125 - Port141 Function */ + PINMUX_DATA(A16_MARK, PORT125_FN1), + PINMUX_DATA(A15_MARK, PORT126_FN1), + PINMUX_DATA(A14_MARK, PORT127_FN1), + PINMUX_DATA(A13_MARK, PORT128_FN1), + PINMUX_DATA(A12_MARK, PORT129_FN1), + PINMUX_DATA(A11_MARK, PORT130_FN1), + PINMUX_DATA(A10_MARK, PORT131_FN1), + PINMUX_DATA(A9_MARK, PORT132_FN1), + PINMUX_DATA(A8_MARK, PORT133_FN1), + PINMUX_DATA(A7_MARK, PORT134_FN1), + PINMUX_DATA(A6_MARK, PORT135_FN1), + PINMUX_DATA(A5_FCDE_MARK, PORT136_FN1), + PINMUX_DATA(A4_FOE_MARK, PORT137_FN1), + PINMUX_DATA(A3_MARK, PORT138_FN1), + PINMUX_DATA(A2_MARK, PORT139_FN1), + PINMUX_DATA(A1_MARK, PORT140_FN1), + PINMUX_DATA(CKO_MARK, PORT141_FN1), + + /* Port142 - Port157 Function1 */ + PINMUX_DATA(D15_NAF15_MARK, PORT142_FN1), + PINMUX_DATA(D14_NAF14_MARK, PORT143_FN1), + PINMUX_DATA(D13_NAF13_MARK, PORT144_FN1), + PINMUX_DATA(D12_NAF12_MARK, PORT145_FN1), + PINMUX_DATA(D11_NAF11_MARK, PORT146_FN1), + PINMUX_DATA(D10_NAF10_MARK, PORT147_FN1), + PINMUX_DATA(D9_NAF9_MARK, PORT148_FN1), + PINMUX_DATA(D8_NAF8_MARK, PORT149_FN1), + PINMUX_DATA(D7_NAF7_MARK, PORT150_FN1), + PINMUX_DATA(D6_NAF6_MARK, PORT151_FN1), + PINMUX_DATA(D5_NAF5_MARK, PORT152_FN1), + PINMUX_DATA(D4_NAF4_MARK, PORT153_FN1), + PINMUX_DATA(D3_NAF3_MARK, PORT154_FN1), + PINMUX_DATA(D2_NAF2_MARK, PORT155_FN1), + PINMUX_DATA(D1_NAF1_MARK, PORT156_FN1), + PINMUX_DATA(D0_NAF0_MARK, PORT157_FN1), + + /* Port142 - Port149 Function3 */ + PINMUX_DATA(MMC1_D7_PORT142_MARK, PORT142_FN3, MSEL4CR_15_1), + PINMUX_DATA(MMC1_D6_PORT143_MARK, PORT143_FN3, MSEL4CR_15_1), + PINMUX_DATA(MMC1_D5_PORT144_MARK, PORT144_FN3, MSEL4CR_15_1), + PINMUX_DATA(MMC1_D4_PORT145_MARK, PORT145_FN3, MSEL4CR_15_1), + PINMUX_DATA(MMC1_D3_PORT146_MARK, PORT146_FN3, MSEL4CR_15_1), + PINMUX_DATA(MMC1_D2_PORT147_MARK, PORT147_FN3, MSEL4CR_15_1), + PINMUX_DATA(MMC1_D1_PORT148_MARK, PORT148_FN3, MSEL4CR_15_1), + PINMUX_DATA(MMC1_D0_PORT149_MARK, PORT149_FN3, MSEL4CR_15_1), + + /* Port158 */ + PINMUX_DATA(D31_MARK, PORT158_FN1), + PINMUX_DATA(SCIFA3_SCK_PORT158_MARK, PORT158_FN2, MSEL5CR_8_1), + PINMUX_DATA(RMII_REF125CK_MARK, PORT158_FN3), + PINMUX_DATA(LCD0_D21_PORT158_MARK, PORT158_FN4, MSEL5CR_6_1), + PINMUX_DATA(IRDA_FIRSEL_MARK, PORT158_FN5), + PINMUX_DATA(IDE_D15_MARK, PORT158_FN6), + + /* Port159 */ + PINMUX_DATA(D30_MARK, PORT159_FN1), + PINMUX_DATA(SCIFA3_RXD_PORT159_MARK, PORT159_FN2, MSEL5CR_8_1), + PINMUX_DATA(RMII_REF50CK_MARK, PORT159_FN3), + PINMUX_DATA(LCD0_D23_PORT159_MARK, PORT159_FN4, MSEL5CR_6_1), + PINMUX_DATA(IDE_D14_MARK, PORT159_FN6), + + /* Port160 */ + PINMUX_DATA(D29_MARK, PORT160_FN1), + PINMUX_DATA(SCIFA3_TXD_PORT160_MARK, PORT160_FN2, MSEL5CR_8_1), + PINMUX_DATA(LCD0_D22_PORT160_MARK, PORT160_FN4, MSEL5CR_6_1), + PINMUX_DATA(VIO1_HD_MARK, PORT160_FN5), + PINMUX_DATA(IDE_D13_MARK, PORT160_FN6), + + /* Port161 */ + PINMUX_DATA(D28_MARK, PORT161_FN1), + PINMUX_DATA(SCIFA3_RTS_PORT161_MARK, PORT161_FN2, MSEL5CR_8_1), + PINMUX_DATA(ET_RX_DV_MARK, PORT161_FN3), + PINMUX_DATA(LCD0_D20_PORT161_MARK, PORT161_FN4, MSEL5CR_6_1), + PINMUX_DATA(IRDA_IN_MARK, PORT161_FN5), + PINMUX_DATA(IDE_D12_MARK, PORT161_FN6), + + /* Port162 */ + PINMUX_DATA(D27_MARK, PORT162_FN1), + PINMUX_DATA(SCIFA3_CTS_PORT162_MARK, PORT162_FN2, MSEL5CR_8_1), + PINMUX_DATA(LCD0_D19_PORT162_MARK, PORT162_FN4, MSEL5CR_6_1), + PINMUX_DATA(IRDA_OUT_MARK, PORT162_FN5), + PINMUX_DATA(IDE_D11_MARK, PORT162_FN6), + + /* Port163 */ + PINMUX_DATA(D26_MARK, PORT163_FN1), + PINMUX_DATA(MSIOF2_SS2_MARK, PORT163_FN2), + PINMUX_DATA(ET_COL_MARK, PORT163_FN3), + PINMUX_DATA(LCD0_D18_PORT163_MARK, PORT163_FN4, MSEL5CR_6_1), + PINMUX_DATA(IROUT_MARK, PORT163_FN5), + PINMUX_DATA(IDE_D10_MARK, PORT163_FN6), + + /* Port164 */ + PINMUX_DATA(D25_MARK, PORT164_FN1), + PINMUX_DATA(MSIOF2_TSYNC_MARK, PORT164_FN2), + PINMUX_DATA(ET_PHY_INT_MARK, PORT164_FN3), + PINMUX_DATA(LCD0_RD_MARK, PORT164_FN4), + PINMUX_DATA(IDE_D9_MARK, PORT164_FN6), + + /* Port165 */ + PINMUX_DATA(D24_MARK, PORT165_FN1), + PINMUX_DATA(MSIOF2_RXD_MARK, PORT165_FN2), + PINMUX_DATA(LCD0_LCLK_PORT165_MARK, PORT165_FN4, MSEL5CR_6_1), + PINMUX_DATA(IDE_D8_MARK, PORT165_FN6), + + /* Port166 - Port171 Function1 */ + PINMUX_DATA(D21_MARK, PORT166_FN1), + PINMUX_DATA(D20_MARK, PORT167_FN1), + PINMUX_DATA(D19_MARK, PORT168_FN1), + PINMUX_DATA(D18_MARK, PORT169_FN1), + PINMUX_DATA(D17_MARK, PORT170_FN1), + PINMUX_DATA(D16_MARK, PORT171_FN1), + + /* Port166 - Port171 Function3 */ + PINMUX_DATA(ET_ETXD5_MARK, PORT166_FN3), + PINMUX_DATA(ET_ETXD4_MARK, PORT167_FN3), + PINMUX_DATA(ET_ETXD3_MARK, PORT168_FN3), + PINMUX_DATA(ET_ETXD2_MARK, PORT169_FN3), + PINMUX_DATA(ET_ETXD1_MARK, PORT170_FN3), + PINMUX_DATA(ET_ETXD0_MARK, PORT171_FN3), + + /* Port166 - Port171 Function6 */ + PINMUX_DATA(IDE_D5_MARK, PORT166_FN6), + PINMUX_DATA(IDE_D4_MARK, PORT167_FN6), + PINMUX_DATA(IDE_D3_MARK, PORT168_FN6), + PINMUX_DATA(IDE_D2_MARK, PORT169_FN6), + PINMUX_DATA(IDE_D1_MARK, PORT170_FN6), + PINMUX_DATA(IDE_D0_MARK, PORT171_FN6), + + /* Port167 - Port171 IRQ */ + PINMUX_DATA(IRQ31_PORT167_MARK, PORT167_FN0, MSEL1CR_31_0), + PINMUX_DATA(IRQ27_PORT168_MARK, PORT168_FN0, MSEL1CR_27_0), + PINMUX_DATA(IRQ28_PORT169_MARK, PORT169_FN0, MSEL1CR_28_0), + PINMUX_DATA(IRQ29_PORT170_MARK, PORT170_FN0, MSEL1CR_29_0), + PINMUX_DATA(IRQ30_PORT171_MARK, PORT171_FN0, MSEL1CR_30_0), + + /* Port172 */ + PINMUX_DATA(D23_MARK, PORT172_FN1), + PINMUX_DATA(SCIFB_RTS_PORT172_MARK, PORT172_FN2, MSEL5CR_17_1), + PINMUX_DATA(ET_ETXD7_MARK, PORT172_FN3), + PINMUX_DATA(IDE_D7_MARK, PORT172_FN6), + PINMUX_DATA(IRQ4_PORT172_MARK, PORT172_FN0, MSEL1CR_4_1), + + /* Port173 */ + PINMUX_DATA(D22_MARK, PORT173_FN1), + PINMUX_DATA(SCIFB_CTS_PORT173_MARK, PORT173_FN2, MSEL5CR_17_1), + PINMUX_DATA(ET_ETXD6_MARK, PORT173_FN3), + PINMUX_DATA(IDE_D6_MARK, PORT173_FN6), + PINMUX_DATA(IRQ6_PORT173_MARK, PORT173_FN0, MSEL1CR_6_1), + + /* Port174 */ + PINMUX_DATA(A26_MARK, PORT174_FN1), + PINMUX_DATA(MSIOF0_TXD_MARK, PORT174_FN2), + PINMUX_DATA(ET_RX_CLK_MARK, PORT174_FN3), + PINMUX_DATA(SCIFA3_RXD_PORT174_MARK, PORT174_FN4, MSEL5CR_8_0), + + /* Port175 */ + PINMUX_DATA(A0_MARK, PORT175_FN1), + PINMUX_DATA(BS_MARK, PORT175_FN2), + PINMUX_DATA(ET_WOL_MARK, PORT175_FN3), + PINMUX_DATA(SCIFA3_TXD_PORT175_MARK, PORT175_FN4, MSEL5CR_8_0), + + /* Port176 */ + PINMUX_DATA(ET_GTX_CLK_MARK, PORT176_FN3), + + /* Port177 */ + PINMUX_DATA(WAIT_PORT177_MARK, PORT177_FN1, MSEL5CR_2_0), + PINMUX_DATA(ET_LINK_MARK, PORT177_FN3), + PINMUX_DATA(IDE_IOWR_MARK, PORT177_FN6), + PINMUX_DATA(SDHI2_WP_PORT177_MARK, PORT177_FN7, MSEL5CR_19_1), + + /* Port178 */ + PINMUX_DATA(VIO0_D12_MARK, PORT178_FN1), + PINMUX_DATA(VIO1_D4_MARK, PORT178_FN5), + PINMUX_DATA(IDE_IORD_MARK, PORT178_FN6), + + /* Port179 */ + PINMUX_DATA(VIO0_D11_MARK, PORT179_FN1), + PINMUX_DATA(VIO1_D3_MARK, PORT179_FN5), + PINMUX_DATA(IDE_IORDY_MARK, PORT179_FN6), + + /* Port180 */ + PINMUX_DATA(VIO0_D10_MARK, PORT180_FN1), + PINMUX_DATA(TPU0TO3_MARK, PORT180_FN4), + PINMUX_DATA(VIO1_D2_MARK, PORT180_FN5), + PINMUX_DATA(IDE_INT_MARK, PORT180_FN6), + PINMUX_DATA(IRQ24_MARK, PORT180_FN0), + + /* Port181 */ + PINMUX_DATA(VIO0_D9_MARK, PORT181_FN1), + PINMUX_DATA(VIO1_D1_MARK, PORT181_FN5), + PINMUX_DATA(IDE_RST_MARK, PORT181_FN6), + + /* Port182 */ + PINMUX_DATA(VIO0_D8_MARK, PORT182_FN1), + PINMUX_DATA(VIO1_D0_MARK, PORT182_FN5), + PINMUX_DATA(IDE_DIRECTION_MARK, PORT182_FN6), + + /* Port183 */ + PINMUX_DATA(DREQ1_MARK, PORT183_FN1), + PINMUX_DATA(BBIF2_TXD2_PORT183_MARK, PORT183_FN2, MSEL5CR_0_1), + PINMUX_DATA(ET_TX_EN_MARK, PORT183_FN3), + + /* Port184 */ + PINMUX_DATA(DACK1_MARK, PORT184_FN1), + PINMUX_DATA(BBIF2_TSYNC2_PORT184_MARK, PORT184_FN2, MSEL5CR_0_1), + PINMUX_DATA(ET_TX_CLK_MARK, PORT184_FN3), + + /* Port185 - Port192 Function1 */ + PINMUX_DATA(SCIFA1_SCK_MARK, PORT185_FN1), + PINMUX_DATA(SCIFB_RTS_PORT186_MARK, PORT186_FN1, MSEL5CR_17_0), + PINMUX_DATA(SCIFB_CTS_PORT187_MARK, PORT187_FN1, MSEL5CR_17_0), + PINMUX_DATA(SCIFA0_SCK_MARK, PORT188_FN1), + PINMUX_DATA(SCIFB_SCK_PORT190_MARK, PORT190_FN1, MSEL5CR_17_0), + PINMUX_DATA(SCIFB_RXD_PORT191_MARK, PORT191_FN1, MSEL5CR_17_0), + PINMUX_DATA(SCIFB_TXD_PORT192_MARK, PORT192_FN1, MSEL5CR_17_0), + + /* Port185 - Port192 Function3 */ + PINMUX_DATA(ET_ERXD0_MARK, PORT185_FN3), + PINMUX_DATA(ET_ERXD1_MARK, PORT186_FN3), + PINMUX_DATA(ET_ERXD2_MARK, PORT187_FN3), + PINMUX_DATA(ET_ERXD3_MARK, PORT188_FN3), + PINMUX_DATA(ET_ERXD4_MARK, PORT189_FN3), + PINMUX_DATA(ET_ERXD5_MARK, PORT190_FN3), + PINMUX_DATA(ET_ERXD6_MARK, PORT191_FN3), + PINMUX_DATA(ET_ERXD7_MARK, PORT192_FN3), + + /* Port185 - Port192 Function6 */ + PINMUX_DATA(STP1_IPCLK_MARK, PORT185_FN6), + PINMUX_DATA(STP1_IPD0_PORT186_MARK, PORT186_FN6, MSEL5CR_23_0), + PINMUX_DATA(STP1_IPEN_PORT187_MARK, PORT187_FN6, MSEL5CR_23_0), + PINMUX_DATA(STP1_IPSYNC_MARK, PORT188_FN6), + PINMUX_DATA(STP0_IPCLK_MARK, PORT189_FN6), + PINMUX_DATA(STP0_IPD0_MARK, PORT190_FN6), + PINMUX_DATA(STP0_IPEN_MARK, PORT191_FN6), + PINMUX_DATA(STP0_IPSYNC_MARK, PORT192_FN6), + + /* Port193 */ + PINMUX_DATA(SCIFA0_CTS_MARK, PORT193_FN1), + PINMUX_DATA(RMII_CRS_DV_MARK, PORT193_FN3), + PINMUX_DATA(STP1_IPEN_PORT193_MARK, PORT193_FN6, MSEL5CR_23_1), /* ? */ + PINMUX_DATA(LCD1_D17_MARK, PORT193_FN7), + + /* Port194 */ + PINMUX_DATA(SCIFA0_RTS_MARK, PORT194_FN1), + PINMUX_DATA(RMII_RX_ER_MARK, PORT194_FN3), + PINMUX_DATA(STP1_IPD0_PORT194_MARK, PORT194_FN6, MSEL5CR_23_1), /* ? */ + PINMUX_DATA(LCD1_D16_MARK, PORT194_FN7), + + /* Port195 */ + PINMUX_DATA(SCIFA1_RXD_MARK, PORT195_FN1), + PINMUX_DATA(RMII_RXD0_MARK, PORT195_FN3), + PINMUX_DATA(STP1_IPD3_MARK, PORT195_FN6), + PINMUX_DATA(LCD1_D15_MARK, PORT195_FN7), + + /* Port196 */ + PINMUX_DATA(SCIFA1_TXD_MARK, PORT196_FN1), + PINMUX_DATA(RMII_RXD1_MARK, PORT196_FN3), + PINMUX_DATA(STP1_IPD2_MARK, PORT196_FN6), + PINMUX_DATA(LCD1_D14_MARK, PORT196_FN7), + + /* Port197 */ + PINMUX_DATA(SCIFA0_RXD_MARK, PORT197_FN1), + PINMUX_DATA(VIO1_CLK_MARK, PORT197_FN5), + PINMUX_DATA(STP1_IPD5_MARK, PORT197_FN6), + PINMUX_DATA(LCD1_D19_MARK, PORT197_FN7), + + /* Port198 */ + PINMUX_DATA(SCIFA0_TXD_MARK, PORT198_FN1), + PINMUX_DATA(VIO1_VD_MARK, PORT198_FN5), + PINMUX_DATA(STP1_IPD4_MARK, PORT198_FN6), + PINMUX_DATA(LCD1_D18_MARK, PORT198_FN7), + + /* Port199 */ + PINMUX_DATA(MEMC_NWE_MARK, PORT199_FN1), + PINMUX_DATA(SCIFA2_SCK_PORT199_MARK, PORT199_FN2, MSEL5CR_7_1), + PINMUX_DATA(RMII_TX_EN_MARK, PORT199_FN3), + PINMUX_DATA(SIM_D_PORT199_MARK, PORT199_FN4, MSEL5CR_21_1), + PINMUX_DATA(STP1_IPD1_MARK, PORT199_FN6), + PINMUX_DATA(LCD1_D13_MARK, PORT199_FN7), + + /* Port200 */ + PINMUX_DATA(MEMC_NOE_MARK, PORT200_FN1), + PINMUX_DATA(SCIFA2_RXD_MARK, PORT200_FN2), + PINMUX_DATA(RMII_TXD0_MARK, PORT200_FN3), + PINMUX_DATA(STP0_IPD7_MARK, PORT200_FN6), + PINMUX_DATA(LCD1_D12_MARK, PORT200_FN7), + + /* Port201 */ + PINMUX_DATA(MEMC_WAIT_MARK, PORT201_FN1, MSEL4CR_6_0), + PINMUX_DATA(MEMC_DREQ1_MARK, PORT201_FN1, MSEL4CR_6_1), + + PINMUX_DATA(SCIFA2_TXD_MARK, PORT201_FN2), + PINMUX_DATA(RMII_TXD1_MARK, PORT201_FN3), + PINMUX_DATA(STP0_IPD6_MARK, PORT201_FN6), + PINMUX_DATA(LCD1_D11_MARK, PORT201_FN7), + + /* Port202 */ + PINMUX_DATA(MEMC_BUSCLK_MARK, PORT202_FN1, MSEL4CR_6_0), + PINMUX_DATA(MEMC_A0_MARK, PORT202_FN1, MSEL4CR_6_1), + + PINMUX_DATA(MSIOF1_SS2_PORT202_MARK, PORT202_FN2, MSEL4CR_10_1), + PINMUX_DATA(RMII_MDC_MARK, PORT202_FN3), + PINMUX_DATA(TPU0TO2_PORT202_MARK, PORT202_FN4, MSEL5CR_25_1), + PINMUX_DATA(IDE_CS0_MARK, PORT202_FN6), + PINMUX_DATA(SDHI2_CD_PORT202_MARK, PORT202_FN7, MSEL5CR_19_1), + PINMUX_DATA(IRQ21_MARK, PORT202_FN0), + + /* Port203 - Port208 Function1 */ + PINMUX_DATA(SDHI2_CLK_MARK, PORT203_FN1), + PINMUX_DATA(SDHI2_CMD_MARK, PORT204_FN1), + PINMUX_DATA(SDHI2_D0_MARK, PORT205_FN1), + PINMUX_DATA(SDHI2_D1_MARK, PORT206_FN1), + PINMUX_DATA(SDHI2_D2_MARK, PORT207_FN1), + PINMUX_DATA(SDHI2_D3_MARK, PORT208_FN1), + + /* Port203 - Port208 Function3 */ + PINMUX_DATA(ET_TX_ER_MARK, PORT203_FN3), + PINMUX_DATA(ET_RX_ER_MARK, PORT204_FN3), + PINMUX_DATA(ET_CRS_MARK, PORT205_FN3), + PINMUX_DATA(ET_MDC_MARK, PORT206_FN3), + PINMUX_DATA(ET_MDIO_MARK, PORT207_FN3), + PINMUX_DATA(RMII_MDIO_MARK, PORT208_FN3), + + /* Port203 - Port208 Function6 */ + PINMUX_DATA(IDE_A2_MARK, PORT203_FN6), + PINMUX_DATA(IDE_A1_MARK, PORT204_FN6), + PINMUX_DATA(IDE_A0_MARK, PORT205_FN6), + PINMUX_DATA(IDE_IODACK_MARK, PORT206_FN6), + PINMUX_DATA(IDE_IODREQ_MARK, PORT207_FN6), + PINMUX_DATA(IDE_CS1_MARK, PORT208_FN6), + + /* Port203 - Port208 Function7 */ + PINMUX_DATA(SCIFA4_TXD_PORT203_MARK, PORT203_FN7, MSEL5CR_12_0, MSEL5CR_11_1), + PINMUX_DATA(SCIFA4_RXD_PORT204_MARK, PORT204_FN7, MSEL5CR_12_0, MSEL5CR_11_1), + PINMUX_DATA(SCIFA4_SCK_PORT205_MARK, PORT205_FN7, MSEL5CR_10_1), + PINMUX_DATA(SCIFA5_SCK_PORT206_MARK, PORT206_FN7, MSEL5CR_13_1), + PINMUX_DATA(SCIFA5_RXD_PORT207_MARK, PORT207_FN7, MSEL5CR_15_0, MSEL5CR_14_1), + PINMUX_DATA(SCIFA5_TXD_PORT208_MARK, PORT208_FN7, MSEL5CR_15_0, MSEL5CR_14_1), + + /* Port209 */ + PINMUX_DATA(VBUS_MARK, PORT209_FN1), + PINMUX_DATA(IRQ7_PORT209_MARK, PORT209_FN0, MSEL1CR_7_1), + + /* Port210 */ + PINMUX_DATA(IRQ9_PORT210_MARK, PORT210_FN0, MSEL1CR_9_1), + + /* Port211 */ + PINMUX_DATA(IRQ16_PORT211_MARK, PORT211_FN0, MSEL1CR_16_1), + + /* LCDC select */ + PINMUX_DATA(LCDC0_SELECT_MARK, MSEL3CR_6_0), + PINMUX_DATA(LCDC1_SELECT_MARK, MSEL3CR_6_1), + + /* SDENC */ + PINMUX_DATA(SDENC_CPG_MARK, MSEL4CR_19_0), + PINMUX_DATA(SDENC_DV_CLKI_MARK, MSEL4CR_19_1), + + /* SYSC */ + PINMUX_DATA(RESETP_PULLUP_MARK, MSEL4CR_4_0), + PINMUX_DATA(RESETP_PLAIN_MARK, MSEL4CR_4_1), + + /* DEBUG */ + PINMUX_DATA(EDEBGREQ_PULLDOWN_MARK, MSEL4CR_1_0), + PINMUX_DATA(EDEBGREQ_PULLUP_MARK, MSEL4CR_1_1), + + PINMUX_DATA(TRACEAUD_FROM_VIO_MARK, MSEL5CR_30_0, MSEL5CR_29_0), + PINMUX_DATA(TRACEAUD_FROM_LCDC0_MARK, MSEL5CR_30_0, MSEL5CR_29_1), + PINMUX_DATA(TRACEAUD_FROM_MEMC_MARK, MSEL5CR_30_1, MSEL5CR_29_0), +}; + +static struct pinmux_gpio pinmux_gpios[] = { + + /* PORT */ + GPIO_PORT_ALL(), + + /* IRQ */ + GPIO_FN(IRQ0_PORT2), GPIO_FN(IRQ0_PORT13), + GPIO_FN(IRQ1), + GPIO_FN(IRQ2_PORT11), GPIO_FN(IRQ2_PORT12), + GPIO_FN(IRQ3_PORT10), GPIO_FN(IRQ3_PORT14), + GPIO_FN(IRQ4_PORT15), GPIO_FN(IRQ4_PORT172), + GPIO_FN(IRQ5_PORT0), GPIO_FN(IRQ5_PORT1), + GPIO_FN(IRQ6_PORT121), GPIO_FN(IRQ6_PORT173), + GPIO_FN(IRQ7_PORT120), GPIO_FN(IRQ7_PORT209), + GPIO_FN(IRQ8), + GPIO_FN(IRQ9_PORT118), GPIO_FN(IRQ9_PORT210), + GPIO_FN(IRQ10), + GPIO_FN(IRQ11), + GPIO_FN(IRQ12_PORT42), GPIO_FN(IRQ12_PORT97), + GPIO_FN(IRQ13_PORT64), GPIO_FN(IRQ13_PORT98), + GPIO_FN(IRQ14_PORT63), GPIO_FN(IRQ14_PORT99), + GPIO_FN(IRQ15_PORT62), GPIO_FN(IRQ15_PORT100), + GPIO_FN(IRQ16_PORT68), GPIO_FN(IRQ16_PORT211), + GPIO_FN(IRQ17), + GPIO_FN(IRQ18), + GPIO_FN(IRQ19), + GPIO_FN(IRQ20), + GPIO_FN(IRQ21), + GPIO_FN(IRQ22), + GPIO_FN(IRQ23), + GPIO_FN(IRQ24), + GPIO_FN(IRQ25), + GPIO_FN(IRQ26_PORT58), GPIO_FN(IRQ26_PORT81), + GPIO_FN(IRQ27_PORT57), GPIO_FN(IRQ27_PORT168), + GPIO_FN(IRQ28_PORT56), GPIO_FN(IRQ28_PORT169), + GPIO_FN(IRQ29_PORT50), GPIO_FN(IRQ29_PORT170), + GPIO_FN(IRQ30_PORT49), GPIO_FN(IRQ30_PORT171), + GPIO_FN(IRQ31_PORT41), GPIO_FN(IRQ31_PORT167), + + /* Function */ + + /* DBGT */ + GPIO_FN(DBGMDT2), GPIO_FN(DBGMDT1), GPIO_FN(DBGMDT0), + GPIO_FN(DBGMD10), GPIO_FN(DBGMD11), GPIO_FN(DBGMD20), + GPIO_FN(DBGMD21), + + /* FSI */ + GPIO_FN(FSIAISLD_PORT0), /* FSIAISLD Port 0/5 */ + GPIO_FN(FSIAISLD_PORT5), + GPIO_FN(FSIASPDIF_PORT9), /* FSIASPDIF Port 9/18 */ + GPIO_FN(FSIASPDIF_PORT18), + GPIO_FN(FSIAOSLD1), GPIO_FN(FSIAOSLD2), GPIO_FN(FSIAOLR), + GPIO_FN(FSIAOBT), GPIO_FN(FSIAOSLD), GPIO_FN(FSIAOMC), + GPIO_FN(FSIACK), GPIO_FN(FSIAILR), GPIO_FN(FSIAIBT), + + /* FMSI */ + GPIO_FN(FMSISLD_PORT1), /* FMSISLD Port 1/6 */ + GPIO_FN(FMSISLD_PORT6), + GPIO_FN(FMSIILR), GPIO_FN(FMSIIBT), GPIO_FN(FMSIOLR), + GPIO_FN(FMSIOBT), GPIO_FN(FMSICK), GPIO_FN(FMSOILR), + GPIO_FN(FMSOIBT), GPIO_FN(FMSOOLR), GPIO_FN(FMSOOBT), + GPIO_FN(FMSOSLD), GPIO_FN(FMSOCK), + + /* SCIFA0 */ + GPIO_FN(SCIFA0_SCK), GPIO_FN(SCIFA0_CTS), GPIO_FN(SCIFA0_RTS), + GPIO_FN(SCIFA0_RXD), GPIO_FN(SCIFA0_TXD), + + /* SCIFA1 */ + GPIO_FN(SCIFA1_CTS), GPIO_FN(SCIFA1_SCK), + GPIO_FN(SCIFA1_RXD), GPIO_FN(SCIFA1_TXD), GPIO_FN(SCIFA1_RTS), + + /* SCIFA2 */ + GPIO_FN(SCIFA2_SCK_PORT22), /* SCIFA2_SCK Port 22/199 */ + GPIO_FN(SCIFA2_SCK_PORT199), + GPIO_FN(SCIFA2_RXD), GPIO_FN(SCIFA2_TXD), + GPIO_FN(SCIFA2_CTS), GPIO_FN(SCIFA2_RTS), + + /* SCIFA3 */ + GPIO_FN(SCIFA3_RTS_PORT105), /* MSEL5CR_8_0 */ + GPIO_FN(SCIFA3_SCK_PORT116), + GPIO_FN(SCIFA3_CTS_PORT117), + GPIO_FN(SCIFA3_RXD_PORT174), + GPIO_FN(SCIFA3_TXD_PORT175), + + GPIO_FN(SCIFA3_RTS_PORT161), /* MSEL5CR_8_1 */ + GPIO_FN(SCIFA3_SCK_PORT158), + GPIO_FN(SCIFA3_CTS_PORT162), + GPIO_FN(SCIFA3_RXD_PORT159), + GPIO_FN(SCIFA3_TXD_PORT160), + + /* SCIFA4 */ + GPIO_FN(SCIFA4_RXD_PORT12), /* MSEL5CR[12:11] = 00 */ + GPIO_FN(SCIFA4_TXD_PORT13), + + GPIO_FN(SCIFA4_RXD_PORT204), /* MSEL5CR[12:11] = 01 */ + GPIO_FN(SCIFA4_TXD_PORT203), + + GPIO_FN(SCIFA4_RXD_PORT94), /* MSEL5CR[12:11] = 10 */ + GPIO_FN(SCIFA4_TXD_PORT93), + + GPIO_FN(SCIFA4_SCK_PORT21), /* SCIFA4_SCK Port 21/205 */ + GPIO_FN(SCIFA4_SCK_PORT205), + + /* SCIFA5 */ + GPIO_FN(SCIFA5_TXD_PORT20), /* MSEL5CR[15:14] = 00 */ + GPIO_FN(SCIFA5_RXD_PORT10), + + GPIO_FN(SCIFA5_RXD_PORT207), /* MSEL5CR[15:14] = 01 */ + GPIO_FN(SCIFA5_TXD_PORT208), + + GPIO_FN(SCIFA5_TXD_PORT91), /* MSEL5CR[15:14] = 10 */ + GPIO_FN(SCIFA5_RXD_PORT92), + + GPIO_FN(SCIFA5_SCK_PORT23), /* SCIFA5_SCK Port 23/206 */ + GPIO_FN(SCIFA5_SCK_PORT206), + + /* SCIFA6 */ + GPIO_FN(SCIFA6_SCK), GPIO_FN(SCIFA6_RXD), GPIO_FN(SCIFA6_TXD), + + /* SCIFA7 */ + GPIO_FN(SCIFA7_TXD), GPIO_FN(SCIFA7_RXD), + + /* SCIFAB */ + GPIO_FN(SCIFB_SCK_PORT190), /* MSEL5CR_17_0 */ + GPIO_FN(SCIFB_RXD_PORT191), + GPIO_FN(SCIFB_TXD_PORT192), + GPIO_FN(SCIFB_RTS_PORT186), + GPIO_FN(SCIFB_CTS_PORT187), + + GPIO_FN(SCIFB_SCK_PORT2), /* MSEL5CR_17_1 */ + GPIO_FN(SCIFB_RXD_PORT3), + GPIO_FN(SCIFB_TXD_PORT4), + GPIO_FN(SCIFB_RTS_PORT172), + GPIO_FN(SCIFB_CTS_PORT173), + + /* LCD0 */ + GPIO_FN(LCD0_D0), GPIO_FN(LCD0_D1), GPIO_FN(LCD0_D2), + GPIO_FN(LCD0_D3), GPIO_FN(LCD0_D4), GPIO_FN(LCD0_D5), + GPIO_FN(LCD0_D6), GPIO_FN(LCD0_D7), GPIO_FN(LCD0_D8), + GPIO_FN(LCD0_D9), GPIO_FN(LCD0_D10), GPIO_FN(LCD0_D11), + GPIO_FN(LCD0_D12), GPIO_FN(LCD0_D13), GPIO_FN(LCD0_D14), + GPIO_FN(LCD0_D15), GPIO_FN(LCD0_D16), GPIO_FN(LCD0_D17), + GPIO_FN(LCD0_DON), GPIO_FN(LCD0_VCPWC), GPIO_FN(LCD0_VEPWC), + GPIO_FN(LCD0_DCK), GPIO_FN(LCD0_VSYN), + GPIO_FN(LCD0_HSYN), GPIO_FN(LCD0_DISP), + GPIO_FN(LCD0_WR), GPIO_FN(LCD0_RD), + GPIO_FN(LCD0_CS), GPIO_FN(LCD0_RS), + + GPIO_FN(LCD0_D18_PORT163), GPIO_FN(LCD0_D19_PORT162), + GPIO_FN(LCD0_D20_PORT161), GPIO_FN(LCD0_D21_PORT158), + GPIO_FN(LCD0_D22_PORT160), GPIO_FN(LCD0_D23_PORT159), + GPIO_FN(LCD0_LCLK_PORT165), /* MSEL5CR_6_1 */ + + GPIO_FN(LCD0_D18_PORT40), GPIO_FN(LCD0_D19_PORT4), + GPIO_FN(LCD0_D20_PORT3), GPIO_FN(LCD0_D21_PORT2), + GPIO_FN(LCD0_D22_PORT0), GPIO_FN(LCD0_D23_PORT1), + GPIO_FN(LCD0_LCLK_PORT102), /* MSEL5CR_6_0 */ + + /* LCD1 */ + GPIO_FN(LCD1_D0), GPIO_FN(LCD1_D1), GPIO_FN(LCD1_D2), + GPIO_FN(LCD1_D3), GPIO_FN(LCD1_D4), GPIO_FN(LCD1_D5), + GPIO_FN(LCD1_D6), GPIO_FN(LCD1_D7), GPIO_FN(LCD1_D8), + GPIO_FN(LCD1_D9), GPIO_FN(LCD1_D10), GPIO_FN(LCD1_D11), + GPIO_FN(LCD1_D12), GPIO_FN(LCD1_D13), GPIO_FN(LCD1_D14), + GPIO_FN(LCD1_D15), GPIO_FN(LCD1_D16), GPIO_FN(LCD1_D17), + GPIO_FN(LCD1_D18), GPIO_FN(LCD1_D19), GPIO_FN(LCD1_D20), + GPIO_FN(LCD1_D21), GPIO_FN(LCD1_D22), GPIO_FN(LCD1_D23), + GPIO_FN(LCD1_RS), GPIO_FN(LCD1_RD), GPIO_FN(LCD1_CS), + GPIO_FN(LCD1_WR), GPIO_FN(LCD1_DCK), GPIO_FN(LCD1_DON), + GPIO_FN(LCD1_VCPWC), GPIO_FN(LCD1_LCLK), GPIO_FN(LCD1_HSYN), + GPIO_FN(LCD1_VSYN), GPIO_FN(LCD1_VEPWC), GPIO_FN(LCD1_DISP), + + /* RSPI */ + GPIO_FN(RSPI_SSL0_A), GPIO_FN(RSPI_SSL1_A), GPIO_FN(RSPI_SSL2_A), + GPIO_FN(RSPI_SSL3_A), GPIO_FN(RSPI_CK_A), GPIO_FN(RSPI_MOSI_A), + GPIO_FN(RSPI_MISO_A), + + /* VIO CKO */ + GPIO_FN(VIO_CKO1), + GPIO_FN(VIO_CKO2), + GPIO_FN(VIO_CKO_1), + GPIO_FN(VIO_CKO), + + /* VIO0 */ + GPIO_FN(VIO0_D0), GPIO_FN(VIO0_D1), GPIO_FN(VIO0_D2), + GPIO_FN(VIO0_D3), GPIO_FN(VIO0_D4), GPIO_FN(VIO0_D5), + GPIO_FN(VIO0_D6), GPIO_FN(VIO0_D7), GPIO_FN(VIO0_D8), + GPIO_FN(VIO0_D9), GPIO_FN(VIO0_D10), GPIO_FN(VIO0_D11), + GPIO_FN(VIO0_D12), GPIO_FN(VIO0_VD), GPIO_FN(VIO0_HD), + GPIO_FN(VIO0_CLK), GPIO_FN(VIO0_FIELD), + + GPIO_FN(VIO0_D13_PORT26), /* MSEL5CR_27_0 */ + GPIO_FN(VIO0_D14_PORT25), + GPIO_FN(VIO0_D15_PORT24), + + GPIO_FN(VIO0_D13_PORT22), /* MSEL5CR_27_1 */ + GPIO_FN(VIO0_D14_PORT95), + GPIO_FN(VIO0_D15_PORT96), + + /* VIO1 */ + GPIO_FN(VIO1_D0), GPIO_FN(VIO1_D1), GPIO_FN(VIO1_D2), + GPIO_FN(VIO1_D3), GPIO_FN(VIO1_D4), GPIO_FN(VIO1_D5), + GPIO_FN(VIO1_D6), GPIO_FN(VIO1_D7), GPIO_FN(VIO1_VD), + GPIO_FN(VIO1_HD), GPIO_FN(VIO1_CLK), GPIO_FN(VIO1_FIELD), + + /* TPU0 */ + GPIO_FN(TPU0TO0), GPIO_FN(TPU0TO1), GPIO_FN(TPU0TO3), + GPIO_FN(TPU0TO2_PORT66), /* TPU0TO2 Port 66/202 */ + GPIO_FN(TPU0TO2_PORT202), + + /* SSP1 0 */ + GPIO_FN(STP0_IPD0), GPIO_FN(STP0_IPD1), GPIO_FN(STP0_IPD2), + GPIO_FN(STP0_IPD3), GPIO_FN(STP0_IPD4), GPIO_FN(STP0_IPD5), + GPIO_FN(STP0_IPD6), GPIO_FN(STP0_IPD7), GPIO_FN(STP0_IPEN), + GPIO_FN(STP0_IPCLK), GPIO_FN(STP0_IPSYNC), + + /* SSP1 1 */ + GPIO_FN(STP1_IPD1), GPIO_FN(STP1_IPD2), GPIO_FN(STP1_IPD3), + GPIO_FN(STP1_IPD4), GPIO_FN(STP1_IPD5), GPIO_FN(STP1_IPD6), + GPIO_FN(STP1_IPD7), GPIO_FN(STP1_IPCLK), GPIO_FN(STP1_IPSYNC), + + GPIO_FN(STP1_IPD0_PORT186), /* MSEL5CR_23_0 */ + GPIO_FN(STP1_IPEN_PORT187), + + GPIO_FN(STP1_IPD0_PORT194), /* MSEL5CR_23_1 */ + GPIO_FN(STP1_IPEN_PORT193), + + /* SIM */ + GPIO_FN(SIM_RST), GPIO_FN(SIM_CLK), + GPIO_FN(SIM_D_PORT22), /* SIM_D Port 22/199 */ + GPIO_FN(SIM_D_PORT199), + + /* SDHI0 */ + GPIO_FN(SDHI0_D0), GPIO_FN(SDHI0_D1), GPIO_FN(SDHI0_D2), + GPIO_FN(SDHI0_D3), GPIO_FN(SDHI0_CD), GPIO_FN(SDHI0_WP), + GPIO_FN(SDHI0_CMD), GPIO_FN(SDHI0_CLK), + + /* SDHI1 */ + GPIO_FN(SDHI1_D0), GPIO_FN(SDHI1_D1), GPIO_FN(SDHI1_D2), + GPIO_FN(SDHI1_D3), GPIO_FN(SDHI1_CD), GPIO_FN(SDHI1_WP), + GPIO_FN(SDHI1_CMD), GPIO_FN(SDHI1_CLK), + + /* SDHI2 */ + GPIO_FN(SDHI2_D0), GPIO_FN(SDHI2_D1), GPIO_FN(SDHI2_D2), + GPIO_FN(SDHI2_D3), GPIO_FN(SDHI2_CLK), GPIO_FN(SDHI2_CMD), + + GPIO_FN(SDHI2_CD_PORT24), /* MSEL5CR_19_0 */ + GPIO_FN(SDHI2_WP_PORT25), + + GPIO_FN(SDHI2_WP_PORT177), /* MSEL5CR_19_1 */ + GPIO_FN(SDHI2_CD_PORT202), + + /* MSIOF2 */ + GPIO_FN(MSIOF2_TXD), GPIO_FN(MSIOF2_RXD), GPIO_FN(MSIOF2_TSCK), + GPIO_FN(MSIOF2_SS2), GPIO_FN(MSIOF2_TSYNC), GPIO_FN(MSIOF2_SS1), + GPIO_FN(MSIOF2_MCK1), GPIO_FN(MSIOF2_MCK0), GPIO_FN(MSIOF2_RSYNC), + GPIO_FN(MSIOF2_RSCK), + + /* KEYSC */ + GPIO_FN(KEYIN4), GPIO_FN(KEYIN5), + GPIO_FN(KEYIN6), GPIO_FN(KEYIN7), + GPIO_FN(KEYOUT0), GPIO_FN(KEYOUT1), GPIO_FN(KEYOUT2), + GPIO_FN(KEYOUT3), GPIO_FN(KEYOUT4), GPIO_FN(KEYOUT5), + GPIO_FN(KEYOUT6), GPIO_FN(KEYOUT7), + + GPIO_FN(KEYIN0_PORT43), /* MSEL4CR_18_0 */ + GPIO_FN(KEYIN1_PORT44), + GPIO_FN(KEYIN2_PORT45), + GPIO_FN(KEYIN3_PORT46), + + GPIO_FN(KEYIN0_PORT58), /* MSEL4CR_18_1 */ + GPIO_FN(KEYIN1_PORT57), + GPIO_FN(KEYIN2_PORT56), + GPIO_FN(KEYIN3_PORT55), + + /* VOU */ + GPIO_FN(DV_D0), GPIO_FN(DV_D1), GPIO_FN(DV_D2), + GPIO_FN(DV_D3), GPIO_FN(DV_D4), GPIO_FN(DV_D5), + GPIO_FN(DV_D6), GPIO_FN(DV_D7), GPIO_FN(DV_D8), + GPIO_FN(DV_D9), GPIO_FN(DV_D10), GPIO_FN(DV_D11), + GPIO_FN(DV_D12), GPIO_FN(DV_D13), GPIO_FN(DV_D14), + GPIO_FN(DV_D15), GPIO_FN(DV_CLK), + GPIO_FN(DV_VSYNC), GPIO_FN(DV_HSYNC), + + /* MEMC */ + GPIO_FN(MEMC_AD0), GPIO_FN(MEMC_AD1), GPIO_FN(MEMC_AD2), + GPIO_FN(MEMC_AD3), GPIO_FN(MEMC_AD4), GPIO_FN(MEMC_AD5), + GPIO_FN(MEMC_AD6), GPIO_FN(MEMC_AD7), GPIO_FN(MEMC_AD8), + GPIO_FN(MEMC_AD9), GPIO_FN(MEMC_AD10), GPIO_FN(MEMC_AD11), + GPIO_FN(MEMC_AD12), GPIO_FN(MEMC_AD13), GPIO_FN(MEMC_AD14), + GPIO_FN(MEMC_AD15), GPIO_FN(MEMC_CS0), GPIO_FN(MEMC_INT), + GPIO_FN(MEMC_NWE), GPIO_FN(MEMC_NOE), GPIO_FN(MEMC_CS1), + GPIO_FN(MEMC_A1), GPIO_FN(MEMC_ADV), GPIO_FN(MEMC_DREQ0), + GPIO_FN(MEMC_WAIT), GPIO_FN(MEMC_DREQ1), GPIO_FN(MEMC_BUSCLK), + GPIO_FN(MEMC_A0), + + /* MMC */ + GPIO_FN(MMC0_D0_PORT68), GPIO_FN(MMC0_D1_PORT69), + GPIO_FN(MMC0_D2_PORT70), GPIO_FN(MMC0_D3_PORT71), + GPIO_FN(MMC0_D4_PORT72), GPIO_FN(MMC0_D5_PORT73), + GPIO_FN(MMC0_D6_PORT74), GPIO_FN(MMC0_D7_PORT75), + GPIO_FN(MMC0_CLK_PORT66), + GPIO_FN(MMC0_CMD_PORT67), /* MSEL4CR_15_0 */ + + GPIO_FN(MMC1_D0_PORT149), GPIO_FN(MMC1_D1_PORT148), + GPIO_FN(MMC1_D2_PORT147), GPIO_FN(MMC1_D3_PORT146), + GPIO_FN(MMC1_D4_PORT145), GPIO_FN(MMC1_D5_PORT144), + GPIO_FN(MMC1_D6_PORT143), GPIO_FN(MMC1_D7_PORT142), + GPIO_FN(MMC1_CLK_PORT103), + GPIO_FN(MMC1_CMD_PORT104), /* MSEL4CR_15_1 */ + + /* MSIOF0 */ + GPIO_FN(MSIOF0_SS1), GPIO_FN(MSIOF0_SS2), GPIO_FN(MSIOF0_RXD), + GPIO_FN(MSIOF0_TXD), GPIO_FN(MSIOF0_MCK0), GPIO_FN(MSIOF0_MCK1), + GPIO_FN(MSIOF0_RSYNC), GPIO_FN(MSIOF0_RSCK), GPIO_FN(MSIOF0_TSCK), + GPIO_FN(MSIOF0_TSYNC), + + /* MSIOF1 */ + GPIO_FN(MSIOF1_RSCK), GPIO_FN(MSIOF1_RSYNC), + GPIO_FN(MSIOF1_MCK0), GPIO_FN(MSIOF1_MCK1), + + GPIO_FN(MSIOF1_SS2_PORT116), GPIO_FN(MSIOF1_SS1_PORT117), + GPIO_FN(MSIOF1_RXD_PORT118), GPIO_FN(MSIOF1_TXD_PORT119), + GPIO_FN(MSIOF1_TSYNC_PORT120), + GPIO_FN(MSIOF1_TSCK_PORT121), /* MSEL4CR_10_0 */ + + GPIO_FN(MSIOF1_SS1_PORT67), GPIO_FN(MSIOF1_TSCK_PORT72), + GPIO_FN(MSIOF1_TSYNC_PORT73), GPIO_FN(MSIOF1_TXD_PORT74), + GPIO_FN(MSIOF1_RXD_PORT75), + GPIO_FN(MSIOF1_SS2_PORT202), /* MSEL4CR_10_1 */ + + /* GPIO */ + GPIO_FN(GPO0), GPIO_FN(GPI0), + GPIO_FN(GPO1), GPIO_FN(GPI1), + + /* USB0 */ + GPIO_FN(USB0_OCI), GPIO_FN(USB0_PPON), GPIO_FN(VBUS), + + /* USB1 */ + GPIO_FN(USB1_OCI), GPIO_FN(USB1_PPON), + + /* BBIF1 */ + GPIO_FN(BBIF1_RXD), GPIO_FN(BBIF1_TXD), GPIO_FN(BBIF1_TSYNC), + GPIO_FN(BBIF1_TSCK), GPIO_FN(BBIF1_RSCK), GPIO_FN(BBIF1_RSYNC), + GPIO_FN(BBIF1_FLOW), GPIO_FN(BBIF1_RX_FLOW_N), + + /* BBIF2 */ + GPIO_FN(BBIF2_TXD2_PORT5), /* MSEL5CR_0_0 */ + GPIO_FN(BBIF2_RXD2_PORT60), + GPIO_FN(BBIF2_TSYNC2_PORT6), + GPIO_FN(BBIF2_TSCK2_PORT59), + + GPIO_FN(BBIF2_RXD2_PORT90), /* MSEL5CR_0_1 */ + GPIO_FN(BBIF2_TXD2_PORT183), + GPIO_FN(BBIF2_TSCK2_PORT89), + GPIO_FN(BBIF2_TSYNC2_PORT184), + + /* BSC / FLCTL / PCMCIA */ + GPIO_FN(CS0), GPIO_FN(CS2), GPIO_FN(CS4), + GPIO_FN(CS5B), GPIO_FN(CS6A), + GPIO_FN(CS5A_PORT105), /* CS5A PORT 19/105 */ + GPIO_FN(CS5A_PORT19), + GPIO_FN(IOIS16), /* ? */ + + GPIO_FN(A0), GPIO_FN(A1), GPIO_FN(A2), GPIO_FN(A3), + GPIO_FN(A4_FOE), GPIO_FN(A5_FCDE), /* share with FLCTL */ + GPIO_FN(A6), GPIO_FN(A7), GPIO_FN(A8), GPIO_FN(A9), + GPIO_FN(A10), GPIO_FN(A11), GPIO_FN(A12), GPIO_FN(A13), + GPIO_FN(A14), GPIO_FN(A15), GPIO_FN(A16), GPIO_FN(A17), + GPIO_FN(A18), GPIO_FN(A19), GPIO_FN(A20), GPIO_FN(A21), + GPIO_FN(A22), GPIO_FN(A23), GPIO_FN(A24), GPIO_FN(A25), + GPIO_FN(A26), + + GPIO_FN(D0_NAF0), GPIO_FN(D1_NAF1), /* share with FLCTL */ + GPIO_FN(D2_NAF2), GPIO_FN(D3_NAF3), /* share with FLCTL */ + GPIO_FN(D4_NAF4), GPIO_FN(D5_NAF5), /* share with FLCTL */ + GPIO_FN(D6_NAF6), GPIO_FN(D7_NAF7), /* share with FLCTL */ + GPIO_FN(D8_NAF8), GPIO_FN(D9_NAF9), /* share with FLCTL */ + GPIO_FN(D10_NAF10), GPIO_FN(D11_NAF11), /* share with FLCTL */ + GPIO_FN(D12_NAF12), GPIO_FN(D13_NAF13), /* share with FLCTL */ + GPIO_FN(D14_NAF14), GPIO_FN(D15_NAF15), /* share with FLCTL */ + GPIO_FN(D16), GPIO_FN(D17), GPIO_FN(D18), GPIO_FN(D19), + GPIO_FN(D20), GPIO_FN(D21), GPIO_FN(D22), GPIO_FN(D23), + GPIO_FN(D24), GPIO_FN(D25), GPIO_FN(D26), GPIO_FN(D27), + GPIO_FN(D28), GPIO_FN(D29), GPIO_FN(D30), GPIO_FN(D31), + + GPIO_FN(WE0_FWE), /* share with FLCTL */ + GPIO_FN(WE1), + GPIO_FN(WE2_ICIORD), /* share with PCMCIA */ + GPIO_FN(WE3_ICIOWR), /* share with PCMCIA */ + GPIO_FN(CKO), GPIO_FN(BS), GPIO_FN(RDWR), + GPIO_FN(RD_FSC), /* share with FLCTL */ + GPIO_FN(WAIT_PORT177), /* WAIT Port 90/177 */ + GPIO_FN(WAIT_PORT90), + + GPIO_FN(FCE0), GPIO_FN(FCE1), GPIO_FN(FRB), /* FLCTL */ + + /* IRDA */ + GPIO_FN(IRDA_FIRSEL), GPIO_FN(IRDA_IN), GPIO_FN(IRDA_OUT), + + /* ATAPI */ + GPIO_FN(IDE_D0), GPIO_FN(IDE_D1), GPIO_FN(IDE_D2), + GPIO_FN(IDE_D3), GPIO_FN(IDE_D4), GPIO_FN(IDE_D5), + GPIO_FN(IDE_D6), GPIO_FN(IDE_D7), GPIO_FN(IDE_D8), + GPIO_FN(IDE_D9), GPIO_FN(IDE_D10), GPIO_FN(IDE_D11), + GPIO_FN(IDE_D12), GPIO_FN(IDE_D13), GPIO_FN(IDE_D14), + GPIO_FN(IDE_D15), GPIO_FN(IDE_A0), GPIO_FN(IDE_A1), + GPIO_FN(IDE_A2), GPIO_FN(IDE_CS0), GPIO_FN(IDE_CS1), + GPIO_FN(IDE_IOWR), GPIO_FN(IDE_IORD), GPIO_FN(IDE_IORDY), + GPIO_FN(IDE_INT), GPIO_FN(IDE_RST), GPIO_FN(IDE_DIRECTION), + GPIO_FN(IDE_EXBUF_ENB), GPIO_FN(IDE_IODACK), GPIO_FN(IDE_IODREQ), + + /* RMII */ + GPIO_FN(RMII_CRS_DV), GPIO_FN(RMII_RX_ER), GPIO_FN(RMII_RXD0), + GPIO_FN(RMII_RXD1), GPIO_FN(RMII_TX_EN), GPIO_FN(RMII_TXD0), + GPIO_FN(RMII_MDC), GPIO_FN(RMII_TXD1), GPIO_FN(RMII_MDIO), + GPIO_FN(RMII_REF50CK), GPIO_FN(RMII_REF125CK), /* for GMII */ + + /* GEther */ + GPIO_FN(ET_TX_CLK), GPIO_FN(ET_TX_EN), GPIO_FN(ET_ETXD0), + GPIO_FN(ET_ETXD1), GPIO_FN(ET_ETXD2), GPIO_FN(ET_ETXD3), + GPIO_FN(ET_ETXD4), GPIO_FN(ET_ETXD5), /* for GEther */ + GPIO_FN(ET_ETXD6), GPIO_FN(ET_ETXD7), /* for GEther */ + GPIO_FN(ET_COL), GPIO_FN(ET_TX_ER), GPIO_FN(ET_RX_CLK), + GPIO_FN(ET_RX_DV), GPIO_FN(ET_ERXD0), GPIO_FN(ET_ERXD1), + GPIO_FN(ET_ERXD2), GPIO_FN(ET_ERXD3), + GPIO_FN(ET_ERXD4), GPIO_FN(ET_ERXD5), /* for GEther */ + GPIO_FN(ET_ERXD6), GPIO_FN(ET_ERXD7), /* for GEther */ + GPIO_FN(ET_RX_ER), GPIO_FN(ET_CRS), GPIO_FN(ET_MDC), + GPIO_FN(ET_MDIO), GPIO_FN(ET_LINK), GPIO_FN(ET_PHY_INT), + GPIO_FN(ET_WOL), GPIO_FN(ET_GTX_CLK), + + /* DMA0 */ + GPIO_FN(DREQ0), GPIO_FN(DACK0), + + /* DMA1 */ + GPIO_FN(DREQ1), GPIO_FN(DACK1), + + /* SYSC */ + GPIO_FN(RESETOUTS), + + /* IRREM */ + GPIO_FN(IROUT), + + /* LCDC */ + GPIO_FN(LCDC0_SELECT), + GPIO_FN(LCDC1_SELECT), + + /* SDENC */ + GPIO_FN(SDENC_CPG), + GPIO_FN(SDENC_DV_CLKI), + + /* SYSC */ + GPIO_FN(RESETP_PULLUP), + GPIO_FN(RESETP_PLAIN), + + /* DEBUG */ + GPIO_FN(EDEBGREQ_PULLDOWN), + GPIO_FN(EDEBGREQ_PULLUP), + + GPIO_FN(TRACEAUD_FROM_VIO), + GPIO_FN(TRACEAUD_FROM_LCDC0), + GPIO_FN(TRACEAUD_FROM_MEMC), +}; + +static struct pinmux_cfg_reg pinmux_config_regs[] = { + PORTCR(0, 0xe6050000), /* PORT0CR */ + PORTCR(1, 0xe6050001), /* PORT1CR */ + PORTCR(2, 0xe6050002), /* PORT2CR */ + PORTCR(3, 0xe6050003), /* PORT3CR */ + PORTCR(4, 0xe6050004), /* PORT4CR */ + PORTCR(5, 0xe6050005), /* PORT5CR */ + PORTCR(6, 0xe6050006), /* PORT6CR */ + PORTCR(7, 0xe6050007), /* PORT7CR */ + PORTCR(8, 0xe6050008), /* PORT8CR */ + PORTCR(9, 0xe6050009), /* PORT9CR */ + PORTCR(10, 0xe605000a), /* PORT10CR */ + PORTCR(11, 0xe605000b), /* PORT11CR */ + PORTCR(12, 0xe605000c), /* PORT12CR */ + PORTCR(13, 0xe605000d), /* PORT13CR */ + PORTCR(14, 0xe605000e), /* PORT14CR */ + PORTCR(15, 0xe605000f), /* PORT15CR */ + PORTCR(16, 0xe6050010), /* PORT16CR */ + PORTCR(17, 0xe6050011), /* PORT17CR */ + PORTCR(18, 0xe6050012), /* PORT18CR */ + PORTCR(19, 0xe6050013), /* PORT19CR */ + PORTCR(20, 0xe6050014), /* PORT20CR */ + PORTCR(21, 0xe6050015), /* PORT21CR */ + PORTCR(22, 0xe6050016), /* PORT22CR */ + PORTCR(23, 0xe6050017), /* PORT23CR */ + PORTCR(24, 0xe6050018), /* PORT24CR */ + PORTCR(25, 0xe6050019), /* PORT25CR */ + PORTCR(26, 0xe605001a), /* PORT26CR */ + PORTCR(27, 0xe605001b), /* PORT27CR */ + PORTCR(28, 0xe605001c), /* PORT28CR */ + PORTCR(29, 0xe605001d), /* PORT29CR */ + PORTCR(30, 0xe605001e), /* PORT30CR */ + PORTCR(31, 0xe605001f), /* PORT31CR */ + PORTCR(32, 0xe6050020), /* PORT32CR */ + PORTCR(33, 0xe6050021), /* PORT33CR */ + PORTCR(34, 0xe6050022), /* PORT34CR */ + PORTCR(35, 0xe6050023), /* PORT35CR */ + PORTCR(36, 0xe6050024), /* PORT36CR */ + PORTCR(37, 0xe6050025), /* PORT37CR */ + PORTCR(38, 0xe6050026), /* PORT38CR */ + PORTCR(39, 0xe6050027), /* PORT39CR */ + PORTCR(40, 0xe6050028), /* PORT40CR */ + PORTCR(41, 0xe6050029), /* PORT41CR */ + PORTCR(42, 0xe605002a), /* PORT42CR */ + PORTCR(43, 0xe605002b), /* PORT43CR */ + PORTCR(44, 0xe605002c), /* PORT44CR */ + PORTCR(45, 0xe605002d), /* PORT45CR */ + PORTCR(46, 0xe605002e), /* PORT46CR */ + PORTCR(47, 0xe605002f), /* PORT47CR */ + PORTCR(48, 0xe6050030), /* PORT48CR */ + PORTCR(49, 0xe6050031), /* PORT49CR */ + PORTCR(50, 0xe6050032), /* PORT50CR */ + PORTCR(51, 0xe6050033), /* PORT51CR */ + PORTCR(52, 0xe6050034), /* PORT52CR */ + PORTCR(53, 0xe6050035), /* PORT53CR */ + PORTCR(54, 0xe6050036), /* PORT54CR */ + PORTCR(55, 0xe6050037), /* PORT55CR */ + PORTCR(56, 0xe6050038), /* PORT56CR */ + PORTCR(57, 0xe6050039), /* PORT57CR */ + PORTCR(58, 0xe605003a), /* PORT58CR */ + PORTCR(59, 0xe605003b), /* PORT59CR */ + PORTCR(60, 0xe605003c), /* PORT60CR */ + PORTCR(61, 0xe605003d), /* PORT61CR */ + PORTCR(62, 0xe605003e), /* PORT62CR */ + PORTCR(63, 0xe605003f), /* PORT63CR */ + PORTCR(64, 0xe6050040), /* PORT64CR */ + PORTCR(65, 0xe6050041), /* PORT65CR */ + PORTCR(66, 0xe6050042), /* PORT66CR */ + PORTCR(67, 0xe6050043), /* PORT67CR */ + PORTCR(68, 0xe6050044), /* PORT68CR */ + PORTCR(69, 0xe6050045), /* PORT69CR */ + PORTCR(70, 0xe6050046), /* PORT70CR */ + PORTCR(71, 0xe6050047), /* PORT71CR */ + PORTCR(72, 0xe6050048), /* PORT72CR */ + PORTCR(73, 0xe6050049), /* PORT73CR */ + PORTCR(74, 0xe605004a), /* PORT74CR */ + PORTCR(75, 0xe605004b), /* PORT75CR */ + PORTCR(76, 0xe605004c), /* PORT76CR */ + PORTCR(77, 0xe605004d), /* PORT77CR */ + PORTCR(78, 0xe605004e), /* PORT78CR */ + PORTCR(79, 0xe605004f), /* PORT79CR */ + PORTCR(80, 0xe6050050), /* PORT80CR */ + PORTCR(81, 0xe6050051), /* PORT81CR */ + PORTCR(82, 0xe6050052), /* PORT82CR */ + PORTCR(83, 0xe6050053), /* PORT83CR */ + + PORTCR(84, 0xe6051054), /* PORT84CR */ + PORTCR(85, 0xe6051055), /* PORT85CR */ + PORTCR(86, 0xe6051056), /* PORT86CR */ + PORTCR(87, 0xe6051057), /* PORT87CR */ + PORTCR(88, 0xe6051058), /* PORT88CR */ + PORTCR(89, 0xe6051059), /* PORT89CR */ + PORTCR(90, 0xe605105a), /* PORT90CR */ + PORTCR(91, 0xe605105b), /* PORT91CR */ + PORTCR(92, 0xe605105c), /* PORT92CR */ + PORTCR(93, 0xe605105d), /* PORT93CR */ + PORTCR(94, 0xe605105e), /* PORT94CR */ + PORTCR(95, 0xe605105f), /* PORT95CR */ + PORTCR(96, 0xe6051060), /* PORT96CR */ + PORTCR(97, 0xe6051061), /* PORT97CR */ + PORTCR(98, 0xe6051062), /* PORT98CR */ + PORTCR(99, 0xe6051063), /* PORT99CR */ + PORTCR(100, 0xe6051064), /* PORT100CR */ + PORTCR(101, 0xe6051065), /* PORT101CR */ + PORTCR(102, 0xe6051066), /* PORT102CR */ + PORTCR(103, 0xe6051067), /* PORT103CR */ + PORTCR(104, 0xe6051068), /* PORT104CR */ + PORTCR(105, 0xe6051069), /* PORT105CR */ + PORTCR(106, 0xe605106a), /* PORT106CR */ + PORTCR(107, 0xe605106b), /* PORT107CR */ + PORTCR(108, 0xe605106c), /* PORT108CR */ + PORTCR(109, 0xe605106d), /* PORT109CR */ + PORTCR(110, 0xe605106e), /* PORT110CR */ + PORTCR(111, 0xe605106f), /* PORT111CR */ + PORTCR(112, 0xe6051070), /* PORT112CR */ + PORTCR(113, 0xe6051071), /* PORT113CR */ + PORTCR(114, 0xe6051072), /* PORT114CR */ + + PORTCR(115, 0xe6052073), /* PORT115CR */ + PORTCR(116, 0xe6052074), /* PORT116CR */ + PORTCR(117, 0xe6052075), /* PORT117CR */ + PORTCR(118, 0xe6052076), /* PORT118CR */ + PORTCR(119, 0xe6052077), /* PORT119CR */ + PORTCR(120, 0xe6052078), /* PORT120CR */ + PORTCR(121, 0xe6052079), /* PORT121CR */ + PORTCR(122, 0xe605207a), /* PORT122CR */ + PORTCR(123, 0xe605207b), /* PORT123CR */ + PORTCR(124, 0xe605207c), /* PORT124CR */ + PORTCR(125, 0xe605207d), /* PORT125CR */ + PORTCR(126, 0xe605207e), /* PORT126CR */ + PORTCR(127, 0xe605207f), /* PORT127CR */ + PORTCR(128, 0xe6052080), /* PORT128CR */ + PORTCR(129, 0xe6052081), /* PORT129CR */ + PORTCR(130, 0xe6052082), /* PORT130CR */ + PORTCR(131, 0xe6052083), /* PORT131CR */ + PORTCR(132, 0xe6052084), /* PORT132CR */ + PORTCR(133, 0xe6052085), /* PORT133CR */ + PORTCR(134, 0xe6052086), /* PORT134CR */ + PORTCR(135, 0xe6052087), /* PORT135CR */ + PORTCR(136, 0xe6052088), /* PORT136CR */ + PORTCR(137, 0xe6052089), /* PORT137CR */ + PORTCR(138, 0xe605208a), /* PORT138CR */ + PORTCR(139, 0xe605208b), /* PORT139CR */ + PORTCR(140, 0xe605208c), /* PORT140CR */ + PORTCR(141, 0xe605208d), /* PORT141CR */ + PORTCR(142, 0xe605208e), /* PORT142CR */ + PORTCR(143, 0xe605208f), /* PORT143CR */ + PORTCR(144, 0xe6052090), /* PORT144CR */ + PORTCR(145, 0xe6052091), /* PORT145CR */ + PORTCR(146, 0xe6052092), /* PORT146CR */ + PORTCR(147, 0xe6052093), /* PORT147CR */ + PORTCR(148, 0xe6052094), /* PORT148CR */ + PORTCR(149, 0xe6052095), /* PORT149CR */ + PORTCR(150, 0xe6052096), /* PORT150CR */ + PORTCR(151, 0xe6052097), /* PORT151CR */ + PORTCR(152, 0xe6052098), /* PORT152CR */ + PORTCR(153, 0xe6052099), /* PORT153CR */ + PORTCR(154, 0xe605209a), /* PORT154CR */ + PORTCR(155, 0xe605209b), /* PORT155CR */ + PORTCR(156, 0xe605209c), /* PORT156CR */ + PORTCR(157, 0xe605209d), /* PORT157CR */ + PORTCR(158, 0xe605209e), /* PORT158CR */ + PORTCR(159, 0xe605209f), /* PORT159CR */ + PORTCR(160, 0xe60520a0), /* PORT160CR */ + PORTCR(161, 0xe60520a1), /* PORT161CR */ + PORTCR(162, 0xe60520a2), /* PORT162CR */ + PORTCR(163, 0xe60520a3), /* PORT163CR */ + PORTCR(164, 0xe60520a4), /* PORT164CR */ + PORTCR(165, 0xe60520a5), /* PORT165CR */ + PORTCR(166, 0xe60520a6), /* PORT166CR */ + PORTCR(167, 0xe60520a7), /* PORT167CR */ + PORTCR(168, 0xe60520a8), /* PORT168CR */ + PORTCR(169, 0xe60520a9), /* PORT169CR */ + PORTCR(170, 0xe60520aa), /* PORT170CR */ + PORTCR(171, 0xe60520ab), /* PORT171CR */ + PORTCR(172, 0xe60520ac), /* PORT172CR */ + PORTCR(173, 0xe60520ad), /* PORT173CR */ + PORTCR(174, 0xe60520ae), /* PORT174CR */ + PORTCR(175, 0xe60520af), /* PORT175CR */ + PORTCR(176, 0xe60520b0), /* PORT176CR */ + PORTCR(177, 0xe60520b1), /* PORT177CR */ + PORTCR(178, 0xe60520b2), /* PORT178CR */ + PORTCR(179, 0xe60520b3), /* PORT179CR */ + PORTCR(180, 0xe60520b4), /* PORT180CR */ + PORTCR(181, 0xe60520b5), /* PORT181CR */ + PORTCR(182, 0xe60520b6), /* PORT182CR */ + PORTCR(183, 0xe60520b7), /* PORT183CR */ + PORTCR(184, 0xe60520b8), /* PORT184CR */ + PORTCR(185, 0xe60520b9), /* PORT185CR */ + PORTCR(186, 0xe60520ba), /* PORT186CR */ + PORTCR(187, 0xe60520bb), /* PORT187CR */ + PORTCR(188, 0xe60520bc), /* PORT188CR */ + PORTCR(189, 0xe60520bd), /* PORT189CR */ + PORTCR(190, 0xe60520be), /* PORT190CR */ + PORTCR(191, 0xe60520bf), /* PORT191CR */ + PORTCR(192, 0xe60520c0), /* PORT192CR */ + PORTCR(193, 0xe60520c1), /* PORT193CR */ + PORTCR(194, 0xe60520c2), /* PORT194CR */ + PORTCR(195, 0xe60520c3), /* PORT195CR */ + PORTCR(196, 0xe60520c4), /* PORT196CR */ + PORTCR(197, 0xe60520c5), /* PORT197CR */ + PORTCR(198, 0xe60520c6), /* PORT198CR */ + PORTCR(199, 0xe60520c7), /* PORT199CR */ + PORTCR(200, 0xe60520c8), /* PORT200CR */ + PORTCR(201, 0xe60520c9), /* PORT201CR */ + PORTCR(202, 0xe60520ca), /* PORT202CR */ + PORTCR(203, 0xe60520cb), /* PORT203CR */ + PORTCR(204, 0xe60520cc), /* PORT204CR */ + PORTCR(205, 0xe60520cd), /* PORT205CR */ + PORTCR(206, 0xe60520ce), /* PORT206CR */ + PORTCR(207, 0xe60520cf), /* PORT207CR */ + PORTCR(208, 0xe60520d0), /* PORT208CR */ + PORTCR(209, 0xe60520d1), /* PORT209CR */ + + PORTCR(210, 0xe60530d2), /* PORT210CR */ + PORTCR(211, 0xe60530d3), /* PORT211CR */ + + { PINMUX_CFG_REG("MSEL1CR", 0xe605800c, 32, 1) { + MSEL1CR_31_0, MSEL1CR_31_1, + MSEL1CR_30_0, MSEL1CR_30_1, + MSEL1CR_29_0, MSEL1CR_29_1, + MSEL1CR_28_0, MSEL1CR_28_1, + MSEL1CR_27_0, MSEL1CR_27_1, + MSEL1CR_26_0, MSEL1CR_26_1, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + MSEL1CR_16_0, MSEL1CR_16_1, + MSEL1CR_15_0, MSEL1CR_15_1, + MSEL1CR_14_0, MSEL1CR_14_1, + MSEL1CR_13_0, MSEL1CR_13_1, + MSEL1CR_12_0, MSEL1CR_12_1, + 0, 0, 0, 0, + MSEL1CR_9_0, MSEL1CR_9_1, + 0, 0, + MSEL1CR_7_0, MSEL1CR_7_1, + MSEL1CR_6_0, MSEL1CR_6_1, + MSEL1CR_5_0, MSEL1CR_5_1, + MSEL1CR_4_0, MSEL1CR_4_1, + MSEL1CR_3_0, MSEL1CR_3_1, + MSEL1CR_2_0, MSEL1CR_2_1, + 0, 0, + MSEL1CR_0_0, MSEL1CR_0_1, + } + }, + { PINMUX_CFG_REG("MSEL3CR", 0xE6058020, 32, 1) { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + MSEL3CR_15_0, MSEL3CR_15_1, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + MSEL3CR_6_0, MSEL3CR_6_1, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, + } + }, + { PINMUX_CFG_REG("MSEL4CR", 0xE6058024, 32, 1) { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + MSEL4CR_19_0, MSEL4CR_19_1, + MSEL4CR_18_0, MSEL4CR_18_1, + 0, 0, 0, 0, + MSEL4CR_15_0, MSEL4CR_15_1, + 0, 0, 0, 0, 0, 0, 0, 0, + MSEL4CR_10_0, MSEL4CR_10_1, + 0, 0, 0, 0, 0, 0, + MSEL4CR_6_0, MSEL4CR_6_1, + 0, 0, + MSEL4CR_4_0, MSEL4CR_4_1, + 0, 0, 0, 0, + MSEL4CR_1_0, MSEL4CR_1_1, + 0, 0, + } + }, + { PINMUX_CFG_REG("MSEL5CR", 0xE6058028, 32, 1) { + MSEL5CR_31_0, MSEL5CR_31_1, + MSEL5CR_30_0, MSEL5CR_30_1, + MSEL5CR_29_0, MSEL5CR_29_1, + 0, 0, + MSEL5CR_27_0, MSEL5CR_27_1, + 0, 0, + MSEL5CR_25_0, MSEL5CR_25_1, + 0, 0, + MSEL5CR_23_0, MSEL5CR_23_1, + 0, 0, + MSEL5CR_21_0, MSEL5CR_21_1, + 0, 0, + MSEL5CR_19_0, MSEL5CR_19_1, + 0, 0, + MSEL5CR_17_0, MSEL5CR_17_1, + 0, 0, + MSEL5CR_15_0, MSEL5CR_15_1, + MSEL5CR_14_0, MSEL5CR_14_1, + MSEL5CR_13_0, MSEL5CR_13_1, + MSEL5CR_12_0, MSEL5CR_12_1, + MSEL5CR_11_0, MSEL5CR_11_1, + MSEL5CR_10_0, MSEL5CR_10_1, + 0, 0, + MSEL5CR_8_0, MSEL5CR_8_1, + MSEL5CR_7_0, MSEL5CR_7_1, + MSEL5CR_6_0, MSEL5CR_6_1, + MSEL5CR_5_0, MSEL5CR_5_1, + MSEL5CR_4_0, MSEL5CR_4_1, + MSEL5CR_3_0, MSEL5CR_3_1, + MSEL5CR_2_0, MSEL5CR_2_1, + 0, 0, + MSEL5CR_0_0, MSEL5CR_0_1, + } + }, + { }, +}; + +static struct pinmux_data_reg pinmux_data_regs[] = { + { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054800, 32) { + PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA, + PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA, + PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA, + PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA, + PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA, + PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA, + PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA, + PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA } + }, + { PINMUX_DATA_REG("PORTL063_032DR", 0xe6054804, 32) { + PORT63_DATA, PORT62_DATA, PORT61_DATA, PORT60_DATA, + PORT59_DATA, PORT58_DATA, PORT57_DATA, PORT56_DATA, + PORT55_DATA, PORT54_DATA, PORT53_DATA, PORT52_DATA, + PORT51_DATA, PORT50_DATA, PORT49_DATA, PORT48_DATA, + PORT47_DATA, PORT46_DATA, PORT45_DATA, PORT44_DATA, + PORT43_DATA, PORT42_DATA, PORT41_DATA, PORT40_DATA, + PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA, + PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA } + }, + { PINMUX_DATA_REG("PORTL095_064DR", 0xe6054808, 32) { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA, + PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA, + PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA, + PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA, + PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA } + }, + { PINMUX_DATA_REG("PORTD095_064DR", 0xe6055808, 32) { + PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA, + PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA, + PORT87_DATA, PORT86_DATA, PORT85_DATA, PORT84_DATA, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0 } + }, + { PINMUX_DATA_REG("PORTD127_096DR", 0xe605580c, 32) { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, PORT114_DATA, PORT113_DATA, PORT112_DATA, + PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA, + PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA, + PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA, + PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA } + }, + { PINMUX_DATA_REG("PORTR127_096DR", 0xe605680C, 32) { + PORT127_DATA, PORT126_DATA, PORT125_DATA, PORT124_DATA, + PORT123_DATA, PORT122_DATA, PORT121_DATA, PORT120_DATA, + PORT119_DATA, PORT118_DATA, PORT117_DATA, PORT116_DATA, + PORT115_DATA, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0 } + }, + { PINMUX_DATA_REG("PORTR159_128DR", 0xe6056810, 32) { + PORT159_DATA, PORT158_DATA, PORT157_DATA, PORT156_DATA, + PORT155_DATA, PORT154_DATA, PORT153_DATA, PORT152_DATA, + PORT151_DATA, PORT150_DATA, PORT149_DATA, PORT148_DATA, + PORT147_DATA, PORT146_DATA, PORT145_DATA, PORT144_DATA, + PORT143_DATA, PORT142_DATA, PORT141_DATA, PORT140_DATA, + PORT139_DATA, PORT138_DATA, PORT137_DATA, PORT136_DATA, + PORT135_DATA, PORT134_DATA, PORT133_DATA, PORT132_DATA, + PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA } + }, + { PINMUX_DATA_REG("PORTR191_160DR", 0xe6056814, 32) { + PORT191_DATA, PORT190_DATA, PORT189_DATA, PORT188_DATA, + PORT187_DATA, PORT186_DATA, PORT185_DATA, PORT184_DATA, + PORT183_DATA, PORT182_DATA, PORT181_DATA, PORT180_DATA, + PORT179_DATA, PORT178_DATA, PORT177_DATA, PORT176_DATA, + PORT175_DATA, PORT174_DATA, PORT173_DATA, PORT172_DATA, + PORT171_DATA, PORT170_DATA, PORT169_DATA, PORT168_DATA, + PORT167_DATA, PORT166_DATA, PORT165_DATA, PORT164_DATA, + PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA } + }, + { PINMUX_DATA_REG("PORTR223_192DR", 0xe6056818, 32) { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, PORT209_DATA, PORT208_DATA, + PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA, + PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA, + PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA, + PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA } + }, + { PINMUX_DATA_REG("PORTU223_192DR", 0xe6057818, 32) { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + PORT211_DATA, PORT210_DATA, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0 } + }, + { }, +}; + +static struct pinmux_info r8a7740_pinmux_info = { + .name = "r8a7740_pfc", + .reserved_id = PINMUX_RESERVED, + .data = { PINMUX_DATA_BEGIN, + PINMUX_DATA_END }, + .input = { PINMUX_INPUT_BEGIN, + PINMUX_INPUT_END }, + .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, + PINMUX_INPUT_PULLUP_END }, + .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, + PINMUX_INPUT_PULLDOWN_END }, + .output = { PINMUX_OUTPUT_BEGIN, + PINMUX_OUTPUT_END }, + .mark = { PINMUX_MARK_BEGIN, + PINMUX_MARK_END }, + .function = { PINMUX_FUNCTION_BEGIN, + PINMUX_FUNCTION_END }, + + .first_gpio = GPIO_PORT0, + .last_gpio = GPIO_FN_TRACEAUD_FROM_MEMC, + + .gpios = pinmux_gpios, + .cfg_regs = pinmux_config_regs, + .data_regs = pinmux_data_regs, + + .gpio_data = pinmux_data, + .gpio_data_size = ARRAY_SIZE(pinmux_data), +}; + +void r8a7740_pinmux_init(void) +{ + register_pinmux(&r8a7740_pinmux_info); +} diff --git a/arch/arm/mach-shmobile/pfc-r8a7779.c b/arch/arm/mach-shmobile/pfc-r8a7779.c new file mode 100644 index 00000000000..963532f2b2c --- /dev/null +++ b/arch/arm/mach-shmobile/pfc-r8a7779.c @@ -0,0 +1,2645 @@ +/* + * r8a7779 processor support - PFC hardware block + * + * Copyright (C) 2011 Renesas Solutions Corp. + * Copyright (C) 2011 Magnus Damm + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/gpio.h> +#include <linux/ioport.h> +#include <mach/r8a7779.h> + +#define CPU_32_PORT(fn, pfx, sfx) \ + PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ + PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx), \ + PORT_1(fn, pfx##31, sfx) + +#define CPU_32_PORT6(fn, pfx, sfx) \ + PORT_1(fn, pfx##0, sfx), PORT_1(fn, pfx##1, sfx), \ + PORT_1(fn, pfx##2, sfx), PORT_1(fn, pfx##3, sfx), \ + PORT_1(fn, pfx##4, sfx), PORT_1(fn, pfx##5, sfx), \ + PORT_1(fn, pfx##6, sfx), PORT_1(fn, pfx##7, sfx), \ + PORT_1(fn, pfx##8, sfx) + +#define CPU_ALL_PORT(fn, pfx, sfx) \ + CPU_32_PORT(fn, pfx##_0_, sfx), \ + CPU_32_PORT(fn, pfx##_1_, sfx), \ + CPU_32_PORT(fn, pfx##_2_, sfx), \ + CPU_32_PORT(fn, pfx##_3_, sfx), \ + CPU_32_PORT(fn, pfx##_4_, sfx), \ + CPU_32_PORT(fn, pfx##_5_, sfx), \ + CPU_32_PORT6(fn, pfx##_6_, sfx) + +#define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA) +#define _GP_DATA(pfx, sfx) PINMUX_DATA(GP##pfx##_DATA, GP##pfx##_FN, \ + GP##pfx##_IN, GP##pfx##_OUT) + +#define _GP_INOUTSEL(pfx, sfx) GP##pfx##_IN, GP##pfx##_OUT +#define _GP_INDT(pfx, sfx) GP##pfx##_DATA + +#define GP_ALL(str) CPU_ALL_PORT(_PORT_ALL, GP, str) +#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, , unused) +#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, , unused) + + +#define PORT_10_REV(fn, pfx, sfx) \ + PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx), \ + PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx), \ + PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx), \ + PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx), \ + PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx) + +#define CPU_32_PORT_REV(fn, pfx, sfx) \ + PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx), \ + PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx), \ + PORT_10_REV(fn, pfx, sfx) + +#define GP_INOUTSEL(bank) CPU_32_PORT_REV(_GP_INOUTSEL, _##bank##_, unused) +#define GP_INDT(bank) CPU_32_PORT_REV(_GP_INDT, _##bank##_, unused) + +#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn) +#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \ + FN_##ipsr, FN_##fn) + +enum { + PINMUX_RESERVED = 0, + + PINMUX_DATA_BEGIN, + GP_ALL(DATA), /* GP_0_0_DATA -> GP_6_8_DATA */ + PINMUX_DATA_END, + + PINMUX_INPUT_BEGIN, + GP_ALL(IN), /* GP_0_0_IN -> GP_6_8_IN */ + PINMUX_INPUT_END, + + PINMUX_OUTPUT_BEGIN, + GP_ALL(OUT), /* GP_0_0_OUT -> GP_6_8_OUT */ + PINMUX_OUTPUT_END, + + PINMUX_FUNCTION_BEGIN, + GP_ALL(FN), /* GP_0_0_FN -> GP_6_8_FN */ + + /* GPSR0 */ + FN_AVS1, FN_AVS2, FN_IP0_7_6, FN_A17, + FN_A18, FN_A19, FN_IP0_9_8, FN_IP0_11_10, + FN_IP0_13_12, FN_IP0_15_14, FN_IP0_18_16, FN_IP0_22_19, + FN_IP0_24_23, FN_IP0_25, FN_IP0_27_26, FN_IP1_1_0, + FN_IP1_3_2, FN_IP1_6_4, FN_IP1_10_7, FN_IP1_14_11, + FN_IP1_18_15, FN_IP0_5_3, FN_IP0_30_28, FN_IP2_18_16, + FN_IP2_21_19, FN_IP2_30_28, FN_IP3_2_0, FN_IP3_11_9, + FN_IP3_14_12, FN_IP3_22_21, FN_IP3_26_24, FN_IP3_31_29, + + /* GPSR1 */ + FN_IP4_1_0, FN_IP4_4_2, FN_IP4_7_5, FN_IP4_10_8, + FN_IP4_11, FN_IP4_12, FN_IP4_13, FN_IP4_14, + FN_IP4_15, FN_IP4_16, FN_IP4_19_17, FN_IP4_22_20, + FN_IP4_23, FN_IP4_24, FN_IP4_25, FN_IP4_26, + FN_IP4_27, FN_IP4_28, FN_IP4_31_29, FN_IP5_2_0, + FN_IP5_3, FN_IP5_4, FN_IP5_5, FN_IP5_6, + FN_IP5_7, FN_IP5_8, FN_IP5_10_9, FN_IP5_12_11, + FN_IP5_14_13, FN_IP5_16_15, FN_IP5_20_17, FN_IP5_23_21, + + /* GPSR2 */ + FN_IP5_27_24, FN_IP8_20, FN_IP8_22_21, FN_IP8_24_23, + FN_IP8_27_25, FN_IP8_30_28, FN_IP9_1_0, FN_IP9_3_2, + FN_IP9_4, FN_IP9_5, FN_IP9_6, FN_IP9_7, + FN_IP9_9_8, FN_IP9_11_10, FN_IP9_13_12, FN_IP9_15_14, + FN_IP9_18_16, FN_IP9_21_19, FN_IP9_23_22, FN_IP9_25_24, + FN_IP9_27_26, FN_IP9_29_28, FN_IP10_2_0, FN_IP10_5_3, + FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_17_15, + FN_IP10_20_18, FN_IP10_23_21, FN_IP10_25_24, FN_IP10_28_26, + + /* GPSR3 */ + FN_IP10_31_29, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_8_6, + FN_IP11_11_9, FN_IP11_14_12, FN_IP11_17_15, FN_IP11_20_18, + FN_IP11_23_21, FN_IP11_26_24, FN_IP11_29_27, FN_IP12_2_0, + FN_IP12_5_3, FN_IP12_8_6, FN_IP12_11_9, FN_IP12_14_12, + FN_IP12_17_15, FN_IP7_16_15, FN_IP7_18_17, FN_IP7_28_27, + FN_IP7_30_29, FN_IP7_20_19, FN_IP7_22_21, FN_IP7_24_23, + FN_IP7_26_25, FN_IP1_20_19, FN_IP1_22_21, FN_IP1_24_23, + FN_IP5_28, FN_IP5_30_29, FN_IP6_1_0, FN_IP6_3_2, + + /* GPSR4 */ + FN_IP6_5_4, FN_IP6_7_6, FN_IP6_8, FN_IP6_11_9, + FN_IP6_14_12, FN_IP6_17_15, FN_IP6_19_18, FN_IP6_22_20, + FN_IP6_24_23, FN_IP6_26_25, FN_IP6_30_29, FN_IP7_1_0, + FN_IP7_3_2, FN_IP7_6_4, FN_IP7_9_7, FN_IP7_12_10, + FN_IP7_14_13, FN_IP2_7_4, FN_IP2_11_8, FN_IP2_15_12, + FN_IP1_28_25, FN_IP2_3_0, FN_IP8_3_0, FN_IP8_7_4, + FN_IP8_11_8, FN_IP8_15_12, FN_PENC0, FN_PENC1, + FN_IP0_2_0, FN_IP8_17_16, FN_IP8_18, FN_IP8_19, + + /* GPSR5 */ + FN_A1, FN_A2, FN_A3, FN_A4, + FN_A5, FN_A6, FN_A7, FN_A8, + FN_A9, FN_A10, FN_A11, FN_A12, + FN_A13, FN_A14, FN_A15, FN_A16, + FN_RD, FN_WE0, FN_WE1, FN_EX_WAIT0, + FN_IP3_23, FN_IP3_27, FN_IP3_28, FN_IP2_22, + FN_IP2_23, FN_IP2_24, FN_IP2_25, FN_IP2_26, + FN_IP2_27, FN_IP3_3, FN_IP3_4, FN_IP3_5, + + /* GPSR6 */ + FN_IP3_6, FN_IP3_7, FN_IP3_8, FN_IP3_15, + FN_IP3_16, FN_IP3_17, FN_IP3_18, FN_IP3_19, + FN_IP3_20, + + /* IPSR0 */ + FN_RD_WR, FN_FWE, FN_ATAG0, FN_VI1_R7, + FN_HRTS1, FN_RX4_C, + FN_CS1_A26, FN_HSPI_TX2, FN_SDSELF_B, + FN_CS0, FN_HSPI_CS2_B, + FN_CLKOUT, FN_TX3C_IRDA_TX_C, FN_PWM0_B, + FN_A25, FN_SD1_WP, FN_MMC0_D5, FN_FD5, + FN_HSPI_RX2, FN_VI1_R3, FN_TX5_B, FN_SSI_SDATA7_B, + FN_CTS0_B, + FN_A24, FN_SD1_CD, FN_MMC0_D4, FN_FD4, + FN_HSPI_CS2, FN_VI1_R2, FN_SSI_WS78_B, + FN_A23, FN_FCLE, FN_HSPI_CLK2, FN_VI1_R1, + FN_A22, FN_RX5_D, FN_HSPI_RX2_B, FN_VI1_R0, + FN_A21, FN_SCK5_D, FN_HSPI_CLK2_B, + FN_A20, FN_TX5_D, FN_HSPI_TX2_B, + FN_A0, FN_SD1_DAT3, FN_MMC0_D3, FN_FD3, + FN_BS, FN_SD1_DAT2, FN_MMC0_D2, FN_FD2, + FN_ATADIR0, FN_SDSELF, FN_HCTS1, FN_TX4_C, + FN_PENC2, FN_SCK0, FN_PWM1, FN_PWMFSW0, + FN_SCIF_CLK, FN_TCLK0_C, + + /* IPSR1 */ + FN_EX_CS0, FN_RX3_C_IRDA_RX_C, FN_MMC0_D6, + FN_FD6, FN_EX_CS1, FN_MMC0_D7, FN_FD7, + FN_EX_CS2, FN_SD1_CLK, FN_MMC0_CLK, FN_FALE, + FN_ATACS00, FN_EX_CS3, FN_SD1_CMD, FN_MMC0_CMD, + FN_FRE, FN_ATACS10, FN_VI1_R4, FN_RX5_B, + FN_HSCK1, FN_SSI_SDATA8_B, FN_RTS0_B_TANS_B, FN_SSI_SDATA9, + FN_EX_CS4, FN_SD1_DAT0, FN_MMC0_D0, FN_FD0, + FN_ATARD0, FN_VI1_R5, FN_SCK5_B, FN_HTX1, + FN_TX2_E, FN_TX0_B, FN_SSI_SCK9, FN_EX_CS5, + FN_SD1_DAT1, FN_MMC0_D1, FN_FD1, FN_ATAWR0, + FN_VI1_R6, FN_HRX1, FN_RX2_E, FN_RX0_B, + FN_SSI_WS9, FN_MLB_CLK, FN_PWM2, FN_SCK4, + FN_MLB_SIG, FN_PWM3, FN_TX4, FN_MLB_DAT, + FN_PWM4, FN_RX4, FN_HTX0, FN_TX1, + FN_SDATA, FN_CTS0_C, FN_SUB_TCK, FN_CC5_STATE2, + FN_CC5_STATE10, FN_CC5_STATE18, FN_CC5_STATE26, FN_CC5_STATE34, + + /* IPSR2 */ + FN_HRX0, FN_RX1, FN_SCKZ, FN_RTS0_C_TANS_C, + FN_SUB_TDI, FN_CC5_STATE3, FN_CC5_STATE11, FN_CC5_STATE19, + FN_CC5_STATE27, FN_CC5_STATE35, FN_HSCK0, FN_SCK1, + FN_MTS, FN_PWM5, FN_SCK0_C, FN_SSI_SDATA9_B, + FN_SUB_TDO, FN_CC5_STATE0, FN_CC5_STATE8, FN_CC5_STATE16, + FN_CC5_STATE24, FN_CC5_STATE32, FN_HCTS0, FN_CTS1, + FN_STM, FN_PWM0_D, FN_RX0_C, FN_SCIF_CLK_C, + FN_SUB_TRST, FN_TCLK1_B, FN_CC5_OSCOUT, FN_HRTS0, + FN_RTS1_TANS, FN_MDATA, FN_TX0_C, FN_SUB_TMS, + FN_CC5_STATE1, FN_CC5_STATE9, FN_CC5_STATE17, FN_CC5_STATE25, + FN_CC5_STATE33, FN_DU0_DR0, FN_LCDOUT0, FN_DREQ0, + FN_GPS_CLK_B, FN_AUDATA0, FN_TX5_C, FN_DU0_DR1, + FN_LCDOUT1, FN_DACK0, FN_DRACK0, FN_GPS_SIGN_B, + FN_AUDATA1, FN_RX5_C, FN_DU0_DR2, FN_LCDOUT2, + FN_DU0_DR3, FN_LCDOUT3, FN_DU0_DR4, FN_LCDOUT4, + FN_DU0_DR5, FN_LCDOUT5, FN_DU0_DR6, FN_LCDOUT6, + FN_DU0_DR7, FN_LCDOUT7, FN_DU0_DG0, FN_LCDOUT8, + FN_DREQ1, FN_SCL2, FN_AUDATA2, + + /* IPSR3 */ + FN_DU0_DG1, FN_LCDOUT9, FN_DACK1, FN_SDA2, + FN_AUDATA3, FN_DU0_DG2, FN_LCDOUT10, FN_DU0_DG3, + FN_LCDOUT11, FN_DU0_DG4, FN_LCDOUT12, FN_DU0_DG5, + FN_LCDOUT13, FN_DU0_DG6, FN_LCDOUT14, FN_DU0_DG7, + FN_LCDOUT15, FN_DU0_DB0, FN_LCDOUT16, FN_EX_WAIT1, + FN_SCL1, FN_TCLK1, FN_AUDATA4, FN_DU0_DB1, + FN_LCDOUT17, FN_EX_WAIT2, FN_SDA1, FN_GPS_MAG_B, + FN_AUDATA5, FN_SCK5_C, FN_DU0_DB2, FN_LCDOUT18, + FN_DU0_DB3, FN_LCDOUT19, FN_DU0_DB4, FN_LCDOUT20, + FN_DU0_DB5, FN_LCDOUT21, FN_DU0_DB6, FN_LCDOUT22, + FN_DU0_DB7, FN_LCDOUT23, FN_DU0_DOTCLKIN, FN_QSTVA_QVS, + FN_TX3_D_IRDA_TX_D, FN_SCL3_B, FN_DU0_DOTCLKOUT0, FN_QCLK, + FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE, FN_RX3_D_IRDA_RX_D, FN_SDA3_B, + FN_SDA2_C, FN_DACK0_B, FN_DRACK0_B, FN_DU0_EXHSYNC_DU0_HSYNC, + FN_QSTH_QHS, FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, + FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, FN_CAN1_TX, + FN_TX2_C, FN_SCL2_C, FN_REMOCON, + + /* IPSR4 */ + FN_DU0_DISP, FN_QPOLA, FN_CAN_CLK_C, FN_SCK2_C, + FN_DU0_CDE, FN_QPOLB, FN_CAN1_RX, FN_RX2_C, + FN_DREQ0_B, FN_SSI_SCK78_B, FN_SCK0_B, FN_DU1_DR0, + FN_VI2_DATA0_VI2_B0, FN_PWM6, FN_SD3_CLK, FN_TX3_E_IRDA_TX_E, + FN_AUDCK, FN_PWMFSW0_B, FN_DU1_DR1, FN_VI2_DATA1_VI2_B1, + FN_PWM0, FN_SD3_CMD, FN_RX3_E_IRDA_RX_E, FN_AUDSYNC, + FN_CTS0_D, FN_DU1_DR2, FN_VI2_G0, FN_DU1_DR3, + FN_VI2_G1, FN_DU1_DR4, FN_VI2_G2, FN_DU1_DR5, + FN_VI2_G3, FN_DU1_DR6, FN_VI2_G4, FN_DU1_DR7, + FN_VI2_G5, FN_DU1_DG0, FN_VI2_DATA2_VI2_B2, FN_SCL1_B, + FN_SD3_DAT2, FN_SCK3_E, FN_AUDATA6, FN_TX0_D, + FN_DU1_DG1, FN_VI2_DATA3_VI2_B3, FN_SDA1_B, FN_SD3_DAT3, + FN_SCK5, FN_AUDATA7, FN_RX0_D, FN_DU1_DG2, + FN_VI2_G6, FN_DU1_DG3, FN_VI2_G7, FN_DU1_DG4, + FN_VI2_R0, FN_DU1_DG5, FN_VI2_R1, FN_DU1_DG6, + FN_VI2_R2, FN_DU1_DG7, FN_VI2_R3, FN_DU1_DB0, + FN_VI2_DATA4_VI2_B4, FN_SCL2_B, FN_SD3_DAT0, FN_TX5, + FN_SCK0_D, + + /* IPSR5 */ + FN_DU1_DB1, FN_VI2_DATA5_VI2_B5, FN_SDA2_B, FN_SD3_DAT1, + FN_RX5, FN_RTS0_D_TANS_D, FN_DU1_DB2, FN_VI2_R4, + FN_DU1_DB3, FN_VI2_R5, FN_DU1_DB4, FN_VI2_R6, + FN_DU1_DB5, FN_VI2_R7, FN_DU1_DB6, FN_SCL2_D, + FN_DU1_DB7, FN_SDA2_D, FN_DU1_DOTCLKIN, FN_VI2_CLKENB, + FN_HSPI_CS1, FN_SCL1_D, FN_DU1_DOTCLKOUT, FN_VI2_FIELD, + FN_SDA1_D, FN_DU1_EXHSYNC_DU1_HSYNC, FN_VI2_HSYNC, + FN_VI3_HSYNC, FN_DU1_EXVSYNC_DU1_VSYNC, FN_VI2_VSYNC, FN_VI3_VSYNC, + FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_VI2_CLK, FN_TX3_B_IRDA_TX_B, + FN_SD3_CD, FN_HSPI_TX1, FN_VI1_CLKENB, FN_VI3_CLKENB, + FN_AUDIO_CLKC, FN_TX2_D, FN_SPEEDIN, FN_GPS_SIGN_D, + FN_DU1_DISP, FN_VI2_DATA6_VI2_B6, FN_TCLK0, FN_QSTVA_B_QVS_B, + FN_HSPI_CLK1, FN_SCK2_D, FN_AUDIO_CLKOUT_B, FN_GPS_MAG_D, + FN_DU1_CDE, FN_VI2_DATA7_VI2_B7, FN_RX3_B_IRDA_RX_B, + FN_SD3_WP, FN_HSPI_RX1, FN_VI1_FIELD, FN_VI3_FIELD, + FN_AUDIO_CLKOUT, FN_RX2_D, FN_GPS_CLK_C, FN_GPS_CLK_D, + FN_AUDIO_CLKA, FN_CAN_TXCLK, FN_AUDIO_CLKB, FN_USB_OVC2, + FN_CAN_DEBUGOUT0, FN_MOUT0, + + /* IPSR6 */ + FN_SSI_SCK0129, FN_CAN_DEBUGOUT1, FN_MOUT1, FN_SSI_WS0129, + FN_CAN_DEBUGOUT2, FN_MOUT2, FN_SSI_SDATA0, FN_CAN_DEBUGOUT3, + FN_MOUT5, FN_SSI_SDATA1, FN_CAN_DEBUGOUT4, FN_MOUT6, + FN_SSI_SDATA2, FN_CAN_DEBUGOUT5, FN_SSI_SCK34, FN_CAN_DEBUGOUT6, + FN_CAN0_TX_B, FN_IERX, FN_SSI_SCK9_C, FN_SSI_WS34, + FN_CAN_DEBUGOUT7, FN_CAN0_RX_B, FN_IETX, FN_SSI_WS9_C, + FN_SSI_SDATA3, FN_PWM0_C, FN_CAN_DEBUGOUT8, FN_CAN_CLK_B, + FN_IECLK, FN_SCIF_CLK_B, FN_TCLK0_B, FN_SSI_SDATA4, + FN_CAN_DEBUGOUT9, FN_SSI_SDATA9_C, FN_SSI_SCK5, FN_ADICLK, + FN_CAN_DEBUGOUT10, FN_SCK3, FN_TCLK0_D, FN_SSI_WS5, + FN_ADICS_SAMP, FN_CAN_DEBUGOUT11, FN_TX3_IRDA_TX, FN_SSI_SDATA5, + FN_ADIDATA, FN_CAN_DEBUGOUT12, FN_RX3_IRDA_RX, FN_SSI_SCK6, + FN_ADICHS0, FN_CAN0_TX, FN_IERX_B, + + /* IPSR7 */ + FN_SSI_WS6, FN_ADICHS1, FN_CAN0_RX, FN_IETX_B, + FN_SSI_SDATA6, FN_ADICHS2, FN_CAN_CLK, FN_IECLK_B, + FN_SSI_SCK78, FN_CAN_DEBUGOUT13, FN_IRQ0_B, FN_SSI_SCK9_B, + FN_HSPI_CLK1_C, FN_SSI_WS78, FN_CAN_DEBUGOUT14, FN_IRQ1_B, + FN_SSI_WS9_B, FN_HSPI_CS1_C, FN_SSI_SDATA7, FN_CAN_DEBUGOUT15, + FN_IRQ2_B, FN_TCLK1_C, FN_HSPI_TX1_C, FN_SSI_SDATA8, + FN_VSP, FN_IRQ3_B, FN_HSPI_RX1_C, FN_SD0_CLK, + FN_ATACS01, FN_SCK1_B, FN_SD0_CMD, FN_ATACS11, + FN_TX1_B, FN_CC5_TDO, FN_SD0_DAT0, FN_ATADIR1, + FN_RX1_B, FN_CC5_TRST, FN_SD0_DAT1, FN_ATAG1, + FN_SCK2_B, FN_CC5_TMS, FN_SD0_DAT2, FN_ATARD1, + FN_TX2_B, FN_CC5_TCK, FN_SD0_DAT3, FN_ATAWR1, + FN_RX2_B, FN_CC5_TDI, FN_SD0_CD, FN_DREQ2, + FN_RTS1_B_TANS_B, FN_SD0_WP, FN_DACK2, FN_CTS1_B, + + /* IPSR8 */ + FN_HSPI_CLK0, FN_CTS0, FN_USB_OVC0, FN_AD_CLK, + FN_CC5_STATE4, FN_CC5_STATE12, FN_CC5_STATE20, FN_CC5_STATE28, + FN_CC5_STATE36, FN_HSPI_CS0, FN_RTS0_TANS, FN_USB_OVC1, + FN_AD_DI, FN_CC5_STATE5, FN_CC5_STATE13, FN_CC5_STATE21, + FN_CC5_STATE29, FN_CC5_STATE37, FN_HSPI_TX0, FN_TX0, + FN_CAN_DEBUG_HW_TRIGGER, FN_AD_DO, FN_CC5_STATE6, FN_CC5_STATE14, + FN_CC5_STATE22, FN_CC5_STATE30, FN_CC5_STATE38, FN_HSPI_RX0, + FN_RX0, FN_CAN_STEP0, FN_AD_NCS, FN_CC5_STATE7, + FN_CC5_STATE15, FN_CC5_STATE23, FN_CC5_STATE31, FN_CC5_STATE39, + FN_FMCLK, FN_RDS_CLK, FN_PCMOE, FN_BPFCLK, + FN_PCMWE, FN_FMIN, FN_RDS_DATA, FN_VI0_CLK, + FN_MMC1_CLK, FN_VI0_CLKENB, FN_TX1_C, FN_HTX1_B, + FN_MT1_SYNC, FN_VI0_FIELD, FN_RX1_C, FN_HRX1_B, + FN_VI0_HSYNC, FN_VI0_DATA0_B_VI0_B0_B, FN_CTS1_C, FN_TX4_D, + FN_MMC1_CMD, FN_HSCK1_B, FN_VI0_VSYNC, FN_VI0_DATA1_B_VI0_B1_B, + FN_RTS1_C_TANS_C, FN_RX4_D, FN_PWMFSW0_C, + + /* IPSR9 */ + FN_VI0_DATA0_VI0_B0, FN_HRTS1_B, FN_MT1_VCXO, FN_VI0_DATA1_VI0_B1, + FN_HCTS1_B, FN_MT1_PWM, FN_VI0_DATA2_VI0_B2, FN_MMC1_D0, + FN_VI0_DATA3_VI0_B3, FN_MMC1_D1, FN_VI0_DATA4_VI0_B4, FN_MMC1_D2, + FN_VI0_DATA5_VI0_B5, FN_MMC1_D3, FN_VI0_DATA6_VI0_B6, FN_MMC1_D4, + FN_ARM_TRACEDATA_0, FN_VI0_DATA7_VI0_B7, FN_MMC1_D5, + FN_ARM_TRACEDATA_1, FN_VI0_G0, FN_SSI_SCK78_C, FN_IRQ0, + FN_ARM_TRACEDATA_2, FN_VI0_G1, FN_SSI_WS78_C, FN_IRQ1, + FN_ARM_TRACEDATA_3, FN_VI0_G2, FN_ETH_TXD1, FN_MMC1_D6, + FN_ARM_TRACEDATA_4, FN_TS_SPSYNC0, FN_VI0_G3, FN_ETH_CRS_DV, + FN_MMC1_D7, FN_ARM_TRACEDATA_5, FN_TS_SDAT0, FN_VI0_G4, + FN_ETH_TX_EN, FN_SD2_DAT0_B, FN_ARM_TRACEDATA_6, FN_VI0_G5, + FN_ETH_RX_ER, FN_SD2_DAT1_B, FN_ARM_TRACEDATA_7, FN_VI0_G6, + FN_ETH_RXD0, FN_SD2_DAT2_B, FN_ARM_TRACEDATA_8, FN_VI0_G7, + FN_ETH_RXD1, FN_SD2_DAT3_B, FN_ARM_TRACEDATA_9, + + /* IPSR10 */ + FN_VI0_R0, FN_SSI_SDATA7_C, FN_SCK1_C, FN_DREQ1_B, + FN_ARM_TRACEDATA_10, FN_DREQ0_C, FN_VI0_R1, FN_SSI_SDATA8_C, + FN_DACK1_B, FN_ARM_TRACEDATA_11, FN_DACK0_C, FN_DRACK0_C, + FN_VI0_R2, FN_ETH_LINK, FN_SD2_CLK_B, FN_IRQ2, + FN_ARM_TRACEDATA_12, FN_VI0_R3, FN_ETH_MAGIC, FN_SD2_CMD_B, + FN_IRQ3, FN_ARM_TRACEDATA_13, FN_VI0_R4, FN_ETH_REFCLK, + FN_SD2_CD_B, FN_HSPI_CLK1_B, FN_ARM_TRACEDATA_14, FN_MT1_CLK, + FN_TS_SCK0, FN_VI0_R5, FN_ETH_TXD0, FN_SD2_WP_B, FN_HSPI_CS1_B, + FN_ARM_TRACEDATA_15, FN_MT1_D, FN_TS_SDEN0, FN_VI0_R6, + FN_ETH_MDC, FN_DREQ2_C, FN_HSPI_TX1_B, FN_TRACECLK, + FN_MT1_BEN, FN_PWMFSW0_D, FN_VI0_R7, FN_ETH_MDIO, + FN_DACK2_C, FN_HSPI_RX1_B, FN_SCIF_CLK_D, FN_TRACECTL, + FN_MT1_PEN, FN_VI1_CLK, FN_SIM_D, FN_SDA3, + FN_VI1_HSYNC, FN_VI3_CLK, FN_SSI_SCK4, FN_GPS_SIGN_C, + FN_PWMFSW0_E, FN_VI1_VSYNC, FN_AUDIO_CLKOUT_C, FN_SSI_WS4, + FN_SIM_CLK, FN_GPS_MAG_C, FN_SPV_TRST, FN_SCL3, + + /* IPSR11 */ + FN_VI1_DATA0_VI1_B0, FN_SD2_DAT0, FN_SIM_RST, FN_SPV_TCK, + FN_ADICLK_B, FN_VI1_DATA1_VI1_B1, FN_SD2_DAT1, FN_MT0_CLK, + FN_SPV_TMS, FN_ADICS_B_SAMP_B, FN_VI1_DATA2_VI1_B2, FN_SD2_DAT2, + FN_MT0_D, FN_SPVTDI, FN_ADIDATA_B, FN_VI1_DATA3_VI1_B3, + FN_SD2_DAT3, FN_MT0_BEN, FN_SPV_TDO, FN_ADICHS0_B, + FN_VI1_DATA4_VI1_B4, FN_SD2_CLK, FN_MT0_PEN, FN_SPA_TRST, + FN_HSPI_CLK1_D, FN_ADICHS1_B, FN_VI1_DATA5_VI1_B5, FN_SD2_CMD, + FN_MT0_SYNC, FN_SPA_TCK, FN_HSPI_CS1_D, FN_ADICHS2_B, + FN_VI1_DATA6_VI1_B6, FN_SD2_CD, FN_MT0_VCXO, FN_SPA_TMS, + FN_HSPI_TX1_D, FN_VI1_DATA7_VI1_B7, FN_SD2_WP, FN_MT0_PWM, + FN_SPA_TDI, FN_HSPI_RX1_D, FN_VI1_G0, FN_VI3_DATA0, + FN_DU1_DOTCLKOUT1, FN_TS_SCK1, FN_DREQ2_B, FN_TX2, + FN_SPA_TDO, FN_HCTS0_B, FN_VI1_G1, FN_VI3_DATA1, + FN_SSI_SCK1, FN_TS_SDEN1, FN_DACK2_B, FN_RX2, FN_HRTS0_B, + + /* IPSR12 */ + FN_VI1_G2, FN_VI3_DATA2, FN_SSI_WS1, FN_TS_SPSYNC1, + FN_SCK2, FN_HSCK0_B, FN_VI1_G3, FN_VI3_DATA3, + FN_SSI_SCK2, FN_TS_SDAT1, FN_SCL1_C, FN_HTX0_B, + FN_VI1_G4, FN_VI3_DATA4, FN_SSI_WS2, FN_SDA1_C, + FN_SIM_RST_B, FN_HRX0_B, FN_VI1_G5, FN_VI3_DATA5, + FN_GPS_CLK, FN_FSE, FN_TX4_B, FN_SIM_D_B, + FN_VI1_G6, FN_VI3_DATA6, FN_GPS_SIGN, FN_FRB, + FN_RX4_B, FN_SIM_CLK_B, FN_VI1_G7, FN_VI3_DATA7, + FN_GPS_MAG, FN_FCE, FN_SCK4_B, + + FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3, + FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3, + FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, + FN_SEL_SCIF3_3, FN_SEL_SCIF3_4, + FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, + FN_SEL_SCIF2_3, FN_SEL_SCIF2_4, + FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, + FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3, + FN_SEL_SSI9_0, FN_SEL_SSI9_1, FN_SEL_SSI9_2, + FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, + FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2, + FN_SEL_VI0_0, FN_SEL_VI0_1, + FN_SEL_SD2_0, FN_SEL_SD2_1, + FN_SEL_INT3_0, FN_SEL_INT3_1, + FN_SEL_INT2_0, FN_SEL_INT2_1, + FN_SEL_INT1_0, FN_SEL_INT1_1, + FN_SEL_INT0_0, FN_SEL_INT0_1, + FN_SEL_IE_0, FN_SEL_IE_1, + FN_SEL_EXBUS2_0, FN_SEL_EXBUS2_1, FN_SEL_EXBUS2_2, + FN_SEL_EXBUS1_0, FN_SEL_EXBUS1_1, + FN_SEL_EXBUS0_0, FN_SEL_EXBUS0_1, FN_SEL_EXBUS0_2, + + FN_SEL_TMU1_0, FN_SEL_TMU1_1, FN_SEL_TMU1_2, + FN_SEL_TMU0_0, FN_SEL_TMU0_1, FN_SEL_TMU0_2, FN_SEL_TMU0_3, + FN_SEL_SCIF_0, FN_SEL_SCIF_1, FN_SEL_SCIF_2, FN_SEL_SCIF_3, + FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2, + FN_SEL_CAN0_0, FN_SEL_CAN0_1, + FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, + FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, + FN_SEL_PWMFSW_0, FN_SEL_PWMFSW_1, FN_SEL_PWMFSW_2, + FN_SEL_PWMFSW_3, FN_SEL_PWMFSW_4, + FN_SEL_ADI_0, FN_SEL_ADI_1, + FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3, + FN_SEL_SIM_0, FN_SEL_SIM_1, + FN_SEL_HSPI2_0, FN_SEL_HSPI2_1, + FN_SEL_HSPI1_0, FN_SEL_HSPI1_1, FN_SEL_HSPI1_2, FN_SEL_HSPI1_3, + FN_SEL_I2C3_0, FN_SEL_I2C3_1, + FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3, + FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, FN_SEL_I2C1_3, + PINMUX_FUNCTION_END, + + PINMUX_MARK_BEGIN, + AVS1_MARK, AVS2_MARK, A17_MARK, A18_MARK, + A19_MARK, + + RD_WR_MARK, FWE_MARK, ATAG0_MARK, VI1_R7_MARK, + HRTS1_MARK, RX4_C_MARK, + CS1_A26_MARK, HSPI_TX2_MARK, SDSELF_B_MARK, + CS0_MARK, HSPI_CS2_B_MARK, + CLKOUT_MARK, TX3C_IRDA_TX_C_MARK, PWM0_B_MARK, + A25_MARK, SD1_WP_MARK, MMC0_D5_MARK, FD5_MARK, + HSPI_RX2_MARK, VI1_R3_MARK, TX5_B_MARK, SSI_SDATA7_B_MARK, CTS0_B_MARK, + A24_MARK, SD1_CD_MARK, MMC0_D4_MARK, FD4_MARK, + HSPI_CS2_MARK, VI1_R2_MARK, SSI_WS78_B_MARK, + A23_MARK, FCLE_MARK, HSPI_CLK2_MARK, VI1_R1_MARK, + A22_MARK, RX5_D_MARK, HSPI_RX2_B_MARK, VI1_R0_MARK, + A21_MARK, SCK5_D_MARK, HSPI_CLK2_B_MARK, + A20_MARK, TX5_D_MARK, HSPI_TX2_B_MARK, + A0_MARK, SD1_DAT3_MARK, MMC0_D3_MARK, FD3_MARK, + BS_MARK, SD1_DAT2_MARK, MMC0_D2_MARK, FD2_MARK, + ATADIR0_MARK, SDSELF_MARK, HCTS1_MARK, TX4_C_MARK, + PENC2_MARK, SCK0_MARK, PWM1_MARK, PWMFSW0_MARK, + SCIF_CLK_MARK, TCLK0_C_MARK, + + EX_CS0_MARK, RX3_C_IRDA_RX_C_MARK, MMC0_D6_MARK, + FD6_MARK, EX_CS1_MARK, MMC0_D7_MARK, FD7_MARK, + EX_CS2_MARK, SD1_CLK_MARK, MMC0_CLK_MARK, FALE_MARK, + ATACS00_MARK, EX_CS3_MARK, SD1_CMD_MARK, MMC0_CMD_MARK, + FRE_MARK, ATACS10_MARK, VI1_R4_MARK, RX5_B_MARK, + HSCK1_MARK, SSI_SDATA8_B_MARK, RTS0_B_TANS_B_MARK, SSI_SDATA9_MARK, + EX_CS4_MARK, SD1_DAT0_MARK, MMC0_D0_MARK, FD0_MARK, + ATARD0_MARK, VI1_R5_MARK, SCK5_B_MARK, HTX1_MARK, + TX2_E_MARK, TX0_B_MARK, SSI_SCK9_MARK, EX_CS5_MARK, + SD1_DAT1_MARK, MMC0_D1_MARK, FD1_MARK, ATAWR0_MARK, + VI1_R6_MARK, HRX1_MARK, RX2_E_MARK, RX0_B_MARK, + SSI_WS9_MARK, MLB_CLK_MARK, PWM2_MARK, SCK4_MARK, + MLB_SIG_MARK, PWM3_MARK, TX4_MARK, MLB_DAT_MARK, + PWM4_MARK, RX4_MARK, HTX0_MARK, TX1_MARK, + SDATA_MARK, CTS0_C_MARK, SUB_TCK_MARK, CC5_STATE2_MARK, + CC5_STATE10_MARK, CC5_STATE18_MARK, CC5_STATE26_MARK, CC5_STATE34_MARK, + + HRX0_MARK, RX1_MARK, SCKZ_MARK, RTS0_C_TANS_C_MARK, + SUB_TDI_MARK, CC5_STATE3_MARK, CC5_STATE11_MARK, CC5_STATE19_MARK, + CC5_STATE27_MARK, CC5_STATE35_MARK, HSCK0_MARK, SCK1_MARK, + MTS_MARK, PWM5_MARK, SCK0_C_MARK, SSI_SDATA9_B_MARK, + SUB_TDO_MARK, CC5_STATE0_MARK, CC5_STATE8_MARK, CC5_STATE16_MARK, + CC5_STATE24_MARK, CC5_STATE32_MARK, HCTS0_MARK, CTS1_MARK, + STM_MARK, PWM0_D_MARK, RX0_C_MARK, SCIF_CLK_C_MARK, + SUB_TRST_MARK, TCLK1_B_MARK, CC5_OSCOUT_MARK, HRTS0_MARK, + RTS1_TANS_MARK, MDATA_MARK, TX0_C_MARK, SUB_TMS_MARK, + CC5_STATE1_MARK, CC5_STATE9_MARK, CC5_STATE17_MARK, CC5_STATE25_MARK, + CC5_STATE33_MARK, DU0_DR0_MARK, LCDOUT0_MARK, DREQ0_MARK, + GPS_CLK_B_MARK, AUDATA0_MARK, TX5_C_MARK, DU0_DR1_MARK, + LCDOUT1_MARK, DACK0_MARK, DRACK0_MARK, GPS_SIGN_B_MARK, + AUDATA1_MARK, RX5_C_MARK, DU0_DR2_MARK, LCDOUT2_MARK, + DU0_DR3_MARK, LCDOUT3_MARK, DU0_DR4_MARK, LCDOUT4_MARK, + DU0_DR5_MARK, LCDOUT5_MARK, DU0_DR6_MARK, LCDOUT6_MARK, + DU0_DR7_MARK, LCDOUT7_MARK, DU0_DG0_MARK, LCDOUT8_MARK, + DREQ1_MARK, SCL2_MARK, AUDATA2_MARK, + + DU0_DG1_MARK, LCDOUT9_MARK, DACK1_MARK, SDA2_MARK, + AUDATA3_MARK, DU0_DG2_MARK, LCDOUT10_MARK, DU0_DG3_MARK, + LCDOUT11_MARK, DU0_DG4_MARK, LCDOUT12_MARK, DU0_DG5_MARK, + LCDOUT13_MARK, DU0_DG6_MARK, LCDOUT14_MARK, DU0_DG7_MARK, + LCDOUT15_MARK, DU0_DB0_MARK, LCDOUT16_MARK, EX_WAIT1_MARK, + SCL1_MARK, TCLK1_MARK, AUDATA4_MARK, DU0_DB1_MARK, + LCDOUT17_MARK, EX_WAIT2_MARK, SDA1_MARK, GPS_MAG_B_MARK, + AUDATA5_MARK, SCK5_C_MARK, DU0_DB2_MARK, LCDOUT18_MARK, + DU0_DB3_MARK, LCDOUT19_MARK, DU0_DB4_MARK, LCDOUT20_MARK, + DU0_DB5_MARK, LCDOUT21_MARK, DU0_DB6_MARK, LCDOUT22_MARK, + DU0_DB7_MARK, LCDOUT23_MARK, DU0_DOTCLKIN_MARK, QSTVA_QVS_MARK, + TX3_D_IRDA_TX_D_MARK, SCL3_B_MARK, DU0_DOTCLKOUT0_MARK, QCLK_MARK, + DU0_DOTCLKOUT1_MARK, QSTVB_QVE_MARK, RX3_D_IRDA_RX_D_MARK, SDA3_B_MARK, + SDA2_C_MARK, DACK0_B_MARK, DRACK0_B_MARK, DU0_EXHSYNC_DU0_HSYNC_MARK, + QSTH_QHS_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK, QSTB_QHE_MARK, + DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK, CAN1_TX_MARK, + TX2_C_MARK, SCL2_C_MARK, REMOCON_MARK, + + DU0_DISP_MARK, QPOLA_MARK, CAN_CLK_C_MARK, SCK2_C_MARK, + DU0_CDE_MARK, QPOLB_MARK, CAN1_RX_MARK, RX2_C_MARK, + DREQ0_B_MARK, SSI_SCK78_B_MARK, SCK0_B_MARK, DU1_DR0_MARK, + VI2_DATA0_VI2_B0_MARK, PWM6_MARK, SD3_CLK_MARK, TX3_E_IRDA_TX_E_MARK, + AUDCK_MARK, PWMFSW0_B_MARK, DU1_DR1_MARK, VI2_DATA1_VI2_B1_MARK, + PWM0_MARK, SD3_CMD_MARK, RX3_E_IRDA_RX_E_MARK, AUDSYNC_MARK, + CTS0_D_MARK, DU1_DR2_MARK, VI2_G0_MARK, DU1_DR3_MARK, + VI2_G1_MARK, DU1_DR4_MARK, VI2_G2_MARK, DU1_DR5_MARK, + VI2_G3_MARK, DU1_DR6_MARK, VI2_G4_MARK, DU1_DR7_MARK, + VI2_G5_MARK, DU1_DG0_MARK, VI2_DATA2_VI2_B2_MARK, SCL1_B_MARK, + SD3_DAT2_MARK, SCK3_E_MARK, AUDATA6_MARK, TX0_D_MARK, + DU1_DG1_MARK, VI2_DATA3_VI2_B3_MARK, SDA1_B_MARK, SD3_DAT3_MARK, + SCK5_MARK, AUDATA7_MARK, RX0_D_MARK, DU1_DG2_MARK, + VI2_G6_MARK, DU1_DG3_MARK, VI2_G7_MARK, DU1_DG4_MARK, + VI2_R0_MARK, DU1_DG5_MARK, VI2_R1_MARK, DU1_DG6_MARK, + VI2_R2_MARK, DU1_DG7_MARK, VI2_R3_MARK, DU1_DB0_MARK, + VI2_DATA4_VI2_B4_MARK, SCL2_B_MARK, SD3_DAT0_MARK, TX5_MARK, + SCK0_D_MARK, + + DU1_DB1_MARK, VI2_DATA5_VI2_B5_MARK, SDA2_B_MARK, SD3_DAT1_MARK, + RX5_MARK, RTS0_D_TANS_D_MARK, DU1_DB2_MARK, VI2_R4_MARK, + DU1_DB3_MARK, VI2_R5_MARK, DU1_DB4_MARK, VI2_R6_MARK, + DU1_DB5_MARK, VI2_R7_MARK, DU1_DB6_MARK, SCL2_D_MARK, + DU1_DB7_MARK, SDA2_D_MARK, DU1_DOTCLKIN_MARK, VI2_CLKENB_MARK, + HSPI_CS1_MARK, SCL1_D_MARK, DU1_DOTCLKOUT_MARK, VI2_FIELD_MARK, + SDA1_D_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK, VI2_HSYNC_MARK, + VI3_HSYNC_MARK, DU1_EXVSYNC_DU1_VSYNC_MARK, VI2_VSYNC_MARK, + VI3_VSYNC_MARK, DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, VI2_CLK_MARK, + TX3_B_IRDA_TX_B_MARK, SD3_CD_MARK, HSPI_TX1_MARK, VI1_CLKENB_MARK, + VI3_CLKENB_MARK, AUDIO_CLKC_MARK, TX2_D_MARK, SPEEDIN_MARK, + GPS_SIGN_D_MARK, DU1_DISP_MARK, VI2_DATA6_VI2_B6_MARK, TCLK0_MARK, + QSTVA_B_QVS_B_MARK, HSPI_CLK1_MARK, SCK2_D_MARK, AUDIO_CLKOUT_B_MARK, + GPS_MAG_D_MARK, DU1_CDE_MARK, VI2_DATA7_VI2_B7_MARK, + RX3_B_IRDA_RX_B_MARK, SD3_WP_MARK, HSPI_RX1_MARK, VI1_FIELD_MARK, + VI3_FIELD_MARK, AUDIO_CLKOUT_MARK, RX2_D_MARK, GPS_CLK_C_MARK, + GPS_CLK_D_MARK, AUDIO_CLKA_MARK, CAN_TXCLK_MARK, AUDIO_CLKB_MARK, + USB_OVC2_MARK, CAN_DEBUGOUT0_MARK, MOUT0_MARK, + + SSI_SCK0129_MARK, CAN_DEBUGOUT1_MARK, MOUT1_MARK, SSI_WS0129_MARK, + CAN_DEBUGOUT2_MARK, MOUT2_MARK, SSI_SDATA0_MARK, CAN_DEBUGOUT3_MARK, + MOUT5_MARK, SSI_SDATA1_MARK, CAN_DEBUGOUT4_MARK, MOUT6_MARK, + SSI_SDATA2_MARK, CAN_DEBUGOUT5_MARK, SSI_SCK34_MARK, + CAN_DEBUGOUT6_MARK, CAN0_TX_B_MARK, IERX_MARK, SSI_SCK9_C_MARK, + SSI_WS34_MARK, CAN_DEBUGOUT7_MARK, CAN0_RX_B_MARK, IETX_MARK, + SSI_WS9_C_MARK, SSI_SDATA3_MARK, PWM0_C_MARK, CAN_DEBUGOUT8_MARK, + CAN_CLK_B_MARK, IECLK_MARK, SCIF_CLK_B_MARK, TCLK0_B_MARK, + SSI_SDATA4_MARK, CAN_DEBUGOUT9_MARK, SSI_SDATA9_C_MARK, SSI_SCK5_MARK, + ADICLK_MARK, CAN_DEBUGOUT10_MARK, SCK3_MARK, TCLK0_D_MARK, + SSI_WS5_MARK, ADICS_SAMP_MARK, CAN_DEBUGOUT11_MARK, TX3_IRDA_TX_MARK, + SSI_SDATA5_MARK, ADIDATA_MARK, CAN_DEBUGOUT12_MARK, RX3_IRDA_RX_MARK, + SSI_SCK6_MARK, ADICHS0_MARK, CAN0_TX_MARK, IERX_B_MARK, + + SSI_WS6_MARK, ADICHS1_MARK, CAN0_RX_MARK, IETX_B_MARK, + SSI_SDATA6_MARK, ADICHS2_MARK, CAN_CLK_MARK, IECLK_B_MARK, + SSI_SCK78_MARK, CAN_DEBUGOUT13_MARK, IRQ0_B_MARK, SSI_SCK9_B_MARK, + HSPI_CLK1_C_MARK, SSI_WS78_MARK, CAN_DEBUGOUT14_MARK, IRQ1_B_MARK, + SSI_WS9_B_MARK, HSPI_CS1_C_MARK, SSI_SDATA7_MARK, CAN_DEBUGOUT15_MARK, + IRQ2_B_MARK, TCLK1_C_MARK, HSPI_TX1_C_MARK, SSI_SDATA8_MARK, + VSP_MARK, IRQ3_B_MARK, HSPI_RX1_C_MARK, SD0_CLK_MARK, + ATACS01_MARK, SCK1_B_MARK, SD0_CMD_MARK, ATACS11_MARK, + TX1_B_MARK, CC5_TDO_MARK, SD0_DAT0_MARK, ATADIR1_MARK, + RX1_B_MARK, CC5_TRST_MARK, SD0_DAT1_MARK, ATAG1_MARK, + SCK2_B_MARK, CC5_TMS_MARK, SD0_DAT2_MARK, ATARD1_MARK, + TX2_B_MARK, CC5_TCK_MARK, SD0_DAT3_MARK, ATAWR1_MARK, + RX2_B_MARK, CC5_TDI_MARK, SD0_CD_MARK, DREQ2_MARK, + RTS1_B_TANS_B_MARK, SD0_WP_MARK, DACK2_MARK, CTS1_B_MARK, + + HSPI_CLK0_MARK, CTS0_MARK, USB_OVC0_MARK, AD_CLK_MARK, + CC5_STATE4_MARK, CC5_STATE12_MARK, CC5_STATE20_MARK, CC5_STATE28_MARK, + CC5_STATE36_MARK, HSPI_CS0_MARK, RTS0_TANS_MARK, USB_OVC1_MARK, + AD_DI_MARK, CC5_STATE5_MARK, CC5_STATE13_MARK, CC5_STATE21_MARK, + CC5_STATE29_MARK, CC5_STATE37_MARK, HSPI_TX0_MARK, TX0_MARK, + CAN_DEBUG_HW_TRIGGER_MARK, AD_DO_MARK, CC5_STATE6_MARK, + CC5_STATE14_MARK, CC5_STATE22_MARK, CC5_STATE30_MARK, + CC5_STATE38_MARK, HSPI_RX0_MARK, RX0_MARK, CAN_STEP0_MARK, + AD_NCS_MARK, CC5_STATE7_MARK, CC5_STATE15_MARK, CC5_STATE23_MARK, + CC5_STATE31_MARK, CC5_STATE39_MARK, FMCLK_MARK, RDS_CLK_MARK, + PCMOE_MARK, BPFCLK_MARK, PCMWE_MARK, FMIN_MARK, RDS_DATA_MARK, + VI0_CLK_MARK, MMC1_CLK_MARK, VI0_CLKENB_MARK, TX1_C_MARK, HTX1_B_MARK, + MT1_SYNC_MARK, VI0_FIELD_MARK, RX1_C_MARK, HRX1_B_MARK, + VI0_HSYNC_MARK, VI0_DATA0_B_VI0_B0_B_MARK, CTS1_C_MARK, TX4_D_MARK, + MMC1_CMD_MARK, HSCK1_B_MARK, VI0_VSYNC_MARK, VI0_DATA1_B_VI0_B1_B_MARK, + RTS1_C_TANS_C_MARK, RX4_D_MARK, PWMFSW0_C_MARK, + + VI0_DATA0_VI0_B0_MARK, HRTS1_B_MARK, MT1_VCXO_MARK, + VI0_DATA1_VI0_B1_MARK, HCTS1_B_MARK, MT1_PWM_MARK, + VI0_DATA2_VI0_B2_MARK, MMC1_D0_MARK, VI0_DATA3_VI0_B3_MARK, + MMC1_D1_MARK, VI0_DATA4_VI0_B4_MARK, MMC1_D2_MARK, + VI0_DATA5_VI0_B5_MARK, MMC1_D3_MARK, VI0_DATA6_VI0_B6_MARK, + MMC1_D4_MARK, ARM_TRACEDATA_0_MARK, VI0_DATA7_VI0_B7_MARK, + MMC1_D5_MARK, ARM_TRACEDATA_1_MARK, VI0_G0_MARK, SSI_SCK78_C_MARK, + IRQ0_MARK, ARM_TRACEDATA_2_MARK, VI0_G1_MARK, SSI_WS78_C_MARK, + IRQ1_MARK, ARM_TRACEDATA_3_MARK, VI0_G2_MARK, ETH_TXD1_MARK, + MMC1_D6_MARK, ARM_TRACEDATA_4_MARK, TS_SPSYNC0_MARK, VI0_G3_MARK, + ETH_CRS_DV_MARK, MMC1_D7_MARK, ARM_TRACEDATA_5_MARK, TS_SDAT0_MARK, + VI0_G4_MARK, ETH_TX_EN_MARK, SD2_DAT0_B_MARK, ARM_TRACEDATA_6_MARK, + VI0_G5_MARK, ETH_RX_ER_MARK, SD2_DAT1_B_MARK, ARM_TRACEDATA_7_MARK, + VI0_G6_MARK, ETH_RXD0_MARK, SD2_DAT2_B_MARK, ARM_TRACEDATA_8_MARK, + VI0_G7_MARK, ETH_RXD1_MARK, SD2_DAT3_B_MARK, ARM_TRACEDATA_9_MARK, + + VI0_R0_MARK, SSI_SDATA7_C_MARK, SCK1_C_MARK, DREQ1_B_MARK, + ARM_TRACEDATA_10_MARK, DREQ0_C_MARK, VI0_R1_MARK, SSI_SDATA8_C_MARK, + DACK1_B_MARK, ARM_TRACEDATA_11_MARK, DACK0_C_MARK, DRACK0_C_MARK, + VI0_R2_MARK, ETH_LINK_MARK, SD2_CLK_B_MARK, IRQ2_MARK, + ARM_TRACEDATA_12_MARK, VI0_R3_MARK, ETH_MAGIC_MARK, SD2_CMD_B_MARK, + IRQ3_MARK, ARM_TRACEDATA_13_MARK, VI0_R4_MARK, ETH_REFCLK_MARK, + SD2_CD_B_MARK, HSPI_CLK1_B_MARK, ARM_TRACEDATA_14_MARK, MT1_CLK_MARK, + TS_SCK0_MARK, VI0_R5_MARK, ETH_TXD0_MARK, SD2_WP_B_MARK, + HSPI_CS1_B_MARK, ARM_TRACEDATA_15_MARK, MT1_D_MARK, TS_SDEN0_MARK, + VI0_R6_MARK, ETH_MDC_MARK, DREQ2_C_MARK, HSPI_TX1_B_MARK, + TRACECLK_MARK, MT1_BEN_MARK, PWMFSW0_D_MARK, VI0_R7_MARK, + ETH_MDIO_MARK, DACK2_C_MARK, HSPI_RX1_B_MARK, SCIF_CLK_D_MARK, + TRACECTL_MARK, MT1_PEN_MARK, VI1_CLK_MARK, SIM_D_MARK, SDA3_MARK, + VI1_HSYNC_MARK, VI3_CLK_MARK, SSI_SCK4_MARK, GPS_SIGN_C_MARK, + PWMFSW0_E_MARK, VI1_VSYNC_MARK, AUDIO_CLKOUT_C_MARK, SSI_WS4_MARK, + SIM_CLK_MARK, GPS_MAG_C_MARK, SPV_TRST_MARK, SCL3_MARK, + + VI1_DATA0_VI1_B0_MARK, SD2_DAT0_MARK, SIM_RST_MARK, SPV_TCK_MARK, + ADICLK_B_MARK, VI1_DATA1_VI1_B1_MARK, SD2_DAT1_MARK, MT0_CLK_MARK, + SPV_TMS_MARK, ADICS_B_SAMP_B_MARK, VI1_DATA2_VI1_B2_MARK, + SD2_DAT2_MARK, MT0_D_MARK, SPVTDI_MARK, ADIDATA_B_MARK, + VI1_DATA3_VI1_B3_MARK, SD2_DAT3_MARK, MT0_BEN_MARK, SPV_TDO_MARK, + ADICHS0_B_MARK, VI1_DATA4_VI1_B4_MARK, SD2_CLK_MARK, MT0_PEN_MARK, + SPA_TRST_MARK, HSPI_CLK1_D_MARK, ADICHS1_B_MARK, + VI1_DATA5_VI1_B5_MARK, SD2_CMD_MARK, MT0_SYNC_MARK, SPA_TCK_MARK, + HSPI_CS1_D_MARK, ADICHS2_B_MARK, VI1_DATA6_VI1_B6_MARK, SD2_CD_MARK, + MT0_VCXO_MARK, SPA_TMS_MARK, HSPI_TX1_D_MARK, VI1_DATA7_VI1_B7_MARK, + SD2_WP_MARK, MT0_PWM_MARK, SPA_TDI_MARK, HSPI_RX1_D_MARK, + VI1_G0_MARK, VI3_DATA0_MARK, DU1_DOTCLKOUT1_MARK, TS_SCK1_MARK, + DREQ2_B_MARK, TX2_MARK, SPA_TDO_MARK, HCTS0_B_MARK, + VI1_G1_MARK, VI3_DATA1_MARK, SSI_SCK1_MARK, TS_SDEN1_MARK, + DACK2_B_MARK, RX2_MARK, HRTS0_B_MARK, + + VI1_G2_MARK, VI3_DATA2_MARK, SSI_WS1_MARK, TS_SPSYNC1_MARK, + SCK2_MARK, HSCK0_B_MARK, VI1_G3_MARK, VI3_DATA3_MARK, + SSI_SCK2_MARK, TS_SDAT1_MARK, SCL1_C_MARK, HTX0_B_MARK, + VI1_G4_MARK, VI3_DATA4_MARK, SSI_WS2_MARK, SDA1_C_MARK, + SIM_RST_B_MARK, HRX0_B_MARK, VI1_G5_MARK, VI3_DATA5_MARK, + GPS_CLK_MARK, FSE_MARK, TX4_B_MARK, SIM_D_B_MARK, + VI1_G6_MARK, VI3_DATA6_MARK, GPS_SIGN_MARK, FRB_MARK, + RX4_B_MARK, SIM_CLK_B_MARK, VI1_G7_MARK, VI3_DATA7_MARK, + GPS_MAG_MARK, FCE_MARK, SCK4_B_MARK, + PINMUX_MARK_END, +}; + +static pinmux_enum_t pinmux_data[] = { + PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */ + + PINMUX_DATA(AVS1_MARK, FN_AVS1), + PINMUX_DATA(AVS1_MARK, FN_AVS1), + PINMUX_DATA(A17_MARK, FN_A17), + PINMUX_DATA(A18_MARK, FN_A18), + PINMUX_DATA(A19_MARK, FN_A19), + + PINMUX_IPSR_DATA(IP0_2_0, PENC2), + PINMUX_IPSR_MODSEL_DATA(IP0_2_0, SCK0, SEL_SCIF0_0), + PINMUX_IPSR_DATA(IP0_2_0, PWM1), + PINMUX_IPSR_MODSEL_DATA(IP0_2_0, PWMFSW0, SEL_PWMFSW_0), + PINMUX_IPSR_MODSEL_DATA(IP0_2_0, SCIF_CLK, SEL_SCIF_0), + PINMUX_IPSR_MODSEL_DATA(IP0_2_0, TCLK0_C, SEL_TMU0_2), + PINMUX_IPSR_DATA(IP0_5_3, BS), + PINMUX_IPSR_DATA(IP0_5_3, SD1_DAT2), + PINMUX_IPSR_DATA(IP0_5_3, MMC0_D2), + PINMUX_IPSR_DATA(IP0_5_3, FD2), + PINMUX_IPSR_DATA(IP0_5_3, ATADIR0), + PINMUX_IPSR_DATA(IP0_5_3, SDSELF), + PINMUX_IPSR_MODSEL_DATA(IP0_5_3, HCTS1, SEL_HSCIF1_0), + PINMUX_IPSR_DATA(IP0_5_3, TX4_C), + PINMUX_IPSR_DATA(IP0_7_6, A0), + PINMUX_IPSR_DATA(IP0_7_6, SD1_DAT3), + PINMUX_IPSR_DATA(IP0_7_6, MMC0_D3), + PINMUX_IPSR_DATA(IP0_7_6, FD3), + PINMUX_IPSR_DATA(IP0_9_8, A20), + PINMUX_IPSR_DATA(IP0_9_8, TX5_D), + PINMUX_IPSR_DATA(IP0_9_8, HSPI_TX2_B), + PINMUX_IPSR_DATA(IP0_11_10, A21), + PINMUX_IPSR_MODSEL_DATA(IP0_11_10, SCK5_D, SEL_SCIF5_3), + PINMUX_IPSR_MODSEL_DATA(IP0_11_10, HSPI_CLK2_B, SEL_HSPI2_1), + PINMUX_IPSR_DATA(IP0_13_12, A22), + PINMUX_IPSR_MODSEL_DATA(IP0_13_12, RX5_D, SEL_SCIF5_3), + PINMUX_IPSR_MODSEL_DATA(IP0_13_12, HSPI_RX2_B, SEL_HSPI2_1), + PINMUX_IPSR_DATA(IP0_13_12, VI1_R0), + PINMUX_IPSR_DATA(IP0_15_14, A23), + PINMUX_IPSR_DATA(IP0_15_14, FCLE), + PINMUX_IPSR_MODSEL_DATA(IP0_15_14, HSPI_CLK2, SEL_HSPI2_0), + PINMUX_IPSR_DATA(IP0_15_14, VI1_R1), + PINMUX_IPSR_DATA(IP0_18_16, A24), + PINMUX_IPSR_DATA(IP0_18_16, SD1_CD), + PINMUX_IPSR_DATA(IP0_18_16, MMC0_D4), + PINMUX_IPSR_DATA(IP0_18_16, FD4), + PINMUX_IPSR_MODSEL_DATA(IP0_18_16, HSPI_CS2, SEL_HSPI2_0), + PINMUX_IPSR_DATA(IP0_18_16, VI1_R2), + PINMUX_IPSR_MODSEL_DATA(IP0_18_16, SSI_WS78_B, SEL_SSI7_1), + PINMUX_IPSR_DATA(IP0_22_19, A25), + PINMUX_IPSR_DATA(IP0_22_19, SD1_WP), + PINMUX_IPSR_DATA(IP0_22_19, MMC0_D5), + PINMUX_IPSR_DATA(IP0_22_19, FD5), + PINMUX_IPSR_MODSEL_DATA(IP0_22_19, HSPI_RX2, SEL_HSPI2_0), + PINMUX_IPSR_DATA(IP0_22_19, VI1_R3), + PINMUX_IPSR_DATA(IP0_22_19, TX5_B), + PINMUX_IPSR_MODSEL_DATA(IP0_22_19, SSI_SDATA7_B, SEL_SSI7_1), + PINMUX_IPSR_MODSEL_DATA(IP0_22_19, CTS0_B, SEL_SCIF0_1), + PINMUX_IPSR_DATA(IP0_24_23, CLKOUT), + PINMUX_IPSR_DATA(IP0_24_23, TX3C_IRDA_TX_C), + PINMUX_IPSR_DATA(IP0_24_23, PWM0_B), + PINMUX_IPSR_DATA(IP0_25, CS0), + PINMUX_IPSR_MODSEL_DATA(IP0_25, HSPI_CS2_B, SEL_HSPI2_1), + PINMUX_IPSR_DATA(IP0_27_26, CS1_A26), + PINMUX_IPSR_DATA(IP0_27_26, HSPI_TX2), + PINMUX_IPSR_DATA(IP0_27_26, SDSELF_B), + PINMUX_IPSR_DATA(IP0_30_28, RD_WR), + PINMUX_IPSR_DATA(IP0_30_28, FWE), + PINMUX_IPSR_DATA(IP0_30_28, ATAG0), + PINMUX_IPSR_DATA(IP0_30_28, VI1_R7), + PINMUX_IPSR_MODSEL_DATA(IP0_30_28, HRTS1, SEL_HSCIF1_0), + PINMUX_IPSR_MODSEL_DATA(IP0_30_28, RX4_C, SEL_SCIF4_2), + + PINMUX_IPSR_DATA(IP1_1_0, EX_CS0), + PINMUX_IPSR_MODSEL_DATA(IP1_1_0, RX3_C_IRDA_RX_C, SEL_SCIF3_2), + PINMUX_IPSR_DATA(IP1_1_0, MMC0_D6), + PINMUX_IPSR_DATA(IP1_1_0, FD6), + PINMUX_IPSR_DATA(IP1_3_2, EX_CS1), + PINMUX_IPSR_DATA(IP1_3_2, MMC0_D7), + PINMUX_IPSR_DATA(IP1_3_2, FD7), + PINMUX_IPSR_DATA(IP1_6_4, EX_CS2), + PINMUX_IPSR_DATA(IP1_6_4, SD1_CLK), + PINMUX_IPSR_DATA(IP1_6_4, MMC0_CLK), + PINMUX_IPSR_DATA(IP1_6_4, FALE), + PINMUX_IPSR_DATA(IP1_6_4, ATACS00), + PINMUX_IPSR_DATA(IP1_10_7, EX_CS3), + PINMUX_IPSR_DATA(IP1_10_7, SD1_CMD), + PINMUX_IPSR_DATA(IP1_10_7, MMC0_CMD), + PINMUX_IPSR_DATA(IP1_10_7, FRE), + PINMUX_IPSR_DATA(IP1_10_7, ATACS10), + PINMUX_IPSR_DATA(IP1_10_7, VI1_R4), + PINMUX_IPSR_MODSEL_DATA(IP1_10_7, RX5_B, SEL_SCIF5_1), + PINMUX_IPSR_MODSEL_DATA(IP1_10_7, HSCK1, SEL_HSCIF1_0), + PINMUX_IPSR_MODSEL_DATA(IP1_10_7, SSI_SDATA8_B, SEL_SSI8_1), + PINMUX_IPSR_MODSEL_DATA(IP1_10_7, RTS0_B_TANS_B, SEL_SCIF0_1), + PINMUX_IPSR_MODSEL_DATA(IP1_10_7, SSI_SDATA9, SEL_SSI9_0), + PINMUX_IPSR_DATA(IP1_14_11, EX_CS4), + PINMUX_IPSR_DATA(IP1_14_11, SD1_DAT0), + PINMUX_IPSR_DATA(IP1_14_11, MMC0_D0), + PINMUX_IPSR_DATA(IP1_14_11, FD0), + PINMUX_IPSR_DATA(IP1_14_11, ATARD0), + PINMUX_IPSR_DATA(IP1_14_11, VI1_R5), + PINMUX_IPSR_MODSEL_DATA(IP1_14_11, SCK5_B, SEL_SCIF5_1), + PINMUX_IPSR_DATA(IP1_14_11, HTX1), + PINMUX_IPSR_DATA(IP1_14_11, TX2_E), + PINMUX_IPSR_DATA(IP1_14_11, TX0_B), + PINMUX_IPSR_MODSEL_DATA(IP1_14_11, SSI_SCK9, SEL_SSI9_0), + PINMUX_IPSR_DATA(IP1_18_15, EX_CS5), + PINMUX_IPSR_DATA(IP1_18_15, SD1_DAT1), + PINMUX_IPSR_DATA(IP1_18_15, MMC0_D1), + PINMUX_IPSR_DATA(IP1_18_15, FD1), + PINMUX_IPSR_DATA(IP1_18_15, ATAWR0), + PINMUX_IPSR_DATA(IP1_18_15, VI1_R6), + PINMUX_IPSR_MODSEL_DATA(IP1_18_15, HRX1, SEL_HSCIF1_0), + PINMUX_IPSR_MODSEL_DATA(IP1_18_15, RX2_E, SEL_SCIF2_4), + PINMUX_IPSR_MODSEL_DATA(IP1_18_15, RX0_B, SEL_SCIF0_1), + PINMUX_IPSR_MODSEL_DATA(IP1_18_15, SSI_WS9, SEL_SSI9_0), + PINMUX_IPSR_DATA(IP1_20_19, MLB_CLK), + PINMUX_IPSR_DATA(IP1_20_19, PWM2), + PINMUX_IPSR_MODSEL_DATA(IP1_20_19, SCK4, SEL_SCIF4_0), + PINMUX_IPSR_DATA(IP1_22_21, MLB_SIG), + PINMUX_IPSR_DATA(IP1_22_21, PWM3), + PINMUX_IPSR_DATA(IP1_22_21, TX4), + PINMUX_IPSR_DATA(IP1_24_23, MLB_DAT), + PINMUX_IPSR_DATA(IP1_24_23, PWM4), + PINMUX_IPSR_MODSEL_DATA(IP1_24_23, RX4, SEL_SCIF4_0), + PINMUX_IPSR_DATA(IP1_28_25, HTX0), + PINMUX_IPSR_DATA(IP1_28_25, TX1), + PINMUX_IPSR_DATA(IP1_28_25, SDATA), + PINMUX_IPSR_MODSEL_DATA(IP1_28_25, CTS0_C, SEL_SCIF0_2), + PINMUX_IPSR_DATA(IP1_28_25, SUB_TCK), + PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE2), + PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE10), + PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE18), + PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE26), + PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE34), + + PINMUX_IPSR_MODSEL_DATA(IP2_3_0, HRX0, SEL_HSCIF0_0), + PINMUX_IPSR_MODSEL_DATA(IP2_3_0, RX1, SEL_SCIF1_0), + PINMUX_IPSR_DATA(IP2_3_0, SCKZ), + PINMUX_IPSR_MODSEL_DATA(IP2_3_0, RTS0_C_TANS_C, SEL_SCIF0_2), + PINMUX_IPSR_DATA(IP2_3_0, SUB_TDI), + PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE3), + PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE11), + PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE19), + PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE27), + PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE35), + PINMUX_IPSR_MODSEL_DATA(IP2_7_4, HSCK0, SEL_HSCIF0_0), + PINMUX_IPSR_MODSEL_DATA(IP2_7_4, SCK1, SEL_SCIF1_0), + PINMUX_IPSR_DATA(IP2_7_4, MTS), + PINMUX_IPSR_DATA(IP2_7_4, PWM5), + PINMUX_IPSR_MODSEL_DATA(IP2_7_4, SCK0_C, SEL_SCIF0_2), + PINMUX_IPSR_MODSEL_DATA(IP2_7_4, SSI_SDATA9_B, SEL_SSI9_1), + PINMUX_IPSR_DATA(IP2_7_4, SUB_TDO), + PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE0), + PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE8), + PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE16), + PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE24), + PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE32), + PINMUX_IPSR_MODSEL_DATA(IP2_11_8, HCTS0, SEL_HSCIF0_0), + PINMUX_IPSR_MODSEL_DATA(IP2_11_8, CTS1, SEL_SCIF1_0), + PINMUX_IPSR_DATA(IP2_11_8, STM), + PINMUX_IPSR_DATA(IP2_11_8, PWM0_D), + PINMUX_IPSR_MODSEL_DATA(IP2_11_8, RX0_C, SEL_SCIF0_2), + PINMUX_IPSR_MODSEL_DATA(IP2_11_8, SCIF_CLK_C, SEL_SCIF_2), + PINMUX_IPSR_DATA(IP2_11_8, SUB_TRST), + PINMUX_IPSR_MODSEL_DATA(IP2_11_8, TCLK1_B, SEL_TMU1_1), + PINMUX_IPSR_DATA(IP2_11_8, CC5_OSCOUT), + PINMUX_IPSR_MODSEL_DATA(IP2_15_12, HRTS0, SEL_HSCIF0_0), + PINMUX_IPSR_MODSEL_DATA(IP2_15_12, RTS1_TANS, SEL_SCIF1_0), + PINMUX_IPSR_DATA(IP2_15_12, MDATA), + PINMUX_IPSR_DATA(IP2_15_12, TX0_C), + PINMUX_IPSR_DATA(IP2_15_12, SUB_TMS), + PINMUX_IPSR_DATA(IP2_15_12, CC5_STATE1), + PINMUX_IPSR_DATA(IP2_15_12, CC5_STATE9), + PINMUX_IPSR_DATA(IP2_15_12, CC5_STATE17), + PINMUX_IPSR_DATA(IP2_15_12, CC5_STATE25), + PINMUX_IPSR_DATA(IP2_15_12, CC5_STATE33), + PINMUX_IPSR_DATA(IP2_18_16, DU0_DR0), + PINMUX_IPSR_DATA(IP2_18_16, LCDOUT0), + PINMUX_IPSR_MODSEL_DATA(IP2_18_16, DREQ0, SEL_EXBUS0_0), + PINMUX_IPSR_MODSEL_DATA(IP2_18_16, GPS_CLK_B, SEL_GPS_1), + PINMUX_IPSR_DATA(IP2_18_16, AUDATA0), + PINMUX_IPSR_DATA(IP2_18_16, TX5_C), + PINMUX_IPSR_DATA(IP2_21_19, DU0_DR1), + PINMUX_IPSR_DATA(IP2_21_19, LCDOUT1), + PINMUX_IPSR_DATA(IP2_21_19, DACK0), + PINMUX_IPSR_DATA(IP2_21_19, DRACK0), + PINMUX_IPSR_MODSEL_DATA(IP2_21_19, GPS_SIGN_B, SEL_GPS_1), + PINMUX_IPSR_DATA(IP2_21_19, AUDATA1), + PINMUX_IPSR_MODSEL_DATA(IP2_21_19, RX5_C, SEL_SCIF5_2), + PINMUX_IPSR_DATA(IP2_22, DU0_DR2), + PINMUX_IPSR_DATA(IP2_22, LCDOUT2), + PINMUX_IPSR_DATA(IP2_23, DU0_DR3), + PINMUX_IPSR_DATA(IP2_23, LCDOUT3), + PINMUX_IPSR_DATA(IP2_24, DU0_DR4), + PINMUX_IPSR_DATA(IP2_24, LCDOUT4), + PINMUX_IPSR_DATA(IP2_25, DU0_DR5), + PINMUX_IPSR_DATA(IP2_25, LCDOUT5), + PINMUX_IPSR_DATA(IP2_26, DU0_DR6), + PINMUX_IPSR_DATA(IP2_26, LCDOUT6), + PINMUX_IPSR_DATA(IP2_27, DU0_DR7), + PINMUX_IPSR_DATA(IP2_27, LCDOUT7), + PINMUX_IPSR_DATA(IP2_30_28, DU0_DG0), + PINMUX_IPSR_DATA(IP2_30_28, LCDOUT8), + PINMUX_IPSR_MODSEL_DATA(IP2_30_28, DREQ1, SEL_EXBUS1_0), + PINMUX_IPSR_MODSEL_DATA(IP2_30_28, SCL2, SEL_I2C2_0), + PINMUX_IPSR_DATA(IP2_30_28, AUDATA2), + + PINMUX_IPSR_DATA(IP3_2_0, DU0_DG1), + PINMUX_IPSR_DATA(IP3_2_0, LCDOUT9), + PINMUX_IPSR_DATA(IP3_2_0, DACK1), + PINMUX_IPSR_MODSEL_DATA(IP3_2_0, SDA2, SEL_I2C2_0), + PINMUX_IPSR_DATA(IP3_2_0, AUDATA3), + PINMUX_IPSR_DATA(IP3_3, DU0_DG2), + PINMUX_IPSR_DATA(IP3_3, LCDOUT10), + PINMUX_IPSR_DATA(IP3_4, DU0_DG3), + PINMUX_IPSR_DATA(IP3_4, LCDOUT11), + PINMUX_IPSR_DATA(IP3_5, DU0_DG4), + PINMUX_IPSR_DATA(IP3_5, LCDOUT12), + PINMUX_IPSR_DATA(IP3_6, DU0_DG5), + PINMUX_IPSR_DATA(IP3_6, LCDOUT13), + PINMUX_IPSR_DATA(IP3_7, DU0_DG6), + PINMUX_IPSR_DATA(IP3_7, LCDOUT14), + PINMUX_IPSR_DATA(IP3_8, DU0_DG7), + PINMUX_IPSR_DATA(IP3_8, LCDOUT15), + PINMUX_IPSR_DATA(IP3_11_9, DU0_DB0), + PINMUX_IPSR_DATA(IP3_11_9, LCDOUT16), + PINMUX_IPSR_DATA(IP3_11_9, EX_WAIT1), + PINMUX_IPSR_MODSEL_DATA(IP3_11_9, SCL1, SEL_I2C1_0), + PINMUX_IPSR_MODSEL_DATA(IP3_11_9, TCLK1, SEL_TMU1_0), + PINMUX_IPSR_DATA(IP3_11_9, AUDATA4), + PINMUX_IPSR_DATA(IP3_14_12, DU0_DB1), + PINMUX_IPSR_DATA(IP3_14_12, LCDOUT17), + PINMUX_IPSR_DATA(IP3_14_12, EX_WAIT2), + PINMUX_IPSR_MODSEL_DATA(IP3_14_12, SDA1, SEL_I2C1_0), + PINMUX_IPSR_MODSEL_DATA(IP3_14_12, GPS_MAG_B, SEL_GPS_1), + PINMUX_IPSR_DATA(IP3_14_12, AUDATA5), + PINMUX_IPSR_MODSEL_DATA(IP3_14_12, SCK5_C, SEL_SCIF5_2), + PINMUX_IPSR_DATA(IP3_15, DU0_DB2), + PINMUX_IPSR_DATA(IP3_15, LCDOUT18), + PINMUX_IPSR_DATA(IP3_16, DU0_DB3), + PINMUX_IPSR_DATA(IP3_16, LCDOUT19), + PINMUX_IPSR_DATA(IP3_17, DU0_DB4), + PINMUX_IPSR_DATA(IP3_17, LCDOUT20), + PINMUX_IPSR_DATA(IP3_18, DU0_DB5), + PINMUX_IPSR_DATA(IP3_18, LCDOUT21), + PINMUX_IPSR_DATA(IP3_19, DU0_DB6), + PINMUX_IPSR_DATA(IP3_19, LCDOUT22), + PINMUX_IPSR_DATA(IP3_20, DU0_DB7), + PINMUX_IPSR_DATA(IP3_20, LCDOUT23), + PINMUX_IPSR_DATA(IP3_22_21, DU0_DOTCLKIN), + PINMUX_IPSR_DATA(IP3_22_21, QSTVA_QVS), + PINMUX_IPSR_DATA(IP3_22_21, TX3_D_IRDA_TX_D), + PINMUX_IPSR_MODSEL_DATA(IP3_22_21, SCL3_B, SEL_I2C3_1), + PINMUX_IPSR_DATA(IP3_23, DU0_DOTCLKOUT0), + PINMUX_IPSR_DATA(IP3_23, QCLK), + PINMUX_IPSR_DATA(IP3_26_24, DU0_DOTCLKOUT1), + PINMUX_IPSR_DATA(IP3_26_24, QSTVB_QVE), + PINMUX_IPSR_MODSEL_DATA(IP3_26_24, RX3_D_IRDA_RX_D, SEL_SCIF3_3), + PINMUX_IPSR_MODSEL_DATA(IP3_26_24, SDA3_B, SEL_I2C3_1), + PINMUX_IPSR_MODSEL_DATA(IP3_26_24, SDA2_C, SEL_I2C2_2), + PINMUX_IPSR_DATA(IP3_26_24, DACK0_B), + PINMUX_IPSR_DATA(IP3_26_24, DRACK0_B), + PINMUX_IPSR_DATA(IP3_27, DU0_EXHSYNC_DU0_HSYNC), + PINMUX_IPSR_DATA(IP3_27, QSTH_QHS), + PINMUX_IPSR_DATA(IP3_28, DU0_EXVSYNC_DU0_VSYNC), + PINMUX_IPSR_DATA(IP3_28, QSTB_QHE), + PINMUX_IPSR_DATA(IP3_31_29, DU0_EXODDF_DU0_ODDF_DISP_CDE), + PINMUX_IPSR_DATA(IP3_31_29, QCPV_QDE), + PINMUX_IPSR_DATA(IP3_31_29, CAN1_TX), + PINMUX_IPSR_DATA(IP3_31_29, TX2_C), + PINMUX_IPSR_MODSEL_DATA(IP3_31_29, SCL2_C, SEL_I2C2_2), + PINMUX_IPSR_DATA(IP3_31_29, REMOCON), + + PINMUX_IPSR_DATA(IP4_1_0, DU0_DISP), + PINMUX_IPSR_DATA(IP4_1_0, QPOLA), + PINMUX_IPSR_MODSEL_DATA(IP4_1_0, CAN_CLK_C, SEL_CANCLK_2), + PINMUX_IPSR_MODSEL_DATA(IP4_1_0, SCK2_C, SEL_SCIF2_2), + PINMUX_IPSR_DATA(IP4_4_2, DU0_CDE), + PINMUX_IPSR_DATA(IP4_4_2, QPOLB), + PINMUX_IPSR_DATA(IP4_4_2, CAN1_RX), + PINMUX_IPSR_MODSEL_DATA(IP4_4_2, RX2_C, SEL_SCIF2_2), + PINMUX_IPSR_MODSEL_DATA(IP4_4_2, DREQ0_B, SEL_EXBUS0_1), + PINMUX_IPSR_MODSEL_DATA(IP4_4_2, SSI_SCK78_B, SEL_SSI7_1), + PINMUX_IPSR_MODSEL_DATA(IP4_4_2, SCK0_B, SEL_SCIF0_1), + PINMUX_IPSR_DATA(IP4_7_5, DU1_DR0), + PINMUX_IPSR_DATA(IP4_7_5, VI2_DATA0_VI2_B0), + PINMUX_IPSR_DATA(IP4_7_5, PWM6), + PINMUX_IPSR_DATA(IP4_7_5, SD3_CLK), + PINMUX_IPSR_DATA(IP4_7_5, TX3_E_IRDA_TX_E), + PINMUX_IPSR_DATA(IP4_7_5, AUDCK), + PINMUX_IPSR_MODSEL_DATA(IP4_7_5, PWMFSW0_B, SEL_PWMFSW_1), + PINMUX_IPSR_DATA(IP4_10_8, DU1_DR1), + PINMUX_IPSR_DATA(IP4_10_8, VI2_DATA1_VI2_B1), + PINMUX_IPSR_DATA(IP4_10_8, PWM0), + PINMUX_IPSR_DATA(IP4_10_8, SD3_CMD), + PINMUX_IPSR_MODSEL_DATA(IP4_10_8, RX3_E_IRDA_RX_E, SEL_SCIF3_4), + PINMUX_IPSR_DATA(IP4_10_8, AUDSYNC), + PINMUX_IPSR_MODSEL_DATA(IP4_10_8, CTS0_D, SEL_SCIF0_3), + PINMUX_IPSR_DATA(IP4_11, DU1_DR2), + PINMUX_IPSR_DATA(IP4_11, VI2_G0), + PINMUX_IPSR_DATA(IP4_12, DU1_DR3), + PINMUX_IPSR_DATA(IP4_12, VI2_G1), + PINMUX_IPSR_DATA(IP4_13, DU1_DR4), + PINMUX_IPSR_DATA(IP4_13, VI2_G2), + PINMUX_IPSR_DATA(IP4_14, DU1_DR5), + PINMUX_IPSR_DATA(IP4_14, VI2_G3), + PINMUX_IPSR_DATA(IP4_15, DU1_DR6), + PINMUX_IPSR_DATA(IP4_15, VI2_G4), + PINMUX_IPSR_DATA(IP4_16, DU1_DR7), + PINMUX_IPSR_DATA(IP4_16, VI2_G5), + PINMUX_IPSR_DATA(IP4_19_17, DU1_DG0), + PINMUX_IPSR_DATA(IP4_19_17, VI2_DATA2_VI2_B2), + PINMUX_IPSR_MODSEL_DATA(IP4_19_17, SCL1_B, SEL_I2C1_1), + PINMUX_IPSR_DATA(IP4_19_17, SD3_DAT2), + PINMUX_IPSR_MODSEL_DATA(IP4_19_17, SCK3_E, SEL_SCIF3_4), + PINMUX_IPSR_DATA(IP4_19_17, AUDATA6), + PINMUX_IPSR_DATA(IP4_19_17, TX0_D), + PINMUX_IPSR_DATA(IP4_22_20, DU1_DG1), + PINMUX_IPSR_DATA(IP4_22_20, VI2_DATA3_VI2_B3), + PINMUX_IPSR_MODSEL_DATA(IP4_22_20, SDA1_B, SEL_I2C1_1), + PINMUX_IPSR_DATA(IP4_22_20, SD3_DAT3), + PINMUX_IPSR_MODSEL_DATA(IP4_22_20, SCK5, SEL_SCIF5_0), + PINMUX_IPSR_DATA(IP4_22_20, AUDATA7), + PINMUX_IPSR_MODSEL_DATA(IP4_22_20, RX0_D, SEL_SCIF0_3), + PINMUX_IPSR_DATA(IP4_23, DU1_DG2), + PINMUX_IPSR_DATA(IP4_23, VI2_G6), + PINMUX_IPSR_DATA(IP4_24, DU1_DG3), + PINMUX_IPSR_DATA(IP4_24, VI2_G7), + PINMUX_IPSR_DATA(IP4_25, DU1_DG4), + PINMUX_IPSR_DATA(IP4_25, VI2_R0), + PINMUX_IPSR_DATA(IP4_26, DU1_DG5), + PINMUX_IPSR_DATA(IP4_26, VI2_R1), + PINMUX_IPSR_DATA(IP4_27, DU1_DG6), + PINMUX_IPSR_DATA(IP4_27, VI2_R2), + PINMUX_IPSR_DATA(IP4_28, DU1_DG7), + PINMUX_IPSR_DATA(IP4_28, VI2_R3), + PINMUX_IPSR_DATA(IP4_31_29, DU1_DB0), + PINMUX_IPSR_DATA(IP4_31_29, VI2_DATA4_VI2_B4), + PINMUX_IPSR_MODSEL_DATA(IP4_31_29, SCL2_B, SEL_I2C2_1), + PINMUX_IPSR_DATA(IP4_31_29, SD3_DAT0), + PINMUX_IPSR_DATA(IP4_31_29, TX5), + PINMUX_IPSR_MODSEL_DATA(IP4_31_29, SCK0_D, SEL_SCIF0_3), + + PINMUX_IPSR_DATA(IP5_2_0, DU1_DB1), + PINMUX_IPSR_DATA(IP5_2_0, VI2_DATA5_VI2_B5), + PINMUX_IPSR_MODSEL_DATA(IP5_2_0, SDA2_B, SEL_I2C2_1), + PINMUX_IPSR_DATA(IP5_2_0, SD3_DAT1), + PINMUX_IPSR_MODSEL_DATA(IP5_2_0, RX5, SEL_SCIF5_0), + PINMUX_IPSR_MODSEL_DATA(IP5_2_0, RTS0_D_TANS_D, SEL_SCIF0_3), + PINMUX_IPSR_DATA(IP5_3, DU1_DB2), + PINMUX_IPSR_DATA(IP5_3, VI2_R4), + PINMUX_IPSR_DATA(IP5_4, DU1_DB3), + PINMUX_IPSR_DATA(IP5_4, VI2_R5), + PINMUX_IPSR_DATA(IP5_5, DU1_DB4), + PINMUX_IPSR_DATA(IP5_5, VI2_R6), + PINMUX_IPSR_DATA(IP5_6, DU1_DB5), + PINMUX_IPSR_DATA(IP5_6, VI2_R7), + PINMUX_IPSR_DATA(IP5_7, DU1_DB6), + PINMUX_IPSR_MODSEL_DATA(IP5_7, SCL2_D, SEL_I2C2_3), + PINMUX_IPSR_DATA(IP5_8, DU1_DB7), + PINMUX_IPSR_MODSEL_DATA(IP5_8, SDA2_D, SEL_I2C2_3), + PINMUX_IPSR_DATA(IP5_10_9, DU1_DOTCLKIN), + PINMUX_IPSR_DATA(IP5_10_9, VI2_CLKENB), + PINMUX_IPSR_MODSEL_DATA(IP5_10_9, HSPI_CS1, SEL_HSPI1_0), + PINMUX_IPSR_MODSEL_DATA(IP5_10_9, SCL1_D, SEL_I2C1_3), + PINMUX_IPSR_DATA(IP5_12_11, DU1_DOTCLKOUT), + PINMUX_IPSR_DATA(IP5_12_11, VI2_FIELD), + PINMUX_IPSR_MODSEL_DATA(IP5_12_11, SDA1_D, SEL_I2C1_3), + PINMUX_IPSR_DATA(IP5_14_13, DU1_EXHSYNC_DU1_HSYNC), + PINMUX_IPSR_DATA(IP5_14_13, VI2_HSYNC), + PINMUX_IPSR_DATA(IP5_14_13, VI3_HSYNC), + PINMUX_IPSR_DATA(IP5_16_15, DU1_EXVSYNC_DU1_VSYNC), + PINMUX_IPSR_DATA(IP5_16_15, VI2_VSYNC), + PINMUX_IPSR_DATA(IP5_16_15, VI3_VSYNC), + PINMUX_IPSR_DATA(IP5_20_17, DU1_EXODDF_DU1_ODDF_DISP_CDE), + PINMUX_IPSR_DATA(IP5_20_17, VI2_CLK), + PINMUX_IPSR_DATA(IP5_20_17, TX3_B_IRDA_TX_B), + PINMUX_IPSR_DATA(IP5_20_17, SD3_CD), + PINMUX_IPSR_DATA(IP5_20_17, HSPI_TX1), + PINMUX_IPSR_DATA(IP5_20_17, VI1_CLKENB), + PINMUX_IPSR_DATA(IP5_20_17, VI3_CLKENB), + PINMUX_IPSR_DATA(IP5_20_17, AUDIO_CLKC), + PINMUX_IPSR_DATA(IP5_20_17, TX2_D), + PINMUX_IPSR_DATA(IP5_20_17, SPEEDIN), + PINMUX_IPSR_MODSEL_DATA(IP5_20_17, GPS_SIGN_D, SEL_GPS_3), + PINMUX_IPSR_DATA(IP5_23_21, DU1_DISP), + PINMUX_IPSR_DATA(IP5_23_21, VI2_DATA6_VI2_B6), + PINMUX_IPSR_MODSEL_DATA(IP5_23_21, TCLK0, SEL_TMU0_0), + PINMUX_IPSR_DATA(IP5_23_21, QSTVA_B_QVS_B), + PINMUX_IPSR_MODSEL_DATA(IP5_23_21, HSPI_CLK1, SEL_HSPI1_0), + PINMUX_IPSR_MODSEL_DATA(IP5_23_21, SCK2_D, SEL_SCIF2_3), + PINMUX_IPSR_DATA(IP5_23_21, AUDIO_CLKOUT_B), + PINMUX_IPSR_MODSEL_DATA(IP5_23_21, GPS_MAG_D, SEL_GPS_3), + PINMUX_IPSR_DATA(IP5_27_24, DU1_CDE), + PINMUX_IPSR_DATA(IP5_27_24, VI2_DATA7_VI2_B7), + PINMUX_IPSR_MODSEL_DATA(IP5_27_24, RX3_B_IRDA_RX_B, SEL_SCIF3_1), + PINMUX_IPSR_DATA(IP5_27_24, SD3_WP), + PINMUX_IPSR_MODSEL_DATA(IP5_27_24, HSPI_RX1, SEL_HSPI1_0), + PINMUX_IPSR_DATA(IP5_27_24, VI1_FIELD), + PINMUX_IPSR_DATA(IP5_27_24, VI3_FIELD), + PINMUX_IPSR_DATA(IP5_27_24, AUDIO_CLKOUT), + PINMUX_IPSR_MODSEL_DATA(IP5_27_24, RX2_D, SEL_SCIF2_3), + PINMUX_IPSR_MODSEL_DATA(IP5_27_24, GPS_CLK_C, SEL_GPS_2), + PINMUX_IPSR_MODSEL_DATA(IP5_27_24, GPS_CLK_D, SEL_GPS_3), + PINMUX_IPSR_DATA(IP5_28, AUDIO_CLKA), + PINMUX_IPSR_DATA(IP5_28, CAN_TXCLK), + PINMUX_IPSR_DATA(IP5_30_29, AUDIO_CLKB), + PINMUX_IPSR_DATA(IP5_30_29, USB_OVC2), + PINMUX_IPSR_DATA(IP5_30_29, CAN_DEBUGOUT0), + PINMUX_IPSR_DATA(IP5_30_29, MOUT0), + + PINMUX_IPSR_DATA(IP6_1_0, SSI_SCK0129), + PINMUX_IPSR_DATA(IP6_1_0, CAN_DEBUGOUT1), + PINMUX_IPSR_DATA(IP6_1_0, MOUT1), + PINMUX_IPSR_DATA(IP6_3_2, SSI_WS0129), + PINMUX_IPSR_DATA(IP6_3_2, CAN_DEBUGOUT2), + PINMUX_IPSR_DATA(IP6_3_2, MOUT2), + PINMUX_IPSR_DATA(IP6_5_4, SSI_SDATA0), + PINMUX_IPSR_DATA(IP6_5_4, CAN_DEBUGOUT3), + PINMUX_IPSR_DATA(IP6_5_4, MOUT5), + PINMUX_IPSR_DATA(IP6_7_6, SSI_SDATA1), + PINMUX_IPSR_DATA(IP6_7_6, CAN_DEBUGOUT4), + PINMUX_IPSR_DATA(IP6_7_6, MOUT6), + PINMUX_IPSR_DATA(IP6_8, SSI_SDATA2), + PINMUX_IPSR_DATA(IP6_8, CAN_DEBUGOUT5), + PINMUX_IPSR_DATA(IP6_11_9, SSI_SCK34), + PINMUX_IPSR_DATA(IP6_11_9, CAN_DEBUGOUT6), + PINMUX_IPSR_DATA(IP6_11_9, CAN0_TX_B), + PINMUX_IPSR_MODSEL_DATA(IP6_11_9, IERX, SEL_IE_0), + PINMUX_IPSR_MODSEL_DATA(IP6_11_9, SSI_SCK9_C, SEL_SSI9_2), + PINMUX_IPSR_DATA(IP6_14_12, SSI_WS34), + PINMUX_IPSR_DATA(IP6_14_12, CAN_DEBUGOUT7), + PINMUX_IPSR_MODSEL_DATA(IP6_14_12, CAN0_RX_B, SEL_CAN0_1), + PINMUX_IPSR_DATA(IP6_14_12, IETX), + PINMUX_IPSR_MODSEL_DATA(IP6_14_12, SSI_WS9_C, SEL_SSI9_2), + PINMUX_IPSR_DATA(IP6_17_15, SSI_SDATA3), + PINMUX_IPSR_DATA(IP6_17_15, PWM0_C), + PINMUX_IPSR_DATA(IP6_17_15, CAN_DEBUGOUT8), + PINMUX_IPSR_MODSEL_DATA(IP6_17_15, CAN_CLK_B, SEL_CANCLK_1), + PINMUX_IPSR_MODSEL_DATA(IP6_17_15, IECLK, SEL_IE_0), + PINMUX_IPSR_MODSEL_DATA(IP6_17_15, SCIF_CLK_B, SEL_SCIF_1), + PINMUX_IPSR_MODSEL_DATA(IP6_17_15, TCLK0_B, SEL_TMU0_1), + PINMUX_IPSR_DATA(IP6_19_18, SSI_SDATA4), + PINMUX_IPSR_DATA(IP6_19_18, CAN_DEBUGOUT9), + PINMUX_IPSR_MODSEL_DATA(IP6_19_18, SSI_SDATA9_C, SEL_SSI9_2), + PINMUX_IPSR_DATA(IP6_22_20, SSI_SCK5), + PINMUX_IPSR_DATA(IP6_22_20, ADICLK), + PINMUX_IPSR_DATA(IP6_22_20, CAN_DEBUGOUT10), + PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCK3, SEL_SCIF3_0), + PINMUX_IPSR_MODSEL_DATA(IP6_22_20, TCLK0_D, SEL_TMU0_3), + PINMUX_IPSR_DATA(IP6_24_23, SSI_WS5), + PINMUX_IPSR_MODSEL_DATA(IP6_24_23, ADICS_SAMP, SEL_ADI_0), + PINMUX_IPSR_DATA(IP6_24_23, CAN_DEBUGOUT11), + PINMUX_IPSR_DATA(IP6_24_23, TX3_IRDA_TX), + PINMUX_IPSR_DATA(IP6_26_25, SSI_SDATA5), + PINMUX_IPSR_MODSEL_DATA(IP6_26_25, ADIDATA, SEL_ADI_0), + PINMUX_IPSR_DATA(IP6_26_25, CAN_DEBUGOUT12), + PINMUX_IPSR_MODSEL_DATA(IP6_26_25, RX3_IRDA_RX, SEL_SCIF3_0), + PINMUX_IPSR_DATA(IP6_30_29, SSI_SCK6), + PINMUX_IPSR_DATA(IP6_30_29, ADICHS0), + PINMUX_IPSR_DATA(IP6_30_29, CAN0_TX), + PINMUX_IPSR_MODSEL_DATA(IP6_30_29, IERX_B, SEL_IE_1), + + PINMUX_IPSR_DATA(IP7_1_0, SSI_WS6), + PINMUX_IPSR_DATA(IP7_1_0, ADICHS1), + PINMUX_IPSR_MODSEL_DATA(IP7_1_0, CAN0_RX, SEL_CAN0_0), + PINMUX_IPSR_DATA(IP7_1_0, IETX_B), + PINMUX_IPSR_DATA(IP7_3_2, SSI_SDATA6), + PINMUX_IPSR_DATA(IP7_3_2, ADICHS2), + PINMUX_IPSR_MODSEL_DATA(IP7_3_2, CAN_CLK, SEL_CANCLK_0), + PINMUX_IPSR_MODSEL_DATA(IP7_3_2, IECLK_B, SEL_IE_1), + PINMUX_IPSR_MODSEL_DATA(IP7_6_4, SSI_SCK78, SEL_SSI7_0), + PINMUX_IPSR_DATA(IP7_6_4, CAN_DEBUGOUT13), + PINMUX_IPSR_MODSEL_DATA(IP7_6_4, IRQ0_B, SEL_INT0_1), + PINMUX_IPSR_MODSEL_DATA(IP7_6_4, SSI_SCK9_B, SEL_SSI9_1), + PINMUX_IPSR_MODSEL_DATA(IP7_6_4, HSPI_CLK1_C, SEL_HSPI1_2), + PINMUX_IPSR_MODSEL_DATA(IP7_9_7, SSI_WS78, SEL_SSI7_0), + PINMUX_IPSR_DATA(IP7_9_7, CAN_DEBUGOUT14), + PINMUX_IPSR_MODSEL_DATA(IP7_9_7, IRQ1_B, SEL_INT1_1), + PINMUX_IPSR_MODSEL_DATA(IP7_9_7, SSI_WS9_B, SEL_SSI9_1), + PINMUX_IPSR_MODSEL_DATA(IP7_9_7, HSPI_CS1_C, SEL_HSPI1_2), + PINMUX_IPSR_MODSEL_DATA(IP7_12_10, SSI_SDATA7, SEL_SSI7_0), + PINMUX_IPSR_DATA(IP7_12_10, CAN_DEBUGOUT15), + PINMUX_IPSR_MODSEL_DATA(IP7_12_10, IRQ2_B, SEL_INT2_1), + PINMUX_IPSR_MODSEL_DATA(IP7_12_10, TCLK1_C, SEL_TMU1_2), + PINMUX_IPSR_DATA(IP7_12_10, HSPI_TX1_C), + PINMUX_IPSR_MODSEL_DATA(IP7_14_13, SSI_SDATA8, SEL_SSI8_0), + PINMUX_IPSR_DATA(IP7_14_13, VSP), + PINMUX_IPSR_MODSEL_DATA(IP7_14_13, IRQ3_B, SEL_INT3_1), + PINMUX_IPSR_MODSEL_DATA(IP7_14_13, HSPI_RX1_C, SEL_HSPI1_2), + PINMUX_IPSR_DATA(IP7_16_15, SD0_CLK), + PINMUX_IPSR_DATA(IP7_16_15, ATACS01), + PINMUX_IPSR_MODSEL_DATA(IP7_16_15, SCK1_B, SEL_SCIF1_1), + PINMUX_IPSR_DATA(IP7_18_17, SD0_CMD), + PINMUX_IPSR_DATA(IP7_18_17, ATACS11), + PINMUX_IPSR_DATA(IP7_18_17, TX1_B), + PINMUX_IPSR_DATA(IP7_18_17, CC5_TDO), + PINMUX_IPSR_DATA(IP7_20_19, SD0_DAT0), + PINMUX_IPSR_DATA(IP7_20_19, ATADIR1), + PINMUX_IPSR_MODSEL_DATA(IP7_20_19, RX1_B, SEL_SCIF1_1), + PINMUX_IPSR_DATA(IP7_20_19, CC5_TRST), + PINMUX_IPSR_DATA(IP7_22_21, SD0_DAT1), + PINMUX_IPSR_DATA(IP7_22_21, ATAG1), + PINMUX_IPSR_MODSEL_DATA(IP7_22_21, SCK2_B, SEL_SCIF2_1), + PINMUX_IPSR_DATA(IP7_22_21, CC5_TMS), + PINMUX_IPSR_DATA(IP7_24_23, SD0_DAT2), + PINMUX_IPSR_DATA(IP7_24_23, ATARD1), + PINMUX_IPSR_DATA(IP7_24_23, TX2_B), + PINMUX_IPSR_DATA(IP7_24_23, CC5_TCK), + PINMUX_IPSR_DATA(IP7_26_25, SD0_DAT3), + PINMUX_IPSR_DATA(IP7_26_25, ATAWR1), + PINMUX_IPSR_MODSEL_DATA(IP7_26_25, RX2_B, SEL_SCIF2_1), + PINMUX_IPSR_DATA(IP7_26_25, CC5_TDI), + PINMUX_IPSR_DATA(IP7_28_27, SD0_CD), + PINMUX_IPSR_MODSEL_DATA(IP7_28_27, DREQ2, SEL_EXBUS2_0), + PINMUX_IPSR_MODSEL_DATA(IP7_28_27, RTS1_B_TANS_B, SEL_SCIF1_1), + PINMUX_IPSR_DATA(IP7_30_29, SD0_WP), + PINMUX_IPSR_DATA(IP7_30_29, DACK2), + PINMUX_IPSR_MODSEL_DATA(IP7_30_29, CTS1_B, SEL_SCIF1_1), + + PINMUX_IPSR_DATA(IP8_3_0, HSPI_CLK0), + PINMUX_IPSR_MODSEL_DATA(IP8_3_0, CTS0, SEL_SCIF0_0), + PINMUX_IPSR_DATA(IP8_3_0, USB_OVC0), + PINMUX_IPSR_DATA(IP8_3_0, AD_CLK), + PINMUX_IPSR_DATA(IP8_3_0, CC5_STATE4), + PINMUX_IPSR_DATA(IP8_3_0, CC5_STATE12), + PINMUX_IPSR_DATA(IP8_3_0, CC5_STATE20), + PINMUX_IPSR_DATA(IP8_3_0, CC5_STATE28), + PINMUX_IPSR_DATA(IP8_3_0, CC5_STATE36), + PINMUX_IPSR_DATA(IP8_7_4, HSPI_CS0), + PINMUX_IPSR_MODSEL_DATA(IP8_7_4, RTS0_TANS, SEL_SCIF0_0), + PINMUX_IPSR_DATA(IP8_7_4, USB_OVC1), + PINMUX_IPSR_DATA(IP8_7_4, AD_DI), + PINMUX_IPSR_DATA(IP8_7_4, CC5_STATE5), + PINMUX_IPSR_DATA(IP8_7_4, CC5_STATE13), + PINMUX_IPSR_DATA(IP8_7_4, CC5_STATE21), + PINMUX_IPSR_DATA(IP8_7_4, CC5_STATE29), + PINMUX_IPSR_DATA(IP8_7_4, CC5_STATE37), + PINMUX_IPSR_DATA(IP8_11_8, HSPI_TX0), + PINMUX_IPSR_DATA(IP8_11_8, TX0), + PINMUX_IPSR_DATA(IP8_11_8, CAN_DEBUG_HW_TRIGGER), + PINMUX_IPSR_DATA(IP8_11_8, AD_DO), + PINMUX_IPSR_DATA(IP8_11_8, CC5_STATE6), + PINMUX_IPSR_DATA(IP8_11_8, CC5_STATE14), + PINMUX_IPSR_DATA(IP8_11_8, CC5_STATE22), + PINMUX_IPSR_DATA(IP8_11_8, CC5_STATE30), + PINMUX_IPSR_DATA(IP8_11_8, CC5_STATE38), + PINMUX_IPSR_DATA(IP8_15_12, HSPI_RX0), + PINMUX_IPSR_MODSEL_DATA(IP8_15_12, RX0, SEL_SCIF0_0), + PINMUX_IPSR_DATA(IP8_15_12, CAN_STEP0), + PINMUX_IPSR_DATA(IP8_15_12, AD_NCS), + PINMUX_IPSR_DATA(IP8_15_12, CC5_STATE7), + PINMUX_IPSR_DATA(IP8_15_12, CC5_STATE15), + PINMUX_IPSR_DATA(IP8_15_12, CC5_STATE23), + PINMUX_IPSR_DATA(IP8_15_12, CC5_STATE31), + PINMUX_IPSR_DATA(IP8_15_12, CC5_STATE39), + PINMUX_IPSR_DATA(IP8_17_16, FMCLK), + PINMUX_IPSR_DATA(IP8_17_16, RDS_CLK), + PINMUX_IPSR_DATA(IP8_17_16, PCMOE), + PINMUX_IPSR_DATA(IP8_18, BPFCLK), + PINMUX_IPSR_DATA(IP8_18, PCMWE), + PINMUX_IPSR_DATA(IP8_19, FMIN), + PINMUX_IPSR_DATA(IP8_19, RDS_DATA), + PINMUX_IPSR_DATA(IP8_20, VI0_CLK), + PINMUX_IPSR_DATA(IP8_20, MMC1_CLK), + PINMUX_IPSR_DATA(IP8_22_21, VI0_CLKENB), + PINMUX_IPSR_DATA(IP8_22_21, TX1_C), + PINMUX_IPSR_DATA(IP8_22_21, HTX1_B), + PINMUX_IPSR_DATA(IP8_22_21, MT1_SYNC), + PINMUX_IPSR_DATA(IP8_24_23, VI0_FIELD), + PINMUX_IPSR_MODSEL_DATA(IP8_24_23, RX1_C, SEL_SCIF1_2), + PINMUX_IPSR_MODSEL_DATA(IP8_24_23, HRX1_B, SEL_HSCIF1_1), + PINMUX_IPSR_DATA(IP8_27_25, VI0_HSYNC), + PINMUX_IPSR_MODSEL_DATA(IP8_27_25, VI0_DATA0_B_VI0_B0_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP8_27_25, CTS1_C, SEL_SCIF1_2), + PINMUX_IPSR_DATA(IP8_27_25, TX4_D), + PINMUX_IPSR_DATA(IP8_27_25, MMC1_CMD), + PINMUX_IPSR_MODSEL_DATA(IP8_27_25, HSCK1_B, SEL_HSCIF1_1), + PINMUX_IPSR_DATA(IP8_30_28, VI0_VSYNC), + PINMUX_IPSR_MODSEL_DATA(IP8_30_28, VI0_DATA1_B_VI0_B1_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP8_30_28, RTS1_C_TANS_C, SEL_SCIF1_2), + PINMUX_IPSR_MODSEL_DATA(IP8_30_28, RX4_D, SEL_SCIF4_3), + PINMUX_IPSR_MODSEL_DATA(IP8_30_28, PWMFSW0_C, SEL_PWMFSW_2), + + PINMUX_IPSR_MODSEL_DATA(IP9_1_0, VI0_DATA0_VI0_B0, SEL_VI0_0), + PINMUX_IPSR_MODSEL_DATA(IP9_1_0, HRTS1_B, SEL_HSCIF1_1), + PINMUX_IPSR_DATA(IP9_1_0, MT1_VCXO), + PINMUX_IPSR_MODSEL_DATA(IP9_3_2, VI0_DATA1_VI0_B1, SEL_VI0_0), + PINMUX_IPSR_MODSEL_DATA(IP9_3_2, HCTS1_B, SEL_HSCIF1_1), + PINMUX_IPSR_DATA(IP9_3_2, MT1_PWM), + PINMUX_IPSR_DATA(IP9_4, VI0_DATA2_VI0_B2), + PINMUX_IPSR_DATA(IP9_4, MMC1_D0), + PINMUX_IPSR_DATA(IP9_5, VI0_DATA3_VI0_B3), + PINMUX_IPSR_DATA(IP9_5, MMC1_D1), + PINMUX_IPSR_DATA(IP9_6, VI0_DATA4_VI0_B4), + PINMUX_IPSR_DATA(IP9_6, MMC1_D2), + PINMUX_IPSR_DATA(IP9_7, VI0_DATA5_VI0_B5), + PINMUX_IPSR_DATA(IP9_7, MMC1_D3), + PINMUX_IPSR_DATA(IP9_9_8, VI0_DATA6_VI0_B6), + PINMUX_IPSR_DATA(IP9_9_8, MMC1_D4), + PINMUX_IPSR_DATA(IP9_9_8, ARM_TRACEDATA_0), + PINMUX_IPSR_DATA(IP9_11_10, VI0_DATA7_VI0_B7), + PINMUX_IPSR_DATA(IP9_11_10, MMC1_D5), + PINMUX_IPSR_DATA(IP9_11_10, ARM_TRACEDATA_1), + PINMUX_IPSR_DATA(IP9_13_12, VI0_G0), + PINMUX_IPSR_MODSEL_DATA(IP9_13_12, SSI_SCK78_C, SEL_SSI7_2), + PINMUX_IPSR_MODSEL_DATA(IP9_13_12, IRQ0, SEL_INT0_0), + PINMUX_IPSR_DATA(IP9_13_12, ARM_TRACEDATA_2), + PINMUX_IPSR_DATA(IP9_15_14, VI0_G1), + PINMUX_IPSR_MODSEL_DATA(IP9_15_14, SSI_WS78_C, SEL_SSI7_2), + PINMUX_IPSR_MODSEL_DATA(IP9_15_14, IRQ1, SEL_INT1_0), + PINMUX_IPSR_DATA(IP9_15_14, ARM_TRACEDATA_3), + PINMUX_IPSR_DATA(IP9_18_16, VI0_G2), + PINMUX_IPSR_DATA(IP9_18_16, ETH_TXD1), + PINMUX_IPSR_DATA(IP9_18_16, MMC1_D6), + PINMUX_IPSR_DATA(IP9_18_16, ARM_TRACEDATA_4), + PINMUX_IPSR_DATA(IP9_18_16, TS_SPSYNC0), + PINMUX_IPSR_DATA(IP9_21_19, VI0_G3), + PINMUX_IPSR_DATA(IP9_21_19, ETH_CRS_DV), + PINMUX_IPSR_DATA(IP9_21_19, MMC1_D7), + PINMUX_IPSR_DATA(IP9_21_19, ARM_TRACEDATA_5), + PINMUX_IPSR_DATA(IP9_21_19, TS_SDAT0), + PINMUX_IPSR_DATA(IP9_23_22, VI0_G4), + PINMUX_IPSR_DATA(IP9_23_22, ETH_TX_EN), + PINMUX_IPSR_MODSEL_DATA(IP9_23_22, SD2_DAT0_B, SEL_SD2_1), + PINMUX_IPSR_DATA(IP9_23_22, ARM_TRACEDATA_6), + PINMUX_IPSR_DATA(IP9_25_24, VI0_G5), + PINMUX_IPSR_DATA(IP9_25_24, ETH_RX_ER), + PINMUX_IPSR_MODSEL_DATA(IP9_25_24, SD2_DAT1_B, SEL_SD2_1), + PINMUX_IPSR_DATA(IP9_25_24, ARM_TRACEDATA_7), + PINMUX_IPSR_DATA(IP9_27_26, VI0_G6), + PINMUX_IPSR_DATA(IP9_27_26, ETH_RXD0), + PINMUX_IPSR_MODSEL_DATA(IP9_27_26, SD2_DAT2_B, SEL_SD2_1), + PINMUX_IPSR_DATA(IP9_27_26, ARM_TRACEDATA_8), + PINMUX_IPSR_DATA(IP9_29_28, VI0_G7), + PINMUX_IPSR_DATA(IP9_29_28, ETH_RXD1), + PINMUX_IPSR_MODSEL_DATA(IP9_29_28, SD2_DAT3_B, SEL_SD2_1), + PINMUX_IPSR_DATA(IP9_29_28, ARM_TRACEDATA_9), + + PINMUX_IPSR_DATA(IP10_2_0, VI0_R0), + PINMUX_IPSR_MODSEL_DATA(IP10_2_0, SSI_SDATA7_C, SEL_SSI7_2), + PINMUX_IPSR_MODSEL_DATA(IP10_2_0, SCK1_C, SEL_SCIF1_2), + PINMUX_IPSR_MODSEL_DATA(IP10_2_0, DREQ1_B, SEL_EXBUS1_0), + PINMUX_IPSR_DATA(IP10_2_0, ARM_TRACEDATA_10), + PINMUX_IPSR_MODSEL_DATA(IP10_2_0, DREQ0_C, SEL_EXBUS0_2), + PINMUX_IPSR_DATA(IP10_5_3, VI0_R1), + PINMUX_IPSR_MODSEL_DATA(IP10_5_3, SSI_SDATA8_C, SEL_SSI8_2), + PINMUX_IPSR_DATA(IP10_5_3, DACK1_B), + PINMUX_IPSR_DATA(IP10_5_3, ARM_TRACEDATA_11), + PINMUX_IPSR_DATA(IP10_5_3, DACK0_C), + PINMUX_IPSR_DATA(IP10_5_3, DRACK0_C), + PINMUX_IPSR_DATA(IP10_8_6, VI0_R2), + PINMUX_IPSR_DATA(IP10_8_6, ETH_LINK), + PINMUX_IPSR_DATA(IP10_8_6, SD2_CLK_B), + PINMUX_IPSR_MODSEL_DATA(IP10_8_6, IRQ2, SEL_INT2_0), + PINMUX_IPSR_DATA(IP10_8_6, ARM_TRACEDATA_12), + PINMUX_IPSR_DATA(IP10_11_9, VI0_R3), + PINMUX_IPSR_DATA(IP10_11_9, ETH_MAGIC), + PINMUX_IPSR_MODSEL_DATA(IP10_11_9, SD2_CMD_B, SEL_SD2_1), + PINMUX_IPSR_MODSEL_DATA(IP10_11_9, IRQ3, SEL_INT3_0), + PINMUX_IPSR_DATA(IP10_11_9, ARM_TRACEDATA_13), + PINMUX_IPSR_DATA(IP10_14_12, VI0_R4), + PINMUX_IPSR_DATA(IP10_14_12, ETH_REFCLK), + PINMUX_IPSR_MODSEL_DATA(IP10_14_12, SD2_CD_B, SEL_SD2_1), + PINMUX_IPSR_MODSEL_DATA(IP10_14_12, HSPI_CLK1_B, SEL_HSPI1_1), + PINMUX_IPSR_DATA(IP10_14_12, ARM_TRACEDATA_14), + PINMUX_IPSR_DATA(IP10_14_12, MT1_CLK), + PINMUX_IPSR_DATA(IP10_14_12, TS_SCK0), + PINMUX_IPSR_DATA(IP10_17_15, VI0_R5), + PINMUX_IPSR_DATA(IP10_17_15, ETH_TXD0), + PINMUX_IPSR_MODSEL_DATA(IP10_17_15, SD2_WP_B, SEL_SD2_1), + PINMUX_IPSR_MODSEL_DATA(IP10_17_15, HSPI_CS1_B, SEL_HSPI1_1), + PINMUX_IPSR_DATA(IP10_17_15, ARM_TRACEDATA_15), + PINMUX_IPSR_DATA(IP10_17_15, MT1_D), + PINMUX_IPSR_DATA(IP10_17_15, TS_SDEN0), + PINMUX_IPSR_DATA(IP10_20_18, VI0_R6), + PINMUX_IPSR_DATA(IP10_20_18, ETH_MDC), + PINMUX_IPSR_MODSEL_DATA(IP10_20_18, DREQ2_C, SEL_EXBUS2_2), + PINMUX_IPSR_DATA(IP10_20_18, HSPI_TX1_B), + PINMUX_IPSR_DATA(IP10_20_18, TRACECLK), + PINMUX_IPSR_DATA(IP10_20_18, MT1_BEN), + PINMUX_IPSR_MODSEL_DATA(IP10_20_18, PWMFSW0_D, SEL_PWMFSW_3), + PINMUX_IPSR_DATA(IP10_23_21, VI0_R7), + PINMUX_IPSR_DATA(IP10_23_21, ETH_MDIO), + PINMUX_IPSR_DATA(IP10_23_21, DACK2_C), + PINMUX_IPSR_MODSEL_DATA(IP10_23_21, HSPI_RX1_B, SEL_HSPI1_1), + PINMUX_IPSR_MODSEL_DATA(IP10_23_21, SCIF_CLK_D, SEL_SCIF_3), + PINMUX_IPSR_DATA(IP10_23_21, TRACECTL), + PINMUX_IPSR_DATA(IP10_23_21, MT1_PEN), + PINMUX_IPSR_DATA(IP10_25_24, VI1_CLK), + PINMUX_IPSR_MODSEL_DATA(IP10_25_24, SIM_D, SEL_SIM_0), + PINMUX_IPSR_MODSEL_DATA(IP10_25_24, SDA3, SEL_I2C3_0), + PINMUX_IPSR_DATA(IP10_28_26, VI1_HSYNC), + PINMUX_IPSR_DATA(IP10_28_26, VI3_CLK), + PINMUX_IPSR_DATA(IP10_28_26, SSI_SCK4), + PINMUX_IPSR_MODSEL_DATA(IP10_28_26, GPS_SIGN_C, SEL_GPS_2), + PINMUX_IPSR_MODSEL_DATA(IP10_28_26, PWMFSW0_E, SEL_PWMFSW_4), + PINMUX_IPSR_DATA(IP10_31_29, VI1_VSYNC), + PINMUX_IPSR_DATA(IP10_31_29, AUDIO_CLKOUT_C), + PINMUX_IPSR_DATA(IP10_31_29, SSI_WS4), + PINMUX_IPSR_DATA(IP10_31_29, SIM_CLK), + PINMUX_IPSR_MODSEL_DATA(IP10_31_29, GPS_MAG_C, SEL_GPS_2), + PINMUX_IPSR_DATA(IP10_31_29, SPV_TRST), + PINMUX_IPSR_MODSEL_DATA(IP10_31_29, SCL3, SEL_I2C3_0), + + PINMUX_IPSR_DATA(IP11_2_0, VI1_DATA0_VI1_B0), + PINMUX_IPSR_MODSEL_DATA(IP11_2_0, SD2_DAT0, SEL_SD2_0), + PINMUX_IPSR_DATA(IP11_2_0, SIM_RST), + PINMUX_IPSR_DATA(IP11_2_0, SPV_TCK), + PINMUX_IPSR_DATA(IP11_2_0, ADICLK_B), + PINMUX_IPSR_DATA(IP11_5_3, VI1_DATA1_VI1_B1), + PINMUX_IPSR_MODSEL_DATA(IP11_5_3, SD2_DAT1, SEL_SD2_0), + PINMUX_IPSR_DATA(IP11_5_3, MT0_CLK), + PINMUX_IPSR_DATA(IP11_5_3, SPV_TMS), + PINMUX_IPSR_MODSEL_DATA(IP11_5_3, ADICS_B_SAMP_B, SEL_ADI_1), + PINMUX_IPSR_DATA(IP11_8_6, VI1_DATA2_VI1_B2), + PINMUX_IPSR_MODSEL_DATA(IP11_8_6, SD2_DAT2, SEL_SD2_0), + PINMUX_IPSR_DATA(IP11_8_6, MT0_D), + PINMUX_IPSR_DATA(IP11_8_6, SPVTDI), + PINMUX_IPSR_MODSEL_DATA(IP11_8_6, ADIDATA_B, SEL_ADI_1), + PINMUX_IPSR_DATA(IP11_11_9, VI1_DATA3_VI1_B3), + PINMUX_IPSR_MODSEL_DATA(IP11_11_9, SD2_DAT3, SEL_SD2_0), + PINMUX_IPSR_DATA(IP11_11_9, MT0_BEN), + PINMUX_IPSR_DATA(IP11_11_9, SPV_TDO), + PINMUX_IPSR_DATA(IP11_11_9, ADICHS0_B), + PINMUX_IPSR_DATA(IP11_14_12, VI1_DATA4_VI1_B4), + PINMUX_IPSR_DATA(IP11_14_12, SD2_CLK), + PINMUX_IPSR_DATA(IP11_14_12, MT0_PEN), + PINMUX_IPSR_DATA(IP11_14_12, SPA_TRST), + PINMUX_IPSR_MODSEL_DATA(IP11_14_12, HSPI_CLK1_D, SEL_HSPI1_3), + PINMUX_IPSR_DATA(IP11_14_12, ADICHS1_B), + PINMUX_IPSR_DATA(IP11_17_15, VI1_DATA5_VI1_B5), + PINMUX_IPSR_MODSEL_DATA(IP11_17_15, SD2_CMD, SEL_SD2_0), + PINMUX_IPSR_DATA(IP11_17_15, MT0_SYNC), + PINMUX_IPSR_DATA(IP11_17_15, SPA_TCK), + PINMUX_IPSR_MODSEL_DATA(IP11_17_15, HSPI_CS1_D, SEL_HSPI1_3), + PINMUX_IPSR_DATA(IP11_17_15, ADICHS2_B), + PINMUX_IPSR_DATA(IP11_20_18, VI1_DATA6_VI1_B6), + PINMUX_IPSR_MODSEL_DATA(IP11_20_18, SD2_CD, SEL_SD2_0), + PINMUX_IPSR_DATA(IP11_20_18, MT0_VCXO), + PINMUX_IPSR_DATA(IP11_20_18, SPA_TMS), + PINMUX_IPSR_DATA(IP11_20_18, HSPI_TX1_D), + PINMUX_IPSR_DATA(IP11_23_21, VI1_DATA7_VI1_B7), + PINMUX_IPSR_MODSEL_DATA(IP11_23_21, SD2_WP, SEL_SD2_0), + PINMUX_IPSR_DATA(IP11_23_21, MT0_PWM), + PINMUX_IPSR_DATA(IP11_23_21, SPA_TDI), + PINMUX_IPSR_MODSEL_DATA(IP11_23_21, HSPI_RX1_D, SEL_HSPI1_3), + PINMUX_IPSR_DATA(IP11_26_24, VI1_G0), + PINMUX_IPSR_DATA(IP11_26_24, VI3_DATA0), + PINMUX_IPSR_DATA(IP11_26_24, DU1_DOTCLKOUT1), + PINMUX_IPSR_DATA(IP11_26_24, TS_SCK1), + PINMUX_IPSR_MODSEL_DATA(IP11_26_24, DREQ2_B, SEL_EXBUS2_1), + PINMUX_IPSR_DATA(IP11_26_24, TX2), + PINMUX_IPSR_DATA(IP11_26_24, SPA_TDO), + PINMUX_IPSR_MODSEL_DATA(IP11_26_24, HCTS0_B, SEL_HSCIF0_1), + PINMUX_IPSR_DATA(IP11_29_27, VI1_G1), + PINMUX_IPSR_DATA(IP11_29_27, VI3_DATA1), + PINMUX_IPSR_DATA(IP11_29_27, SSI_SCK1), + PINMUX_IPSR_DATA(IP11_29_27, TS_SDEN1), + PINMUX_IPSR_DATA(IP11_29_27, DACK2_B), + PINMUX_IPSR_MODSEL_DATA(IP11_29_27, RX2, SEL_SCIF2_0), + PINMUX_IPSR_MODSEL_DATA(IP11_29_27, HRTS0_B, SEL_HSCIF0_1), + + PINMUX_IPSR_DATA(IP12_2_0, VI1_G2), + PINMUX_IPSR_DATA(IP12_2_0, VI3_DATA2), + PINMUX_IPSR_DATA(IP12_2_0, SSI_WS1), + PINMUX_IPSR_DATA(IP12_2_0, TS_SPSYNC1), + PINMUX_IPSR_MODSEL_DATA(IP12_2_0, SCK2, SEL_SCIF2_0), + PINMUX_IPSR_MODSEL_DATA(IP12_2_0, HSCK0_B, SEL_HSCIF0_1), + PINMUX_IPSR_DATA(IP12_5_3, VI1_G3), + PINMUX_IPSR_DATA(IP12_5_3, VI3_DATA3), + PINMUX_IPSR_DATA(IP12_5_3, SSI_SCK2), + PINMUX_IPSR_DATA(IP12_5_3, TS_SDAT1), + PINMUX_IPSR_MODSEL_DATA(IP12_5_3, SCL1_C, SEL_I2C1_2), + PINMUX_IPSR_DATA(IP12_5_3, HTX0_B), + PINMUX_IPSR_DATA(IP12_8_6, VI1_G4), + PINMUX_IPSR_DATA(IP12_8_6, VI3_DATA4), + PINMUX_IPSR_DATA(IP12_8_6, SSI_WS2), + PINMUX_IPSR_MODSEL_DATA(IP12_8_6, SDA1_C, SEL_I2C1_2), + PINMUX_IPSR_DATA(IP12_8_6, SIM_RST_B), + PINMUX_IPSR_MODSEL_DATA(IP12_8_6, HRX0_B, SEL_HSCIF0_1), + PINMUX_IPSR_DATA(IP12_11_9, VI1_G5), + PINMUX_IPSR_DATA(IP12_11_9, VI3_DATA5), + PINMUX_IPSR_MODSEL_DATA(IP12_11_9, GPS_CLK, SEL_GPS_0), + PINMUX_IPSR_DATA(IP12_11_9, FSE), + PINMUX_IPSR_DATA(IP12_11_9, TX4_B), + PINMUX_IPSR_MODSEL_DATA(IP12_11_9, SIM_D_B, SEL_SIM_1), + PINMUX_IPSR_DATA(IP12_14_12, VI1_G6), + PINMUX_IPSR_DATA(IP12_14_12, VI3_DATA6), + PINMUX_IPSR_MODSEL_DATA(IP12_14_12, GPS_SIGN, SEL_GPS_0), + PINMUX_IPSR_DATA(IP12_14_12, FRB), + PINMUX_IPSR_MODSEL_DATA(IP12_14_12, RX4_B, SEL_SCIF4_1), + PINMUX_IPSR_DATA(IP12_14_12, SIM_CLK_B), + PINMUX_IPSR_DATA(IP12_17_15, VI1_G7), + PINMUX_IPSR_DATA(IP12_17_15, VI3_DATA7), + PINMUX_IPSR_MODSEL_DATA(IP12_17_15, GPS_MAG, SEL_GPS_0), + PINMUX_IPSR_DATA(IP12_17_15, FCE), + PINMUX_IPSR_MODSEL_DATA(IP12_17_15, SCK4_B, SEL_SCIF4_1), +}; + +static struct pinmux_gpio pinmux_gpios[] = { + PINMUX_GPIO_GP_ALL(), + GPIO_FN(AVS1), GPIO_FN(AVS2), GPIO_FN(A17), GPIO_FN(A18), + GPIO_FN(A19), + + /* IPSR0 */ + GPIO_FN(PENC2), GPIO_FN(SCK0), GPIO_FN(PWM1), GPIO_FN(PWMFSW0), + GPIO_FN(SCIF_CLK), GPIO_FN(TCLK0_C), GPIO_FN(BS), GPIO_FN(SD1_DAT2), + GPIO_FN(MMC0_D2), GPIO_FN(FD2), GPIO_FN(ATADIR0), GPIO_FN(SDSELF), + GPIO_FN(HCTS1), GPIO_FN(TX4_C), GPIO_FN(A0), GPIO_FN(SD1_DAT3), + GPIO_FN(MMC0_D3), GPIO_FN(FD3), GPIO_FN(A20), GPIO_FN(TX5_D), + GPIO_FN(HSPI_TX2_B), GPIO_FN(A21), GPIO_FN(SCK5_D), + GPIO_FN(HSPI_CLK2_B), GPIO_FN(A22), GPIO_FN(RX5_D), + GPIO_FN(HSPI_RX2_B), GPIO_FN(VI1_R0), GPIO_FN(A23), GPIO_FN(FCLE), + GPIO_FN(HSPI_CLK2), GPIO_FN(VI1_R1), GPIO_FN(A24), GPIO_FN(SD1_CD), + GPIO_FN(MMC0_D4), GPIO_FN(FD4), GPIO_FN(HSPI_CS2), GPIO_FN(VI1_R2), + GPIO_FN(SSI_WS78_B), GPIO_FN(A25), GPIO_FN(SD1_WP), GPIO_FN(MMC0_D5), + GPIO_FN(FD5), GPIO_FN(HSPI_RX2), GPIO_FN(VI1_R3), GPIO_FN(TX5_B), + GPIO_FN(SSI_SDATA7_B), GPIO_FN(CTS0_B), GPIO_FN(CLKOUT), + GPIO_FN(TX3C_IRDA_TX_C), GPIO_FN(PWM0_B), GPIO_FN(CS0), + GPIO_FN(HSPI_CS2_B), GPIO_FN(CS1_A26), GPIO_FN(HSPI_TX2), + GPIO_FN(SDSELF_B), GPIO_FN(RD_WR), GPIO_FN(FWE), GPIO_FN(ATAG0), + GPIO_FN(VI1_R7), GPIO_FN(HRTS1), GPIO_FN(RX4_C), + + /* IPSR1 */ + GPIO_FN(EX_CS0), GPIO_FN(RX3_C_IRDA_RX_C), GPIO_FN(MMC0_D6), + GPIO_FN(FD6), GPIO_FN(EX_CS1), GPIO_FN(MMC0_D7), GPIO_FN(FD7), + GPIO_FN(EX_CS2), GPIO_FN(SD1_CLK), GPIO_FN(MMC0_CLK), GPIO_FN(FALE), + GPIO_FN(ATACS00), GPIO_FN(EX_CS3), GPIO_FN(SD1_CMD), GPIO_FN(MMC0_CMD), + GPIO_FN(FRE), GPIO_FN(ATACS10), GPIO_FN(VI1_R4), GPIO_FN(RX5_B), + GPIO_FN(HSCK1), GPIO_FN(SSI_SDATA8_B), GPIO_FN(RTS0_B_TANS_B), + GPIO_FN(SSI_SDATA9), GPIO_FN(EX_CS4), GPIO_FN(SD1_DAT0), + GPIO_FN(MMC0_D0), GPIO_FN(FD0), GPIO_FN(ATARD0), GPIO_FN(VI1_R5), + GPIO_FN(SCK5_B), GPIO_FN(HTX1), GPIO_FN(TX2_E), GPIO_FN(TX0_B), + GPIO_FN(SSI_SCK9), GPIO_FN(EX_CS5), GPIO_FN(SD1_DAT1), + GPIO_FN(MMC0_D1), GPIO_FN(FD1), GPIO_FN(ATAWR0), GPIO_FN(VI1_R6), + GPIO_FN(HRX1), GPIO_FN(RX2_E), GPIO_FN(RX0_B), GPIO_FN(SSI_WS9), + GPIO_FN(MLB_CLK), GPIO_FN(PWM2), GPIO_FN(SCK4), GPIO_FN(MLB_SIG), + GPIO_FN(PWM3), GPIO_FN(TX4), GPIO_FN(MLB_DAT), GPIO_FN(PWM4), + GPIO_FN(RX4), GPIO_FN(HTX0), GPIO_FN(TX1), GPIO_FN(SDATA), + GPIO_FN(CTS0_C), GPIO_FN(SUB_TCK), GPIO_FN(CC5_STATE2), + GPIO_FN(CC5_STATE10), GPIO_FN(CC5_STATE18), GPIO_FN(CC5_STATE26), + GPIO_FN(CC5_STATE34), + + /* IPSR2 */ + GPIO_FN(HRX0), GPIO_FN(RX1), GPIO_FN(SCKZ), GPIO_FN(RTS0_C_TANS_C), + GPIO_FN(SUB_TDI), GPIO_FN(CC5_STATE3), GPIO_FN(CC5_STATE11), + GPIO_FN(CC5_STATE19), GPIO_FN(CC5_STATE27), GPIO_FN(CC5_STATE35), + GPIO_FN(HSCK0), GPIO_FN(SCK1), GPIO_FN(MTS), GPIO_FN(PWM5), + GPIO_FN(SCK0_C), GPIO_FN(SSI_SDATA9_B), GPIO_FN(SUB_TDO), + GPIO_FN(CC5_STATE0), GPIO_FN(CC5_STATE8), GPIO_FN(CC5_STATE16), + GPIO_FN(CC5_STATE24), GPIO_FN(CC5_STATE32), GPIO_FN(HCTS0), + GPIO_FN(CTS1), GPIO_FN(STM), GPIO_FN(PWM0_D), GPIO_FN(RX0_C), + GPIO_FN(SCIF_CLK_C), GPIO_FN(SUB_TRST), GPIO_FN(TCLK1_B), + GPIO_FN(CC5_OSCOUT), GPIO_FN(HRTS0), GPIO_FN(RTS1_TANS), + GPIO_FN(MDATA), GPIO_FN(TX0_C), GPIO_FN(SUB_TMS), GPIO_FN(CC5_STATE1), + GPIO_FN(CC5_STATE9), GPIO_FN(CC5_STATE17), GPIO_FN(CC5_STATE25), + GPIO_FN(CC5_STATE33), GPIO_FN(DU0_DR0), GPIO_FN(LCDOUT0), + GPIO_FN(DREQ0), GPIO_FN(GPS_CLK_B), GPIO_FN(AUDATA0), + GPIO_FN(TX5_C), GPIO_FN(DU0_DR1), GPIO_FN(LCDOUT1), GPIO_FN(DACK0), + GPIO_FN(DRACK0), GPIO_FN(GPS_SIGN_B), GPIO_FN(AUDATA1), GPIO_FN(RX5_C), + GPIO_FN(DU0_DR2), GPIO_FN(LCDOUT2), GPIO_FN(DU0_DR3), GPIO_FN(LCDOUT3), + GPIO_FN(DU0_DR4), GPIO_FN(LCDOUT4), GPIO_FN(DU0_DR5), GPIO_FN(LCDOUT5), + GPIO_FN(DU0_DR6), GPIO_FN(LCDOUT6), GPIO_FN(DU0_DR7), GPIO_FN(LCDOUT7), + GPIO_FN(DU0_DG0), GPIO_FN(LCDOUT8), GPIO_FN(DREQ1), GPIO_FN(SCL2), + GPIO_FN(AUDATA2), + + /* IPSR3 */ + GPIO_FN(DU0_DG1), GPIO_FN(LCDOUT9), GPIO_FN(DACK1), GPIO_FN(SDA2), + GPIO_FN(AUDATA3), GPIO_FN(DU0_DG2), GPIO_FN(LCDOUT10), + GPIO_FN(DU0_DG3), GPIO_FN(LCDOUT11), GPIO_FN(DU0_DG4), + GPIO_FN(LCDOUT12), GPIO_FN(DU0_DG5), GPIO_FN(LCDOUT13), + GPIO_FN(DU0_DG6), GPIO_FN(LCDOUT14), GPIO_FN(DU0_DG7), + GPIO_FN(LCDOUT15), GPIO_FN(DU0_DB0), GPIO_FN(LCDOUT16), + GPIO_FN(EX_WAIT1), GPIO_FN(SCL1), GPIO_FN(TCLK1), GPIO_FN(AUDATA4), + GPIO_FN(DU0_DB1), GPIO_FN(LCDOUT17), GPIO_FN(EX_WAIT2), GPIO_FN(SDA1), + GPIO_FN(GPS_MAG_B), GPIO_FN(AUDATA5), GPIO_FN(SCK5_C), + GPIO_FN(DU0_DB2), GPIO_FN(LCDOUT18), GPIO_FN(DU0_DB3), + GPIO_FN(LCDOUT19), GPIO_FN(DU0_DB4), GPIO_FN(LCDOUT20), + GPIO_FN(DU0_DB5), GPIO_FN(LCDOUT21), GPIO_FN(DU0_DB6), + GPIO_FN(LCDOUT22), GPIO_FN(DU0_DB7), GPIO_FN(LCDOUT23), + GPIO_FN(DU0_DOTCLKIN), GPIO_FN(QSTVA_QVS), GPIO_FN(TX3_D_IRDA_TX_D), + GPIO_FN(SCL3_B), GPIO_FN(DU0_DOTCLKOUT0), GPIO_FN(QCLK), + GPIO_FN(DU0_DOTCLKOUT1), GPIO_FN(QSTVB_QVE), GPIO_FN(RX3_D_IRDA_RX_D), + GPIO_FN(SDA3_B), GPIO_FN(SDA2_C), GPIO_FN(DACK0_B), GPIO_FN(DRACK0_B), + GPIO_FN(DU0_EXHSYNC_DU0_HSYNC), GPIO_FN(QSTH_QHS), + GPIO_FN(DU0_EXVSYNC_DU0_VSYNC), GPIO_FN(QSTB_QHE), + GPIO_FN(DU0_EXODDF_DU0_ODDF_DISP_CDE), GPIO_FN(QCPV_QDE), + GPIO_FN(CAN1_TX), GPIO_FN(TX2_C), GPIO_FN(SCL2_C), GPIO_FN(REMOCON), + + /* IPSR4 */ + GPIO_FN(DU0_DISP), GPIO_FN(QPOLA), GPIO_FN(CAN_CLK_C), GPIO_FN(SCK2_C), + GPIO_FN(DU0_CDE), GPIO_FN(QPOLB), GPIO_FN(CAN1_RX), GPIO_FN(RX2_C), + GPIO_FN(DREQ0_B), GPIO_FN(SSI_SCK78_B), GPIO_FN(SCK0_B), + GPIO_FN(DU1_DR0), GPIO_FN(VI2_DATA0_VI2_B0), GPIO_FN(PWM6), + GPIO_FN(SD3_CLK), GPIO_FN(TX3_E_IRDA_TX_E), GPIO_FN(AUDCK), + GPIO_FN(PWMFSW0_B), GPIO_FN(DU1_DR1), GPIO_FN(VI2_DATA1_VI2_B1), + GPIO_FN(PWM0), GPIO_FN(SD3_CMD), GPIO_FN(RX3_E_IRDA_RX_E), + GPIO_FN(AUDSYNC), GPIO_FN(CTS0_D), GPIO_FN(DU1_DR2), GPIO_FN(VI2_G0), + GPIO_FN(DU1_DR3), GPIO_FN(VI2_G1), GPIO_FN(DU1_DR4), GPIO_FN(VI2_G2), + GPIO_FN(DU1_DR5), GPIO_FN(VI2_G3), GPIO_FN(DU1_DR6), GPIO_FN(VI2_G4), + GPIO_FN(DU1_DR7), GPIO_FN(VI2_G5), GPIO_FN(DU1_DG0), + GPIO_FN(VI2_DATA2_VI2_B2), GPIO_FN(SCL1_B), GPIO_FN(SD3_DAT2), + GPIO_FN(SCK3_E), GPIO_FN(AUDATA6), GPIO_FN(TX0_D), GPIO_FN(DU1_DG1), + GPIO_FN(VI2_DATA3_VI2_B3), GPIO_FN(SDA1_B), GPIO_FN(SD3_DAT3), + GPIO_FN(SCK5), GPIO_FN(AUDATA7), GPIO_FN(RX0_D), GPIO_FN(DU1_DG2), + GPIO_FN(VI2_G6), GPIO_FN(DU1_DG3), GPIO_FN(VI2_G7), GPIO_FN(DU1_DG4), + GPIO_FN(VI2_R0), GPIO_FN(DU1_DG5), GPIO_FN(VI2_R1), GPIO_FN(DU1_DG6), + GPIO_FN(VI2_R2), GPIO_FN(DU1_DG7), GPIO_FN(VI2_R3), GPIO_FN(DU1_DB0), + GPIO_FN(VI2_DATA4_VI2_B4), GPIO_FN(SCL2_B), GPIO_FN(SD3_DAT0), + GPIO_FN(TX5), GPIO_FN(SCK0_D), + + /* IPSR5 */ + GPIO_FN(DU1_DB1), GPIO_FN(VI2_DATA5_VI2_B5), GPIO_FN(SDA2_B), + GPIO_FN(SD3_DAT1), GPIO_FN(RX5), GPIO_FN(RTS0_D_TANS_D), + GPIO_FN(DU1_DB2), GPIO_FN(VI2_R4), GPIO_FN(DU1_DB3), GPIO_FN(VI2_R5), + GPIO_FN(DU1_DB4), GPIO_FN(VI2_R6), GPIO_FN(DU1_DB5), GPIO_FN(VI2_R7), + GPIO_FN(DU1_DB6), GPIO_FN(SCL2_D), GPIO_FN(DU1_DB7), GPIO_FN(SDA2_D), + GPIO_FN(DU1_DOTCLKIN), GPIO_FN(VI2_CLKENB), GPIO_FN(HSPI_CS1), + GPIO_FN(SCL1_D), GPIO_FN(DU1_DOTCLKOUT), GPIO_FN(VI2_FIELD), + GPIO_FN(SDA1_D), GPIO_FN(DU1_EXHSYNC_DU1_HSYNC), GPIO_FN(VI2_HSYNC), + GPIO_FN(VI3_HSYNC), GPIO_FN(DU1_EXVSYNC_DU1_VSYNC), GPIO_FN(VI2_VSYNC), + GPIO_FN(VI3_VSYNC), GPIO_FN(DU1_EXODDF_DU1_ODDF_DISP_CDE), + GPIO_FN(VI2_CLK), GPIO_FN(TX3_B_IRDA_TX_B), GPIO_FN(SD3_CD), + GPIO_FN(HSPI_TX1), GPIO_FN(VI1_CLKENB), GPIO_FN(VI3_CLKENB), + GPIO_FN(AUDIO_CLKC), GPIO_FN(TX2_D), GPIO_FN(SPEEDIN), + GPIO_FN(GPS_SIGN_D), GPIO_FN(DU1_DISP), GPIO_FN(VI2_DATA6_VI2_B6), + GPIO_FN(TCLK0), GPIO_FN(QSTVA_B_QVS_B), GPIO_FN(HSPI_CLK1), + GPIO_FN(SCK2_D), GPIO_FN(AUDIO_CLKOUT_B), GPIO_FN(GPS_MAG_D), + GPIO_FN(DU1_CDE), GPIO_FN(VI2_DATA7_VI2_B7), GPIO_FN(RX3_B_IRDA_RX_B), + GPIO_FN(SD3_WP), GPIO_FN(HSPI_RX1), GPIO_FN(VI1_FIELD), + GPIO_FN(VI3_FIELD), GPIO_FN(AUDIO_CLKOUT), GPIO_FN(RX2_D), + GPIO_FN(GPS_CLK_C), GPIO_FN(GPS_CLK_D), GPIO_FN(AUDIO_CLKA), + GPIO_FN(CAN_TXCLK), GPIO_FN(AUDIO_CLKB), GPIO_FN(USB_OVC2), + GPIO_FN(CAN_DEBUGOUT0), GPIO_FN(MOUT0), + + /* IPSR6 */ + GPIO_FN(SSI_SCK0129), GPIO_FN(CAN_DEBUGOUT1), GPIO_FN(MOUT1), + GPIO_FN(SSI_WS0129), GPIO_FN(CAN_DEBUGOUT2), GPIO_FN(MOUT2), + GPIO_FN(SSI_SDATA0), GPIO_FN(CAN_DEBUGOUT3), GPIO_FN(MOUT5), + GPIO_FN(SSI_SDATA1), GPIO_FN(CAN_DEBUGOUT4), GPIO_FN(MOUT6), + GPIO_FN(SSI_SDATA2), GPIO_FN(CAN_DEBUGOUT5), GPIO_FN(SSI_SCK34), + GPIO_FN(CAN_DEBUGOUT6), GPIO_FN(CAN0_TX_B), GPIO_FN(IERX), + GPIO_FN(SSI_SCK9_C), GPIO_FN(SSI_WS34), GPIO_FN(CAN_DEBUGOUT7), + GPIO_FN(CAN0_RX_B), GPIO_FN(IETX), GPIO_FN(SSI_WS9_C), + GPIO_FN(SSI_SDATA3), GPIO_FN(PWM0_C), GPIO_FN(CAN_DEBUGOUT8), + GPIO_FN(CAN_CLK_B), GPIO_FN(IECLK), GPIO_FN(SCIF_CLK_B), + GPIO_FN(TCLK0_B), GPIO_FN(SSI_SDATA4), GPIO_FN(CAN_DEBUGOUT9), + GPIO_FN(SSI_SDATA9_C), GPIO_FN(SSI_SCK5), GPIO_FN(ADICLK), + GPIO_FN(CAN_DEBUGOUT10), GPIO_FN(SCK3), GPIO_FN(TCLK0_D), + GPIO_FN(SSI_WS5), GPIO_FN(ADICS_SAMP), GPIO_FN(CAN_DEBUGOUT11), + GPIO_FN(TX3_IRDA_TX), GPIO_FN(SSI_SDATA5), GPIO_FN(ADIDATA), + GPIO_FN(CAN_DEBUGOUT12), GPIO_FN(RX3_IRDA_RX), GPIO_FN(SSI_SCK6), + GPIO_FN(ADICHS0), GPIO_FN(CAN0_TX), GPIO_FN(IERX_B), + + /* IPSR7 */ + GPIO_FN(SSI_WS6), GPIO_FN(ADICHS1), GPIO_FN(CAN0_RX), GPIO_FN(IETX_B), + GPIO_FN(SSI_SDATA6), GPIO_FN(ADICHS2), GPIO_FN(CAN_CLK), + GPIO_FN(IECLK_B), GPIO_FN(SSI_SCK78), GPIO_FN(CAN_DEBUGOUT13), + GPIO_FN(IRQ0_B), GPIO_FN(SSI_SCK9_B), GPIO_FN(HSPI_CLK1_C), + GPIO_FN(SSI_WS78), GPIO_FN(CAN_DEBUGOUT14), GPIO_FN(IRQ1_B), + GPIO_FN(SSI_WS9_B), GPIO_FN(HSPI_CS1_C), GPIO_FN(SSI_SDATA7), + GPIO_FN(CAN_DEBUGOUT15), GPIO_FN(IRQ2_B), GPIO_FN(TCLK1_C), + GPIO_FN(HSPI_TX1_C), GPIO_FN(SSI_SDATA8), GPIO_FN(VSP), + GPIO_FN(IRQ3_B), GPIO_FN(HSPI_RX1_C), GPIO_FN(SD0_CLK), + GPIO_FN(ATACS01), GPIO_FN(SCK1_B), GPIO_FN(SD0_CMD), GPIO_FN(ATACS11), + GPIO_FN(TX1_B), GPIO_FN(CC5_TDO), GPIO_FN(SD0_DAT0), GPIO_FN(ATADIR1), + GPIO_FN(RX1_B), GPIO_FN(CC5_TRST), GPIO_FN(SD0_DAT1), GPIO_FN(ATAG1), + GPIO_FN(SCK2_B), GPIO_FN(CC5_TMS), GPIO_FN(SD0_DAT2), GPIO_FN(ATARD1), + GPIO_FN(TX2_B), GPIO_FN(CC5_TCK), GPIO_FN(SD0_DAT3), GPIO_FN(ATAWR1), + GPIO_FN(RX2_B), GPIO_FN(CC5_TDI), GPIO_FN(SD0_CD), GPIO_FN(DREQ2), + GPIO_FN(RTS1_B_TANS_B), GPIO_FN(SD0_WP), GPIO_FN(DACK2), + GPIO_FN(CTS1_B), + + /* IPSR8 */ + GPIO_FN(HSPI_CLK0), GPIO_FN(CTS0), GPIO_FN(USB_OVC0), GPIO_FN(AD_CLK), + GPIO_FN(CC5_STATE4), GPIO_FN(CC5_STATE12), GPIO_FN(CC5_STATE20), + GPIO_FN(CC5_STATE28), GPIO_FN(CC5_STATE36), GPIO_FN(HSPI_CS0), + GPIO_FN(RTS0_TANS), GPIO_FN(USB_OVC1), GPIO_FN(AD_DI), + GPIO_FN(CC5_STATE5), GPIO_FN(CC5_STATE13), GPIO_FN(CC5_STATE21), + GPIO_FN(CC5_STATE29), GPIO_FN(CC5_STATE37), GPIO_FN(HSPI_TX0), + GPIO_FN(TX0), GPIO_FN(CAN_DEBUG_HW_TRIGGER), GPIO_FN(AD_DO), + GPIO_FN(CC5_STATE6), GPIO_FN(CC5_STATE14), GPIO_FN(CC5_STATE22), + GPIO_FN(CC5_STATE30), GPIO_FN(CC5_STATE38), GPIO_FN(HSPI_RX0), + GPIO_FN(RX0), GPIO_FN(CAN_STEP0), GPIO_FN(AD_NCS), GPIO_FN(CC5_STATE7), + GPIO_FN(CC5_STATE15), GPIO_FN(CC5_STATE23), GPIO_FN(CC5_STATE31), + GPIO_FN(CC5_STATE39), GPIO_FN(FMCLK), GPIO_FN(RDS_CLK), GPIO_FN(PCMOE), + GPIO_FN(BPFCLK), GPIO_FN(PCMWE), GPIO_FN(FMIN), GPIO_FN(RDS_DATA), + GPIO_FN(VI0_CLK), GPIO_FN(MMC1_CLK), GPIO_FN(VI0_CLKENB), + GPIO_FN(TX1_C), GPIO_FN(HTX1_B), GPIO_FN(MT1_SYNC), + GPIO_FN(VI0_FIELD), GPIO_FN(RX1_C), GPIO_FN(HRX1_B), + GPIO_FN(VI0_HSYNC), GPIO_FN(VI0_DATA0_B_VI0_B0_B), GPIO_FN(CTS1_C), + GPIO_FN(TX4_D), GPIO_FN(MMC1_CMD), GPIO_FN(HSCK1_B), + GPIO_FN(VI0_VSYNC), GPIO_FN(VI0_DATA1_B_VI0_B1_B), + GPIO_FN(RTS1_C_TANS_C), GPIO_FN(RX4_D), GPIO_FN(PWMFSW0_C), + + /* IPSR9 */ + GPIO_FN(VI0_DATA0_VI0_B0), GPIO_FN(HRTS1_B), GPIO_FN(MT1_VCXO), + GPIO_FN(VI0_DATA1_VI0_B1), GPIO_FN(HCTS1_B), GPIO_FN(MT1_PWM), + GPIO_FN(VI0_DATA2_VI0_B2), GPIO_FN(MMC1_D0), GPIO_FN(VI0_DATA3_VI0_B3), + GPIO_FN(MMC1_D1), GPIO_FN(VI0_DATA4_VI0_B4), GPIO_FN(MMC1_D2), + GPIO_FN(VI0_DATA5_VI0_B5), GPIO_FN(MMC1_D3), GPIO_FN(VI0_DATA6_VI0_B6), + GPIO_FN(MMC1_D4), GPIO_FN(ARM_TRACEDATA_0), GPIO_FN(VI0_DATA7_VI0_B7), + GPIO_FN(MMC1_D5), GPIO_FN(ARM_TRACEDATA_1), GPIO_FN(VI0_G0), + GPIO_FN(SSI_SCK78_C), GPIO_FN(IRQ0), GPIO_FN(ARM_TRACEDATA_2), + GPIO_FN(VI0_G1), GPIO_FN(SSI_WS78_C), GPIO_FN(IRQ1), + GPIO_FN(ARM_TRACEDATA_3), GPIO_FN(VI0_G2), GPIO_FN(ETH_TXD1), + GPIO_FN(MMC1_D6), GPIO_FN(ARM_TRACEDATA_4), GPIO_FN(TS_SPSYNC0), + GPIO_FN(VI0_G3), GPIO_FN(ETH_CRS_DV), GPIO_FN(MMC1_D7), + GPIO_FN(ARM_TRACEDATA_5), GPIO_FN(TS_SDAT0), GPIO_FN(VI0_G4), + GPIO_FN(ETH_TX_EN), GPIO_FN(SD2_DAT0_B), GPIO_FN(ARM_TRACEDATA_6), + GPIO_FN(VI0_G5), GPIO_FN(ETH_RX_ER), GPIO_FN(SD2_DAT1_B), + GPIO_FN(ARM_TRACEDATA_7), GPIO_FN(VI0_G6), GPIO_FN(ETH_RXD0), + GPIO_FN(SD2_DAT2_B), GPIO_FN(ARM_TRACEDATA_8), GPIO_FN(VI0_G7), + GPIO_FN(ETH_RXD1), GPIO_FN(SD2_DAT3_B), GPIO_FN(ARM_TRACEDATA_9), + + /* IPSR10 */ + GPIO_FN(VI0_R0), GPIO_FN(SSI_SDATA7_C), GPIO_FN(SCK1_C), + GPIO_FN(DREQ1_B), GPIO_FN(ARM_TRACEDATA_10), GPIO_FN(DREQ0_C), + GPIO_FN(VI0_R1), GPIO_FN(SSI_SDATA8_C), GPIO_FN(DACK1_B), + GPIO_FN(ARM_TRACEDATA_11), GPIO_FN(DACK0_C), GPIO_FN(DRACK0_C), + GPIO_FN(VI0_R2), GPIO_FN(ETH_LINK), GPIO_FN(SD2_CLK_B), GPIO_FN(IRQ2), + GPIO_FN(ARM_TRACEDATA_12), GPIO_FN(VI0_R3), GPIO_FN(ETH_MAGIC), + GPIO_FN(SD2_CMD_B), GPIO_FN(IRQ3), GPIO_FN(ARM_TRACEDATA_13), + GPIO_FN(VI0_R4), GPIO_FN(ETH_REFCLK), GPIO_FN(SD2_CD_B), + GPIO_FN(HSPI_CLK1_B), GPIO_FN(ARM_TRACEDATA_14), GPIO_FN(MT1_CLK), + GPIO_FN(TS_SCK0), GPIO_FN(VI0_R5), GPIO_FN(ETH_TXD0), + GPIO_FN(SD2_WP_B), GPIO_FN(HSPI_CS1_B), GPIO_FN(ARM_TRACEDATA_15), + GPIO_FN(MT1_D), GPIO_FN(TS_SDEN0), GPIO_FN(VI0_R6), GPIO_FN(ETH_MDC), + GPIO_FN(DREQ2_C), GPIO_FN(HSPI_TX1_B), GPIO_FN(TRACECLK), + GPIO_FN(MT1_BEN), GPIO_FN(PWMFSW0_D), GPIO_FN(VI0_R7), + GPIO_FN(ETH_MDIO), GPIO_FN(DACK2_C), GPIO_FN(HSPI_RX1_B), + GPIO_FN(SCIF_CLK_D), GPIO_FN(TRACECTL), GPIO_FN(MT1_PEN), + GPIO_FN(VI1_CLK), GPIO_FN(SIM_D), GPIO_FN(SDA3), GPIO_FN(VI1_HSYNC), + GPIO_FN(VI3_CLK), GPIO_FN(SSI_SCK4), GPIO_FN(GPS_SIGN_C), + GPIO_FN(PWMFSW0_E), GPIO_FN(VI1_VSYNC), GPIO_FN(AUDIO_CLKOUT_C), + GPIO_FN(SSI_WS4), GPIO_FN(SIM_CLK), GPIO_FN(GPS_MAG_C), + GPIO_FN(SPV_TRST), GPIO_FN(SCL3), + + /* IPSR11 */ + GPIO_FN(VI1_DATA0_VI1_B0), GPIO_FN(SD2_DAT0), GPIO_FN(SIM_RST), + GPIO_FN(SPV_TCK), GPIO_FN(ADICLK_B), GPIO_FN(VI1_DATA1_VI1_B1), + GPIO_FN(SD2_DAT1), GPIO_FN(MT0_CLK), GPIO_FN(SPV_TMS), + GPIO_FN(ADICS_B_SAMP_B), GPIO_FN(VI1_DATA2_VI1_B2), GPIO_FN(SD2_DAT2), + GPIO_FN(MT0_D), GPIO_FN(SPVTDI), GPIO_FN(ADIDATA_B), + GPIO_FN(VI1_DATA3_VI1_B3), GPIO_FN(SD2_DAT3), GPIO_FN(MT0_BEN), + GPIO_FN(SPV_TDO), GPIO_FN(ADICHS0_B), GPIO_FN(VI1_DATA4_VI1_B4), + GPIO_FN(SD2_CLK), GPIO_FN(MT0_PEN), GPIO_FN(SPA_TRST), + GPIO_FN(HSPI_CLK1_D), GPIO_FN(ADICHS1_B), GPIO_FN(VI1_DATA5_VI1_B5), + GPIO_FN(SD2_CMD), GPIO_FN(MT0_SYNC), GPIO_FN(SPA_TCK), + GPIO_FN(HSPI_CS1_D), GPIO_FN(ADICHS2_B), GPIO_FN(VI1_DATA6_VI1_B6), + GPIO_FN(SD2_CD), GPIO_FN(MT0_VCXO), GPIO_FN(SPA_TMS), + GPIO_FN(HSPI_TX1_D), GPIO_FN(VI1_DATA7_VI1_B7), GPIO_FN(SD2_WP), + GPIO_FN(MT0_PWM), GPIO_FN(SPA_TDI), GPIO_FN(HSPI_RX1_D), + GPIO_FN(VI1_G0), GPIO_FN(VI3_DATA0), GPIO_FN(DU1_DOTCLKOUT1), + GPIO_FN(TS_SCK1), GPIO_FN(DREQ2_B), GPIO_FN(TX2), GPIO_FN(SPA_TDO), + GPIO_FN(HCTS0_B), GPIO_FN(VI1_G1), GPIO_FN(VI3_DATA1), + GPIO_FN(SSI_SCK1), GPIO_FN(TS_SDEN1), GPIO_FN(DACK2_B), GPIO_FN(RX2), + GPIO_FN(HRTS0_B), + + /* IPSR12 */ + GPIO_FN(VI1_G2), GPIO_FN(VI3_DATA2), GPIO_FN(SSI_WS1), + GPIO_FN(TS_SPSYNC1), GPIO_FN(SCK2), GPIO_FN(HSCK0_B), GPIO_FN(VI1_G3), + GPIO_FN(VI3_DATA3), GPIO_FN(SSI_SCK2), GPIO_FN(TS_SDAT1), + GPIO_FN(SCL1_C), GPIO_FN(HTX0_B), GPIO_FN(VI1_G4), GPIO_FN(VI3_DATA4), + GPIO_FN(SSI_WS2), GPIO_FN(SDA1_C), GPIO_FN(SIM_RST_B), + GPIO_FN(HRX0_B), GPIO_FN(VI1_G5), GPIO_FN(VI3_DATA5), + GPIO_FN(GPS_CLK), GPIO_FN(FSE), GPIO_FN(TX4_B), GPIO_FN(SIM_D_B), + GPIO_FN(VI1_G6), GPIO_FN(VI3_DATA6), GPIO_FN(GPS_SIGN), GPIO_FN(FRB), + GPIO_FN(RX4_B), GPIO_FN(SIM_CLK_B), GPIO_FN(VI1_G7), + GPIO_FN(VI3_DATA7), GPIO_FN(GPS_MAG), GPIO_FN(FCE), GPIO_FN(SCK4_B), +}; + +static struct pinmux_cfg_reg pinmux_config_regs[] = { + { PINMUX_CFG_REG("GPSR0", 0xfffc0004, 32, 1) { + GP_0_31_FN, FN_IP3_31_29, + GP_0_30_FN, FN_IP3_26_24, + GP_0_29_FN, FN_IP3_22_21, + GP_0_28_FN, FN_IP3_14_12, + GP_0_27_FN, FN_IP3_11_9, + GP_0_26_FN, FN_IP3_2_0, + GP_0_25_FN, FN_IP2_30_28, + GP_0_24_FN, FN_IP2_21_19, + GP_0_23_FN, FN_IP2_18_16, + GP_0_22_FN, FN_IP0_30_28, + GP_0_21_FN, FN_IP0_5_3, + GP_0_20_FN, FN_IP1_18_15, + GP_0_19_FN, FN_IP1_14_11, + GP_0_18_FN, FN_IP1_10_7, + GP_0_17_FN, FN_IP1_6_4, + GP_0_16_FN, FN_IP1_3_2, + GP_0_15_FN, FN_IP1_1_0, + GP_0_14_FN, FN_IP0_27_26, + GP_0_13_FN, FN_IP0_25, + GP_0_12_FN, FN_IP0_24_23, + GP_0_11_FN, FN_IP0_22_19, + GP_0_10_FN, FN_IP0_18_16, + GP_0_9_FN, FN_IP0_15_14, + GP_0_8_FN, FN_IP0_13_12, + GP_0_7_FN, FN_IP0_11_10, + GP_0_6_FN, FN_IP0_9_8, + GP_0_5_FN, FN_A19, + GP_0_4_FN, FN_A18, + GP_0_3_FN, FN_A17, + GP_0_2_FN, FN_IP0_7_6, + GP_0_1_FN, FN_AVS2, + GP_0_0_FN, FN_AVS1 } + }, + { PINMUX_CFG_REG("GPSR1", 0xfffc0008, 32, 1) { + GP_1_31_FN, FN_IP5_23_21, + GP_1_30_FN, FN_IP5_20_17, + GP_1_29_FN, FN_IP5_16_15, + GP_1_28_FN, FN_IP5_14_13, + GP_1_27_FN, FN_IP5_12_11, + GP_1_26_FN, FN_IP5_10_9, + GP_1_25_FN, FN_IP5_8, + GP_1_24_FN, FN_IP5_7, + GP_1_23_FN, FN_IP5_6, + GP_1_22_FN, FN_IP5_5, + GP_1_21_FN, FN_IP5_4, + GP_1_20_FN, FN_IP5_3, + GP_1_19_FN, FN_IP5_2_0, + GP_1_18_FN, FN_IP4_31_29, + GP_1_17_FN, FN_IP4_28, + GP_1_16_FN, FN_IP4_27, + GP_1_15_FN, FN_IP4_26, + GP_1_14_FN, FN_IP4_25, + GP_1_13_FN, FN_IP4_24, + GP_1_12_FN, FN_IP4_23, + GP_1_11_FN, FN_IP4_22_20, + GP_1_10_FN, FN_IP4_19_17, + GP_1_9_FN, FN_IP4_16, + GP_1_8_FN, FN_IP4_15, + GP_1_7_FN, FN_IP4_14, + GP_1_6_FN, FN_IP4_13, + GP_1_5_FN, FN_IP4_12, + GP_1_4_FN, FN_IP4_11, + GP_1_3_FN, FN_IP4_10_8, + GP_1_2_FN, FN_IP4_7_5, + GP_1_1_FN, FN_IP4_4_2, + GP_1_0_FN, FN_IP4_1_0 } + }, + { PINMUX_CFG_REG("GPSR2", 0xfffc000c, 32, 1) { + GP_2_31_FN, FN_IP10_28_26, + GP_2_30_FN, FN_IP10_25_24, + GP_2_29_FN, FN_IP10_23_21, + GP_2_28_FN, FN_IP10_20_18, + GP_2_27_FN, FN_IP10_17_15, + GP_2_26_FN, FN_IP10_14_12, + GP_2_25_FN, FN_IP10_11_9, + GP_2_24_FN, FN_IP10_8_6, + GP_2_23_FN, FN_IP10_5_3, + GP_2_22_FN, FN_IP10_2_0, + GP_2_21_FN, FN_IP9_29_28, + GP_2_20_FN, FN_IP9_27_26, + GP_2_19_FN, FN_IP9_25_24, + GP_2_18_FN, FN_IP9_23_22, + GP_2_17_FN, FN_IP9_21_19, + GP_2_16_FN, FN_IP9_18_16, + GP_2_15_FN, FN_IP9_15_14, + GP_2_14_FN, FN_IP9_13_12, + GP_2_13_FN, FN_IP9_11_10, + GP_2_12_FN, FN_IP9_9_8, + GP_2_11_FN, FN_IP9_7, + GP_2_10_FN, FN_IP9_6, + GP_2_9_FN, FN_IP9_5, + GP_2_8_FN, FN_IP9_4, + GP_2_7_FN, FN_IP9_3_2, + GP_2_6_FN, FN_IP9_1_0, + GP_2_5_FN, FN_IP8_30_28, + GP_2_4_FN, FN_IP8_27_25, + GP_2_3_FN, FN_IP8_24_23, + GP_2_2_FN, FN_IP8_22_21, + GP_2_1_FN, FN_IP8_20, + GP_2_0_FN, FN_IP5_27_24 } + }, + { PINMUX_CFG_REG("GPSR3", 0xfffc0010, 32, 1) { + GP_3_31_FN, FN_IP6_3_2, + GP_3_30_FN, FN_IP6_1_0, + GP_3_29_FN, FN_IP5_30_29, + GP_3_28_FN, FN_IP5_28, + GP_3_27_FN, FN_IP1_24_23, + GP_3_26_FN, FN_IP1_22_21, + GP_3_25_FN, FN_IP1_20_19, + GP_3_24_FN, FN_IP7_26_25, + GP_3_23_FN, FN_IP7_24_23, + GP_3_22_FN, FN_IP7_22_21, + GP_3_21_FN, FN_IP7_20_19, + GP_3_20_FN, FN_IP7_30_29, + GP_3_19_FN, FN_IP7_28_27, + GP_3_18_FN, FN_IP7_18_17, + GP_3_17_FN, FN_IP7_16_15, + GP_3_16_FN, FN_IP12_17_15, + GP_3_15_FN, FN_IP12_14_12, + GP_3_14_FN, FN_IP12_11_9, + GP_3_13_FN, FN_IP12_8_6, + GP_3_12_FN, FN_IP12_5_3, + GP_3_11_FN, FN_IP12_2_0, + GP_3_10_FN, FN_IP11_29_27, + GP_3_9_FN, FN_IP11_26_24, + GP_3_8_FN, FN_IP11_23_21, + GP_3_7_FN, FN_IP11_20_18, + GP_3_6_FN, FN_IP11_17_15, + GP_3_5_FN, FN_IP11_14_12, + GP_3_4_FN, FN_IP11_11_9, + GP_3_3_FN, FN_IP11_8_6, + GP_3_2_FN, FN_IP11_5_3, + GP_3_1_FN, FN_IP11_2_0, + GP_3_0_FN, FN_IP10_31_29 } + }, + { PINMUX_CFG_REG("GPSR4", 0xfffc0014, 32, 1) { + GP_4_31_FN, FN_IP8_19, + GP_4_30_FN, FN_IP8_18, + GP_4_29_FN, FN_IP8_17_16, + GP_4_28_FN, FN_IP0_2_0, + GP_4_27_FN, FN_PENC1, + GP_4_26_FN, FN_PENC0, + GP_4_25_FN, FN_IP8_15_12, + GP_4_24_FN, FN_IP8_11_8, + GP_4_23_FN, FN_IP8_7_4, + GP_4_22_FN, FN_IP8_3_0, + GP_4_21_FN, FN_IP2_3_0, + GP_4_20_FN, FN_IP1_28_25, + GP_4_19_FN, FN_IP2_15_12, + GP_4_18_FN, FN_IP2_11_8, + GP_4_17_FN, FN_IP2_7_4, + GP_4_16_FN, FN_IP7_14_13, + GP_4_15_FN, FN_IP7_12_10, + GP_4_14_FN, FN_IP7_9_7, + GP_4_13_FN, FN_IP7_6_4, + GP_4_12_FN, FN_IP7_3_2, + GP_4_11_FN, FN_IP7_1_0, + GP_4_10_FN, FN_IP6_30_29, + GP_4_9_FN, FN_IP6_26_25, + GP_4_8_FN, FN_IP6_24_23, + GP_4_7_FN, FN_IP6_22_20, + GP_4_6_FN, FN_IP6_19_18, + GP_4_5_FN, FN_IP6_17_15, + GP_4_4_FN, FN_IP6_14_12, + GP_4_3_FN, FN_IP6_11_9, + GP_4_2_FN, FN_IP6_8, + GP_4_1_FN, FN_IP6_7_6, + GP_4_0_FN, FN_IP6_5_4 } + }, + { PINMUX_CFG_REG("GPSR5", 0xfffc0018, 32, 1) { + GP_5_31_FN, FN_IP3_5, + GP_5_30_FN, FN_IP3_4, + GP_5_29_FN, FN_IP3_3, + GP_5_28_FN, FN_IP2_27, + GP_5_27_FN, FN_IP2_26, + GP_5_26_FN, FN_IP2_25, + GP_5_25_FN, FN_IP2_24, + GP_5_24_FN, FN_IP2_23, + GP_5_23_FN, FN_IP2_22, + GP_5_22_FN, FN_IP3_28, + GP_5_21_FN, FN_IP3_27, + GP_5_20_FN, FN_IP3_23, + GP_5_19_FN, FN_EX_WAIT0, + GP_5_18_FN, FN_WE1, + GP_5_17_FN, FN_WE0, + GP_5_16_FN, FN_RD, + GP_5_15_FN, FN_A16, + GP_5_14_FN, FN_A15, + GP_5_13_FN, FN_A14, + GP_5_12_FN, FN_A13, + GP_5_11_FN, FN_A12, + GP_5_10_FN, FN_A11, + GP_5_9_FN, FN_A10, + GP_5_8_FN, FN_A9, + GP_5_7_FN, FN_A8, + GP_5_6_FN, FN_A7, + GP_5_5_FN, FN_A6, + GP_5_4_FN, FN_A5, + GP_5_3_FN, FN_A4, + GP_5_2_FN, FN_A3, + GP_5_1_FN, FN_A2, + GP_5_0_FN, FN_A1 } + }, + { PINMUX_CFG_REG("GPSR6", 0xfffc001c, 32, 1) { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_6_8_FN, FN_IP3_20, + GP_6_7_FN, FN_IP3_19, + GP_6_6_FN, FN_IP3_18, + GP_6_5_FN, FN_IP3_17, + GP_6_4_FN, FN_IP3_16, + GP_6_3_FN, FN_IP3_15, + GP_6_2_FN, FN_IP3_8, + GP_6_1_FN, FN_IP3_7, + GP_6_0_FN, FN_IP3_6 } + }, + + { PINMUX_CFG_REG_VAR("IPSR0", 0xfffc0020, 32, + 1, 3, 2, 1, 2, 4, 3, 2, 2, 2, 2, 2, 3, 3) { + /* IP0_31 [1] */ + 0, 0, + /* IP0_30_28 [3] */ + FN_RD_WR, FN_FWE, FN_ATAG0, FN_VI1_R7, + FN_HRTS1, FN_RX4_C, 0, 0, + /* IP0_27_26 [2] */ + FN_CS1_A26, FN_HSPI_TX2, FN_SDSELF_B, 0, + /* IP0_25 [1] */ + FN_CS0, FN_HSPI_CS2_B, + /* IP0_24_23 [2] */ + FN_CLKOUT, FN_TX3C_IRDA_TX_C, FN_PWM0_B, 0, + /* IP0_22_19 [4] */ + FN_A25, FN_SD1_WP, FN_MMC0_D5, FN_FD5, + FN_HSPI_RX2, FN_VI1_R3, FN_TX5_B, FN_SSI_SDATA7_B, + FN_CTS0_B, 0, 0, 0, + 0, 0, 0, 0, + /* IP0_18_16 [3] */ + FN_A24, FN_SD1_CD, FN_MMC0_D4, FN_FD4, + FN_HSPI_CS2, FN_VI1_R2, FN_SSI_WS78_B, 0, + /* IP0_15_14 [2] */ + FN_A23, FN_FCLE, FN_HSPI_CLK2, FN_VI1_R1, + /* IP0_13_12 [2] */ + FN_A22, FN_RX5_D, FN_HSPI_RX2_B, FN_VI1_R0, + /* IP0_11_10 [2] */ + FN_A21, FN_SCK5_D, FN_HSPI_CLK2_B, 0, + /* IP0_9_8 [2] */ + FN_A20, FN_TX5_D, FN_HSPI_TX2_B, 0, + /* IP0_7_6 [2] */ + FN_A0, FN_SD1_DAT3, FN_MMC0_D3, FN_FD3, + /* IP0_5_3 [3] */ + FN_BS, FN_SD1_DAT2, FN_MMC0_D2, FN_FD2, + FN_ATADIR0, FN_SDSELF, FN_HCTS1, FN_TX4_C, + /* IP0_2_0 [3] */ + FN_PENC2, FN_SCK0, FN_PWM1, FN_PWMFSW0, + FN_SCIF_CLK, FN_TCLK0_C, 0, 0 } + }, + { PINMUX_CFG_REG_VAR("IPSR1", 0xfffc0024, 32, + 3, 4, 2, 2, 2, 4, 4, 4, 3, 2, 2) { + /* IP1_31_29 [3] */ + 0, 0, 0, 0, 0, 0, 0, 0, + /* IP1_28_25 [4] */ + FN_HTX0, FN_TX1, FN_SDATA, FN_CTS0_C, + FN_SUB_TCK, FN_CC5_STATE2, FN_CC5_STATE10, FN_CC5_STATE18, + FN_CC5_STATE26, FN_CC5_STATE34, 0, 0, + 0, 0, 0, 0, + /* IP1_24_23 [2] */ + FN_MLB_DAT, FN_PWM4, FN_RX4, 0, + /* IP1_22_21 [2] */ + FN_MLB_SIG, FN_PWM3, FN_TX4, 0, + /* IP1_20_19 [2] */ + FN_MLB_CLK, FN_PWM2, FN_SCK4, 0, + /* IP1_18_15 [4] */ + FN_EX_CS5, FN_SD1_DAT1, FN_MMC0_D1, FN_FD1, + FN_ATAWR0, FN_VI1_R6, FN_HRX1, FN_RX2_E, + FN_RX0_B, FN_SSI_WS9, 0, 0, + 0, 0, 0, 0, + /* IP1_14_11 [4] */ + FN_EX_CS4, FN_SD1_DAT0, FN_MMC0_D0, FN_FD0, + FN_ATARD0, FN_VI1_R5, FN_SCK5_B, FN_HTX1, + FN_TX2_E, FN_TX0_B, FN_SSI_SCK9, 0, + 0, 0, 0, 0, + /* IP1_10_7 [4] */ + FN_EX_CS3, FN_SD1_CMD, FN_MMC0_CMD, FN_FRE, + FN_ATACS10, FN_VI1_R4, FN_RX5_B, FN_HSCK1, + FN_SSI_SDATA8_B, FN_RTS0_B_TANS_B, FN_SSI_SDATA9, 0, + 0, 0, 0, 0, + /* IP1_6_4 [3] */ + FN_EX_CS2, FN_SD1_CLK, FN_MMC0_CLK, FN_FALE, + FN_ATACS00, 0, 0, 0, + /* IP1_3_2 [2] */ + FN_EX_CS1, FN_MMC0_D7, FN_FD7, 0, + /* IP1_1_0 [2] */ + FN_EX_CS0, FN_RX3_C_IRDA_RX_C, FN_MMC0_D6, FN_FD6 } + }, + { PINMUX_CFG_REG_VAR("IPSR2", 0xfffc0028, 32, + 1, 3, 1, 1, 1, 1, 1, 1, 3, 3, 4, 4, 4, 4) { + /* IP2_31 [1] */ + 0, 0, + /* IP2_30_28 [3] */ + FN_DU0_DG0, FN_LCDOUT8, FN_DREQ1, FN_SCL2, + FN_AUDATA2, 0, 0, 0, + /* IP2_27 [1] */ + FN_DU0_DR7, FN_LCDOUT7, + /* IP2_26 [1] */ + FN_DU0_DR6, FN_LCDOUT6, + /* IP2_25 [1] */ + FN_DU0_DR5, FN_LCDOUT5, + /* IP2_24 [1] */ + FN_DU0_DR4, FN_LCDOUT4, + /* IP2_23 [1] */ + FN_DU0_DR3, FN_LCDOUT3, + /* IP2_22 [1] */ + FN_DU0_DR2, FN_LCDOUT2, + /* IP2_21_19 [3] */ + FN_DU0_DR1, FN_LCDOUT1, FN_DACK0, FN_DRACK0, + FN_GPS_SIGN_B, FN_AUDATA1, FN_RX5_C, 0, + /* IP2_18_16 [3] */ + FN_DU0_DR0, FN_LCDOUT0, FN_DREQ0, FN_GPS_CLK_B, + FN_AUDATA0, FN_TX5_C, 0, 0, + /* IP2_15_12 [4] */ + FN_HRTS0, FN_RTS1_TANS, FN_MDATA, FN_TX0_C, + FN_SUB_TMS, FN_CC5_STATE1, FN_CC5_STATE9, FN_CC5_STATE17, + FN_CC5_STATE25, FN_CC5_STATE33, 0, 0, + 0, 0, 0, 0, + /* IP2_11_8 [4] */ + FN_HCTS0, FN_CTS1, FN_STM, FN_PWM0_D, + FN_RX0_C, FN_SCIF_CLK_C, FN_SUB_TRST, FN_TCLK1_B, + FN_CC5_OSCOUT, 0, 0, 0, + 0, 0, 0, 0, + /* IP2_7_4 [4] */ + FN_HSCK0, FN_SCK1, FN_MTS, FN_PWM5, + FN_SCK0_C, FN_SSI_SDATA9_B, FN_SUB_TDO, FN_CC5_STATE0, + FN_CC5_STATE8, FN_CC5_STATE16, FN_CC5_STATE24, FN_CC5_STATE32, + 0, 0, 0, 0, + /* IP2_3_0 [4] */ + FN_HRX0, FN_RX1, FN_SCKZ, FN_RTS0_C_TANS_C, + FN_SUB_TDI, FN_CC5_STATE3, FN_CC5_STATE11, FN_CC5_STATE19, + FN_CC5_STATE27, FN_CC5_STATE35, 0, 0, + 0, 0, 0, 0 } + }, + { PINMUX_CFG_REG_VAR("IPSR3", 0xfffc002c, 32, + 3, 1, 1, 3, 1, 2, 1, 1, 1, 1, 1, + 1, 3, 3, 1, 1, 1, 1, 1, 1, 3) { + /* IP3_31_29 [3] */ + FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, FN_CAN1_TX, FN_TX2_C, + FN_SCL2_C, FN_REMOCON, 0, 0, + /* IP3_28 [1] */ + FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, + /* IP3_27 [1] */ + FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS, + /* IP3_26_24 [3] */ + FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE, FN_RX3_D_IRDA_RX_D, FN_SDA3_B, + FN_SDA2_C, FN_DACK0_B, FN_DRACK0_B, 0, + /* IP3_23 [1] */ + FN_DU0_DOTCLKOUT0, FN_QCLK, + /* IP3_22_21 [2] */ + FN_DU0_DOTCLKIN, FN_QSTVA_QVS, FN_TX3_D_IRDA_TX_D, FN_SCL3_B, + /* IP3_20 [1] */ + FN_DU0_DB7, FN_LCDOUT23, + /* IP3_19 [1] */ + FN_DU0_DB6, FN_LCDOUT22, + /* IP3_18 [1] */ + FN_DU0_DB5, FN_LCDOUT21, + /* IP3_17 [1] */ + FN_DU0_DB4, FN_LCDOUT20, + /* IP3_16 [1] */ + FN_DU0_DB3, FN_LCDOUT19, + /* IP3_15 [1] */ + FN_DU0_DB2, FN_LCDOUT18, + /* IP3_14_12 [3] */ + FN_DU0_DB1, FN_LCDOUT17, FN_EX_WAIT2, FN_SDA1, + FN_GPS_MAG_B, FN_AUDATA5, FN_SCK5_C, 0, + /* IP3_11_9 [3] */ + FN_DU0_DB0, FN_LCDOUT16, FN_EX_WAIT1, FN_SCL1, + FN_TCLK1, FN_AUDATA4, 0, 0, + /* IP3_8 [1] */ + FN_DU0_DG7, FN_LCDOUT15, + /* IP3_7 [1] */ + FN_DU0_DG6, FN_LCDOUT14, + /* IP3_6 [1] */ + FN_DU0_DG5, FN_LCDOUT13, + /* IP3_5 [1] */ + FN_DU0_DG4, FN_LCDOUT12, + /* IP3_4 [1] */ + FN_DU0_DG3, FN_LCDOUT11, + /* IP3_3 [1] */ + FN_DU0_DG2, FN_LCDOUT10, + /* IP3_2_0 [3] */ + FN_DU0_DG1, FN_LCDOUT9, FN_DACK1, FN_SDA2, + FN_AUDATA3, 0, 0, 0 } + }, + { PINMUX_CFG_REG_VAR("IPSR4", 0xfffc0030, 32, + 3, 1, 1, 1, 1, 1, 1, 3, 3, 1, + 1, 1, 1, 1, 1, 1, 3, 3, 3, 2) { + /* IP4_31_29 [3] */ + FN_DU1_DB0, FN_VI2_DATA4_VI2_B4, FN_SCL2_B, FN_SD3_DAT0, + FN_TX5, FN_SCK0_D, 0, 0, + /* IP4_28 [1] */ + FN_DU1_DG7, FN_VI2_R3, + /* IP4_27 [1] */ + FN_DU1_DG6, FN_VI2_R2, + /* IP4_26 [1] */ + FN_DU1_DG5, FN_VI2_R1, + /* IP4_25 [1] */ + FN_DU1_DG4, FN_VI2_R0, + /* IP4_24 [1] */ + FN_DU1_DG3, FN_VI2_G7, + /* IP4_23 [1] */ + FN_DU1_DG2, FN_VI2_G6, + /* IP4_22_20 [3] */ + FN_DU1_DG1, FN_VI2_DATA3_VI2_B3, FN_SDA1_B, FN_SD3_DAT3, + FN_SCK5, FN_AUDATA7, FN_RX0_D, 0, + /* IP4_19_17 [3] */ + FN_DU1_DG0, FN_VI2_DATA2_VI2_B2, FN_SCL1_B, FN_SD3_DAT2, + FN_SCK3_E, FN_AUDATA6, FN_TX0_D, 0, + /* IP4_16 [1] */ + FN_DU1_DR7, FN_VI2_G5, + /* IP4_15 [1] */ + FN_DU1_DR6, FN_VI2_G4, + /* IP4_14 [1] */ + FN_DU1_DR5, FN_VI2_G3, + /* IP4_13 [1] */ + FN_DU1_DR4, FN_VI2_G2, + /* IP4_12 [1] */ + FN_DU1_DR3, FN_VI2_G1, + /* IP4_11 [1] */ + FN_DU1_DR2, FN_VI2_G0, + /* IP4_10_8 [3] */ + FN_DU1_DR1, FN_VI2_DATA1_VI2_B1, FN_PWM0, FN_SD3_CMD, + FN_RX3_E_IRDA_RX_E, FN_AUDSYNC, FN_CTS0_D, 0, + /* IP4_7_5 [3] */ + FN_DU1_DR0, FN_VI2_DATA0_VI2_B0, FN_PWM6, FN_SD3_CLK, + FN_TX3_E_IRDA_TX_E, FN_AUDCK, FN_PWMFSW0_B, 0, + /* IP4_4_2 [3] */ + FN_DU0_CDE, FN_QPOLB, FN_CAN1_RX, FN_RX2_C, + FN_DREQ0_B, FN_SSI_SCK78_B, FN_SCK0_B, 0, + /* IP4_1_0 [2] */ + FN_DU0_DISP, FN_QPOLA, FN_CAN_CLK_C, FN_SCK2_C } + }, + { PINMUX_CFG_REG_VAR("IPSR5", 0xfffc0034, 32, + 1, 2, 1, 4, 3, 4, 2, 2, + 2, 2, 1, 1, 1, 1, 1, 1, 3) { + /* IP5_31 [1] */ + 0, 0, + /* IP5_30_29 [2] */ + FN_AUDIO_CLKB, FN_USB_OVC2, FN_CAN_DEBUGOUT0, FN_MOUT0, + /* IP5_28 [1] */ + FN_AUDIO_CLKA, FN_CAN_TXCLK, + /* IP5_27_24 [4] */ + FN_DU1_CDE, FN_VI2_DATA7_VI2_B7, FN_RX3_B_IRDA_RX_B, FN_SD3_WP, + FN_HSPI_RX1, FN_VI1_FIELD, FN_VI3_FIELD, FN_AUDIO_CLKOUT, + FN_RX2_D, FN_GPS_CLK_C, FN_GPS_CLK_D, 0, + 0, 0, 0, 0, + /* IP5_23_21 [3] */ + FN_DU1_DISP, FN_VI2_DATA6_VI2_B6, FN_TCLK0, FN_QSTVA_B_QVS_B, + FN_HSPI_CLK1, FN_SCK2_D, FN_AUDIO_CLKOUT_B, FN_GPS_MAG_D, + /* IP5_20_17 [4] */ + FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_VI2_CLK, FN_TX3_B_IRDA_TX_B, + FN_SD3_CD, FN_HSPI_TX1, FN_VI1_CLKENB, FN_VI3_CLKENB, + FN_AUDIO_CLKC, FN_TX2_D, FN_SPEEDIN, FN_GPS_SIGN_D, 0, + 0, 0, 0, 0, + /* IP5_16_15 [2] */ + FN_DU1_EXVSYNC_DU1_VSYNC, FN_VI2_VSYNC, FN_VI3_VSYNC, 0, + /* IP5_14_13 [2] */ + FN_DU1_EXHSYNC_DU1_HSYNC, FN_VI2_HSYNC, FN_VI3_HSYNC, 0, + /* IP5_12_11 [2] */ + FN_DU1_DOTCLKOUT, FN_VI2_FIELD, FN_SDA1_D, 0, + /* IP5_10_9 [2] */ + FN_DU1_DOTCLKIN, FN_VI2_CLKENB, FN_HSPI_CS1, FN_SCL1_D, + /* IP5_8 [1] */ + FN_DU1_DB7, FN_SDA2_D, + /* IP5_7 [1] */ + FN_DU1_DB6, FN_SCL2_D, + /* IP5_6 [1] */ + FN_DU1_DB5, FN_VI2_R7, + /* IP5_5 [1] */ + FN_DU1_DB4, FN_VI2_R6, + /* IP5_4 [1] */ + FN_DU1_DB3, FN_VI2_R5, + /* IP5_3 [1] */ + FN_DU1_DB2, FN_VI2_R4, + /* IP5_2_0 [3] */ + FN_DU1_DB1, FN_VI2_DATA5_VI2_B5, FN_SDA2_B, FN_SD3_DAT1, + FN_RX5, FN_RTS0_D_TANS_D, 0, 0 } + }, + { PINMUX_CFG_REG_VAR("IPSR6", 0xfffc0038, 32, + 1, 2, 2, 2, 2, 3, 2, 3, 3, 3, 1, 2, 2, 2, 2) { + /* IP6_31 [1] */ + 0, 0, + /* IP6_30_29 [2] */ + FN_SSI_SCK6, FN_ADICHS0, FN_CAN0_TX, FN_IERX_B, + /* IP_28_27 [2] */ + 0, 0, 0, 0, + /* IP6_26_25 [2] */ + FN_SSI_SDATA5, FN_ADIDATA, FN_CAN_DEBUGOUT12, FN_RX3_IRDA_RX, + /* IP6_24_23 [2] */ + FN_SSI_WS5, FN_ADICS_SAMP, FN_CAN_DEBUGOUT11, FN_TX3_IRDA_TX, + /* IP6_22_20 [3] */ + FN_SSI_SCK5, FN_ADICLK, FN_CAN_DEBUGOUT10, FN_SCK3, + FN_TCLK0_D, 0, 0, 0, + /* IP6_19_18 [2] */ + FN_SSI_SDATA4, FN_CAN_DEBUGOUT9, FN_SSI_SDATA9_C, 0, + /* IP6_17_15 [3] */ + FN_SSI_SDATA3, FN_PWM0_C, FN_CAN_DEBUGOUT8, FN_CAN_CLK_B, + FN_IECLK, FN_SCIF_CLK_B, FN_TCLK0_B, 0, + /* IP6_14_12 [3] */ + FN_SSI_WS34, FN_CAN_DEBUGOUT7, FN_CAN0_RX_B, FN_IETX, + FN_SSI_WS9_C, 0, 0, 0, + /* IP6_11_9 [3] */ + FN_SSI_SCK34, FN_CAN_DEBUGOUT6, FN_CAN0_TX_B, FN_IERX, + FN_SSI_SCK9_C, 0, 0, 0, + /* IP6_8 [1] */ + FN_SSI_SDATA2, FN_CAN_DEBUGOUT5, + /* IP6_7_6 [2] */ + FN_SSI_SDATA1, FN_CAN_DEBUGOUT4, FN_MOUT6, 0, + /* IP6_5_4 [2] */ + FN_SSI_SDATA0, FN_CAN_DEBUGOUT3, FN_MOUT5, 0, + /* IP6_3_2 [2] */ + FN_SSI_WS0129, FN_CAN_DEBUGOUT2, FN_MOUT2, 0, + /* IP6_1_0 [2] */ + FN_SSI_SCK0129, FN_CAN_DEBUGOUT1, FN_MOUT1, 0 } + }, + { PINMUX_CFG_REG_VAR("IPSR7", 0xfffc003c, 32, + 1, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 2, 2) { + /* IP7_31 [1] */ + 0, 0, + /* IP7_30_29 [2] */ + FN_SD0_WP, FN_DACK2, FN_CTS1_B, 0, + /* IP7_28_27 [2] */ + FN_SD0_CD, FN_DREQ2, FN_RTS1_B_TANS_B, 0, + /* IP7_26_25 [2] */ + FN_SD0_DAT3, FN_ATAWR1, FN_RX2_B, FN_CC5_TDI, + /* IP7_24_23 [2] */ + FN_SD0_DAT2, FN_ATARD1, FN_TX2_B, FN_CC5_TCK, + /* IP7_22_21 [2] */ + FN_SD0_DAT1, FN_ATAG1, FN_SCK2_B, FN_CC5_TMS, + /* IP7_20_19 [2] */ + FN_SD0_DAT0, FN_ATADIR1, FN_RX1_B, FN_CC5_TRST, + /* IP7_18_17 [2] */ + FN_SD0_CMD, FN_ATACS11, FN_TX1_B, FN_CC5_TDO, + /* IP7_16_15 [2] */ + FN_SD0_CLK, FN_ATACS01, FN_SCK1_B, 0, + /* IP7_14_13 [2] */ + FN_SSI_SDATA8, FN_VSP, FN_IRQ3_B, FN_HSPI_RX1_C, + /* IP7_12_10 [3] */ + FN_SSI_SDATA7, FN_CAN_DEBUGOUT15, FN_IRQ2_B, FN_TCLK1_C, + FN_HSPI_TX1_C, 0, 0, 0, + /* IP7_9_7 [3] */ + FN_SSI_WS78, FN_CAN_DEBUGOUT14, FN_IRQ1_B, FN_SSI_WS9_B, + FN_HSPI_CS1_C, 0, 0, 0, + /* IP7_6_4 [3] */ + FN_SSI_SCK78, FN_CAN_DEBUGOUT13, FN_IRQ0_B, FN_SSI_SCK9_B, + FN_HSPI_CLK1_C, 0, 0, 0, + /* IP7_3_2 [2] */ + FN_SSI_SDATA6, FN_ADICHS2, FN_CAN_CLK, FN_IECLK_B, + /* IP7_1_0 [2] */ + FN_SSI_WS6, FN_ADICHS1, FN_CAN0_RX, FN_IETX_B } + }, + { PINMUX_CFG_REG_VAR("IPSR8", 0xfffc0040, 32, + 1, 3, 3, 2, 2, 1, 1, 1, 2, 4, 4, 4, 4) { + /* IP8_31 [1] */ + 0, 0, + /* IP8_30_28 [3] */ + FN_VI0_VSYNC, FN_VI0_DATA1_B_VI0_B1_B, FN_RTS1_C_TANS_C, FN_RX4_D, + FN_PWMFSW0_C, 0, 0, 0, + /* IP8_27_25 [3] */ + FN_VI0_HSYNC, FN_VI0_DATA0_B_VI0_B0_B, FN_CTS1_C, FN_TX4_D, + FN_MMC1_CMD, FN_HSCK1_B, 0, 0, + /* IP8_24_23 [2] */ + FN_VI0_FIELD, FN_RX1_C, FN_HRX1_B, 0, + /* IP8_22_21 [2] */ + FN_VI0_CLKENB, FN_TX1_C, FN_HTX1_B, FN_MT1_SYNC, + /* IP8_20 [1] */ + FN_VI0_CLK, FN_MMC1_CLK, + /* IP8_19 [1] */ + FN_FMIN, FN_RDS_DATA, + /* IP8_18 [1] */ + FN_BPFCLK, FN_PCMWE, + /* IP8_17_16 [2] */ + FN_FMCLK, FN_RDS_CLK, FN_PCMOE, 0, + /* IP8_15_12 [4] */ + FN_HSPI_RX0, FN_RX0, FN_CAN_STEP0, FN_AD_NCS, + FN_CC5_STATE7, FN_CC5_STATE15, FN_CC5_STATE23, FN_CC5_STATE31, + FN_CC5_STATE39, 0, 0, 0, + 0, 0, 0, 0, + /* IP8_11_8 [4] */ + FN_HSPI_TX0, FN_TX0, FN_CAN_DEBUG_HW_TRIGGER, FN_AD_DO, + FN_CC5_STATE6, FN_CC5_STATE14, FN_CC5_STATE22, FN_CC5_STATE30, + FN_CC5_STATE38, 0, 0, 0, + 0, 0, 0, 0, + /* IP8_7_4 [4] */ + FN_HSPI_CS0, FN_RTS0_TANS, FN_USB_OVC1, FN_AD_DI, + FN_CC5_STATE5, FN_CC5_STATE13, FN_CC5_STATE21, FN_CC5_STATE29, + FN_CC5_STATE37, 0, 0, 0, + 0, 0, 0, 0, + /* IP8_3_0 [4] */ + FN_HSPI_CLK0, FN_CTS0, FN_USB_OVC0, FN_AD_CLK, + FN_CC5_STATE4, FN_CC5_STATE12, FN_CC5_STATE20, FN_CC5_STATE28, + FN_CC5_STATE36, 0, 0, 0, + 0, 0, 0, 0 } + }, + { PINMUX_CFG_REG_VAR("IPSR9", 0xfffc0044, 32, + 2, 2, 2, 2, 2, 3, 3, 2, 2, + 2, 2, 1, 1, 1, 1, 2, 2) { + /* IP9_31_30 [2] */ + 0, 0, 0, 0, + /* IP9_29_28 [2] */ + FN_VI0_G7, FN_ETH_RXD1, FN_SD2_DAT3_B, FN_ARM_TRACEDATA_9, + /* IP9_27_26 [2] */ + FN_VI0_G6, FN_ETH_RXD0, FN_SD2_DAT2_B, FN_ARM_TRACEDATA_8, + /* IP9_25_24 [2] */ + FN_VI0_G5, FN_ETH_RX_ER, FN_SD2_DAT1_B, FN_ARM_TRACEDATA_7, + /* IP9_23_22 [2] */ + FN_VI0_G4, FN_ETH_TX_EN, FN_SD2_DAT0_B, FN_ARM_TRACEDATA_6, + /* IP9_21_19 [3] */ + FN_VI0_G3, FN_ETH_CRS_DV, FN_MMC1_D7, FN_ARM_TRACEDATA_5, + FN_TS_SDAT0, 0, 0, 0, + /* IP9_18_16 [3] */ + FN_VI0_G2, FN_ETH_TXD1, FN_MMC1_D6, FN_ARM_TRACEDATA_4, + FN_TS_SPSYNC0, 0, 0, 0, + /* IP9_15_14 [2] */ + FN_VI0_G1, FN_SSI_WS78_C, FN_IRQ1, FN_ARM_TRACEDATA_3, + /* IP9_13_12 [2] */ + FN_VI0_G0, FN_SSI_SCK78_C, FN_IRQ0, FN_ARM_TRACEDATA_2, + /* IP9_11_10 [2] */ + FN_VI0_DATA7_VI0_B7, FN_MMC1_D5, FN_ARM_TRACEDATA_1, 0, + /* IP9_9_8 [2] */ + FN_VI0_DATA6_VI0_B6, FN_MMC1_D4, FN_ARM_TRACEDATA_0, 0, + /* IP9_7 [1] */ + FN_VI0_DATA5_VI0_B5, FN_MMC1_D3, + /* IP9_6 [1] */ + FN_VI0_DATA4_VI0_B4, FN_MMC1_D2, + /* IP9_5 [1] */ + FN_VI0_DATA3_VI0_B3, FN_MMC1_D1, + /* IP9_4 [1] */ + FN_VI0_DATA2_VI0_B2, FN_MMC1_D0, + /* IP9_3_2 [2] */ + FN_VI0_DATA1_VI0_B1, FN_HCTS1_B, FN_MT1_PWM, 0, + /* IP9_1_0 [2] */ + FN_VI0_DATA0_VI0_B0, FN_HRTS1_B, FN_MT1_VCXO, 0 } + }, + { PINMUX_CFG_REG_VAR("IPSR10", 0xfffc0048, 32, + 3, 3, 2, 3, 3, 3, 3, 3, 3, 3, 3) { + /* IP10_31_29 [3] */ + FN_VI1_VSYNC, FN_AUDIO_CLKOUT_C, FN_SSI_WS4, FN_SIM_CLK, + FN_GPS_MAG_C, FN_SPV_TRST, FN_SCL3, 0, + /* IP10_28_26 [3] */ + FN_VI1_HSYNC, FN_VI3_CLK, FN_SSI_SCK4, FN_GPS_SIGN_C, + FN_PWMFSW0_E, 0, 0, 0, + /* IP10_25_24 [2] */ + FN_VI1_CLK, FN_SIM_D, FN_SDA3, 0, + /* IP10_23_21 [3] */ + FN_VI0_R7, FN_ETH_MDIO, FN_DACK2_C, FN_HSPI_RX1_B, + FN_SCIF_CLK_D, FN_TRACECTL, FN_MT1_PEN, 0, + /* IP10_20_18 [3] */ + FN_VI0_R6, FN_ETH_MDC, FN_DREQ2_C, FN_HSPI_TX1_B, + FN_TRACECLK, FN_MT1_BEN, FN_PWMFSW0_D, 0, + /* IP10_17_15 [3] */ + FN_VI0_R5, FN_ETH_TXD0, FN_SD2_WP_B, FN_HSPI_CS1_B, + FN_ARM_TRACEDATA_15, FN_MT1_D, FN_TS_SDEN0, 0, + /* IP10_14_12 [3] */ + FN_VI0_R4, FN_ETH_REFCLK, FN_SD2_CD_B, FN_HSPI_CLK1_B, + FN_ARM_TRACEDATA_14, FN_MT1_CLK, FN_TS_SCK0, 0, + /* IP10_11_9 [3] */ + FN_VI0_R3, FN_ETH_MAGIC, FN_SD2_CMD_B, FN_IRQ3, + FN_ARM_TRACEDATA_13, 0, 0, 0, + /* IP10_8_6 [3] */ + FN_VI0_R2, FN_ETH_LINK, FN_SD2_CLK_B, FN_IRQ2, + FN_ARM_TRACEDATA_12, 0, 0, 0, + /* IP10_5_3 [3] */ + FN_VI0_R1, FN_SSI_SDATA8_C, FN_DACK1_B, FN_ARM_TRACEDATA_11, + FN_DACK0_C, FN_DRACK0_C, 0, 0, + /* IP10_2_0 [3] */ + FN_VI0_R0, FN_SSI_SDATA7_C, FN_SCK1_C, FN_DREQ1_B, + FN_ARM_TRACEDATA_10, FN_DREQ0_C, 0, 0 } + }, + { PINMUX_CFG_REG_VAR("IPSR11", 0xfffc004c, 32, + 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) { + /* IP11_31_30 [2] */ + 0, 0, 0, 0, + /* IP11_29_27 [3] */ + FN_VI1_G1, FN_VI3_DATA1, FN_SSI_SCK1, FN_TS_SDEN1, + FN_DACK2_B, FN_RX2, FN_HRTS0_B, 0, + /* IP11_26_24 [3] */ + FN_VI1_G0, FN_VI3_DATA0, FN_DU1_DOTCLKOUT1, FN_TS_SCK1, + FN_DREQ2_B, FN_TX2, FN_SPA_TDO, FN_HCTS0_B, + /* IP11_23_21 [3] */ + FN_VI1_DATA7_VI1_B7, FN_SD2_WP, FN_MT0_PWM, FN_SPA_TDI, + FN_HSPI_RX1_D, 0, 0, 0, + /* IP11_20_18 [3] */ + FN_VI1_DATA6_VI1_B6, FN_SD2_CD, FN_MT0_VCXO, FN_SPA_TMS, + FN_HSPI_TX1_D, 0, 0, 0, + /* IP11_17_15 [3] */ + FN_VI1_DATA5_VI1_B5, FN_SD2_CMD, FN_MT0_SYNC, FN_SPA_TCK, + FN_HSPI_CS1_D, FN_ADICHS2_B, 0, 0, + /* IP11_14_12 [3] */ + FN_VI1_DATA4_VI1_B4, FN_SD2_CLK, FN_MT0_PEN, FN_SPA_TRST, + FN_HSPI_CLK1_D, FN_ADICHS1_B, 0, 0, + /* IP11_11_9 [3] */ + FN_VI1_DATA3_VI1_B3, FN_SD2_DAT3, FN_MT0_BEN, FN_SPV_TDO, + FN_ADICHS0_B, 0, 0, 0, + /* IP11_8_6 [3] */ + FN_VI1_DATA2_VI1_B2, FN_SD2_DAT2, FN_MT0_D, FN_SPVTDI, + FN_ADIDATA_B, 0, 0, 0, + /* IP11_5_3 [3] */ + FN_VI1_DATA1_VI1_B1, FN_SD2_DAT1, FN_MT0_CLK, FN_SPV_TMS, + FN_ADICS_B_SAMP_B, 0, 0, 0, + /* IP11_2_0 [3] */ + FN_VI1_DATA0_VI1_B0, FN_SD2_DAT0, FN_SIM_RST, FN_SPV_TCK, + FN_ADICLK_B, 0, 0, 0 } + }, + { PINMUX_CFG_REG_VAR("IPSR12", 0xfffc0050, 32, + 4, 4, 4, 2, 3, 3, 3, 3, 3, 3) { + /* IP12_31_28 [4] */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + /* IP12_27_24 [4] */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + /* IP12_23_20 [4] */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + /* IP12_19_18 [2] */ + 0, 0, 0, 0, + /* IP12_17_15 [3] */ + FN_VI1_G7, FN_VI3_DATA7, FN_GPS_MAG, FN_FCE, + FN_SCK4_B, 0, 0, 0, + /* IP12_14_12 [3] */ + FN_VI1_G6, FN_VI3_DATA6, FN_GPS_SIGN, FN_FRB, + FN_RX4_B, FN_SIM_CLK_B, 0, 0, + /* IP12_11_9 [3] */ + FN_VI1_G5, FN_VI3_DATA5, FN_GPS_CLK, FN_FSE, + FN_TX4_B, FN_SIM_D_B, 0, 0, + /* IP12_8_6 [3] */ + FN_VI1_G4, FN_VI3_DATA4, FN_SSI_WS2, FN_SDA1_C, + FN_SIM_RST_B, FN_HRX0_B, 0, 0, + /* IP12_5_3 [3] */ + FN_VI1_G3, FN_VI3_DATA3, FN_SSI_SCK2, FN_TS_SDAT1, + FN_SCL1_C, FN_HTX0_B, 0, 0, + /* IP12_2_0 [3] */ + FN_VI1_G2, FN_VI3_DATA2, FN_SSI_WS1, FN_TS_SPSYNC1, + FN_SCK2, FN_HSCK0_B, 0, 0 } + }, + { PINMUX_CFG_REG_VAR("MOD_SEL", 0xfffc0090, 32, + 2, 2, 3, 3, 2, 2, 2, 2, 2, + 1, 1, 1, 1, 1, 1, 1, 2, 1, 2) { + /* SEL_SCIF5 [2] */ + FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3, + /* SEL_SCIF4 [2] */ + FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3, + /* SEL_SCIF3 [3] */ + FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3, + FN_SEL_SCIF3_4, 0, 0, 0, + /* SEL_SCIF2 [3] */ + FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF2_3, + FN_SEL_SCIF2_4, 0, 0, 0, + /* SEL_SCIF1 [2] */ + FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, 0, + /* SEL_SCIF0 [2] */ + FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3, + /* SEL_SSI9 [2] */ + FN_SEL_SSI9_0, FN_SEL_SSI9_1, FN_SEL_SSI9_2, 0, + /* SEL_SSI8 [2] */ + FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, 0, + /* SEL_SSI7 [2] */ + FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2, 0, + /* SEL_VI0 [1] */ + FN_SEL_VI0_0, FN_SEL_VI0_1, + /* SEL_SD2 [1] */ + FN_SEL_SD2_0, FN_SEL_SD2_1, + /* SEL_INT3 [1] */ + FN_SEL_INT3_0, FN_SEL_INT3_1, + /* SEL_INT2 [1] */ + FN_SEL_INT2_0, FN_SEL_INT2_1, + /* SEL_INT1 [1] */ + FN_SEL_INT1_0, FN_SEL_INT1_1, + /* SEL_INT0 [1] */ + FN_SEL_INT0_0, FN_SEL_INT0_1, + /* SEL_IE [1] */ + FN_SEL_IE_0, FN_SEL_IE_1, + /* SEL_EXBUS2 [2] */ + FN_SEL_EXBUS2_0, FN_SEL_EXBUS2_1, FN_SEL_EXBUS2_2, 0, + /* SEL_EXBUS1 [1] */ + FN_SEL_EXBUS1_0, FN_SEL_EXBUS1_1, + /* SEL_EXBUS0 [2] */ + FN_SEL_EXBUS0_0, FN_SEL_EXBUS0_1, FN_SEL_EXBUS0_2, 0 } + }, + { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xfffc0094, 32, + 2, 2, 2, 2, 1, 1, 1, 3, 1, + 2, 2, 2, 2, 1, 1, 2, 1, 2, 2) { + /* SEL_TMU1 [2] */ + FN_SEL_TMU1_0, FN_SEL_TMU1_1, FN_SEL_TMU1_2, 0, + /* SEL_TMU0 [2] */ + FN_SEL_TMU0_0, FN_SEL_TMU0_1, FN_SEL_TMU0_2, FN_SEL_TMU0_3, + /* SEL_SCIF [2] */ + FN_SEL_SCIF_0, FN_SEL_SCIF_1, FN_SEL_SCIF_2, FN_SEL_SCIF_3, + /* SEL_CANCLK [2] */ + FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2, + /* SEL_CAN0 [1] */ + FN_SEL_CAN0_0, FN_SEL_CAN0_1, + /* SEL_HSCIF1 [1] */ + FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, + /* SEL_HSCIF0 [1] */ + FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, + /* SEL_PWMFSW [3] */ + FN_SEL_PWMFSW_0, FN_SEL_PWMFSW_1, FN_SEL_PWMFSW_2, + FN_SEL_PWMFSW_3, FN_SEL_PWMFSW_4, 0, 0, 0, + /* SEL_ADI [1] */ + FN_SEL_ADI_0, FN_SEL_ADI_1, + /* [2] */ + 0, 0, 0, 0, + /* [2] */ + 0, 0, 0, 0, + /* [2] */ + 0, 0, 0, 0, + /* SEL_GPS [2] */ + FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3, + /* SEL_SIM [1] */ + FN_SEL_SIM_0, FN_SEL_SIM_1, + /* SEL_HSPI2 [1] */ + FN_SEL_HSPI2_0, FN_SEL_HSPI2_1, + /* SEL_HSPI1 [2] */ + FN_SEL_HSPI1_0, FN_SEL_HSPI1_1, FN_SEL_HSPI1_2, FN_SEL_HSPI1_3, + /* SEL_I2C3 [1] */ + FN_SEL_I2C3_0, FN_SEL_I2C3_1, + /* SEL_I2C2 [2] */ + FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3, + /* SEL_I2C1 [2] */ + FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, FN_SEL_I2C1_3 } + }, + { PINMUX_CFG_REG("INOUTSEL0", 0xffc40004, 32, 1) { GP_INOUTSEL(0) } }, + { PINMUX_CFG_REG("INOUTSEL1", 0xffc41004, 32, 1) { GP_INOUTSEL(1) } }, + { PINMUX_CFG_REG("INOUTSEL2", 0xffc42004, 32, 1) { GP_INOUTSEL(2) } }, + { PINMUX_CFG_REG("INOUTSEL3", 0xffc43004, 32, 1) { GP_INOUTSEL(3) } }, + { PINMUX_CFG_REG("INOUTSEL4", 0xffc44004, 32, 1) { GP_INOUTSEL(4) } }, + { PINMUX_CFG_REG("INOUTSEL5", 0xffc45004, 32, 1) { GP_INOUTSEL(5) } }, + { PINMUX_CFG_REG("INOUTSEL6", 0xffc46004, 32, 1) { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_6_8_IN, GP_6_8_OUT, + GP_6_7_IN, GP_6_7_OUT, + GP_6_6_IN, GP_6_6_OUT, + GP_6_5_IN, GP_6_5_OUT, + GP_6_4_IN, GP_6_4_OUT, + GP_6_3_IN, GP_6_3_OUT, + GP_6_2_IN, GP_6_2_OUT, + GP_6_1_IN, GP_6_1_OUT, + GP_6_0_IN, GP_6_0_OUT, } + }, + { }, +}; + +static struct pinmux_data_reg pinmux_data_regs[] = { + { PINMUX_DATA_REG("INDT0", 0xffc40008, 32) { GP_INDT(0) } }, + { PINMUX_DATA_REG("INDT1", 0xffc41008, 32) { GP_INDT(1) } }, + { PINMUX_DATA_REG("INDT2", 0xffc42008, 32) { GP_INDT(2) } }, + { PINMUX_DATA_REG("INDT3", 0xffc43008, 32) { GP_INDT(3) } }, + { PINMUX_DATA_REG("INDT4", 0xffc44008, 32) { GP_INDT(4) } }, + { PINMUX_DATA_REG("INDT5", 0xffc45008, 32) { GP_INDT(5) } }, + { PINMUX_DATA_REG("INDT6", 0xffc46008, 32) { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, GP_6_8_DATA, + GP_6_7_DATA, GP_6_6_DATA, GP_6_5_DATA, GP_6_4_DATA, + GP_6_3_DATA, GP_6_2_DATA, GP_6_1_DATA, GP_6_0_DATA } + }, + { }, +}; + +static struct resource r8a7779_pfc_resources[] = { + [0] = { + .start = 0xfffc0000, + .end = 0xfffc023b, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = 0xffc40000, + .end = 0xffc46fff, + .flags = IORESOURCE_MEM, + } +}; + +static struct pinmux_info r8a7779_pinmux_info = { + .name = "r8a7779_pfc", + + .resource = r8a7779_pfc_resources, + .num_resources = ARRAY_SIZE(r8a7779_pfc_resources), + + .unlock_reg = 0xfffc0000, /* PMMR */ + + .reserved_id = PINMUX_RESERVED, + .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, + .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, + .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, + .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, + .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, + + .first_gpio = GPIO_GP_0_0, + .last_gpio = GPIO_FN_SCK4_B, + + .gpios = pinmux_gpios, + .cfg_regs = pinmux_config_regs, + .data_regs = pinmux_data_regs, + + .gpio_data = pinmux_data, + .gpio_data_size = ARRAY_SIZE(pinmux_data), +}; + +void r8a7779_pinmux_init(void) +{ + register_pinmux(&r8a7779_pinmux_info); +} diff --git a/arch/arm/mach-shmobile/platsmp.c b/arch/arm/mach-shmobile/platsmp.c index c49a833bf9b..993381257f6 100644 --- a/arch/arm/mach-shmobile/platsmp.c +++ b/arch/arm/mach-shmobile/platsmp.c @@ -22,12 +22,16 @@ #include <mach/common.h> #define is_sh73a0() (machine_is_ag5evm() || machine_is_kota2()) +#define is_r8a7779() machine_is_marzen() static unsigned int __init shmobile_smp_get_core_count(void) { if (is_sh73a0()) return sh73a0_get_core_count(); + if (is_r8a7779()) + return r8a7779_get_core_count(); + return 1; } @@ -35,6 +39,17 @@ static void __init shmobile_smp_prepare_cpus(void) { if (is_sh73a0()) sh73a0_smp_prepare_cpus(); + + if (is_r8a7779()) + r8a7779_smp_prepare_cpus(); +} + +int shmobile_platform_cpu_kill(unsigned int cpu) +{ + if (is_r8a7779()) + return r8a7779_platform_cpu_kill(cpu); + + return 1; } void __cpuinit platform_secondary_init(unsigned int cpu) @@ -43,6 +58,9 @@ void __cpuinit platform_secondary_init(unsigned int cpu) if (is_sh73a0()) sh73a0_secondary_init(cpu); + + if (is_r8a7779()) + r8a7779_secondary_init(cpu); } int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) @@ -50,6 +68,9 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) if (is_sh73a0()) return sh73a0_boot_secondary(cpu); + if (is_r8a7779()) + return r8a7779_boot_secondary(cpu); + return -ENOSYS; } diff --git a/arch/arm/mach-shmobile/pm-r8a7779.c b/arch/arm/mach-shmobile/pm-r8a7779.c new file mode 100644 index 00000000000..c38ba7b43ef --- /dev/null +++ b/arch/arm/mach-shmobile/pm-r8a7779.c @@ -0,0 +1,249 @@ +/* + * r8a7779 Power management support + * + * Copyright (C) 2011 Renesas Solutions Corp. + * Copyright (C) 2011 Magnus Damm + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ + +#include <linux/pm.h> +#include <linux/suspend.h> +#include <linux/err.h> +#include <linux/pm_clock.h> +#include <linux/platform_device.h> +#include <linux/delay.h> +#include <linux/irq.h> +#include <linux/interrupt.h> +#include <linux/console.h> +#include <asm/system.h> +#include <asm/io.h> +#include <mach/common.h> +#include <mach/r8a7779.h> + +static void __iomem *r8a7779_sysc_base; + +/* SYSC */ +#define SYSCSR 0x00 +#define SYSCISR 0x04 +#define SYSCISCR 0x08 +#define SYSCIER 0x0c +#define SYSCIMR 0x10 +#define PWRSR0 0x40 +#define PWRSR1 0x80 +#define PWRSR2 0xc0 +#define PWRSR3 0x100 +#define PWRSR4 0x140 + +#define PWRSR_OFFS 0x00 +#define PWROFFCR_OFFS 0x04 +#define PWRONCR_OFFS 0x0c +#define PWRER_OFFS 0x14 + +#define SYSCSR_RETRIES 100 +#define SYSCSR_DELAY_US 1 + +#define SYSCISR_RETRIES 1000 +#define SYSCISR_DELAY_US 1 + +#if defined(CONFIG_PM) || defined(CONFIG_SMP) + +static DEFINE_SPINLOCK(r8a7779_sysc_lock); /* SMP CPUs + I/O devices */ + +static int r8a7779_sysc_pwr_on_off(struct r8a7779_pm_ch *r8a7779_ch, + int sr_bit, int reg_offs) +{ + int k; + + for (k = 0; k < SYSCSR_RETRIES; k++) { + if (ioread32(r8a7779_sysc_base + SYSCSR) & (1 << sr_bit)) + break; + udelay(SYSCSR_DELAY_US); + } + + if (k == SYSCSR_RETRIES) + return -EAGAIN; + + iowrite32(1 << r8a7779_ch->chan_bit, + r8a7779_sysc_base + r8a7779_ch->chan_offs + reg_offs); + + return 0; +} + +static int r8a7779_sysc_pwr_off(struct r8a7779_pm_ch *r8a7779_ch) +{ + return r8a7779_sysc_pwr_on_off(r8a7779_ch, 0, PWROFFCR_OFFS); +} + +static int r8a7779_sysc_pwr_on(struct r8a7779_pm_ch *r8a7779_ch) +{ + return r8a7779_sysc_pwr_on_off(r8a7779_ch, 1, PWRONCR_OFFS); +} + +static int r8a7779_sysc_update(struct r8a7779_pm_ch *r8a7779_ch, + int (*on_off_fn)(struct r8a7779_pm_ch *)) +{ + unsigned int isr_mask = 1 << r8a7779_ch->isr_bit; + unsigned int chan_mask = 1 << r8a7779_ch->chan_bit; + unsigned int status; + unsigned long flags; + int ret = 0; + int k; + + spin_lock_irqsave(&r8a7779_sysc_lock, flags); + + iowrite32(isr_mask, r8a7779_sysc_base + SYSCISCR); + + do { + ret = on_off_fn(r8a7779_ch); + if (ret) + goto out; + + status = ioread32(r8a7779_sysc_base + + r8a7779_ch->chan_offs + PWRER_OFFS); + } while (status & chan_mask); + + for (k = 0; k < SYSCISR_RETRIES; k++) { + if (ioread32(r8a7779_sysc_base + SYSCISR) & isr_mask) + break; + udelay(SYSCISR_DELAY_US); + } + + if (k == SYSCISR_RETRIES) + ret = -EIO; + + iowrite32(isr_mask, r8a7779_sysc_base + SYSCISCR); + + out: + spin_unlock_irqrestore(&r8a7779_sysc_lock, flags); + + pr_debug("r8a7779 power domain %d: %02x %02x %02x %02x %02x -> %d\n", + r8a7779_ch->isr_bit, ioread32(r8a7779_sysc_base + PWRSR0), + ioread32(r8a7779_sysc_base + PWRSR1), + ioread32(r8a7779_sysc_base + PWRSR2), + ioread32(r8a7779_sysc_base + PWRSR3), + ioread32(r8a7779_sysc_base + PWRSR4), ret); + return ret; +} + +int r8a7779_sysc_power_down(struct r8a7779_pm_ch *r8a7779_ch) +{ + return r8a7779_sysc_update(r8a7779_ch, r8a7779_sysc_pwr_off); +} + +int r8a7779_sysc_power_up(struct r8a7779_pm_ch *r8a7779_ch) +{ + return r8a7779_sysc_update(r8a7779_ch, r8a7779_sysc_pwr_on); +} + +static void __init r8a7779_sysc_init(void) +{ + r8a7779_sysc_base = ioremap_nocache(0xffd85000, PAGE_SIZE); + if (!r8a7779_sysc_base) + panic("unable to ioremap r8a7779 SYSC hardware block\n"); + + /* enable all interrupt sources, but do not use interrupt handler */ + iowrite32(0x0131000e, r8a7779_sysc_base + SYSCIER); + iowrite32(0, r8a7779_sysc_base + SYSCIMR); +} + +#else /* CONFIG_PM || CONFIG_SMP */ + +static inline void r8a7779_sysc_init(void) {} + +#endif /* CONFIG_PM || CONFIG_SMP */ + +#ifdef CONFIG_PM + +static int pd_power_down(struct generic_pm_domain *genpd) +{ + return r8a7779_sysc_power_down(to_r8a7779_ch(genpd)); +} + +static int pd_power_up(struct generic_pm_domain *genpd) +{ + return r8a7779_sysc_power_up(to_r8a7779_ch(genpd)); +} + +static bool pd_is_off(struct generic_pm_domain *genpd) +{ + struct r8a7779_pm_ch *r8a7779_ch = to_r8a7779_ch(genpd); + unsigned int st; + + st = ioread32(r8a7779_sysc_base + r8a7779_ch->chan_offs + PWRSR_OFFS); + if (st & (1 << r8a7779_ch->chan_bit)) + return true; + + return false; +} + +static bool pd_active_wakeup(struct device *dev) +{ + return true; +} + +void r8a7779_init_pm_domain(struct r8a7779_pm_domain *r8a7779_pd) +{ + struct generic_pm_domain *genpd = &r8a7779_pd->genpd; + + pm_genpd_init(genpd, NULL, false); + genpd->dev_ops.stop = pm_clk_suspend; + genpd->dev_ops.start = pm_clk_resume; + genpd->dev_ops.active_wakeup = pd_active_wakeup; + genpd->dev_irq_safe = true; + genpd->power_off = pd_power_down; + genpd->power_on = pd_power_up; + + if (pd_is_off(&r8a7779_pd->genpd)) + pd_power_up(&r8a7779_pd->genpd); +} + +void r8a7779_add_device_to_domain(struct r8a7779_pm_domain *r8a7779_pd, + struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + + pm_genpd_add_device(&r8a7779_pd->genpd, dev); + if (pm_clk_no_clocks(dev)) + pm_clk_add(dev, NULL); +} + +struct r8a7779_pm_domain r8a7779_sh4a = { + .ch = { + .chan_offs = 0x80, /* PWRSR1 .. PWRER1 */ + .isr_bit = 16, /* SH4A */ + } +}; + +struct r8a7779_pm_domain r8a7779_sgx = { + .ch = { + .chan_offs = 0xc0, /* PWRSR2 .. PWRER2 */ + .isr_bit = 20, /* SGX */ + } +}; + +struct r8a7779_pm_domain r8a7779_vdp1 = { + .ch = { + .chan_offs = 0x100, /* PWRSR3 .. PWRER3 */ + .isr_bit = 21, /* VDP */ + } +}; + +struct r8a7779_pm_domain r8a7779_impx3 = { + .ch = { + .chan_offs = 0x140, /* PWRSR4 .. PWRER4 */ + .isr_bit = 24, /* IMP */ + } +}; + +#endif /* CONFIG_PM */ + +void __init r8a7779_pm_init(void) +{ + static int once; + + if (!once++) + r8a7779_sysc_init(); +} diff --git a/arch/arm/mach-shmobile/pm-sh7372.c b/arch/arm/mach-shmobile/pm-sh7372.c index 34bbcbfb170..77b8fc12fc2 100644 --- a/arch/arm/mach-shmobile/pm-sh7372.c +++ b/arch/arm/mach-shmobile/pm-sh7372.c @@ -82,11 +82,12 @@ static int pd_power_down(struct generic_pm_domain *genpd) struct sh7372_pm_domain *sh7372_pd = to_sh7372_pd(genpd); unsigned int mask = 1 << sh7372_pd->bit_shift; - if (sh7372_pd->suspend) - sh7372_pd->suspend(); + if (sh7372_pd->suspend) { + int ret = sh7372_pd->suspend(); - if (sh7372_pd->stay_on) - return 0; + if (ret) + return ret; + } if (__raw_readl(PSTR) & mask) { unsigned int retry_count; @@ -101,8 +102,8 @@ static int pd_power_down(struct generic_pm_domain *genpd) } if (!sh7372_pd->no_debug) - pr_debug("sh7372 power domain down 0x%08x -> PSTR = 0x%08x\n", - mask, __raw_readl(PSTR)); + pr_debug("%s: Power off, 0x%08x -> PSTR = 0x%08x\n", + genpd->name, mask, __raw_readl(PSTR)); return 0; } @@ -113,9 +114,6 @@ static int __pd_power_up(struct sh7372_pm_domain *sh7372_pd, bool do_resume) unsigned int retry_count; int ret = 0; - if (sh7372_pd->stay_on) - goto out; - if (__raw_readl(PSTR) & mask) goto out; @@ -133,8 +131,8 @@ static int __pd_power_up(struct sh7372_pm_domain *sh7372_pd, bool do_resume) ret = -EIO; if (!sh7372_pd->no_debug) - pr_debug("sh7372 power domain up 0x%08x -> PSTR = 0x%08x\n", - mask, __raw_readl(PSTR)); + pr_debug("%s: Power on, 0x%08x -> PSTR = 0x%08x\n", + sh7372_pd->genpd.name, mask, __raw_readl(PSTR)); out: if (ret == 0 && sh7372_pd->resume && do_resume) @@ -148,35 +146,60 @@ static int pd_power_up(struct generic_pm_domain *genpd) return __pd_power_up(to_sh7372_pd(genpd), true); } -static void sh7372_a4r_suspend(void) +static int sh7372_a4r_suspend(void) { sh7372_intcs_suspend(); __raw_writel(0x300fffff, WUPRMSK); /* avoid wakeup */ + return 0; } static bool pd_active_wakeup(struct device *dev) { - return true; + bool (*active_wakeup)(struct device *dev); + + active_wakeup = dev_gpd_data(dev)->ops.active_wakeup; + return active_wakeup ? active_wakeup(dev) : true; } -static bool sh7372_power_down_forbidden(struct dev_pm_domain *domain) +static int sh7372_stop_dev(struct device *dev) { - return false; + int (*stop)(struct device *dev); + + stop = dev_gpd_data(dev)->ops.stop; + if (stop) { + int ret = stop(dev); + if (ret) + return ret; + } + return pm_clk_suspend(dev); } -struct dev_power_governor sh7372_always_on_gov = { - .power_down_ok = sh7372_power_down_forbidden, -}; +static int sh7372_start_dev(struct device *dev) +{ + int (*start)(struct device *dev); + int ret; + + ret = pm_clk_resume(dev); + if (ret) + return ret; + + start = dev_gpd_data(dev)->ops.start; + if (start) + ret = start(dev); + + return ret; +} void sh7372_init_pm_domain(struct sh7372_pm_domain *sh7372_pd) { struct generic_pm_domain *genpd = &sh7372_pd->genpd; + struct dev_power_governor *gov = sh7372_pd->gov; - pm_genpd_init(genpd, sh7372_pd->gov, false); - genpd->stop_device = pm_clk_suspend; - genpd->start_device = pm_clk_resume; + pm_genpd_init(genpd, gov ? : &simple_qos_governor, false); + genpd->dev_ops.stop = sh7372_stop_dev; + genpd->dev_ops.start = sh7372_start_dev; + genpd->dev_ops.active_wakeup = pd_active_wakeup; genpd->dev_irq_safe = true; - genpd->active_wakeup = pd_active_wakeup; genpd->power_off = pd_power_down; genpd->power_on = pd_power_up; __pd_power_up(sh7372_pd, false); @@ -199,48 +222,73 @@ void sh7372_pm_add_subdomain(struct sh7372_pm_domain *sh7372_pd, } struct sh7372_pm_domain sh7372_a4lc = { + .genpd.name = "A4LC", .bit_shift = 1, }; struct sh7372_pm_domain sh7372_a4mp = { + .genpd.name = "A4MP", .bit_shift = 2, }; struct sh7372_pm_domain sh7372_d4 = { + .genpd.name = "D4", .bit_shift = 3, }; struct sh7372_pm_domain sh7372_a4r = { + .genpd.name = "A4R", .bit_shift = 5, - .gov = &sh7372_always_on_gov, .suspend = sh7372_a4r_suspend, .resume = sh7372_intcs_resume, - .stay_on = true, }; struct sh7372_pm_domain sh7372_a3rv = { + .genpd.name = "A3RV", .bit_shift = 6, }; struct sh7372_pm_domain sh7372_a3ri = { + .genpd.name = "A3RI", .bit_shift = 8, }; -struct sh7372_pm_domain sh7372_a3sp = { - .bit_shift = 11, - .gov = &sh7372_always_on_gov, +static int sh7372_a4s_suspend(void) +{ + /* + * The A4S domain contains the CPU core and therefore it should + * only be turned off if the CPU is in use. + */ + return -EBUSY; +} + +struct sh7372_pm_domain sh7372_a4s = { + .genpd.name = "A4S", + .bit_shift = 10, + .gov = &pm_domain_always_on_gov, .no_debug = true, + .suspend = sh7372_a4s_suspend, }; -static void sh7372_a3sp_init(void) +static int sh7372_a3sp_suspend(void) { - /* serial consoles make use of SCIF hardware located in A3SP, + /* + * Serial consoles make use of SCIF hardware located in A3SP, * keep such power domain on if "no_console_suspend" is set. */ - sh7372_a3sp.stay_on = !console_suspend_enabled; + return console_suspend_enabled ? -EBUSY : 0; } +struct sh7372_pm_domain sh7372_a3sp = { + .genpd.name = "A3SP", + .bit_shift = 11, + .gov = &pm_domain_always_on_gov, + .no_debug = true, + .suspend = sh7372_a3sp_suspend, +}; + struct sh7372_pm_domain sh7372_a3sg = { + .genpd.name = "A3SG", .bit_shift = 13, }; @@ -257,11 +305,16 @@ static int sh7372_do_idle_core_standby(unsigned long unused) return 0; } -static void sh7372_enter_core_standby(void) +static void sh7372_set_reset_vector(unsigned long address) { /* set reset vector, translate 4k */ - __raw_writel(__pa(sh7372_resume_core_standby_a3sm), SBAR); + __raw_writel(address, SBAR); __raw_writel(0, APARMBAREA); +} + +static void sh7372_enter_core_standby(void) +{ + sh7372_set_reset_vector(__pa(sh7372_resume_core_standby_sysc)); /* enter sleep mode with SYSTBCR to 0x10 */ __raw_writel(0x10, SYSTBCR); @@ -274,27 +327,22 @@ static void sh7372_enter_core_standby(void) #endif #ifdef CONFIG_SUSPEND -static void sh7372_enter_a3sm_common(int pllc0_on) +static void sh7372_enter_sysc(int pllc0_on, unsigned long sleep_mode) { - /* set reset vector, translate 4k */ - __raw_writel(__pa(sh7372_resume_core_standby_a3sm), SBAR); - __raw_writel(0, APARMBAREA); - if (pllc0_on) __raw_writel(0, PLLC01STPCR); else __raw_writel(1 << 28, PLLC01STPCR); - __raw_writel(0, PDNSEL); /* power-down A3SM only, not A4S */ __raw_readl(WUPSFAC); /* read wakeup int. factor before sleep */ - cpu_suspend(0, sh7372_do_idle_a3sm); + cpu_suspend(sleep_mode, sh7372_do_idle_sysc); __raw_readl(WUPSFAC); /* read wakeup int. factor after wakeup */ /* disable reset vector translation */ __raw_writel(0, SBAR); } -static int sh7372_a3sm_valid(unsigned long *mskp, unsigned long *msk2p) +static int sh7372_sysc_valid(unsigned long *mskp, unsigned long *msk2p) { unsigned long mstpsr0, mstpsr1, mstpsr2, mstpsr3, mstpsr4; unsigned long msk, msk2; @@ -382,7 +430,7 @@ static void sh7372_icr_to_irqcr(unsigned long icr, u16 *irqcr1p, u16 *irqcr2p) *irqcr2p = irqcr2; } -static void sh7372_setup_a3sm(unsigned long msk, unsigned long msk2) +static void sh7372_setup_sysc(unsigned long msk, unsigned long msk2) { u16 irqcrx_low, irqcrx_high, irqcry_low, irqcry_high; unsigned long tmp; @@ -415,6 +463,22 @@ static void sh7372_setup_a3sm(unsigned long msk, unsigned long msk2) __raw_writel((irqcrx_high << 16) | irqcrx_low, IRQCR3); __raw_writel((irqcry_high << 16) | irqcry_low, IRQCR4); } + +static void sh7372_enter_a3sm_common(int pllc0_on) +{ + sh7372_set_reset_vector(__pa(sh7372_resume_core_standby_sysc)); + sh7372_enter_sysc(pllc0_on, 1 << 12); +} + +static void sh7372_enter_a4s_common(int pllc0_on) +{ + sh7372_intca_suspend(); + memcpy((void *)SMFRAM, sh7372_resume_core_standby_sysc, 0x100); + sh7372_set_reset_vector(SMFRAM); + sh7372_enter_sysc(pllc0_on, 1 << 10); + sh7372_intca_resume(); +} + #endif #ifdef CONFIG_CPU_IDLE @@ -448,14 +512,20 @@ static int sh7372_enter_suspend(suspend_state_t suspend_state) unsigned long msk, msk2; /* check active clocks to determine potential wakeup sources */ - if (sh7372_a3sm_valid(&msk, &msk2)) { - + if (sh7372_sysc_valid(&msk, &msk2)) { /* convert INTC mask and sense to SYSC mask and sense */ - sh7372_setup_a3sm(msk, msk2); - - /* enter A3SM sleep with PLLC0 off */ - pr_debug("entering A3SM\n"); - sh7372_enter_a3sm_common(0); + sh7372_setup_sysc(msk, msk2); + + if (!console_suspend_enabled && + sh7372_a4s.genpd.status == GPD_STATE_POWER_OFF) { + /* enter A4S sleep with PLLC0 off */ + pr_debug("entering A4S\n"); + sh7372_enter_a4s_common(0); + } else { + /* enter A3SM sleep with PLLC0 off */ + pr_debug("entering A3SM\n"); + sh7372_enter_a3sm_common(0); + } } else { /* default to Core Standby that supports all wakeup sources */ pr_debug("entering Core Standby\n"); @@ -464,9 +534,37 @@ static int sh7372_enter_suspend(suspend_state_t suspend_state) return 0; } +/** + * sh7372_pm_notifier_fn - SH7372 PM notifier routine. + * @notifier: Unused. + * @pm_event: Event being handled. + * @unused: Unused. + */ +static int sh7372_pm_notifier_fn(struct notifier_block *notifier, + unsigned long pm_event, void *unused) +{ + switch (pm_event) { + case PM_SUSPEND_PREPARE: + /* + * This is necessary, because the A4R domain has to be "on" + * when suspend_device_irqs() and resume_device_irqs() are + * executed during system suspend and resume, respectively, so + * that those functions don't crash while accessing the INTCS. + */ + pm_genpd_poweron(&sh7372_a4r.genpd); + break; + case PM_POST_SUSPEND: + pm_genpd_poweroff_unused(); + break; + } + + return NOTIFY_DONE; +} + static void sh7372_suspend_init(void) { shmobile_suspend_ops.enter = sh7372_enter_suspend; + pm_notifier(sh7372_pm_notifier_fn, 0); } #else static void sh7372_suspend_init(void) {} @@ -482,8 +580,6 @@ void __init sh7372_pm_init(void) /* do not convert A3SM, A3SP, A3SG, A4R power down into A4S */ __raw_writel(0, PDNSEL); - sh7372_a3sp_init(); - sh7372_suspend_init(); sh7372_cpuidle_init(); } diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c new file mode 100644 index 00000000000..986dca6b3fa --- /dev/null +++ b/arch/arm/mach-shmobile/setup-r8a7740.c @@ -0,0 +1,352 @@ +/* + * R8A7740 processor support + * + * Copyright (C) 2011 Renesas Solutions Corp. + * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include <linux/delay.h> +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/platform_device.h> +#include <linux/serial_sci.h> +#include <linux/sh_timer.h> +#include <mach/r8a7740.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> + +/* SCIFA0 */ +static struct plat_sci_port scif0_platform_data = { + .mapbase = 0xe6c40000, + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RE | SCSCR_TE, + .scbrr_algo_id = SCBRR_ALGO_4, + .type = PORT_SCIFA, + .irqs = SCIx_IRQ_MUXED(evt2irq(0x0c00)), +}; + +static struct platform_device scif0_device = { + .name = "sh-sci", + .id = 0, + .dev = { + .platform_data = &scif0_platform_data, + }, +}; + +/* SCIFA1 */ +static struct plat_sci_port scif1_platform_data = { + .mapbase = 0xe6c50000, + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RE | SCSCR_TE, + .scbrr_algo_id = SCBRR_ALGO_4, + .type = PORT_SCIFA, + .irqs = SCIx_IRQ_MUXED(evt2irq(0x0c20)), +}; + +static struct platform_device scif1_device = { + .name = "sh-sci", + .id = 1, + .dev = { + .platform_data = &scif1_platform_data, + }, +}; + +/* SCIFA2 */ +static struct plat_sci_port scif2_platform_data = { + .mapbase = 0xe6c60000, + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RE | SCSCR_TE, + .scbrr_algo_id = SCBRR_ALGO_4, + .type = PORT_SCIFA, + .irqs = SCIx_IRQ_MUXED(evt2irq(0x0c40)), +}; + +static struct platform_device scif2_device = { + .name = "sh-sci", + .id = 2, + .dev = { + .platform_data = &scif2_platform_data, + }, +}; + +/* SCIFA3 */ +static struct plat_sci_port scif3_platform_data = { + .mapbase = 0xe6c70000, + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RE | SCSCR_TE, + .scbrr_algo_id = SCBRR_ALGO_4, + .type = PORT_SCIFA, + .irqs = SCIx_IRQ_MUXED(evt2irq(0x0c60)), +}; + +static struct platform_device scif3_device = { + .name = "sh-sci", + .id = 3, + .dev = { + .platform_data = &scif3_platform_data, + }, +}; + +/* SCIFA4 */ +static struct plat_sci_port scif4_platform_data = { + .mapbase = 0xe6c80000, + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RE | SCSCR_TE, + .scbrr_algo_id = SCBRR_ALGO_4, + .type = PORT_SCIFA, + .irqs = SCIx_IRQ_MUXED(evt2irq(0x0d20)), +}; + +static struct platform_device scif4_device = { + .name = "sh-sci", + .id = 4, + .dev = { + .platform_data = &scif4_platform_data, + }, +}; + +/* SCIFA5 */ +static struct plat_sci_port scif5_platform_data = { + .mapbase = 0xe6cb0000, + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RE | SCSCR_TE, + .scbrr_algo_id = SCBRR_ALGO_4, + .type = PORT_SCIFA, + .irqs = SCIx_IRQ_MUXED(evt2irq(0x0d40)), +}; + +static struct platform_device scif5_device = { + .name = "sh-sci", + .id = 5, + .dev = { + .platform_data = &scif5_platform_data, + }, +}; + +/* SCIFA6 */ +static struct plat_sci_port scif6_platform_data = { + .mapbase = 0xe6cc0000, + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RE | SCSCR_TE, + .scbrr_algo_id = SCBRR_ALGO_4, + .type = PORT_SCIFA, + .irqs = SCIx_IRQ_MUXED(evt2irq(0x04c0)), +}; + +static struct platform_device scif6_device = { + .name = "sh-sci", + .id = 6, + .dev = { + .platform_data = &scif6_platform_data, + }, +}; + +/* SCIFA7 */ +static struct plat_sci_port scif7_platform_data = { + .mapbase = 0xe6cd0000, + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RE | SCSCR_TE, + .scbrr_algo_id = SCBRR_ALGO_4, + .type = PORT_SCIFA, + .irqs = SCIx_IRQ_MUXED(evt2irq(0x04e0)), +}; + +static struct platform_device scif7_device = { + .name = "sh-sci", + .id = 7, + .dev = { + .platform_data = &scif7_platform_data, + }, +}; + +/* SCIFB */ +static struct plat_sci_port scifb_platform_data = { + .mapbase = 0xe6c30000, + .flags = UPF_BOOT_AUTOCONF, + .scscr = SCSCR_RE | SCSCR_TE, + .scbrr_algo_id = SCBRR_ALGO_4, + .type = PORT_SCIFB, + .irqs = SCIx_IRQ_MUXED(evt2irq(0x0d60)), +}; + +static struct platform_device scifb_device = { + .name = "sh-sci", + .id = 8, + .dev = { + .platform_data = &scifb_platform_data, + }, +}; + +/* CMT */ +static struct sh_timer_config cmt10_platform_data = { + .name = "CMT10", + .channel_offset = 0x10, + .timer_bit = 0, + .clockevent_rating = 125, + .clocksource_rating = 125, +}; + +static struct resource cmt10_resources[] = { + [0] = { + .name = "CMT10", + .start = 0xe6138010, + .end = 0xe613801b, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0x0b00), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device cmt10_device = { + .name = "sh_cmt", + .id = 10, + .dev = { + .platform_data = &cmt10_platform_data, + }, + .resource = cmt10_resources, + .num_resources = ARRAY_SIZE(cmt10_resources), +}; + +static struct platform_device *r8a7740_early_devices[] __initdata = { + &scif0_device, + &scif1_device, + &scif2_device, + &scif3_device, + &scif4_device, + &scif5_device, + &scif6_device, + &scif7_device, + &scifb_device, + &cmt10_device, +}; + +/* I2C */ +static struct resource i2c0_resources[] = { + [0] = { + .name = "IIC0", + .start = 0xfff20000, + .end = 0xfff20425 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = intcs_evt2irq(0xe00), + .end = intcs_evt2irq(0xe60), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource i2c1_resources[] = { + [0] = { + .name = "IIC1", + .start = 0xe6c20000, + .end = 0xe6c20425 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0x780), /* IIC1_ALI1 */ + .end = evt2irq(0x7e0), /* IIC1_DTEI1 */ + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device i2c0_device = { + .name = "i2c-sh_mobile", + .id = 0, + .resource = i2c0_resources, + .num_resources = ARRAY_SIZE(i2c0_resources), +}; + +static struct platform_device i2c1_device = { + .name = "i2c-sh_mobile", + .id = 1, + .resource = i2c1_resources, + .num_resources = ARRAY_SIZE(i2c1_resources), +}; + +static struct platform_device *r8a7740_late_devices[] __initdata = { + &i2c0_device, + &i2c1_device, +}; + +#define ICCR 0x0004 +#define ICSTART 0x0070 + +#define i2c_read(reg, offset) ioread8(reg + offset) +#define i2c_write(reg, offset, data) iowrite8(data, reg + offset) + +/* + * r8a7740 chip has lasting errata on I2C I/O pad reset. + * this is work-around for it. + */ +static void r8a7740_i2c_workaround(struct platform_device *pdev) +{ + struct resource *res; + void __iomem *reg; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (unlikely(!res)) { + pr_err("r8a7740 i2c workaround fail (cannot find resource)\n"); + return; + } + + reg = ioremap(res->start, resource_size(res)); + if (unlikely(!reg)) { + pr_err("r8a7740 i2c workaround fail (cannot map IO)\n"); + return; + } + + i2c_write(reg, ICCR, i2c_read(reg, ICCR) | 0x80); + i2c_read(reg, ICCR); /* dummy read */ + + i2c_write(reg, ICSTART, i2c_read(reg, ICSTART) | 0x10); + i2c_read(reg, ICSTART); /* dummy read */ + + mdelay(100); + + i2c_write(reg, ICCR, 0x01); + i2c_read(reg, ICCR); + i2c_write(reg, ICSTART, 0x00); + i2c_read(reg, ICSTART); + + i2c_write(reg, ICCR, 0x10); + mdelay(100); + i2c_write(reg, ICCR, 0x00); + mdelay(100); + i2c_write(reg, ICCR, 0x10); + mdelay(100); + + iounmap(reg); +} + +void __init r8a7740_add_standard_devices(void) +{ + /* I2C work-around */ + r8a7740_i2c_workaround(&i2c0_device); + r8a7740_i2c_workaround(&i2c1_device); + + platform_add_devices(r8a7740_early_devices, + ARRAY_SIZE(r8a7740_early_devices)); + platform_add_devices(r8a7740_late_devices, + ARRAY_SIZE(r8a7740_late_devices)); +} + +void __init r8a7740_add_early_devices(void) +{ + early_platform_add_devices(r8a7740_early_devices, + ARRAY_SIZE(r8a7740_early_devices)); +} diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c new file mode 100644 index 00000000000..4725663bd03 --- /dev/null +++ b/arch/arm/mach-shmobile/setup-r8a7779.c @@ -0,0 +1,239 @@ +/* + * r8a7779 processor support + * + * Copyright (C) 2011 Renesas Solutions Corp. + * Copyright (C) 2011 Magnus Damm + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/platform_device.h> +#include <linux/delay.h> +#include <linux/input.h> +#include <linux/io.h> +#include <linux/serial_sci.h> +#include <linux/sh_intc.h> +#include <linux/sh_timer.h> +#include <mach/hardware.h> +#include <mach/r8a7779.h> +#include <mach/common.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> + +static struct plat_sci_port scif0_platform_data = { + .mapbase = 0xffe40000, + .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, + .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, + .scbrr_algo_id = SCBRR_ALGO_2, + .type = PORT_SCIF, + .irqs = { gic_spi(88), gic_spi(88), + gic_spi(88), gic_spi(88) }, +}; + +static struct platform_device scif0_device = { + .name = "sh-sci", + .id = 0, + .dev = { + .platform_data = &scif0_platform_data, + }, +}; + +static struct plat_sci_port scif1_platform_data = { + .mapbase = 0xffe41000, + .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, + .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, + .scbrr_algo_id = SCBRR_ALGO_2, + .type = PORT_SCIF, + .irqs = { gic_spi(89), gic_spi(89), + gic_spi(89), gic_spi(89) }, +}; + +static struct platform_device scif1_device = { + .name = "sh-sci", + .id = 1, + .dev = { + .platform_data = &scif1_platform_data, + }, +}; + +static struct plat_sci_port scif2_platform_data = { + .mapbase = 0xffe42000, + .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, + .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, + .scbrr_algo_id = SCBRR_ALGO_2, + .type = PORT_SCIF, + .irqs = { gic_spi(90), gic_spi(90), + gic_spi(90), gic_spi(90) }, +}; + +static struct platform_device scif2_device = { + .name = "sh-sci", + .id = 2, + .dev = { + .platform_data = &scif2_platform_data, + }, +}; + +static struct plat_sci_port scif3_platform_data = { + .mapbase = 0xffe43000, + .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, + .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, + .scbrr_algo_id = SCBRR_ALGO_2, + .type = PORT_SCIF, + .irqs = { gic_spi(91), gic_spi(91), + gic_spi(91), gic_spi(91) }, +}; + +static struct platform_device scif3_device = { + .name = "sh-sci", + .id = 3, + .dev = { + .platform_data = &scif3_platform_data, + }, +}; + +static struct plat_sci_port scif4_platform_data = { + .mapbase = 0xffe44000, + .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, + .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, + .scbrr_algo_id = SCBRR_ALGO_2, + .type = PORT_SCIF, + .irqs = { gic_spi(92), gic_spi(92), + gic_spi(92), gic_spi(92) }, +}; + +static struct platform_device scif4_device = { + .name = "sh-sci", + .id = 4, + .dev = { + .platform_data = &scif4_platform_data, + }, +}; + +static struct plat_sci_port scif5_platform_data = { + .mapbase = 0xffe45000, + .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, + .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, + .scbrr_algo_id = SCBRR_ALGO_2, + .type = PORT_SCIF, + .irqs = { gic_spi(93), gic_spi(93), + gic_spi(93), gic_spi(93) }, +}; + +static struct platform_device scif5_device = { + .name = "sh-sci", + .id = 5, + .dev = { + .platform_data = &scif5_platform_data, + }, +}; + +/* TMU */ +static struct sh_timer_config tmu00_platform_data = { + .name = "TMU00", + .channel_offset = 0x4, + .timer_bit = 0, + .clockevent_rating = 200, +}; + +static struct resource tmu00_resources[] = { + [0] = { + .name = "TMU00", + .start = 0xffd80008, + .end = 0xffd80013, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = gic_spi(32), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device tmu00_device = { + .name = "sh_tmu", + .id = 0, + .dev = { + .platform_data = &tmu00_platform_data, + }, + .resource = tmu00_resources, + .num_resources = ARRAY_SIZE(tmu00_resources), +}; + +static struct sh_timer_config tmu01_platform_data = { + .name = "TMU01", + .channel_offset = 0x10, + .timer_bit = 1, + .clocksource_rating = 200, +}; + +static struct resource tmu01_resources[] = { + [0] = { + .name = "TMU01", + .start = 0xffd80014, + .end = 0xffd8001f, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = gic_spi(33), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device tmu01_device = { + .name = "sh_tmu", + .id = 1, + .dev = { + .platform_data = &tmu01_platform_data, + }, + .resource = tmu01_resources, + .num_resources = ARRAY_SIZE(tmu01_resources), +}; + +static struct platform_device *r8a7779_early_devices[] __initdata = { + &scif0_device, + &scif1_device, + &scif2_device, + &scif3_device, + &scif4_device, + &scif5_device, + &tmu00_device, + &tmu01_device, +}; + +static struct platform_device *r8a7779_late_devices[] __initdata = { +}; + +void __init r8a7779_add_standard_devices(void) +{ + r8a7779_pm_init(); + + r8a7779_init_pm_domain(&r8a7779_sh4a); + r8a7779_init_pm_domain(&r8a7779_sgx); + r8a7779_init_pm_domain(&r8a7779_vdp1); + r8a7779_init_pm_domain(&r8a7779_impx3); + + platform_add_devices(r8a7779_early_devices, + ARRAY_SIZE(r8a7779_early_devices)); + platform_add_devices(r8a7779_late_devices, + ARRAY_SIZE(r8a7779_late_devices)); +} + +void __init r8a7779_add_early_devices(void) +{ + early_platform_add_devices(r8a7779_early_devices, + ARRAY_SIZE(r8a7779_early_devices)); +} diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c index 2380389e6ac..1ea89be63e2 100644 --- a/arch/arm/mach-shmobile/setup-sh7372.c +++ b/arch/arm/mach-shmobile/setup-sh7372.c @@ -504,7 +504,7 @@ static struct resource sh7372_dmae0_resources[] = { .flags = IORESOURCE_MEM, }, { - /* DMA error IRQ */ + .name = "error_irq", .start = evt2irq(0x20c0), .end = evt2irq(0x20c0), .flags = IORESOURCE_IRQ, @@ -532,7 +532,7 @@ static struct resource sh7372_dmae1_resources[] = { .flags = IORESOURCE_MEM, }, { - /* DMA error IRQ */ + .name = "error_irq", .start = evt2irq(0x21c0), .end = evt2irq(0x21c0), .flags = IORESOURCE_IRQ, @@ -560,7 +560,7 @@ static struct resource sh7372_dmae2_resources[] = { .flags = IORESOURCE_MEM, }, { - /* DMA error IRQ */ + .name = "error_irq", .start = evt2irq(0x22c0), .end = evt2irq(0x22c0), .flags = IORESOURCE_IRQ, @@ -994,12 +994,16 @@ void __init sh7372_add_standard_devices(void) sh7372_init_pm_domain(&sh7372_a4r); sh7372_init_pm_domain(&sh7372_a3rv); sh7372_init_pm_domain(&sh7372_a3ri); - sh7372_init_pm_domain(&sh7372_a3sg); + sh7372_init_pm_domain(&sh7372_a4s); sh7372_init_pm_domain(&sh7372_a3sp); + sh7372_init_pm_domain(&sh7372_a3sg); sh7372_pm_add_subdomain(&sh7372_a4lc, &sh7372_a3rv); sh7372_pm_add_subdomain(&sh7372_a4r, &sh7372_a4lc); + sh7372_pm_add_subdomain(&sh7372_a4s, &sh7372_a3sg); + sh7372_pm_add_subdomain(&sh7372_a4s, &sh7372_a3sp); + platform_add_devices(sh7372_early_devices, ARRAY_SIZE(sh7372_early_devices)); diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c index e46821c0a62..20e71e5cace 100644 --- a/arch/arm/mach-shmobile/setup-sh73a0.c +++ b/arch/arm/mach-shmobile/setup-sh73a0.c @@ -607,7 +607,7 @@ static struct resource sh73a0_dmae_resources[] = { .flags = IORESOURCE_MEM, }, { - /* DMA error IRQ */ + .name = "error_irq", .start = gic_spi(129), .end = gic_spi(129), .flags = IORESOURCE_IRQ, diff --git a/arch/arm/mach-shmobile/sleep-sh7372.S b/arch/arm/mach-shmobile/sleep-sh7372.S index f3ab3c5810e..1d564674451 100644 --- a/arch/arm/mach-shmobile/sleep-sh7372.S +++ b/arch/arm/mach-shmobile/sleep-sh7372.S @@ -37,13 +37,18 @@ #if defined(CONFIG_SUSPEND) || defined(CONFIG_CPU_IDLE) .align 12 .text - .global sh7372_resume_core_standby_a3sm -sh7372_resume_core_standby_a3sm: + .global sh7372_resume_core_standby_sysc +sh7372_resume_core_standby_sysc: ldr pc, 1f 1: .long cpu_resume - PAGE_OFFSET + PLAT_PHYS_OFFSET - .global sh7372_do_idle_a3sm -sh7372_do_idle_a3sm: +#define SPDCR 0xe6180008 + + /* A3SM & A4S power down */ + .global sh7372_do_idle_sysc +sh7372_do_idle_sysc: + mov r8, r0 /* sleep mode passed in r0 */ + /* * Clear the SCTLR.C bit to prevent further data cache * allocation. Clearing SCTLR.C would make all the data accesses @@ -80,13 +85,9 @@ sh7372_do_idle_a3sm: dsb dmb -#define SPDCR 0xe6180008 -#define A3SM (1 << 12) - - /* A3SM power down */ + /* SYSC power down */ ldr r0, =SPDCR - ldr r1, =A3SM - str r1, [r0] + str r8, [r0] 1: b 1b diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c new file mode 100644 index 00000000000..cc97ef892d1 --- /dev/null +++ b/arch/arm/mach-shmobile/smp-r8a7779.c @@ -0,0 +1,153 @@ +/* + * SMP support for R-Mobile / SH-Mobile - r8a7779 portion + * + * Copyright (C) 2011 Renesas Solutions Corp. + * Copyright (C) 2011 Magnus Damm + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/smp.h> +#include <linux/spinlock.h> +#include <linux/io.h> +#include <linux/delay.h> +#include <mach/common.h> +#include <mach/r8a7779.h> +#include <asm/smp_scu.h> +#include <asm/smp_twd.h> +#include <asm/hardware/gic.h> + +#define AVECR 0xfe700040 + +static struct r8a7779_pm_ch r8a7779_ch_cpu1 = { + .chan_offs = 0x40, /* PWRSR0 .. PWRER0 */ + .chan_bit = 1, /* ARM1 */ + .isr_bit = 1, /* ARM1 */ +}; + +static struct r8a7779_pm_ch r8a7779_ch_cpu2 = { + .chan_offs = 0x40, /* PWRSR0 .. PWRER0 */ + .chan_bit = 2, /* ARM2 */ + .isr_bit = 2, /* ARM2 */ +}; + +static struct r8a7779_pm_ch r8a7779_ch_cpu3 = { + .chan_offs = 0x40, /* PWRSR0 .. PWRER0 */ + .chan_bit = 3, /* ARM3 */ + .isr_bit = 3, /* ARM3 */ +}; + +static struct r8a7779_pm_ch *r8a7779_ch_cpu[4] = { + [1] = &r8a7779_ch_cpu1, + [2] = &r8a7779_ch_cpu2, + [3] = &r8a7779_ch_cpu3, +}; + +static void __iomem *scu_base_addr(void) +{ + return (void __iomem *)0xf0000000; +} + +static DEFINE_SPINLOCK(scu_lock); +static unsigned long tmp; + +static void modify_scu_cpu_psr(unsigned long set, unsigned long clr) +{ + void __iomem *scu_base = scu_base_addr(); + + spin_lock(&scu_lock); + tmp = __raw_readl(scu_base + 8); + tmp &= ~clr; + tmp |= set; + spin_unlock(&scu_lock); + + /* disable cache coherency after releasing the lock */ + __raw_writel(tmp, scu_base + 8); +} + +unsigned int __init r8a7779_get_core_count(void) +{ + void __iomem *scu_base = scu_base_addr(); + +#ifdef CONFIG_HAVE_ARM_TWD + /* twd_base needs to be initialized before percpu_timer_setup() */ + twd_base = (void __iomem *)0xf0000600; +#endif + + return scu_get_core_count(scu_base); +} + +int r8a7779_platform_cpu_kill(unsigned int cpu) +{ + struct r8a7779_pm_ch *ch = NULL; + int ret = -EIO; + + cpu = cpu_logical_map(cpu); + + /* disable cache coherency */ + modify_scu_cpu_psr(3 << (cpu * 8), 0); + + if (cpu < ARRAY_SIZE(r8a7779_ch_cpu)) + ch = r8a7779_ch_cpu[cpu]; + + if (ch) + ret = r8a7779_sysc_power_down(ch); + + return ret ? ret : 1; +} + +void __cpuinit r8a7779_secondary_init(unsigned int cpu) +{ + gic_secondary_init(0); +} + +int __cpuinit r8a7779_boot_secondary(unsigned int cpu) +{ + struct r8a7779_pm_ch *ch = NULL; + int ret = -EIO; + + cpu = cpu_logical_map(cpu); + + /* enable cache coherency */ + modify_scu_cpu_psr(0, 3 << (cpu * 8)); + + if (cpu < ARRAY_SIZE(r8a7779_ch_cpu)) + ch = r8a7779_ch_cpu[cpu]; + + if (ch) + ret = r8a7779_sysc_power_up(ch); + + return ret; +} + +void __init r8a7779_smp_prepare_cpus(void) +{ + int cpu = cpu_logical_map(0); + + scu_enable(scu_base_addr()); + + /* Map the reset vector (in headsmp.S) */ + __raw_writel(__pa(shmobile_secondary_vector), __io(AVECR)); + + /* enable cache coherency on CPU0 */ + modify_scu_cpu_psr(0, 3 << (cpu * 8)); + + r8a7779_pm_init(); + + /* power off secondary CPUs */ + r8a7779_platform_cpu_kill(1); + r8a7779_platform_cpu_kill(2); + r8a7779_platform_cpu_kill(3); +} diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index 91aff7cb828..373652d76b9 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -2,11 +2,8 @@ if ARCH_TEGRA comment "NVIDIA Tegra options" -choice - prompt "Select Tegra processor family for target system" - config ARCH_TEGRA_2x_SOC - bool "Tegra 2 family" + bool "Enable support for Tegra20 family" select CPU_V7 select ARM_GIC select ARCH_REQUIRE_GPIOLIB @@ -17,22 +14,36 @@ config ARCH_TEGRA_2x_SOC Support for NVIDIA Tegra AP20 and T20 processors, based on the ARM CortexA9MP CPU and the ARM PL310 L2 cache controller -endchoice +config ARCH_TEGRA_3x_SOC + bool "Enable support for Tegra30 family" + select CPU_V7 + select ARM_GIC + select ARCH_REQUIRE_GPIOLIB + select USB_ARCH_HAS_EHCI if USB_SUPPORT + select USB_ULPI if USB_SUPPORT + select USB_ULPI_VIEWPORT if USB_SUPPORT + select USE_OF + help + Support for NVIDIA Tegra T30 processor family, based on the + ARM CortexA9MP CPU and the ARM PL310 L2 cache controller config TEGRA_PCI bool "PCI Express support" + depends on ARCH_TEGRA_2x_SOC select PCI comment "Tegra board type" config MACH_HARMONY bool "Harmony board" + depends on ARCH_TEGRA_2x_SOC select MACH_HAS_SND_SOC_TEGRA_WM8903 if SND_SOC help Support for nVidia Harmony development platform config MACH_KAEN bool "Kaen board" + depends on ARCH_TEGRA_2x_SOC select MACH_SEABOARD select MACH_HAS_SND_SOC_TEGRA_WM8903 if SND_SOC help @@ -40,11 +51,13 @@ config MACH_KAEN config MACH_PAZ00 bool "Paz00 board" + depends on ARCH_TEGRA_2x_SOC help Support for the Toshiba AC100/Dynabook AZ netbook config MACH_SEABOARD bool "Seaboard board" + depends on ARCH_TEGRA_2x_SOC select MACH_HAS_SND_SOC_TEGRA_WM8903 if SND_SOC help Support for nVidia Seaboard development platform. It will @@ -52,25 +65,29 @@ config MACH_SEABOARD have large similarities with the seaboard design. config MACH_TEGRA_DT - bool "Generic Tegra board (FDT support)" + bool "Generic Tegra20 board (FDT support)" + depends on ARCH_TEGRA_2x_SOC select USE_OF help - Support for generic nVidia Tegra boards using Flattened Device Tree + Support for generic NVIDIA Tegra20 boards using Flattened Device Tree config MACH_TRIMSLICE bool "TrimSlice board" + depends on ARCH_TEGRA_2x_SOC select TEGRA_PCI help Support for CompuLab TrimSlice platform config MACH_WARIO bool "Wario board" + depends on ARCH_TEGRA_2x_SOC select MACH_SEABOARD help Support for the Wario version of Seaboard config MACH_VENTANA bool "Ventana board" + depends on ARCH_TEGRA_2x_SOC select MACH_TEGRA_DT help Support for the nVidia Ventana development platform diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index 91a07e18720..e120ff54f66 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -1,3 +1,4 @@ +obj-y += board-pinmux.o obj-y += common.o obj-y += devices.o obj-y += io.o @@ -5,12 +6,13 @@ obj-y += irq.o obj-y += clock.o obj-y += timer.o obj-y += pinmux.o -obj-y += powergate.o obj-y += fuse.o -obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += clock.o +obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += powergate.o obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_clocks.o obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_emc.o -obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += pinmux-t2-tables.o +obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += pinmux-tegra20-tables.o +obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += pinmux-tegra30-tables.o +obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += board-dt-tegra30.o obj-$(CONFIG_SMP) += platsmp.o localtimer.o headsmp.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o obj-$(CONFIG_TEGRA_SYSTEM_DMA) += dma.o @@ -18,20 +20,22 @@ obj-$(CONFIG_CPU_FREQ) += cpu-tegra.o obj-$(CONFIG_TEGRA_PCI) += pcie.o obj-$(CONFIG_USB_SUPPORT) += usb_phy.o -obj-${CONFIG_MACH_HARMONY} += board-harmony.o -obj-${CONFIG_MACH_HARMONY} += board-harmony-pinmux.o -obj-${CONFIG_MACH_HARMONY} += board-harmony-pcie.o -obj-${CONFIG_MACH_HARMONY} += board-harmony-power.o +obj-$(CONFIG_MACH_HARMONY) += board-harmony.o +obj-$(CONFIG_MACH_HARMONY) += board-harmony-pinmux.o +obj-$(CONFIG_MACH_HARMONY) += board-harmony-pcie.o +obj-$(CONFIG_MACH_HARMONY) += board-harmony-power.o -obj-${CONFIG_MACH_PAZ00} += board-paz00.o -obj-${CONFIG_MACH_PAZ00} += board-paz00-pinmux.o +obj-$(CONFIG_MACH_PAZ00) += board-paz00.o +obj-$(CONFIG_MACH_PAZ00) += board-paz00-pinmux.o -obj-${CONFIG_MACH_SEABOARD} += board-seaboard.o -obj-${CONFIG_MACH_SEABOARD} += board-seaboard-pinmux.o +obj-$(CONFIG_MACH_SEABOARD) += board-seaboard.o +obj-$(CONFIG_MACH_SEABOARD) += board-seaboard-pinmux.o -obj-${CONFIG_MACH_TEGRA_DT} += board-dt.o -obj-${CONFIG_MACH_TEGRA_DT} += board-harmony-pinmux.o -obj-${CONFIG_MACH_TEGRA_DT} += board-seaboard-pinmux.o +obj-$(CONFIG_MACH_TEGRA_DT) += board-dt-tegra20.o +obj-$(CONFIG_MACH_TEGRA_DT) += board-harmony-pinmux.o +obj-$(CONFIG_MACH_TEGRA_DT) += board-seaboard-pinmux.o +obj-$(CONFIG_MACH_TEGRA_DT) += board-paz00-pinmux.o +obj-$(CONFIG_MACH_TEGRA_DT) += board-trimslice-pinmux.o -obj-${CONFIG_MACH_TRIMSLICE} += board-trimslice.o -obj-${CONFIG_MACH_TRIMSLICE} += board-trimslice-pinmux.o +obj-$(CONFIG_MACH_TRIMSLICE) += board-trimslice.o +obj-$(CONFIG_MACH_TRIMSLICE) += board-trimslice-pinmux.o diff --git a/arch/arm/mach-tegra/Makefile.boot b/arch/arm/mach-tegra/Makefile.boot index bd12c9fb81e..9a82094092d 100644 --- a/arch/arm/mach-tegra/Makefile.boot +++ b/arch/arm/mach-tegra/Makefile.boot @@ -3,5 +3,8 @@ params_phys-$(CONFIG_ARCH_TEGRA_2x_SOC) := 0x00000100 initrd_phys-$(CONFIG_ARCH_TEGRA_2x_SOC) := 0x00800000 dtb-$(CONFIG_MACH_HARMONY) += tegra-harmony.dtb +dtb-$(CONFIG_MACH_PAZ00) += tegra-paz00.dtb dtb-$(CONFIG_MACH_SEABOARD) += tegra-seaboard.dtb +dtb-$(CONFIG_MACH_TRIMSLICE) += tegra-trimslice.dtb dtb-$(CONFIG_MACH_VENTANA) += tegra-ventana.dtb +dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra-cardhu.dtb diff --git a/arch/arm/mach-tegra/board-dt.c b/arch/arm/mach-tegra/board-dt-tegra20.c index e417a8383db..7a95e0bc4ab 100644 --- a/arch/arm/mach-tegra/board-dt.c +++ b/arch/arm/mach-tegra/board-dt-tegra20.c @@ -37,6 +37,7 @@ #include <asm/mach/arch.h> #include <asm/mach/time.h> #include <asm/setup.h> +#include <asm/hardware/gic.h> #include <mach/iomap.h> #include <mach/irqs.h> @@ -47,10 +48,14 @@ #include "devices.h" void harmony_pinmux_init(void); +void paz00_pinmux_init(void); void seaboard_pinmux_init(void); +void trimslice_pinmux_init(void); void ventana_pinmux_init(void); struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = { + OF_DEV_AUXDATA("nvidia,tegra20-pinmux", TEGRA_APB_MISC_BASE + 0x14, "tegra-pinmux", NULL), + OF_DEV_AUXDATA("nvidia,tegra20-gpio", TEGRA_GPIO_BASE, "tegra-gpio", NULL), OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC1_BASE, "sdhci-tegra.0", NULL), OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC2_BASE, "sdhci-tegra.1", NULL), OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC3_BASE, "sdhci-tegra.2", NULL), @@ -58,16 +63,30 @@ struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = { OF_DEV_AUXDATA("nvidia,tegra20-i2c", TEGRA_I2C_BASE, "tegra-i2c.0", NULL), OF_DEV_AUXDATA("nvidia,tegra20-i2c", TEGRA_I2C2_BASE, "tegra-i2c.1", NULL), OF_DEV_AUXDATA("nvidia,tegra20-i2c", TEGRA_I2C3_BASE, "tegra-i2c.2", NULL), - OF_DEV_AUXDATA("nvidia,tegra20-i2c", TEGRA_DVC_BASE, "tegra-i2c.3", NULL), + OF_DEV_AUXDATA("nvidia,tegra20-i2c-dvc", TEGRA_DVC_BASE, "tegra-i2c.3", NULL), OF_DEV_AUXDATA("nvidia,tegra20-i2s", TEGRA_I2S1_BASE, "tegra-i2s.0", NULL), - OF_DEV_AUXDATA("nvidia,tegra20-i2s", TEGRA_I2S1_BASE, "tegra-i2s.1", NULL), + OF_DEV_AUXDATA("nvidia,tegra20-i2s", TEGRA_I2S2_BASE, "tegra-i2s.1", NULL), OF_DEV_AUXDATA("nvidia,tegra20-das", TEGRA_APB_MISC_DAS_BASE, "tegra-das", NULL), + OF_DEV_AUXDATA("nvidia,tegra20-ehci", TEGRA_USB_BASE, "tegra-ehci.0", + &tegra_ehci1_device.dev.platform_data), + OF_DEV_AUXDATA("nvidia,tegra20-ehci", TEGRA_USB2_BASE, "tegra-ehci.1", + &tegra_ehci2_device.dev.platform_data), + OF_DEV_AUXDATA("nvidia,tegra20-ehci", TEGRA_USB3_BASE, "tegra-ehci.2", + &tegra_ehci3_device.dev.platform_data), {} }; static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = { /* name parent rate enabled */ { "uartd", "pll_p", 216000000, true }, + { "usbd", "clk_m", 12000000, false }, + { "usb2", "clk_m", 12000000, false }, + { "usb3", "clk_m", 12000000, false }, + { "pll_a", "pll_p_out1", 56448000, true }, + { "pll_a_out0", "pll_a", 11289600, true }, + { "cdev1", NULL, 0, true }, + { "i2s1", "pll_a_out0", 11289600, false}, + { "i2s2", "pll_a_out0", 11289600, false}, { NULL, NULL, 0, 0}, }; @@ -76,39 +95,23 @@ static struct of_device_id tegra_dt_match_table[] __initdata = { {} }; -static struct of_device_id tegra_dt_gic_match[] __initdata = { - { .compatible = "nvidia,tegra20-gic", }, - {} -}; - static struct { char *machine; void (*init)(void); } pinmux_configs[] = { + { "compulab,trimslice", trimslice_pinmux_init }, { "nvidia,harmony", harmony_pinmux_init }, + { "compal,paz00", paz00_pinmux_init }, { "nvidia,seaboard", seaboard_pinmux_init }, { "nvidia,ventana", ventana_pinmux_init }, }; static void __init tegra_dt_init(void) { - struct device_node *node; int i; - node = of_find_matching_node_by_address(NULL, tegra_dt_gic_match, - TEGRA_ARM_INT_DIST_BASE); - if (node) - irq_domain_add_simple(node, INT_GIC_BASE); - tegra_clk_init_from_table(tegra_dt_clk_init_table); - /* - * Finished with the static registrations now; fill in the missing - * devices - */ - of_platform_populate(NULL, tegra_dt_match_table, - tegra20_auxdata_lookup, NULL); - for (i = 0; i < ARRAY_SIZE(pinmux_configs); i++) { if (of_machine_is_compatible(pinmux_configs[i].machine)) { pinmux_configs[i].init(); @@ -118,22 +121,31 @@ static void __init tegra_dt_init(void) WARN(i == ARRAY_SIZE(pinmux_configs), "Unknown platform! Pinmuxing not initialized\n"); + + /* + * Finished with the static registrations now; fill in the missing + * devices + */ + of_platform_populate(NULL, tegra_dt_match_table, + tegra20_auxdata_lookup, NULL); } -static const char * tegra_dt_board_compat[] = { +static const char *tegra20_dt_board_compat[] = { + "compulab,trimslice", "nvidia,harmony", + "compal,paz00", "nvidia,seaboard", "nvidia,ventana", NULL }; -DT_MACHINE_START(TEGRA_DT, "nVidia Tegra (Flattened Device Tree)") +DT_MACHINE_START(TEGRA_DT, "nVidia Tegra20 (Flattened Device Tree)") .map_io = tegra_map_common_io, - .init_early = tegra_init_early, - .init_irq = tegra_init_irq, + .init_early = tegra20_init_early, + .init_irq = tegra_dt_init_irq, .handle_irq = gic_handle_irq, .timer = &tegra_timer, .init_machine = tegra_dt_init, .restart = tegra_assert_system_reset, - .dt_compat = tegra_dt_board_compat, + .dt_compat = tegra20_dt_board_compat, MACHINE_END diff --git a/arch/arm/mach-tegra/board-dt-tegra30.c b/arch/arm/mach-tegra/board-dt-tegra30.c new file mode 100644 index 00000000000..3c197e2440b --- /dev/null +++ b/arch/arm/mach-tegra/board-dt-tegra30.c @@ -0,0 +1,63 @@ +/* + * arch/arm/mach-tegra/board-dt-tegra30.c + * + * NVIDIA Tegra30 device tree board support + * + * Copyright (C) 2011 NVIDIA Corporation + * + * Derived from: + * + * arch/arm/mach-tegra/board-dt-tegra20.c + * + * Copyright (C) 2010 Secret Lab Technologies, Ltd. + * Copyright (C) 2010 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <linux/kernel.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/of_fdt.h> +#include <linux/of_irq.h> +#include <linux/of_platform.h> + +#include <asm/mach/arch.h> +#include <asm/hardware/gic.h> + +#include "board.h" + +static struct of_device_id tegra_dt_match_table[] __initdata = { + { .compatible = "simple-bus", }, + {} +}; + +static void __init tegra30_dt_init(void) +{ + of_platform_populate(NULL, tegra_dt_match_table, + NULL, NULL); +} + +static const char *tegra30_dt_board_compat[] = { + "nvidia,cardhu", + NULL +}; + +DT_MACHINE_START(TEGRA30_DT, "NVIDIA Tegra30 (Flattened Device Tree)") + .map_io = tegra_map_common_io, + .init_early = tegra30_init_early, + .init_irq = tegra_dt_init_irq, + .handle_irq = gic_handle_irq, + .timer = &tegra_timer, + .init_machine = tegra30_dt_init, + .restart = tegra_assert_system_reset, + .dt_compat = tegra30_dt_board_compat, +MACHINE_END diff --git a/arch/arm/mach-tegra/board-harmony-pcie.c b/arch/arm/mach-tegra/board-harmony-pcie.c index 6db7d699ef1..33c4fedab84 100644 --- a/arch/arm/mach-tegra/board-harmony-pcie.c +++ b/arch/arm/mach-tegra/board-harmony-pcie.c @@ -22,7 +22,6 @@ #include <asm/mach-types.h> -#include <mach/pinmux.h> #include "board.h" #include "board-harmony.h" @@ -48,10 +47,6 @@ static int __init harmony_pcie_init(void) regulator_enable(regulator); - tegra_pinmux_set_tristate(TEGRA_PINGROUP_GPV, TEGRA_TRI_NORMAL); - tegra_pinmux_set_tristate(TEGRA_PINGROUP_SLXA, TEGRA_TRI_NORMAL); - tegra_pinmux_set_tristate(TEGRA_PINGROUP_SLXK, TEGRA_TRI_NORMAL); - err = tegra_pcie_init(true, true); if (err) goto err_pcie; @@ -59,10 +54,6 @@ static int __init harmony_pcie_init(void) return 0; err_pcie: - tegra_pinmux_set_tristate(TEGRA_PINGROUP_GPV, TEGRA_TRI_TRISTATE); - tegra_pinmux_set_tristate(TEGRA_PINGROUP_SLXA, TEGRA_TRI_TRISTATE); - tegra_pinmux_set_tristate(TEGRA_PINGROUP_SLXK, TEGRA_TRI_TRISTATE); - regulator_disable(regulator); regulator_put(regulator); err_reg: diff --git a/arch/arm/mach-tegra/board-harmony-pinmux.c b/arch/arm/mach-tegra/board-harmony-pinmux.c index 7a4a26d5174..465808c8ac0 100644 --- a/arch/arm/mach-tegra/board-harmony-pinmux.c +++ b/arch/arm/mach-tegra/board-harmony-pinmux.c @@ -19,10 +19,11 @@ #include <linux/of.h> #include <mach/pinmux.h> +#include <mach/pinmux-tegra20.h> #include "gpio-names.h" #include "board-harmony.h" -#include "devices.h" +#include "board-pinmux.h" static struct tegra_pingroup_config harmony_pinmux[] = { {TEGRA_PINGROUP_ATA, TEGRA_MUX_IDE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, @@ -143,11 +144,6 @@ static struct tegra_pingroup_config harmony_pinmux[] = { {TEGRA_PINGROUP_XM2D, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, }; -static struct platform_device *pinmux_devices[] = { - &tegra_gpio_device, - &tegra_pinmux_device, -}; - static struct tegra_gpio_table gpio_table[] = { { .gpio = TEGRA_GPIO_SD2_CD, .enable = true }, { .gpio = TEGRA_GPIO_SD2_WP, .enable = true }, @@ -161,13 +157,14 @@ static struct tegra_gpio_table gpio_table[] = { { .gpio = TEGRA_GPIO_EXT_MIC_EN, .enable = true }, }; +static struct tegra_board_pinmux_conf conf = { + .pgs = harmony_pinmux, + .pg_count = ARRAY_SIZE(harmony_pinmux), + .gpios = gpio_table, + .gpio_count = ARRAY_SIZE(gpio_table), +}; + void harmony_pinmux_init(void) { - if (!of_machine_is_compatible("nvidia,tegra20")) - platform_add_devices(pinmux_devices, - ARRAY_SIZE(pinmux_devices)); - - tegra_pinmux_config_table(harmony_pinmux, ARRAY_SIZE(harmony_pinmux)); - - tegra_gpio_config(gpio_table, ARRAY_SIZE(gpio_table)); + tegra_board_pinmux_init(&conf, NULL); } diff --git a/arch/arm/mach-tegra/board-harmony.c b/arch/arm/mach-tegra/board-harmony.c index 70ee674131f..789bdc9e8f9 100644 --- a/arch/arm/mach-tegra/board-harmony.c +++ b/arch/arm/mach-tegra/board-harmony.c @@ -90,11 +90,11 @@ static struct wm8903_platform_data harmony_wm8903_pdata = { .micdet_delay = 100, .gpio_base = HARMONY_GPIO_WM8903(0), .gpio_cfg = { - WM8903_GPIO_NO_CONFIG, - WM8903_GPIO_NO_CONFIG, 0, - WM8903_GPIO_NO_CONFIG, - WM8903_GPIO_NO_CONFIG, + 0, + WM8903_GPIO_CONFIG_ZERO, + 0, + 0, }, }; @@ -186,7 +186,7 @@ MACHINE_START(HARMONY, "harmony") .atag_offset = 0x100, .fixup = tegra_harmony_fixup, .map_io = tegra_map_common_io, - .init_early = tegra_init_early, + .init_early = tegra20_init_early, .init_irq = tegra_init_irq, .handle_irq = gic_handle_irq, .timer = &tegra_timer, diff --git a/arch/arm/mach-tegra/board-paz00-pinmux.c b/arch/arm/mach-tegra/board-paz00-pinmux.c index be30e215f4b..c775572dcea 100644 --- a/arch/arm/mach-tegra/board-paz00-pinmux.c +++ b/arch/arm/mach-tegra/board-paz00-pinmux.c @@ -19,10 +19,11 @@ #include <linux/of.h> #include <mach/pinmux.h> +#include <mach/pinmux-tegra20.h> #include "gpio-names.h" #include "board-paz00.h" -#include "devices.h" +#include "board-pinmux.h" static struct tegra_pingroup_config paz00_pinmux[] = { {TEGRA_PINGROUP_ATA, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, @@ -30,7 +31,7 @@ static struct tegra_pingroup_config paz00_pinmux[] = { {TEGRA_PINGROUP_ATC, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, {TEGRA_PINGROUP_ATD, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, {TEGRA_PINGROUP_ATE, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, - {TEGRA_PINGROUP_CDEV1, TEGRA_MUX_PLLA_OUT, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_CDEV1, TEGRA_MUX_PLLA_OUT, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, {TEGRA_PINGROUP_CDEV2, TEGRA_MUX_PLLP_OUT4, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, {TEGRA_PINGROUP_CRTP, TEGRA_MUX_CRT, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, {TEGRA_PINGROUP_CSUS, TEGRA_MUX_PLLC_OUT1, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, @@ -143,11 +144,6 @@ static struct tegra_pingroup_config paz00_pinmux[] = { {TEGRA_PINGROUP_XM2D, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, }; -static struct platform_device *pinmux_devices[] = { - &tegra_gpio_device, - &tegra_pinmux_device, -}; - static struct tegra_gpio_table gpio_table[] = { { .gpio = TEGRA_GPIO_SD1_CD, .enable = true }, { .gpio = TEGRA_GPIO_SD1_WP, .enable = true }, @@ -158,13 +154,14 @@ static struct tegra_gpio_table gpio_table[] = { { .gpio = TEGRA_WIFI_LED, .enable = true }, }; +static struct tegra_board_pinmux_conf conf = { + .pgs = paz00_pinmux, + .pg_count = ARRAY_SIZE(paz00_pinmux), + .gpios = gpio_table, + .gpio_count = ARRAY_SIZE(gpio_table), +}; + void paz00_pinmux_init(void) { - if (!of_machine_is_compatible("nvidia,tegra20")) - platform_add_devices(pinmux_devices, - ARRAY_SIZE(pinmux_devices)); - - tegra_pinmux_config_table(paz00_pinmux, ARRAY_SIZE(paz00_pinmux)); - - tegra_gpio_config(gpio_table, ARRAY_SIZE(gpio_table)); + tegra_board_pinmux_init(&conf, NULL); } diff --git a/arch/arm/mach-tegra/board-paz00.c b/arch/arm/mach-tegra/board-paz00.c index 33d6205ad30..fcf4f377b1d 100644 --- a/arch/arm/mach-tegra/board-paz00.c +++ b/arch/arm/mach-tegra/board-paz00.c @@ -23,8 +23,10 @@ #include <linux/serial_8250.h> #include <linux/clk.h> #include <linux/dma-mapping.h> +#include <linux/gpio_keys.h> #include <linux/pda_power.h> #include <linux/io.h> +#include <linux/input.h> #include <linux/i2c.h> #include <linux/gpio.h> #include <linux/rfkill-gpio.h> @@ -115,12 +117,37 @@ static struct platform_device leds_gpio = { }, }; +static struct gpio_keys_button paz00_gpio_keys_buttons[] = { + { + .code = KEY_POWER, + .gpio = TEGRA_GPIO_POWERKEY, + .active_low = 1, + .desc = "Power", + .type = EV_KEY, + .wakeup = 1, + }, +}; + +static struct gpio_keys_platform_data paz00_gpio_keys = { + .buttons = paz00_gpio_keys_buttons, + .nbuttons = ARRAY_SIZE(paz00_gpio_keys_buttons), +}; + +static struct platform_device gpio_keys_device = { + .name = "gpio-keys", + .id = -1, + .dev = { + .platform_data = &paz00_gpio_keys, + }, +}; + static struct platform_device *paz00_devices[] __initdata = { &debug_uart, &tegra_sdhci_device4, &tegra_sdhci_device1, &wifi_rfkill_device, &leds_gpio, + &gpio_keys_device, }; static void paz00_i2c_init(void) @@ -189,7 +216,7 @@ MACHINE_START(PAZ00, "Toshiba AC100 / Dynabook AZ") .atag_offset = 0x100, .fixup = tegra_paz00_fixup, .map_io = tegra_map_common_io, - .init_early = tegra_init_early, + .init_early = tegra20_init_early, .init_irq = tegra_init_irq, .handle_irq = gic_handle_irq, .timer = &tegra_timer, diff --git a/arch/arm/mach-tegra/board-paz00.h b/arch/arm/mach-tegra/board-paz00.h index 8aff06eb58c..ffa83f580db 100644 --- a/arch/arm/mach-tegra/board-paz00.h +++ b/arch/arm/mach-tegra/board-paz00.h @@ -32,6 +32,9 @@ #define TEGRA_WIFI_RST TEGRA_GPIO_PD1 #define TEGRA_WIFI_LED TEGRA_GPIO_PD0 +/* WakeUp */ +#define TEGRA_GPIO_POWERKEY TEGRA_GPIO_PJ7 + void paz00_pinmux_init(void); #endif diff --git a/arch/arm/mach-tegra/board-pinmux.c b/arch/arm/mach-tegra/board-pinmux.c new file mode 100644 index 00000000000..adc3efe979b --- /dev/null +++ b/arch/arm/mach-tegra/board-pinmux.c @@ -0,0 +1,104 @@ +/* + * Copyright (c) 2011, NVIDIA CORPORATION. All rights reserved. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <linux/device.h> +#include <linux/kernel.h> +#include <linux/notifier.h> +#include <linux/of.h> +#include <linux/string.h> + +#include <mach/gpio-tegra.h> +#include <mach/pinmux.h> + +#include "board-pinmux.h" +#include "devices.h" + +struct tegra_board_pinmux_conf *confs[2]; + +static void tegra_board_pinmux_setup_gpios(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(confs); i++) { + if (!confs[i]) + continue; + + tegra_gpio_config(confs[i]->gpios, confs[i]->gpio_count); + } +} + +static void tegra_board_pinmux_setup_pinmux(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(confs); i++) { + if (!confs[i]) + continue; + + tegra_pinmux_config_table(confs[i]->pgs, confs[i]->pg_count); + + if (confs[i]->drives) + tegra_drive_pinmux_config_table(confs[i]->drives, + confs[i]->drive_count); + } +} + +static int tegra_board_pinmux_bus_notify(struct notifier_block *nb, + unsigned long event, void *vdev) +{ + static bool had_gpio; + static bool had_pinmux; + + struct device *dev = vdev; + const char *devname; + + if (event != BUS_NOTIFY_BOUND_DRIVER) + return NOTIFY_DONE; + + devname = dev_name(dev); + + if (!had_gpio && !strcmp(devname, GPIO_DEV)) { + tegra_board_pinmux_setup_gpios(); + had_gpio = true; + } else if (!had_pinmux && !strcmp(devname, PINMUX_DEV)) { + tegra_board_pinmux_setup_pinmux(); + had_pinmux = true; + } + + if (had_gpio && had_pinmux) + return NOTIFY_STOP_MASK; + else + return NOTIFY_DONE; +} + +static struct notifier_block nb = { + .notifier_call = tegra_board_pinmux_bus_notify, +}; + +static struct platform_device *devices[] = { + &tegra_gpio_device, + &tegra_pinmux_device, +}; + +void tegra_board_pinmux_init(struct tegra_board_pinmux_conf *conf_a, + struct tegra_board_pinmux_conf *conf_b) +{ + confs[0] = conf_a; + confs[1] = conf_b; + + bus_register_notifier(&platform_bus_type, &nb); + + if (!of_machine_is_compatible("nvidia,tegra20")) + platform_add_devices(devices, ARRAY_SIZE(devices)); +} diff --git a/arch/arm/mach-tegra/board-pinmux.h b/arch/arm/mach-tegra/board-pinmux.h new file mode 100644 index 00000000000..4aac73546f5 --- /dev/null +++ b/arch/arm/mach-tegra/board-pinmux.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2011, NVIDIA CORPORATION. All rights reserved. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __MACH_TEGRA_BOARD_PINMUX_H +#define __MACH_TEGRA_BOARD_PINMUX_H + +#define GPIO_DEV "tegra-gpio" +#define PINMUX_DEV "tegra-pinmux" + +struct tegra_pingroup_config; +struct tegra_gpio_table; + +struct tegra_board_pinmux_conf { + struct tegra_pingroup_config *pgs; + int pg_count; + + struct tegra_drive_pingroup_config *drives; + int drive_count; + + struct tegra_gpio_table *gpios; + int gpio_count; +}; + +void tegra_board_pinmux_init(struct tegra_board_pinmux_conf *conf_a, + struct tegra_board_pinmux_conf *conf_b); + +#endif diff --git a/arch/arm/mach-tegra/board-seaboard-pinmux.c b/arch/arm/mach-tegra/board-seaboard-pinmux.c index b1c2972f62f..55e7e43a14a 100644 --- a/arch/arm/mach-tegra/board-seaboard-pinmux.c +++ b/arch/arm/mach-tegra/board-seaboard-pinmux.c @@ -19,11 +19,11 @@ #include <linux/of.h> #include <mach/pinmux.h> -#include <mach/pinmux-t2.h> +#include <mach/pinmux-tegra20.h> #include "gpio-names.h" +#include "board-pinmux.h" #include "board-seaboard.h" -#include "devices.h" #define DEFAULT_DRIVE(_name) \ { \ @@ -37,11 +37,11 @@ .slew_falling = TEGRA_SLEW_SLOWEST, \ } -static __initdata struct tegra_drive_pingroup_config seaboard_drive_pinmux[] = { +static struct tegra_drive_pingroup_config seaboard_drive_pinmux[] = { DEFAULT_DRIVE(SDIO1), }; -static __initdata struct tegra_pingroup_config seaboard_pinmux[] = { +static struct tegra_pingroup_config common_pinmux[] = { {TEGRA_PINGROUP_ATA, TEGRA_MUX_IDE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, {TEGRA_PINGROUP_ATB, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, {TEGRA_PINGROUP_ATC, TEGRA_MUX_NAND, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, @@ -55,7 +55,6 @@ static __initdata struct tegra_pingroup_config seaboard_pinmux[] = { {TEGRA_PINGROUP_DAP2, TEGRA_MUX_DAP2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, {TEGRA_PINGROUP_DAP3, TEGRA_MUX_DAP3, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, {TEGRA_PINGROUP_DAP4, TEGRA_MUX_DAP4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, - {TEGRA_PINGROUP_DDC, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, {TEGRA_PINGROUP_DTA, TEGRA_MUX_VI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, {TEGRA_PINGROUP_DTB, TEGRA_MUX_VI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, {TEGRA_PINGROUP_DTC, TEGRA_MUX_VI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, @@ -65,7 +64,6 @@ static __initdata struct tegra_pingroup_config seaboard_pinmux[] = { {TEGRA_PINGROUP_GMA, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, {TEGRA_PINGROUP_GMB, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, {TEGRA_PINGROUP_GMC, TEGRA_MUX_UARTD, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, - {TEGRA_PINGROUP_GMD, TEGRA_MUX_SFLASH, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, {TEGRA_PINGROUP_GME, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, {TEGRA_PINGROUP_GPU, TEGRA_MUX_PWM, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, {TEGRA_PINGROUP_GPU7, TEGRA_MUX_RTCK, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, @@ -108,13 +106,8 @@ static __initdata struct tegra_pingroup_config seaboard_pinmux[] = { {TEGRA_PINGROUP_LM0, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, {TEGRA_PINGROUP_LM1, TEGRA_MUX_CRT, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, {TEGRA_PINGROUP_LPP, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, - {TEGRA_PINGROUP_LPW0, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, {TEGRA_PINGROUP_LPW1, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, - {TEGRA_PINGROUP_LPW2, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, {TEGRA_PINGROUP_LSC0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, - {TEGRA_PINGROUP_LSC1, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, - {TEGRA_PINGROUP_LSCK, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, - {TEGRA_PINGROUP_LSDA, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, {TEGRA_PINGROUP_LSDI, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, {TEGRA_PINGROUP_LSPI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, {TEGRA_PINGROUP_LVP0, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, @@ -122,25 +115,19 @@ static __initdata struct tegra_pingroup_config seaboard_pinmux[] = { {TEGRA_PINGROUP_LVS, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, {TEGRA_PINGROUP_OWC, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, {TEGRA_PINGROUP_PMC, TEGRA_MUX_PWR_ON, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, - {TEGRA_PINGROUP_PTA, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, {TEGRA_PINGROUP_RM, TEGRA_MUX_I2C, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, {TEGRA_PINGROUP_SDB, TEGRA_MUX_SDIO3, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, {TEGRA_PINGROUP_SDC, TEGRA_MUX_SDIO3, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, {TEGRA_PINGROUP_SDD, TEGRA_MUX_SDIO3, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, {TEGRA_PINGROUP_SDIO1, TEGRA_MUX_SDIO1, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, {TEGRA_PINGROUP_SLXA, TEGRA_MUX_PCIE, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, - {TEGRA_PINGROUP_SLXC, TEGRA_MUX_SPDIF, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, {TEGRA_PINGROUP_SLXD, TEGRA_MUX_SPDIF, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, - {TEGRA_PINGROUP_SLXK, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, {TEGRA_PINGROUP_SPDI, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, {TEGRA_PINGROUP_SPDO, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, - {TEGRA_PINGROUP_SPIA, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, {TEGRA_PINGROUP_SPIB, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, - {TEGRA_PINGROUP_SPIC, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, {TEGRA_PINGROUP_SPID, TEGRA_MUX_SPI1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, {TEGRA_PINGROUP_SPIE, TEGRA_MUX_SPI1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, {TEGRA_PINGROUP_SPIF, TEGRA_MUX_SPI1, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, - {TEGRA_PINGROUP_SPIG, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, {TEGRA_PINGROUP_SPIH, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, {TEGRA_PINGROUP_UAA, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, {TEGRA_PINGROUP_UAB, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, @@ -160,13 +147,24 @@ static __initdata struct tegra_pingroup_config seaboard_pinmux[] = { {TEGRA_PINGROUP_XM2D, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, }; -static __initdata struct tegra_pingroup_config ventana_pinmux[] = { - {TEGRA_PINGROUP_DAP3, TEGRA_MUX_DAP3, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, +static struct tegra_pingroup_config seaboard_pinmux[] = { + {TEGRA_PINGROUP_DDC, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_GMD, TEGRA_MUX_SFLASH, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LPW0, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LPW2, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LSC1, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LSCK, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LSDA, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_PTA, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SLXC, TEGRA_MUX_SPDIF, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SLXK, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SPIA, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SPIC, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SPIG, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, +}; + +static struct tegra_pingroup_config ventana_pinmux[] = { {TEGRA_PINGROUP_DDC, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, - {TEGRA_PINGROUP_DTA, TEGRA_MUX_VI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, - {TEGRA_PINGROUP_DTB, TEGRA_MUX_VI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, - {TEGRA_PINGROUP_DTC, TEGRA_MUX_VI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, - {TEGRA_PINGROUP_DTD, TEGRA_MUX_VI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, {TEGRA_PINGROUP_GMD, TEGRA_MUX_SFLASH, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, {TEGRA_PINGROUP_LPW0, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, {TEGRA_PINGROUP_LPW2, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, @@ -181,65 +179,59 @@ static __initdata struct tegra_pingroup_config ventana_pinmux[] = { {TEGRA_PINGROUP_SPIG, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, }; -static struct platform_device *pinmux_devices[] = { - &tegra_gpio_device, - &tegra_pinmux_device, -}; - static struct tegra_gpio_table common_gpio_table[] = { { .gpio = TEGRA_GPIO_SD2_CD, .enable = true }, { .gpio = TEGRA_GPIO_SD2_WP, .enable = true }, { .gpio = TEGRA_GPIO_SD2_POWER, .enable = true }, + { .gpio = TEGRA_GPIO_CDC_IRQ, .enable = true }, +}; + +static struct tegra_gpio_table seaboard_gpio_table[] = { { .gpio = TEGRA_GPIO_LIDSWITCH, .enable = true }, { .gpio = TEGRA_GPIO_POWERKEY, .enable = true }, { .gpio = TEGRA_GPIO_HP_DET, .enable = true }, { .gpio = TEGRA_GPIO_ISL29018_IRQ, .enable = true }, - { .gpio = TEGRA_GPIO_CDC_IRQ, .enable = true }, { .gpio = TEGRA_GPIO_USB1, .enable = true }, }; -static void __init update_pinmux(struct tegra_pingroup_config *newtbl, int size) -{ - int i, j; - struct tegra_pingroup_config *new_pingroup, *base_pingroup; - - /* Update base seaboard pinmux table with secondary board - * specific pinmux table table. - */ - for (i = 0; i < size; i++) { - new_pingroup = &newtbl[i]; - for (j = 0; j < ARRAY_SIZE(seaboard_pinmux); j++) { - base_pingroup = &seaboard_pinmux[j]; - if (new_pingroup->pingroup == base_pingroup->pingroup) { - *base_pingroup = *new_pingroup; - break; - } - } - } -} - -void __init seaboard_common_pinmux_init(void) -{ - if (!of_machine_is_compatible("nvidia,tegra20")) - platform_add_devices(pinmux_devices, - ARRAY_SIZE(pinmux_devices)); +static struct tegra_gpio_table ventana_gpio_table[] = { + /* hp_det */ + { .gpio = TEGRA_GPIO_PW2, .enable = true }, + /* int_mic_en */ + { .gpio = TEGRA_GPIO_PX0, .enable = true }, + /* ext_mic_en */ + { .gpio = TEGRA_GPIO_PX1, .enable = true }, +}; - tegra_pinmux_config_table(seaboard_pinmux, ARRAY_SIZE(seaboard_pinmux)); +static struct tegra_board_pinmux_conf common_conf = { + .pgs = common_pinmux, + .pg_count = ARRAY_SIZE(common_pinmux), + .gpios = common_gpio_table, + .gpio_count = ARRAY_SIZE(common_gpio_table), +}; - tegra_drive_pinmux_config_table(seaboard_drive_pinmux, - ARRAY_SIZE(seaboard_drive_pinmux)); +static struct tegra_board_pinmux_conf seaboard_conf = { + .pgs = seaboard_pinmux, + .pg_count = ARRAY_SIZE(seaboard_pinmux), + .drives = seaboard_drive_pinmux, + .drive_count = ARRAY_SIZE(seaboard_drive_pinmux), + .gpios = seaboard_gpio_table, + .gpio_count = ARRAY_SIZE(seaboard_gpio_table), +}; - tegra_gpio_config(common_gpio_table, ARRAY_SIZE(common_gpio_table)); -} +static struct tegra_board_pinmux_conf ventana_conf = { + .pgs = ventana_pinmux, + .pg_count = ARRAY_SIZE(ventana_pinmux), + .gpios = ventana_gpio_table, + .gpio_count = ARRAY_SIZE(ventana_gpio_table), +}; -void __init seaboard_pinmux_init(void) +void seaboard_pinmux_init(void) { - seaboard_common_pinmux_init(); + tegra_board_pinmux_init(&common_conf, &seaboard_conf); } -void __init ventana_pinmux_init(void) +void ventana_pinmux_init(void) { - update_pinmux(ventana_pinmux, ARRAY_SIZE(ventana_pinmux)); - seaboard_common_pinmux_init(); + tegra_board_pinmux_init(&common_conf, &ventana_conf); } - diff --git a/arch/arm/mach-tegra/board-seaboard.c b/arch/arm/mach-tegra/board-seaboard.c index c1599eb8e0c..ebac65f5251 100644 --- a/arch/arm/mach-tegra/board-seaboard.c +++ b/arch/arm/mach-tegra/board-seaboard.c @@ -172,11 +172,11 @@ static struct wm8903_platform_data wm8903_pdata = { .micdet_delay = 100, .gpio_base = SEABOARD_GPIO_WM8903(0), .gpio_cfg = { - WM8903_GPIO_NO_CONFIG, - WM8903_GPIO_NO_CONFIG, 0, - WM8903_GPIO_NO_CONFIG, - WM8903_GPIO_NO_CONFIG, + 0, + WM8903_GPIO_CONFIG_ZERO, + 0, + 0, }, }; @@ -283,7 +283,7 @@ static void __init tegra_wario_init(void) MACHINE_START(SEABOARD, "seaboard") .atag_offset = 0x100, .map_io = tegra_map_common_io, - .init_early = tegra_init_early, + .init_early = tegra20_init_early, .init_irq = tegra_init_irq, .handle_irq = gic_handle_irq, .timer = &tegra_timer, @@ -294,7 +294,7 @@ MACHINE_END MACHINE_START(KAEN, "kaen") .atag_offset = 0x100, .map_io = tegra_map_common_io, - .init_early = tegra_init_early, + .init_early = tegra20_init_early, .init_irq = tegra_init_irq, .handle_irq = gic_handle_irq, .timer = &tegra_timer, @@ -305,7 +305,7 @@ MACHINE_END MACHINE_START(WARIO, "wario") .atag_offset = 0x100, .map_io = tegra_map_common_io, - .init_early = tegra_init_early, + .init_early = tegra20_init_early, .init_irq = tegra_init_irq, .handle_irq = gic_handle_irq, .timer = &tegra_timer, diff --git a/arch/arm/mach-tegra/board-trimslice-pinmux.c b/arch/arm/mach-tegra/board-trimslice-pinmux.c index 7ab719d46da..a21a2be57cb 100644 --- a/arch/arm/mach-tegra/board-trimslice-pinmux.c +++ b/arch/arm/mach-tegra/board-trimslice-pinmux.c @@ -19,12 +19,13 @@ #include <linux/of.h> #include <mach/pinmux.h> +#include <mach/pinmux-tegra20.h> #include "gpio-names.h" +#include "board-pinmux.h" #include "board-trimslice.h" -#include "devices.h" -static __initdata struct tegra_pingroup_config trimslice_pinmux[] = { +static struct tegra_pingroup_config trimslice_pinmux[] = { {TEGRA_PINGROUP_ATA, TEGRA_MUX_IDE, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, {TEGRA_PINGROUP_ATB, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, {TEGRA_PINGROUP_ATC, TEGRA_MUX_NAND, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, @@ -105,7 +106,7 @@ static __initdata struct tegra_pingroup_config trimslice_pinmux[] = { {TEGRA_PINGROUP_LVS, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, {TEGRA_PINGROUP_OWC, TEGRA_MUX_RSVD2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, {TEGRA_PINGROUP_PMC, TEGRA_MUX_PWR_ON, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, - {TEGRA_PINGROUP_PTA, TEGRA_MUX_RSVD3, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_PTA, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, {TEGRA_PINGROUP_RM, TEGRA_MUX_I2C, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, {TEGRA_PINGROUP_SDB, TEGRA_MUX_PWM, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, {TEGRA_PINGROUP_SDC, TEGRA_MUX_PWM, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, @@ -143,11 +144,6 @@ static __initdata struct tegra_pingroup_config trimslice_pinmux[] = { {TEGRA_PINGROUP_XM2D, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, }; -static struct platform_device *pinmux_devices[] = { - &tegra_gpio_device, - &tegra_pinmux_device, -}; - static struct tegra_gpio_table gpio_table[] = { { .gpio = TRIMSLICE_GPIO_SD4_CD, .enable = true }, /* mmc4 cd */ { .gpio = TRIMSLICE_GPIO_SD4_WP, .enable = true }, /* mmc4 wp */ @@ -156,11 +152,14 @@ static struct tegra_gpio_table gpio_table[] = { { .gpio = TRIMSLICE_GPIO_USB2_RST, .enable = true }, /* USB2 PHY rst */ }; -void __init trimslice_pinmux_init(void) +static struct tegra_board_pinmux_conf conf = { + .pgs = trimslice_pinmux, + .pg_count = ARRAY_SIZE(trimslice_pinmux), + .gpios = gpio_table, + .gpio_count = ARRAY_SIZE(gpio_table), +}; + +void trimslice_pinmux_init(void) { - if (!of_machine_is_compatible("nvidia,tegra20")) - platform_add_devices(pinmux_devices, - ARRAY_SIZE(pinmux_devices)); - tegra_pinmux_config_table(trimslice_pinmux, ARRAY_SIZE(trimslice_pinmux)); - tegra_gpio_config(gpio_table, ARRAY_SIZE(gpio_table)); + tegra_board_pinmux_init(&conf, NULL); } diff --git a/arch/arm/mach-tegra/board-trimslice.c b/arch/arm/mach-tegra/board-trimslice.c index c242314a1db..cd52820a3e3 100644 --- a/arch/arm/mach-tegra/board-trimslice.c +++ b/arch/arm/mach-tegra/board-trimslice.c @@ -175,7 +175,7 @@ MACHINE_START(TRIMSLICE, "trimslice") .atag_offset = 0x100, .fixup = tegra_trimslice_fixup, .map_io = tegra_map_common_io, - .init_early = tegra_init_early, + .init_early = tegra20_init_early, .init_irq = tegra_init_irq, .handle_irq = gic_handle_irq, .timer = &tegra_timer, diff --git a/arch/arm/mach-tegra/board.h b/arch/arm/mach-tegra/board.h index 1d14df7eb7d..75d1543d77c 100644 --- a/arch/arm/mach-tegra/board.h +++ b/arch/arm/mach-tegra/board.h @@ -25,10 +25,11 @@ void tegra_assert_system_reset(char mode, const char *cmd); -void __init tegra_init_early(void); +void __init tegra20_init_early(void); +void __init tegra30_init_early(void); void __init tegra_map_common_io(void); void __init tegra_init_irq(void); -void __init tegra_init_clock(void); +void __init tegra_dt_init_irq(void); int __init tegra_pcie_init(bool init_port0, bool init_port1); extern struct sys_timer tegra_timer; diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c index f8d41ffc0ca..8337068a4ab 100644 --- a/arch/arm/mach-tegra/clock.c +++ b/arch/arm/mach-tegra/clock.c @@ -387,35 +387,18 @@ EXPORT_SYMBOL(tegra_clk_init_from_table); void tegra_periph_reset_deassert(struct clk *c) { - tegra2_periph_reset_deassert(c); + BUG_ON(!c->ops->reset); + c->ops->reset(c, false); } EXPORT_SYMBOL(tegra_periph_reset_deassert); void tegra_periph_reset_assert(struct clk *c) { - tegra2_periph_reset_assert(c); + BUG_ON(!c->ops->reset); + c->ops->reset(c, true); } EXPORT_SYMBOL(tegra_periph_reset_assert); -void __init tegra_init_clock(void) -{ - tegra2_init_clocks(); -} - -/* - * The SDMMC controllers have extra bits in the clock source register that - * adjust the delay between the clock and data to compenstate for delays - * on the PCB. - */ -void tegra_sdmmc_tap_delay(struct clk *c, int delay) -{ - unsigned long flags; - - spin_lock_irqsave(&c->spinlock, flags); - tegra2_sdmmc_tap_delay(c, delay); - spin_unlock_irqrestore(&c->spinlock, flags); -} - #ifdef CONFIG_DEBUG_FS static int __clk_lock_all_spinlocks(void) diff --git a/arch/arm/mach-tegra/clock.h b/arch/arm/mach-tegra/clock.h index 688316abc64..5c44106616c 100644 --- a/arch/arm/mach-tegra/clock.h +++ b/arch/arm/mach-tegra/clock.h @@ -146,15 +146,11 @@ struct tegra_clk_init_table { }; void tegra2_init_clocks(void); -void tegra2_periph_reset_deassert(struct clk *c); -void tegra2_periph_reset_assert(struct clk *c); void clk_init(struct clk *clk); struct clk *tegra_get_clock_by_name(const char *name); -unsigned long clk_measure_input_freq(void); int clk_reparent(struct clk *c, struct clk *parent); void tegra_clk_init_from_table(struct tegra_clk_init_table *table); unsigned long clk_get_rate_locked(struct clk *c); int clk_set_rate_locked(struct clk *c, unsigned long rate); -void tegra2_sdmmc_tap_delay(struct clk *c, int delay); #endif diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c index 20f396d740f..a2eb90169ae 100644 --- a/arch/arm/mach-tegra/common.c +++ b/arch/arm/mach-tegra/common.c @@ -1,5 +1,5 @@ /* - * arch/arm/mach-tegra/board-harmony.c + * arch/arm/mach-tegra/common.c * * Copyright (C) 2010 Google, Inc. * @@ -21,8 +21,10 @@ #include <linux/io.h> #include <linux/clk.h> #include <linux/delay.h> +#include <linux/of_irq.h> #include <asm/hardware/cache-l2x0.h> +#include <asm/hardware/gic.h> #include <mach/iomap.h> #include <mach/system.h> @@ -31,18 +33,31 @@ #include "clock.h" #include "fuse.h" +#ifdef CONFIG_OF +static const struct of_device_id tegra_dt_irq_match[] __initconst = { + { .compatible = "arm,cortex-a9-gic", .data = gic_of_init }, + { } +}; + +void __init tegra_dt_init_irq(void) +{ + tegra_init_irq(); + of_irq_init(tegra_dt_irq_match); +} +#endif + void tegra_assert_system_reset(char mode, const char *cmd) { - void __iomem *reset = IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x04); + void __iomem *reset = IO_ADDRESS(TEGRA_PMC_BASE + 0); u32 reg; - /* use *_related to avoid spinlock since caches are off */ reg = readl_relaxed(reset); - reg |= 0x04; + reg |= 0x10; writel_relaxed(reg, reset); } -static __initdata struct tegra_clk_init_table common_clk_init_table[] = { +#ifdef CONFIG_ARCH_TEGRA_2x_SOC +static __initdata struct tegra_clk_init_table tegra20_clk_init_table[] = { /* name parent rate enabled */ { "clk_m", NULL, 0, true }, { "pll_p", "clk_m", 216000000, true }, @@ -58,24 +73,38 @@ static __initdata struct tegra_clk_init_table common_clk_init_table[] = { { "cpu", NULL, 0, true }, { NULL, NULL, 0, 0}, }; +#endif -static void __init tegra_init_cache(void) +static void __init tegra_init_cache(u32 tag_latency, u32 data_latency) { #ifdef CONFIG_CACHE_L2X0 void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000; + u32 aux_ctrl, cache_type; + + writel_relaxed(tag_latency, p + L2X0_TAG_LATENCY_CTRL); + writel_relaxed(data_latency, p + L2X0_DATA_LATENCY_CTRL); - writel_relaxed(0x331, p + L2X0_TAG_LATENCY_CTRL); - writel_relaxed(0x441, p + L2X0_DATA_LATENCY_CTRL); + cache_type = readl(p + L2X0_CACHE_TYPE); + aux_ctrl = (cache_type & 0x700) << (17-8); + aux_ctrl |= 0x6C000001; - l2x0_init(p, 0x6C080001, 0x8200c3fe); + l2x0_init(p, aux_ctrl, 0x8200c3fe); #endif } -void __init tegra_init_early(void) +#ifdef CONFIG_ARCH_TEGRA_2x_SOC +void __init tegra20_init_early(void) { tegra_init_fuse(); - tegra_init_clock(); - tegra_clk_init_from_table(common_clk_init_table); - tegra_init_cache(); + tegra2_init_clocks(); + tegra_clk_init_from_table(tegra20_clk_init_table); + tegra_init_cache(0x331, 0x441); +} +#endif +#ifdef CONFIG_ARCH_TEGRA_3x_SOC +void __init tegra30_init_early(void) +{ + tegra_init_cache(0x441, 0x551); } +#endif diff --git a/arch/arm/mach-tegra/include/mach/clk.h b/arch/arm/mach-tegra/include/mach/clk.h index c8baf8f80d2..fc3ecb66de0 100644 --- a/arch/arm/mach-tegra/include/mach/clk.h +++ b/arch/arm/mach-tegra/include/mach/clk.h @@ -26,6 +26,6 @@ void tegra_periph_reset_deassert(struct clk *c); void tegra_periph_reset_assert(struct clk *c); unsigned long clk_get_rate_all_locked(struct clk *c); -void tegra_sdmmc_tap_delay(struct clk *c, int delay); +void tegra2_sdmmc_tap_delay(struct clk *c, int delay); #endif diff --git a/arch/arm/mach-tegra/include/mach/entry-macro.S b/arch/arm/mach-tegra/include/mach/entry-macro.S index ac11262149c..e577cfe27e7 100644 --- a/arch/arm/mach-tegra/include/mach/entry-macro.S +++ b/arch/arm/mach-tegra/include/mach/entry-macro.S @@ -18,21 +18,3 @@ .macro arch_ret_to_user, tmp1, tmp2 .endm - -#if !defined(CONFIG_ARM_GIC) - /* legacy interrupt controller for AP16 */ - - .macro get_irqnr_preamble, base, tmp - @ enable imprecise aborts - cpsie a - @ EVP base at 0xf010f000 - mov \base, #0xf0000000 - orr \base, #0x00100000 - orr \base, #0x0000f000 - .endm - - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - ldr \irqnr, [\base, #0x20] @ EVT_IRQ_STS - cmp \irqnr, #0x80 - .endm -#endif diff --git a/arch/arm/mach-tegra/include/mach/irqs.h b/arch/arm/mach-tegra/include/mach/irqs.h index 73265af4dda..a2146cd6867 100644 --- a/arch/arm/mach-tegra/include/mach/irqs.h +++ b/arch/arm/mach-tegra/include/mach/irqs.h @@ -25,7 +25,6 @@ #define IRQ_LOCALTIMER 29 -#ifdef CONFIG_ARCH_TEGRA_2x_SOC /* Primary Interrupt Controller */ #define INT_PRI_BASE (INT_GIC_BASE + 32) #define INT_TMR1 (INT_PRI_BASE + 0) @@ -178,6 +177,5 @@ #define NR_BOARD_IRQS 32 #define NR_IRQS (INT_BOARD_BASE + NR_BOARD_IRQS) -#endif #endif diff --git a/arch/arm/mach-tegra/include/mach/kbc.h b/arch/arm/mach-tegra/include/mach/kbc.h index 4f3572a1c68..20bb0545f99 100644 --- a/arch/arm/mach-tegra/include/mach/kbc.h +++ b/arch/arm/mach-tegra/include/mach/kbc.h @@ -53,6 +53,7 @@ struct tegra_kbc_platform_data { struct tegra_kbc_pin_cfg pin_cfg[KBC_MAX_GPIO]; const struct matrix_keymap_data *keymap_data; + u32 wakeup_key; bool wakeup; bool use_fn_map; bool use_ghost_filter; diff --git a/arch/arm/mach-tegra/include/mach/pinmux-t2.h b/arch/arm/mach-tegra/include/mach/pinmux-tegra20.h index 4c262634726..6a40c1dbab1 100644 --- a/arch/arm/mach-tegra/include/mach/pinmux-t2.h +++ b/arch/arm/mach-tegra/include/mach/pinmux-tegra20.h @@ -1,5 +1,5 @@ /* - * linux/arch/arm/mach-tegra/include/mach/pinmux-t2.h + * linux/arch/arm/mach-tegra/include/mach/pinmux-tegra20.h * * Copyright (C) 2010 Google, Inc. * @@ -14,8 +14,8 @@ * */ -#ifndef __MACH_TEGRA_PINMUX_T2_H -#define __MACH_TEGRA_PINMUX_T2_H +#ifndef __MACH_TEGRA_PINMUX_TEGRA20_H +#define __MACH_TEGRA_PINMUX_TEGRA20_H enum tegra_pingroup { TEGRA_PINGROUP_ATA = 0, diff --git a/arch/arm/mach-tegra/include/mach/pinmux-tegra30.h b/arch/arm/mach-tegra/include/mach/pinmux-tegra30.h new file mode 100644 index 00000000000..c1aee3eb2df --- /dev/null +++ b/arch/arm/mach-tegra/include/mach/pinmux-tegra30.h @@ -0,0 +1,320 @@ +/* + * linux/arch/arm/mach-tegra/include/mach/pinmux-tegra30.h + * + * Copyright (C) 2010 Google, Inc. + * Copyright (C) 2010,2011 Nvidia, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __MACH_TEGRA_PINMUX_TEGRA30_H +#define __MACH_TEGRA_PINMUX_TEGRA30_H + +enum tegra_pingroup { + TEGRA_PINGROUP_ULPI_DATA0 = 0, + TEGRA_PINGROUP_ULPI_DATA1, + TEGRA_PINGROUP_ULPI_DATA2, + TEGRA_PINGROUP_ULPI_DATA3, + TEGRA_PINGROUP_ULPI_DATA4, + TEGRA_PINGROUP_ULPI_DATA5, + TEGRA_PINGROUP_ULPI_DATA6, + TEGRA_PINGROUP_ULPI_DATA7, + TEGRA_PINGROUP_ULPI_CLK, + TEGRA_PINGROUP_ULPI_DIR, + TEGRA_PINGROUP_ULPI_NXT, + TEGRA_PINGROUP_ULPI_STP, + TEGRA_PINGROUP_DAP3_FS, + TEGRA_PINGROUP_DAP3_DIN, + TEGRA_PINGROUP_DAP3_DOUT, + TEGRA_PINGROUP_DAP3_SCLK, + TEGRA_PINGROUP_GPIO_PV0, + TEGRA_PINGROUP_GPIO_PV1, + TEGRA_PINGROUP_SDMMC1_CLK, + TEGRA_PINGROUP_SDMMC1_CMD, + TEGRA_PINGROUP_SDMMC1_DAT3, + TEGRA_PINGROUP_SDMMC1_DAT2, + TEGRA_PINGROUP_SDMMC1_DAT1, + TEGRA_PINGROUP_SDMMC1_DAT0, + TEGRA_PINGROUP_GPIO_PV2, + TEGRA_PINGROUP_GPIO_PV3, + TEGRA_PINGROUP_CLK2_OUT, + TEGRA_PINGROUP_CLK2_REQ, + TEGRA_PINGROUP_LCD_PWR1, + TEGRA_PINGROUP_LCD_PWR2, + TEGRA_PINGROUP_LCD_SDIN, + TEGRA_PINGROUP_LCD_SDOUT, + TEGRA_PINGROUP_LCD_WR_N, + TEGRA_PINGROUP_LCD_CS0_N, + TEGRA_PINGROUP_LCD_DC0, + TEGRA_PINGROUP_LCD_SCK, + TEGRA_PINGROUP_LCD_PWR0, + TEGRA_PINGROUP_LCD_PCLK, + TEGRA_PINGROUP_LCD_DE, + TEGRA_PINGROUP_LCD_HSYNC, + TEGRA_PINGROUP_LCD_VSYNC, + TEGRA_PINGROUP_LCD_D0, + TEGRA_PINGROUP_LCD_D1, + TEGRA_PINGROUP_LCD_D2, + TEGRA_PINGROUP_LCD_D3, + TEGRA_PINGROUP_LCD_D4, + TEGRA_PINGROUP_LCD_D5, + TEGRA_PINGROUP_LCD_D6, + TEGRA_PINGROUP_LCD_D7, + TEGRA_PINGROUP_LCD_D8, + TEGRA_PINGROUP_LCD_D9, + TEGRA_PINGROUP_LCD_D10, + TEGRA_PINGROUP_LCD_D11, + TEGRA_PINGROUP_LCD_D12, + TEGRA_PINGROUP_LCD_D13, + TEGRA_PINGROUP_LCD_D14, + TEGRA_PINGROUP_LCD_D15, + TEGRA_PINGROUP_LCD_D16, + TEGRA_PINGROUP_LCD_D17, + TEGRA_PINGROUP_LCD_D18, + TEGRA_PINGROUP_LCD_D19, + TEGRA_PINGROUP_LCD_D20, + TEGRA_PINGROUP_LCD_D21, + TEGRA_PINGROUP_LCD_D22, + TEGRA_PINGROUP_LCD_D23, + TEGRA_PINGROUP_LCD_CS1_N, + TEGRA_PINGROUP_LCD_M1, + TEGRA_PINGROUP_LCD_DC1, + TEGRA_PINGROUP_HDMI_INT, + TEGRA_PINGROUP_DDC_SCL, + TEGRA_PINGROUP_DDC_SDA, + TEGRA_PINGROUP_CRT_HSYNC, + TEGRA_PINGROUP_CRT_VSYNC, + TEGRA_PINGROUP_VI_D0, + TEGRA_PINGROUP_VI_D1, + TEGRA_PINGROUP_VI_D2, + TEGRA_PINGROUP_VI_D3, + TEGRA_PINGROUP_VI_D4, + TEGRA_PINGROUP_VI_D5, + TEGRA_PINGROUP_VI_D6, + TEGRA_PINGROUP_VI_D7, + TEGRA_PINGROUP_VI_D8, + TEGRA_PINGROUP_VI_D9, + TEGRA_PINGROUP_VI_D10, + TEGRA_PINGROUP_VI_D11, + TEGRA_PINGROUP_VI_PCLK, + TEGRA_PINGROUP_VI_MCLK, + TEGRA_PINGROUP_VI_VSYNC, + TEGRA_PINGROUP_VI_HSYNC, + TEGRA_PINGROUP_UART2_RXD, + TEGRA_PINGROUP_UART2_TXD, + TEGRA_PINGROUP_UART2_RTS_N, + TEGRA_PINGROUP_UART2_CTS_N, + TEGRA_PINGROUP_UART3_TXD, + TEGRA_PINGROUP_UART3_RXD, + TEGRA_PINGROUP_UART3_CTS_N, + TEGRA_PINGROUP_UART3_RTS_N, + TEGRA_PINGROUP_GPIO_PU0, + TEGRA_PINGROUP_GPIO_PU1, + TEGRA_PINGROUP_GPIO_PU2, + TEGRA_PINGROUP_GPIO_PU3, + TEGRA_PINGROUP_GPIO_PU4, + TEGRA_PINGROUP_GPIO_PU5, + TEGRA_PINGROUP_GPIO_PU6, + TEGRA_PINGROUP_GEN1_I2C_SDA, + TEGRA_PINGROUP_GEN1_I2C_SCL, + TEGRA_PINGROUP_DAP4_FS, + TEGRA_PINGROUP_DAP4_DIN, + TEGRA_PINGROUP_DAP4_DOUT, + TEGRA_PINGROUP_DAP4_SCLK, + TEGRA_PINGROUP_CLK3_OUT, + TEGRA_PINGROUP_CLK3_REQ, + TEGRA_PINGROUP_GMI_WP_N, + TEGRA_PINGROUP_GMI_IORDY, + TEGRA_PINGROUP_GMI_WAIT, + TEGRA_PINGROUP_GMI_ADV_N, + TEGRA_PINGROUP_GMI_CLK, + TEGRA_PINGROUP_GMI_CS0_N, + TEGRA_PINGROUP_GMI_CS1_N, + TEGRA_PINGROUP_GMI_CS2_N, + TEGRA_PINGROUP_GMI_CS3_N, + TEGRA_PINGROUP_GMI_CS4_N, + TEGRA_PINGROUP_GMI_CS6_N, + TEGRA_PINGROUP_GMI_CS7_N, + TEGRA_PINGROUP_GMI_AD0, + TEGRA_PINGROUP_GMI_AD1, + TEGRA_PINGROUP_GMI_AD2, + TEGRA_PINGROUP_GMI_AD3, + TEGRA_PINGROUP_GMI_AD4, + TEGRA_PINGROUP_GMI_AD5, + TEGRA_PINGROUP_GMI_AD6, + TEGRA_PINGROUP_GMI_AD7, + TEGRA_PINGROUP_GMI_AD8, + TEGRA_PINGROUP_GMI_AD9, + TEGRA_PINGROUP_GMI_AD10, + TEGRA_PINGROUP_GMI_AD11, + TEGRA_PINGROUP_GMI_AD12, + TEGRA_PINGROUP_GMI_AD13, + TEGRA_PINGROUP_GMI_AD14, + TEGRA_PINGROUP_GMI_AD15, + TEGRA_PINGROUP_GMI_A16, + TEGRA_PINGROUP_GMI_A17, + TEGRA_PINGROUP_GMI_A18, + TEGRA_PINGROUP_GMI_A19, + TEGRA_PINGROUP_GMI_WR_N, + TEGRA_PINGROUP_GMI_OE_N, + TEGRA_PINGROUP_GMI_DQS, + TEGRA_PINGROUP_GMI_RST_N, + TEGRA_PINGROUP_GEN2_I2C_SCL, + TEGRA_PINGROUP_GEN2_I2C_SDA, + TEGRA_PINGROUP_SDMMC4_CLK, + TEGRA_PINGROUP_SDMMC4_CMD, + TEGRA_PINGROUP_SDMMC4_DAT0, + TEGRA_PINGROUP_SDMMC4_DAT1, + TEGRA_PINGROUP_SDMMC4_DAT2, + TEGRA_PINGROUP_SDMMC4_DAT3, + TEGRA_PINGROUP_SDMMC4_DAT4, + TEGRA_PINGROUP_SDMMC4_DAT5, + TEGRA_PINGROUP_SDMMC4_DAT6, + TEGRA_PINGROUP_SDMMC4_DAT7, + TEGRA_PINGROUP_SDMMC4_RST_N, + TEGRA_PINGROUP_CAM_MCLK, + TEGRA_PINGROUP_GPIO_PCC1, + TEGRA_PINGROUP_GPIO_PBB0, + TEGRA_PINGROUP_CAM_I2C_SCL, + TEGRA_PINGROUP_CAM_I2C_SDA, + TEGRA_PINGROUP_GPIO_PBB3, + TEGRA_PINGROUP_GPIO_PBB4, + TEGRA_PINGROUP_GPIO_PBB5, + TEGRA_PINGROUP_GPIO_PBB6, + TEGRA_PINGROUP_GPIO_PBB7, + TEGRA_PINGROUP_GPIO_PCC2, + TEGRA_PINGROUP_JTAG_RTCK, + TEGRA_PINGROUP_PWR_I2C_SCL, + TEGRA_PINGROUP_PWR_I2C_SDA, + TEGRA_PINGROUP_KB_ROW0, + TEGRA_PINGROUP_KB_ROW1, + TEGRA_PINGROUP_KB_ROW2, + TEGRA_PINGROUP_KB_ROW3, + TEGRA_PINGROUP_KB_ROW4, + TEGRA_PINGROUP_KB_ROW5, + TEGRA_PINGROUP_KB_ROW6, + TEGRA_PINGROUP_KB_ROW7, + TEGRA_PINGROUP_KB_ROW8, + TEGRA_PINGROUP_KB_ROW9, + TEGRA_PINGROUP_KB_ROW10, + TEGRA_PINGROUP_KB_ROW11, + TEGRA_PINGROUP_KB_ROW12, + TEGRA_PINGROUP_KB_ROW13, + TEGRA_PINGROUP_KB_ROW14, + TEGRA_PINGROUP_KB_ROW15, + TEGRA_PINGROUP_KB_COL0, + TEGRA_PINGROUP_KB_COL1, + TEGRA_PINGROUP_KB_COL2, + TEGRA_PINGROUP_KB_COL3, + TEGRA_PINGROUP_KB_COL4, + TEGRA_PINGROUP_KB_COL5, + TEGRA_PINGROUP_KB_COL6, + TEGRA_PINGROUP_KB_COL7, + TEGRA_PINGROUP_CLK_32K_OUT, + TEGRA_PINGROUP_SYS_CLK_REQ, + TEGRA_PINGROUP_CORE_PWR_REQ, + TEGRA_PINGROUP_CPU_PWR_REQ, + TEGRA_PINGROUP_PWR_INT_N, + TEGRA_PINGROUP_CLK_32K_IN, + TEGRA_PINGROUP_OWR, + TEGRA_PINGROUP_DAP1_FS, + TEGRA_PINGROUP_DAP1_DIN, + TEGRA_PINGROUP_DAP1_DOUT, + TEGRA_PINGROUP_DAP1_SCLK, + TEGRA_PINGROUP_CLK1_REQ, + TEGRA_PINGROUP_CLK1_OUT, + TEGRA_PINGROUP_SPDIF_IN, + TEGRA_PINGROUP_SPDIF_OUT, + TEGRA_PINGROUP_DAP2_FS, + TEGRA_PINGROUP_DAP2_DIN, + TEGRA_PINGROUP_DAP2_DOUT, + TEGRA_PINGROUP_DAP2_SCLK, + TEGRA_PINGROUP_SPI2_MOSI, + TEGRA_PINGROUP_SPI2_MISO, + TEGRA_PINGROUP_SPI2_CS0_N, + TEGRA_PINGROUP_SPI2_SCK, + TEGRA_PINGROUP_SPI1_MOSI, + TEGRA_PINGROUP_SPI1_SCK, + TEGRA_PINGROUP_SPI1_CS0_N, + TEGRA_PINGROUP_SPI1_MISO, + TEGRA_PINGROUP_SPI2_CS1_N, + TEGRA_PINGROUP_SPI2_CS2_N, + TEGRA_PINGROUP_SDMMC3_CLK, + TEGRA_PINGROUP_SDMMC3_CMD, + TEGRA_PINGROUP_SDMMC3_DAT0, + TEGRA_PINGROUP_SDMMC3_DAT1, + TEGRA_PINGROUP_SDMMC3_DAT2, + TEGRA_PINGROUP_SDMMC3_DAT3, + TEGRA_PINGROUP_SDMMC3_DAT4, + TEGRA_PINGROUP_SDMMC3_DAT5, + TEGRA_PINGROUP_SDMMC3_DAT6, + TEGRA_PINGROUP_SDMMC3_DAT7, + TEGRA_PINGROUP_PEX_L0_PRSNT_N, + TEGRA_PINGROUP_PEX_L0_RST_N, + TEGRA_PINGROUP_PEX_L0_CLKREQ_N, + TEGRA_PINGROUP_PEX_WAKE_N, + TEGRA_PINGROUP_PEX_L1_PRSNT_N, + TEGRA_PINGROUP_PEX_L1_RST_N, + TEGRA_PINGROUP_PEX_L1_CLKREQ_N, + TEGRA_PINGROUP_PEX_L2_PRSNT_N, + TEGRA_PINGROUP_PEX_L2_RST_N, + TEGRA_PINGROUP_PEX_L2_CLKREQ_N, + TEGRA_PINGROUP_HDMI_CEC, + TEGRA_MAX_PINGROUP, +}; + +enum tegra_drive_pingroup { + TEGRA_DRIVE_PINGROUP_AO1 = 0, + TEGRA_DRIVE_PINGROUP_AO2, + TEGRA_DRIVE_PINGROUP_AT1, + TEGRA_DRIVE_PINGROUP_AT2, + TEGRA_DRIVE_PINGROUP_AT3, + TEGRA_DRIVE_PINGROUP_AT4, + TEGRA_DRIVE_PINGROUP_AT5, + TEGRA_DRIVE_PINGROUP_CDEV1, + TEGRA_DRIVE_PINGROUP_CDEV2, + TEGRA_DRIVE_PINGROUP_CSUS, + TEGRA_DRIVE_PINGROUP_DAP1, + TEGRA_DRIVE_PINGROUP_DAP2, + TEGRA_DRIVE_PINGROUP_DAP3, + TEGRA_DRIVE_PINGROUP_DAP4, + TEGRA_DRIVE_PINGROUP_DBG, + TEGRA_DRIVE_PINGROUP_LCD1, + TEGRA_DRIVE_PINGROUP_LCD2, + TEGRA_DRIVE_PINGROUP_SDIO2, + TEGRA_DRIVE_PINGROUP_SDIO3, + TEGRA_DRIVE_PINGROUP_SPI, + TEGRA_DRIVE_PINGROUP_UAA, + TEGRA_DRIVE_PINGROUP_UAB, + TEGRA_DRIVE_PINGROUP_UART2, + TEGRA_DRIVE_PINGROUP_UART3, + TEGRA_DRIVE_PINGROUP_VI1, + TEGRA_DRIVE_PINGROUP_SDIO1, + TEGRA_DRIVE_PINGROUP_CRT, + TEGRA_DRIVE_PINGROUP_DDC, + TEGRA_DRIVE_PINGROUP_GMA, + TEGRA_DRIVE_PINGROUP_GMB, + TEGRA_DRIVE_PINGROUP_GMC, + TEGRA_DRIVE_PINGROUP_GMD, + TEGRA_DRIVE_PINGROUP_GME, + TEGRA_DRIVE_PINGROUP_GMF, + TEGRA_DRIVE_PINGROUP_GMG, + TEGRA_DRIVE_PINGROUP_GMH, + TEGRA_DRIVE_PINGROUP_OWR, + TEGRA_DRIVE_PINGROUP_UAD, + TEGRA_DRIVE_PINGROUP_GPV, + TEGRA_DRIVE_PINGROUP_DEV3, + TEGRA_DRIVE_PINGROUP_CEC, + TEGRA_MAX_DRIVE_PINGROUP, +}; + +#endif + diff --git a/arch/arm/mach-tegra/include/mach/pinmux.h b/arch/arm/mach-tegra/include/mach/pinmux.h index bb7dfdb6120..055f1792c8f 100644 --- a/arch/arm/mach-tegra/include/mach/pinmux.h +++ b/arch/arm/mach-tegra/include/mach/pinmux.h @@ -2,6 +2,7 @@ * linux/arch/arm/mach-tegra/include/mach/pinmux.h * * Copyright (C) 2010 Google, Inc. + * Copyright (C) 2010,2011 Nvidia, Inc. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -17,18 +18,13 @@ #ifndef __MACH_TEGRA_PINMUX_H #define __MACH_TEGRA_PINMUX_H -#if defined(CONFIG_ARCH_TEGRA_2x_SOC) -#include "pinmux-t2.h" -#else -#error "Undefined Tegra architecture" -#endif - enum tegra_mux_func { TEGRA_MUX_RSVD = 0x8000, TEGRA_MUX_RSVD1 = 0x8000, TEGRA_MUX_RSVD2 = 0x8001, TEGRA_MUX_RSVD3 = 0x8002, TEGRA_MUX_RSVD4 = 0x8003, + TEGRA_MUX_INVALID = 0x4000, TEGRA_MUX_NONE = -1, TEGRA_MUX_AHB_CLK, TEGRA_MUX_APB_CLK, @@ -90,6 +86,49 @@ enum tegra_mux_func { TEGRA_MUX_VI, TEGRA_MUX_VI_SENSOR_CLK, TEGRA_MUX_XIO, + TEGRA_MUX_BLINK, + TEGRA_MUX_CEC, + TEGRA_MUX_CLK12, + TEGRA_MUX_DAP, + TEGRA_MUX_DAPSDMMC2, + TEGRA_MUX_DDR, + TEGRA_MUX_DEV3, + TEGRA_MUX_DTV, + TEGRA_MUX_VI_ALT1, + TEGRA_MUX_VI_ALT2, + TEGRA_MUX_VI_ALT3, + TEGRA_MUX_EMC_DLL, + TEGRA_MUX_EXTPERIPH1, + TEGRA_MUX_EXTPERIPH2, + TEGRA_MUX_EXTPERIPH3, + TEGRA_MUX_GMI_ALT, + TEGRA_MUX_HDA, + TEGRA_MUX_HSI, + TEGRA_MUX_I2C4, + TEGRA_MUX_I2C5, + TEGRA_MUX_I2CPWR, + TEGRA_MUX_I2S0, + TEGRA_MUX_I2S1, + TEGRA_MUX_I2S2, + TEGRA_MUX_I2S3, + TEGRA_MUX_I2S4, + TEGRA_MUX_NAND_ALT, + TEGRA_MUX_POPSDIO4, + TEGRA_MUX_POPSDMMC4, + TEGRA_MUX_PWM0, + TEGRA_MUX_PWM1, + TEGRA_MUX_PWM2, + TEGRA_MUX_PWM3, + TEGRA_MUX_SATA, + TEGRA_MUX_SPI5, + TEGRA_MUX_SPI6, + TEGRA_MUX_SYSCLK, + TEGRA_MUX_VGP1, + TEGRA_MUX_VGP2, + TEGRA_MUX_VGP3, + TEGRA_MUX_VGP4, + TEGRA_MUX_VGP5, + TEGRA_MUX_VGP6, TEGRA_MUX_SAFE, TEGRA_MAX_MUX, }; @@ -105,6 +144,11 @@ enum tegra_tristate { TEGRA_TRI_TRISTATE = 1, }; +enum tegra_pin_io { + TEGRA_PIN_OUTPUT = 0, + TEGRA_PIN_INPUT = 1, +}; + enum tegra_vddio { TEGRA_VDDIO_BB = 0, TEGRA_VDDIO_LCD, @@ -115,10 +159,16 @@ enum tegra_vddio { TEGRA_VDDIO_SYS, TEGRA_VDDIO_AUDIO, TEGRA_VDDIO_SD, + TEGRA_VDDIO_CAM, + TEGRA_VDDIO_GMI, + TEGRA_VDDIO_PEXCTL, + TEGRA_VDDIO_SDMMC1, + TEGRA_VDDIO_SDMMC3, + TEGRA_VDDIO_SDMMC4, }; struct tegra_pingroup_config { - enum tegra_pingroup pingroup; + int pingroup; enum tegra_mux_func func; enum tegra_pullupdown pupd; enum tegra_tristate tristate; @@ -187,7 +237,7 @@ enum tegra_schmitt { }; struct tegra_drive_pingroup_config { - enum tegra_drive_pingroup pingroup; + int pingroup; enum tegra_hsm hsm; enum tegra_schmitt schmitt; enum tegra_drive drive; @@ -208,6 +258,7 @@ struct tegra_pingroup_desc { int funcs[4]; int func_safe; int vddio; + enum tegra_pin_io io_default; s16 tri_bank; /* Register bank the tri_reg exists within */ s16 mux_bank; /* Register bank the mux_reg exists within */ s16 pupd_bank; /* Register bank the pupd_reg exists within */ @@ -217,15 +268,23 @@ struct tegra_pingroup_desc { s8 tri_bit; /* offset into the TRISTATE_REG_* register bit */ s8 mux_bit; /* offset into the PIN_MUX_CTL_* register bit */ s8 pupd_bit; /* offset into the PULL_UPDOWN_REG_* register bit */ + s8 lock_bit; /* offset of the LOCK bit into mux register bit */ + s8 od_bit; /* offset of the OD bit into mux register bit */ + s8 ioreset_bit; /* offset of the IO_RESET bit into mux register bit */ }; -extern const struct tegra_pingroup_desc tegra_soc_pingroups[]; -extern const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[]; +typedef void (*pinmux_init) (const struct tegra_pingroup_desc **pg, + int *pg_max, const struct tegra_drive_pingroup_desc **pgdrive, + int *pgdrive_max); -int tegra_pinmux_set_tristate(enum tegra_pingroup pg, - enum tegra_tristate tristate); -int tegra_pinmux_set_pullupdown(enum tegra_pingroup pg, - enum tegra_pullupdown pupd); +void tegra20_pinmux_init(const struct tegra_pingroup_desc **pg, int *pg_max, + const struct tegra_drive_pingroup_desc **pgdrive, int *pgdrive_max); + +void tegra30_pinmux_init(const struct tegra_pingroup_desc **pg, int *pg_max, + const struct tegra_drive_pingroup_desc **pgdrive, int *pgdrive_max); + +int tegra_pinmux_set_tristate(int pg, enum tegra_tristate tristate); +int tegra_pinmux_set_pullupdown(int pg, enum tegra_pullupdown pupd); void tegra_pinmux_config_table(const struct tegra_pingroup_config *config, int len); @@ -241,4 +300,3 @@ void tegra_pinmux_config_tristate_table(const struct tegra_pingroup_config *conf void tegra_pinmux_config_pullupdown_table(const struct tegra_pingroup_config *config, int len, enum tegra_pullupdown pupd); #endif - diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c index 4956c3cea73..4e1afcd54fa 100644 --- a/arch/arm/mach-tegra/irq.c +++ b/arch/arm/mach-tegra/irq.c @@ -21,6 +21,7 @@ #include <linux/interrupt.h> #include <linux/irq.h> #include <linux/io.h> +#include <linux/of.h> #include <asm/hardware/gic.h> @@ -28,10 +29,6 @@ #include "board.h" -#define INT_SYS_NR (INT_GPIO_BASE - INT_PRI_BASE) -#define INT_SYS_SZ (INT_SEC_BASE - INT_PRI_BASE) -#define PPI_NR ((INT_SYS_NR+INT_SYS_SZ-1)/INT_SYS_SZ) - #define ICTLR_CPU_IEP_VFIQ 0x08 #define ICTLR_CPU_IEP_FIR 0x14 #define ICTLR_CPU_IEP_FIR_SET 0x18 @@ -129,6 +126,11 @@ void __init tegra_init_irq(void) gic_arch_extn.irq_unmask = tegra_unmask; gic_arch_extn.irq_retrigger = tegra_retrigger; - gic_init(0, 29, IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE), - IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100)); + /* + * Check if there is a devicetree present, since the GIC will be + * initialized elsewhere under DT. + */ + if (!of_have_populated_dt()) + gic_init(0, 29, IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE), + IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100)); } diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c index 97ef3e55dfd..af8b6343572 100644 --- a/arch/arm/mach-tegra/pcie.c +++ b/arch/arm/mach-tegra/pcie.c @@ -37,7 +37,6 @@ #include <asm/sizes.h> #include <asm/mach/pci.h> -#include <mach/pinmux.h> #include <mach/iomap.h> #include <mach/clk.h> #include <mach/powergate.h> @@ -409,7 +408,7 @@ static int tegra_pcie_setup(int nr, struct pci_sys_data *sys) pp->res[0].flags = IORESOURCE_IO; if (request_resource(&ioport_resource, &pp->res[0])) panic("Request PCIe IO resource failed\n"); - sys->resource[0] = &pp->res[0]; + pci_add_resource(&sys->resources, &pp->res[0]); /* * IORESOURCE_MEM @@ -428,7 +427,7 @@ static int tegra_pcie_setup(int nr, struct pci_sys_data *sys) pp->res[1].flags = IORESOURCE_MEM; if (request_resource(&iomem_resource, &pp->res[1])) panic("Request PCIe Memory resource failed\n"); - sys->resource[1] = &pp->res[1]; + pci_add_resource(&sys->resources, &pp->res[1]); /* * IORESOURCE_MEM | IORESOURCE_PREFETCH @@ -447,7 +446,7 @@ static int tegra_pcie_setup(int nr, struct pci_sys_data *sys) pp->res[2].flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; if (request_resource(&iomem_resource, &pp->res[2])) panic("Request PCIe Prefetch Memory resource failed\n"); - sys->resource[2] = &pp->res[2]; + pci_add_resource(&sys->resources, &pp->res[2]); return 1; } @@ -468,7 +467,8 @@ static struct pci_bus __init *tegra_pcie_scan_bus(int nr, pp = tegra_pcie.port + nr; pp->root_bus_nr = sys->busnr; - return pci_scan_bus(sys->busnr, &tegra_pcie_ops, sys); + return pci_scan_root_bus(NULL, sys->busnr, &tegra_pcie_ops, sys, + &sys->resources); } static struct hw_pci tegra_pcie_hw __initdata = { diff --git a/arch/arm/mach-tegra/pinmux-t2-tables.c b/arch/arm/mach-tegra/pinmux-tegra20-tables.c index a0dc2bc28ed..734add1280b 100644 --- a/arch/arm/mach-tegra/pinmux-t2-tables.c +++ b/arch/arm/mach-tegra/pinmux-tegra20-tables.c @@ -1,7 +1,7 @@ /* - * linux/arch/arm/mach-tegra/pinmux-t2-tables.c + * linux/arch/arm/mach-tegra/pinmux-tegra20-tables.c * - * Common pinmux configurations for Tegra 2 SoCs + * Common pinmux configurations for Tegra20 SoCs * * Copyright (C) 2010 NVIDIA Corporation * @@ -29,6 +29,7 @@ #include <mach/iomap.h> #include <mach/pinmux.h> +#include <mach/pinmux-tegra20.h> #include <mach/suspend.h> #define TRISTATE_REG_A 0x14 @@ -43,7 +44,7 @@ .reg = ((r) - PINGROUP_REG_A) \ } -const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE_PINGROUP] = { +static const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE_PINGROUP] = { DRIVE_PINGROUP(AO1, 0x868), DRIVE_PINGROUP(AO2, 0x86c), DRIVE_PINGROUP(AT1, 0x870), @@ -105,9 +106,13 @@ const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE .pupd_bank = 2, \ .pupd_reg = ((pupd_r) - PULLUPDOWN_REG_A), \ .pupd_bit = pupd_b, \ + .lock_bit = -1, \ + .od_bit = -1, \ + .ioreset_bit = -1, \ + .io_default = -1, \ } -const struct tegra_pingroup_desc tegra_soc_pingroups[TEGRA_MAX_PINGROUP] = { +static const struct tegra_pingroup_desc tegra_soc_pingroups[TEGRA_MAX_PINGROUP] = { PINGROUP(ATA, NAND, IDE, NAND, GMI, RSVD, IDE, 0x14, 0, 0x80, 24, 0xA0, 0), PINGROUP(ATB, NAND, IDE, NAND, GMI, SDIO4, IDE, 0x14, 1, 0x80, 16, 0xA0, 2), PINGROUP(ATC, NAND, IDE, NAND, GMI, SDIO4, IDE, 0x14, 2, 0x80, 22, 0xA0, 4), @@ -226,3 +231,14 @@ const struct tegra_pingroup_desc tegra_soc_pingroups[TEGRA_MAX_PINGROUP] = { PINGROUP(XM2C, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xA8, 30), PINGROUP(XM2D, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xA8, 28), }; + +void __devinit tegra20_pinmux_init(const struct tegra_pingroup_desc **pg, + int *pg_max, const struct tegra_drive_pingroup_desc **pgdrive, + int *pgdrive_max) +{ + *pg = tegra_soc_pingroups; + *pg_max = TEGRA_MAX_PINGROUP; + *pgdrive = tegra_soc_drive_pingroups; + *pgdrive_max = TEGRA_MAX_DRIVE_PINGROUP; +} + diff --git a/arch/arm/mach-tegra/pinmux-tegra30-tables.c b/arch/arm/mach-tegra/pinmux-tegra30-tables.c new file mode 100644 index 00000000000..14fc0e4c1c4 --- /dev/null +++ b/arch/arm/mach-tegra/pinmux-tegra30-tables.c @@ -0,0 +1,376 @@ +/* + * linux/arch/arm/mach-tegra/pinmux-tegra30-tables.c + * + * Common pinmux configurations for Tegra30 SoCs + * + * Copyright (C) 2010,2011 NVIDIA Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#include <linux/kernel.h> +#include <linux/errno.h> +#include <linux/spinlock.h> +#include <linux/io.h> +#include <linux/init.h> +#include <linux/string.h> + +#include <mach/iomap.h> +#include <mach/pinmux.h> +#include <mach/pinmux-tegra30.h> +#include <mach/suspend.h> + +#define PINGROUP_REG_A 0x868 +#define MUXCTL_REG_A 0x3000 + +#define DRIVE_PINGROUP(pg_name, r) \ + [TEGRA_DRIVE_PINGROUP_ ## pg_name] = { \ + .name = #pg_name, \ + .reg_bank = 0, \ + .reg = ((r) - PINGROUP_REG_A) \ + } + +static const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE_PINGROUP] = { + DRIVE_PINGROUP(AO1, 0x868), + DRIVE_PINGROUP(AO2, 0x86c), + DRIVE_PINGROUP(AT1, 0x870), + DRIVE_PINGROUP(AT2, 0x874), + DRIVE_PINGROUP(AT3, 0x878), + DRIVE_PINGROUP(AT4, 0x87c), + DRIVE_PINGROUP(AT5, 0x880), + DRIVE_PINGROUP(CDEV1, 0x884), + DRIVE_PINGROUP(CDEV2, 0x888), + DRIVE_PINGROUP(CSUS, 0x88c), + DRIVE_PINGROUP(DAP1, 0x890), + DRIVE_PINGROUP(DAP2, 0x894), + DRIVE_PINGROUP(DAP3, 0x898), + DRIVE_PINGROUP(DAP4, 0x89c), + DRIVE_PINGROUP(DBG, 0x8a0), + DRIVE_PINGROUP(LCD1, 0x8a4), + DRIVE_PINGROUP(LCD2, 0x8a8), + DRIVE_PINGROUP(SDIO2, 0x8ac), + DRIVE_PINGROUP(SDIO3, 0x8b0), + DRIVE_PINGROUP(SPI, 0x8b4), + DRIVE_PINGROUP(UAA, 0x8b8), + DRIVE_PINGROUP(UAB, 0x8bc), + DRIVE_PINGROUP(UART2, 0x8c0), + DRIVE_PINGROUP(UART3, 0x8c4), + DRIVE_PINGROUP(VI1, 0x8c8), + DRIVE_PINGROUP(SDIO1, 0x8ec), + DRIVE_PINGROUP(CRT, 0x8f8), + DRIVE_PINGROUP(DDC, 0x8fc), + DRIVE_PINGROUP(GMA, 0x900), + DRIVE_PINGROUP(GMB, 0x904), + DRIVE_PINGROUP(GMC, 0x908), + DRIVE_PINGROUP(GMD, 0x90c), + DRIVE_PINGROUP(GME, 0x910), + DRIVE_PINGROUP(GMF, 0x914), + DRIVE_PINGROUP(GMG, 0x918), + DRIVE_PINGROUP(GMH, 0x91c), + DRIVE_PINGROUP(OWR, 0x920), + DRIVE_PINGROUP(UAD, 0x924), + DRIVE_PINGROUP(GPV, 0x928), + DRIVE_PINGROUP(DEV3, 0x92c), + DRIVE_PINGROUP(CEC, 0x938), +}; + +#define PINGROUP(pg_name, vdd, f0, f1, f2, f3, fs, iod, reg) \ + [TEGRA_PINGROUP_ ## pg_name] = { \ + .name = #pg_name, \ + .vddio = TEGRA_VDDIO_ ## vdd, \ + .funcs = { \ + TEGRA_MUX_ ## f0, \ + TEGRA_MUX_ ## f1, \ + TEGRA_MUX_ ## f2, \ + TEGRA_MUX_ ## f3, \ + }, \ + .func_safe = TEGRA_MUX_ ## fs, \ + .tri_bank = 1, \ + .tri_reg = ((reg) - MUXCTL_REG_A), \ + .tri_bit = 4, \ + .mux_bank = 1, \ + .mux_reg = ((reg) - MUXCTL_REG_A), \ + .mux_bit = 0, \ + .pupd_bank = 1, \ + .pupd_reg = ((reg) - MUXCTL_REG_A), \ + .pupd_bit = 2, \ + .io_default = TEGRA_PIN_ ## iod, \ + .od_bit = 6, \ + .lock_bit = 7, \ + .ioreset_bit = 8, \ + } + +static const struct tegra_pingroup_desc tegra_soc_pingroups[TEGRA_MAX_PINGROUP] = { + /* NAME VDD f0 f1 f2 f3 fSafe io reg */ + PINGROUP(ULPI_DATA0, BB, SPI3, HSI, UARTA, ULPI, RSVD, INPUT, 0x3000), + PINGROUP(ULPI_DATA1, BB, SPI3, HSI, UARTA, ULPI, RSVD, INPUT, 0x3004), + PINGROUP(ULPI_DATA2, BB, SPI3, HSI, UARTA, ULPI, RSVD, INPUT, 0x3008), + PINGROUP(ULPI_DATA3, BB, SPI3, HSI, UARTA, ULPI, RSVD, INPUT, 0x300c), + PINGROUP(ULPI_DATA4, BB, SPI2, HSI, UARTA, ULPI, RSVD, INPUT, 0x3010), + PINGROUP(ULPI_DATA5, BB, SPI2, HSI, UARTA, ULPI, RSVD, INPUT, 0x3014), + PINGROUP(ULPI_DATA6, BB, SPI2, HSI, UARTA, ULPI, RSVD, INPUT, 0x3018), + PINGROUP(ULPI_DATA7, BB, SPI2, HSI, UARTA, ULPI, RSVD, INPUT, 0x301c), + PINGROUP(ULPI_CLK, BB, SPI1, RSVD, UARTD, ULPI, RSVD, INPUT, 0x3020), + PINGROUP(ULPI_DIR, BB, SPI1, RSVD, UARTD, ULPI, RSVD, INPUT, 0x3024), + PINGROUP(ULPI_NXT, BB, SPI1, RSVD, UARTD, ULPI, RSVD, INPUT, 0x3028), + PINGROUP(ULPI_STP, BB, SPI1, RSVD, UARTD, ULPI, RSVD, INPUT, 0x302c), + PINGROUP(DAP3_FS, BB, I2S2, RSVD1, DISPLAYA, DISPLAYB, RSVD, INPUT, 0x3030), + PINGROUP(DAP3_DIN, BB, I2S2, RSVD1, DISPLAYA, DISPLAYB, RSVD, INPUT, 0x3034), + PINGROUP(DAP3_DOUT, BB, I2S2, RSVD1, DISPLAYA, DISPLAYB, RSVD, INPUT, 0x3038), + PINGROUP(DAP3_SCLK, BB, I2S2, RSVD1, DISPLAYA, DISPLAYB, RSVD, INPUT, 0x303c), + PINGROUP(GPIO_PV0, BB, RSVD, RSVD, RSVD, RSVD, RSVD, INPUT, 0x3040), + PINGROUP(GPIO_PV1, BB, RSVD, RSVD, RSVD, RSVD, RSVD, INPUT, 0x3044), + PINGROUP(SDMMC1_CLK, SDMMC1, SDIO1, RSVD1, RSVD2, INVALID, RSVD, INPUT, 0x3048), + PINGROUP(SDMMC1_CMD, SDMMC1, SDIO1, RSVD1, RSVD2, INVALID, RSVD, INPUT, 0x304c), + PINGROUP(SDMMC1_DAT3, SDMMC1, SDIO1, RSVD1, UARTE, INVALID, RSVD, INPUT, 0x3050), + PINGROUP(SDMMC1_DAT2, SDMMC1, SDIO1, RSVD1, UARTE, INVALID, RSVD, INPUT, 0x3054), + PINGROUP(SDMMC1_DAT1, SDMMC1, SDIO1, RSVD1, UARTE, INVALID, RSVD, INPUT, 0x3058), + PINGROUP(SDMMC1_DAT0, SDMMC1, SDIO1, RSVD1, UARTE, INVALID, RSVD, INPUT, 0x305c), + PINGROUP(GPIO_PV2, SDMMC1, OWR, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x3060), + PINGROUP(GPIO_PV3, SDMMC1, INVALID, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x3064), + PINGROUP(CLK2_OUT, SDMMC1, EXTPERIPH2, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x3068), + PINGROUP(CLK2_REQ, SDMMC1, DAP, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x306c), + PINGROUP(LCD_PWR1, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x3070), + PINGROUP(LCD_PWR2, LCD, DISPLAYA, DISPLAYB, SPI5, INVALID, RSVD, OUTPUT, 0x3074), + PINGROUP(LCD_SDIN, LCD, DISPLAYA, DISPLAYB, SPI5, RSVD, RSVD, OUTPUT, 0x3078), + PINGROUP(LCD_SDOUT, LCD, DISPLAYA, DISPLAYB, SPI5, INVALID, RSVD, OUTPUT, 0x307c), + PINGROUP(LCD_WR_N, LCD, DISPLAYA, DISPLAYB, SPI5, INVALID, RSVD, OUTPUT, 0x3080), + PINGROUP(LCD_CS0_N, LCD, DISPLAYA, DISPLAYB, SPI5, RSVD, RSVD, OUTPUT, 0x3084), + PINGROUP(LCD_DC0, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x3088), + PINGROUP(LCD_SCK, LCD, DISPLAYA, DISPLAYB, SPI5, INVALID, RSVD, OUTPUT, 0x308c), + PINGROUP(LCD_PWR0, LCD, DISPLAYA, DISPLAYB, SPI5, INVALID, RSVD, OUTPUT, 0x3090), + PINGROUP(LCD_PCLK, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x3094), + PINGROUP(LCD_DE, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x3098), + PINGROUP(LCD_HSYNC, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x309c), + PINGROUP(LCD_VSYNC, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30a0), + PINGROUP(LCD_D0, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30a4), + PINGROUP(LCD_D1, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30a8), + PINGROUP(LCD_D2, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30ac), + PINGROUP(LCD_D3, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30b0), + PINGROUP(LCD_D4, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30b4), + PINGROUP(LCD_D5, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30b8), + PINGROUP(LCD_D6, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30bc), + PINGROUP(LCD_D7, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30c0), + PINGROUP(LCD_D8, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30c4), + PINGROUP(LCD_D9, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30c8), + PINGROUP(LCD_D10, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30cc), + PINGROUP(LCD_D11, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30d0), + PINGROUP(LCD_D12, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30d4), + PINGROUP(LCD_D13, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30d8), + PINGROUP(LCD_D14, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30dc), + PINGROUP(LCD_D15, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30e0), + PINGROUP(LCD_D16, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30e4), + PINGROUP(LCD_D17, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30e8), + PINGROUP(LCD_D18, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30ec), + PINGROUP(LCD_D19, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30f0), + PINGROUP(LCD_D20, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30f4), + PINGROUP(LCD_D21, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30f8), + PINGROUP(LCD_D22, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30fc), + PINGROUP(LCD_D23, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x3100), + PINGROUP(LCD_CS1_N, LCD, DISPLAYA, DISPLAYB, SPI5, RSVD2, RSVD, OUTPUT, 0x3104), + PINGROUP(LCD_M1, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x3108), + PINGROUP(LCD_DC1, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x310c), + PINGROUP(HDMI_INT, LCD, RSVD, RSVD, RSVD, RSVD, RSVD, INPUT, 0x3110), + PINGROUP(DDC_SCL, LCD, I2C4, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x3114), + PINGROUP(DDC_SDA, LCD, I2C4, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x3118), + PINGROUP(CRT_HSYNC, LCD, CRT, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x311c), + PINGROUP(CRT_VSYNC, LCD, CRT, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x3120), + PINGROUP(VI_D0, VI, INVALID, RSVD1, VI, RSVD2, RSVD, INPUT, 0x3124), + PINGROUP(VI_D1, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x3128), + PINGROUP(VI_D2, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x312c), + PINGROUP(VI_D3, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x3130), + PINGROUP(VI_D4, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x3134), + PINGROUP(VI_D5, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x3138), + PINGROUP(VI_D6, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x313c), + PINGROUP(VI_D7, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x3140), + PINGROUP(VI_D8, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x3144), + PINGROUP(VI_D9, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x3148), + PINGROUP(VI_D10, VI, INVALID, RSVD1, VI, RSVD2, RSVD, INPUT, 0x314c), + PINGROUP(VI_D11, VI, INVALID, RSVD1, VI, RSVD2, RSVD, INPUT, 0x3150), + PINGROUP(VI_PCLK, VI, RSVD1, SDIO2, VI, RSVD2, RSVD, INPUT, 0x3154), + PINGROUP(VI_MCLK, VI, VI, INVALID, INVALID, INVALID, RSVD, INPUT, 0x3158), + PINGROUP(VI_VSYNC, VI, INVALID, RSVD1, VI, RSVD2, RSVD, INPUT, 0x315c), + PINGROUP(VI_HSYNC, VI, INVALID, RSVD1, VI, RSVD2, RSVD, INPUT, 0x3160), + PINGROUP(UART2_RXD, UART, IRDA, SPDIF, UARTA, SPI4, RSVD, INPUT, 0x3164), + PINGROUP(UART2_TXD, UART, IRDA, SPDIF, UARTA, SPI4, RSVD, INPUT, 0x3168), + PINGROUP(UART2_RTS_N, UART, UARTA, UARTB, GMI, SPI4, RSVD, INPUT, 0x316c), + PINGROUP(UART2_CTS_N, UART, UARTA, UARTB, GMI, SPI4, RSVD, INPUT, 0x3170), + PINGROUP(UART3_TXD, UART, UARTC, RSVD1, GMI, RSVD2, RSVD, INPUT, 0x3174), + PINGROUP(UART3_RXD, UART, UARTC, RSVD1, GMI, RSVD2, RSVD, INPUT, 0x3178), + PINGROUP(UART3_CTS_N, UART, UARTC, RSVD1, GMI, RSVD2, RSVD, INPUT, 0x317c), + PINGROUP(UART3_RTS_N, UART, UARTC, PWM0, GMI, RSVD2, RSVD, INPUT, 0x3180), + PINGROUP(GPIO_PU0, UART, OWR, UARTA, GMI, RSVD1, RSVD, INPUT, 0x3184), + PINGROUP(GPIO_PU1, UART, RSVD1, UARTA, GMI, RSVD2, RSVD, INPUT, 0x3188), + PINGROUP(GPIO_PU2, UART, RSVD1, UARTA, GMI, RSVD2, RSVD, INPUT, 0x318c), + PINGROUP(GPIO_PU3, UART, PWM0, UARTA, GMI, RSVD1, RSVD, INPUT, 0x3190), + PINGROUP(GPIO_PU4, UART, PWM1, UARTA, GMI, RSVD1, RSVD, INPUT, 0x3194), + PINGROUP(GPIO_PU5, UART, PWM2, UARTA, GMI, RSVD1, RSVD, INPUT, 0x3198), + PINGROUP(GPIO_PU6, UART, PWM3, UARTA, GMI, RSVD1, RSVD, INPUT, 0x319c), + PINGROUP(GEN1_I2C_SDA, UART, I2C, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x31a0), + PINGROUP(GEN1_I2C_SCL, UART, I2C, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x31a4), + PINGROUP(DAP4_FS, UART, I2S3, RSVD1, GMI, RSVD2, RSVD, INPUT, 0x31a8), + PINGROUP(DAP4_DIN, UART, I2S3, RSVD1, GMI, RSVD2, RSVD, INPUT, 0x31ac), + PINGROUP(DAP4_DOUT, UART, I2S3, RSVD1, GMI, RSVD2, RSVD, INPUT, 0x31b0), + PINGROUP(DAP4_SCLK, UART, I2S3, RSVD1, GMI, RSVD2, RSVD, INPUT, 0x31b4), + PINGROUP(CLK3_OUT, UART, EXTPERIPH3, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x31b8), + PINGROUP(CLK3_REQ, UART, DEV3, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x31bc), + PINGROUP(GMI_WP_N, GMI, RSVD1, NAND, GMI, GMI_ALT, RSVD, INPUT, 0x31c0), + PINGROUP(GMI_IORDY, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31c4), + PINGROUP(GMI_WAIT, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31c8), + PINGROUP(GMI_ADV_N, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31cc), + PINGROUP(GMI_CLK, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31d0), + PINGROUP(GMI_CS0_N, GMI, RSVD1, NAND, GMI, INVALID, RSVD, INPUT, 0x31d4), + PINGROUP(GMI_CS1_N, GMI, RSVD1, NAND, GMI, DTV, RSVD, INPUT, 0x31d8), + PINGROUP(GMI_CS2_N, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31dc), + PINGROUP(GMI_CS3_N, GMI, RSVD1, NAND, GMI, GMI_ALT, RSVD, INPUT, 0x31e0), + PINGROUP(GMI_CS4_N, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31e4), + PINGROUP(GMI_CS6_N, GMI, NAND, NAND_ALT, GMI, SATA, RSVD, INPUT, 0x31e8), + PINGROUP(GMI_CS7_N, GMI, NAND, NAND_ALT, GMI, GMI_ALT, RSVD, INPUT, 0x31ec), + PINGROUP(GMI_AD0, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31f0), + PINGROUP(GMI_AD1, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31f4), + PINGROUP(GMI_AD2, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31f8), + PINGROUP(GMI_AD3, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31fc), + PINGROUP(GMI_AD4, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x3200), + PINGROUP(GMI_AD5, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x3204), + PINGROUP(GMI_AD6, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x3208), + PINGROUP(GMI_AD7, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x320c), + PINGROUP(GMI_AD8, GMI, PWM0, NAND, GMI, RSVD2, RSVD, INPUT, 0x3210), + PINGROUP(GMI_AD9, GMI, PWM1, NAND, GMI, RSVD2, RSVD, INPUT, 0x3214), + PINGROUP(GMI_AD10, GMI, PWM2, NAND, GMI, RSVD2, RSVD, INPUT, 0x3218), + PINGROUP(GMI_AD11, GMI, PWM3, NAND, GMI, RSVD2, RSVD, INPUT, 0x321c), + PINGROUP(GMI_AD12, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x3220), + PINGROUP(GMI_AD13, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x3224), + PINGROUP(GMI_AD14, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x3228), + PINGROUP(GMI_AD15, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x322c), + PINGROUP(GMI_A16, GMI, UARTD, SPI4, GMI, GMI_ALT, RSVD, INPUT, 0x3230), + PINGROUP(GMI_A17, GMI, UARTD, SPI4, GMI, INVALID, RSVD, INPUT, 0x3234), + PINGROUP(GMI_A18, GMI, UARTD, SPI4, GMI, INVALID, RSVD, INPUT, 0x3238), + PINGROUP(GMI_A19, GMI, UARTD, SPI4, GMI, RSVD3, RSVD, INPUT, 0x323c), + PINGROUP(GMI_WR_N, GMI, RSVD1, NAND, GMI, RSVD3, RSVD, INPUT, 0x3240), + PINGROUP(GMI_OE_N, GMI, RSVD1, NAND, GMI, RSVD3, RSVD, INPUT, 0x3244), + PINGROUP(GMI_DQS, GMI, RSVD1, NAND, GMI, RSVD3, RSVD, INPUT, 0x3248), + PINGROUP(GMI_RST_N, GMI, NAND, NAND_ALT, GMI, RSVD3, RSVD, INPUT, 0x324c), + PINGROUP(GEN2_I2C_SCL, GMI, I2C2, INVALID, GMI, RSVD3, RSVD, INPUT, 0x3250), + PINGROUP(GEN2_I2C_SDA, GMI, I2C2, INVALID, GMI, RSVD3, RSVD, INPUT, 0x3254), + PINGROUP(SDMMC4_CLK, SDMMC4, INVALID, NAND, GMI, SDIO4, RSVD, INPUT, 0x3258), + PINGROUP(SDMMC4_CMD, SDMMC4, I2C3, NAND, GMI, SDIO4, RSVD, INPUT, 0x325c), + PINGROUP(SDMMC4_DAT0, SDMMC4, UARTE, SPI3, GMI, SDIO4, RSVD, INPUT, 0x3260), + PINGROUP(SDMMC4_DAT1, SDMMC4, UARTE, SPI3, GMI, SDIO4, RSVD, INPUT, 0x3264), + PINGROUP(SDMMC4_DAT2, SDMMC4, UARTE, SPI3, GMI, SDIO4, RSVD, INPUT, 0x3268), + PINGROUP(SDMMC4_DAT3, SDMMC4, UARTE, SPI3, GMI, SDIO4, RSVD, INPUT, 0x326c), + PINGROUP(SDMMC4_DAT4, SDMMC4, I2C3, I2S4, GMI, SDIO4, RSVD, INPUT, 0x3270), + PINGROUP(SDMMC4_DAT5, SDMMC4, VGP3, I2S4, GMI, SDIO4, RSVD, INPUT, 0x3274), + PINGROUP(SDMMC4_DAT6, SDMMC4, VGP4, I2S4, GMI, SDIO4, RSVD, INPUT, 0x3278), + PINGROUP(SDMMC4_DAT7, SDMMC4, VGP5, I2S4, GMI, SDIO4, RSVD, INPUT, 0x327c), + PINGROUP(SDMMC4_RST_N, SDMMC4, VGP6, RSVD1, RSVD2, POPSDMMC4, RSVD, INPUT, 0x3280), + PINGROUP(CAM_MCLK, CAM, VI, INVALID, VI_ALT2, POPSDMMC4, RSVD, INPUT, 0x3284), + PINGROUP(GPIO_PCC1, CAM, I2S4, RSVD1, RSVD2, POPSDMMC4, RSVD, INPUT, 0x3288), + PINGROUP(GPIO_PBB0, CAM, I2S4, RSVD1, RSVD2, POPSDMMC4, RSVD, INPUT, 0x328c), + PINGROUP(CAM_I2C_SCL, CAM, INVALID, I2C3, RSVD2, POPSDMMC4, RSVD, INPUT, 0x3290), + PINGROUP(CAM_I2C_SDA, CAM, INVALID, I2C3, RSVD2, POPSDMMC4, RSVD, INPUT, 0x3294), + PINGROUP(GPIO_PBB3, CAM, VGP3, DISPLAYA, DISPLAYB, POPSDMMC4, RSVD, INPUT, 0x3298), + PINGROUP(GPIO_PBB4, CAM, VGP4, DISPLAYA, DISPLAYB, POPSDMMC4, RSVD, INPUT, 0x329c), + PINGROUP(GPIO_PBB5, CAM, VGP5, DISPLAYA, DISPLAYB, POPSDMMC4, RSVD, INPUT, 0x32a0), + PINGROUP(GPIO_PBB6, CAM, VGP6, DISPLAYA, DISPLAYB, POPSDMMC4, RSVD, INPUT, 0x32a4), + PINGROUP(GPIO_PBB7, CAM, I2S4, RSVD1, RSVD2, POPSDMMC4, RSVD, INPUT, 0x32a8), + PINGROUP(GPIO_PCC2, CAM, I2S4, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x32ac), + PINGROUP(JTAG_RTCK, SYS, RTCK, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x32b0), + PINGROUP(PWR_I2C_SCL, SYS, I2CPWR, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x32b4), + PINGROUP(PWR_I2C_SDA, SYS, I2CPWR, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x32b8), + PINGROUP(KB_ROW0, SYS, KBC, INVALID, RSVD2, RSVD3, RSVD, INPUT, 0x32bc), + PINGROUP(KB_ROW1, SYS, KBC, INVALID, RSVD2, RSVD3, RSVD, INPUT, 0x32c0), + PINGROUP(KB_ROW2, SYS, KBC, INVALID, RSVD2, RSVD3, RSVD, INPUT, 0x32c4), + PINGROUP(KB_ROW3, SYS, KBC, INVALID, RSVD2, INVALID, RSVD, INPUT, 0x32c8), + PINGROUP(KB_ROW4, SYS, KBC, INVALID, TRACE, RSVD3, RSVD, INPUT, 0x32cc), + PINGROUP(KB_ROW5, SYS, KBC, INVALID, TRACE, OWR, RSVD, INPUT, 0x32d0), + PINGROUP(KB_ROW6, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32d4), + PINGROUP(KB_ROW7, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32d8), + PINGROUP(KB_ROW8, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32dc), + PINGROUP(KB_ROW9, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32e0), + PINGROUP(KB_ROW10, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32e4), + PINGROUP(KB_ROW11, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32e8), + PINGROUP(KB_ROW12, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32ec), + PINGROUP(KB_ROW13, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32f0), + PINGROUP(KB_ROW14, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32f4), + PINGROUP(KB_ROW15, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32f8), + PINGROUP(KB_COL0, SYS, KBC, INVALID, TRACE, INVALID, RSVD, INPUT, 0x32fc), + PINGROUP(KB_COL1, SYS, KBC, INVALID, TRACE, INVALID, RSVD, INPUT, 0x3300), + PINGROUP(KB_COL2, SYS, KBC, INVALID, TRACE, RSVD, RSVD, INPUT, 0x3304), + PINGROUP(KB_COL3, SYS, KBC, INVALID, TRACE, RSVD, RSVD, INPUT, 0x3308), + PINGROUP(KB_COL4, SYS, KBC, INVALID, TRACE, RSVD, RSVD, INPUT, 0x330c), + PINGROUP(KB_COL5, SYS, KBC, INVALID, TRACE, RSVD, RSVD, INPUT, 0x3310), + PINGROUP(KB_COL6, SYS, KBC, INVALID, TRACE, INVALID, RSVD, INPUT, 0x3314), + PINGROUP(KB_COL7, SYS, KBC, INVALID, TRACE, INVALID, RSVD, INPUT, 0x3318), + PINGROUP(CLK_32K_OUT, SYS, BLINK, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x331c), + PINGROUP(SYS_CLK_REQ, SYS, SYSCLK, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x3320), + PINGROUP(CORE_PWR_REQ, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, INPUT, 0x3324), + PINGROUP(CPU_PWR_REQ, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, INPUT, 0x3328), + PINGROUP(PWR_INT_N, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, INPUT, 0x332c), + PINGROUP(CLK_32K_IN, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, INPUT, 0x3330), + PINGROUP(OWR, SYS, OWR, RSVD, RSVD, RSVD, RSVD, INPUT, 0x3334), + PINGROUP(DAP1_FS, AUDIO, I2S0, HDA, GMI, SDIO2, RSVD, INPUT, 0x3338), + PINGROUP(DAP1_DIN, AUDIO, I2S0, HDA, GMI, SDIO2, RSVD, INPUT, 0x333c), + PINGROUP(DAP1_DOUT, AUDIO, I2S0, HDA, GMI, SDIO2, RSVD, INPUT, 0x3340), + PINGROUP(DAP1_SCLK, AUDIO, I2S0, HDA, GMI, SDIO2, RSVD, INPUT, 0x3344), + PINGROUP(CLK1_REQ, AUDIO, DAP, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x3348), + PINGROUP(CLK1_OUT, AUDIO, EXTPERIPH1, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x334c), + PINGROUP(SPDIF_IN, AUDIO, SPDIF, HDA, INVALID, DAPSDMMC2, RSVD, INPUT, 0x3350), + PINGROUP(SPDIF_OUT, AUDIO, SPDIF, RSVD1, INVALID, DAPSDMMC2, RSVD, INPUT, 0x3354), + PINGROUP(DAP2_FS, AUDIO, I2S1, HDA, RSVD2, GMI, RSVD, INPUT, 0x3358), + PINGROUP(DAP2_DIN, AUDIO, I2S1, HDA, RSVD2, GMI, RSVD, INPUT, 0x335c), + PINGROUP(DAP2_DOUT, AUDIO, I2S1, HDA, RSVD2, GMI, RSVD, INPUT, 0x3360), + PINGROUP(DAP2_SCLK, AUDIO, I2S1, HDA, RSVD2, GMI, RSVD, INPUT, 0x3364), + PINGROUP(SPI2_MOSI, AUDIO, SPI6, SPI2, INVALID, GMI, RSVD, INPUT, 0x3368), + PINGROUP(SPI2_MISO, AUDIO, SPI6, SPI2, INVALID, GMI, RSVD, INPUT, 0x336c), + PINGROUP(SPI2_CS0_N, AUDIO, SPI6, SPI2, INVALID, GMI, RSVD, INPUT, 0x3370), + PINGROUP(SPI2_SCK, AUDIO, SPI6, SPI2, INVALID, GMI, RSVD, INPUT, 0x3374), + PINGROUP(SPI1_MOSI, AUDIO, SPI2, SPI1, INVALID, GMI, RSVD, INPUT, 0x3378), + PINGROUP(SPI1_SCK, AUDIO, SPI2, SPI1, INVALID, GMI, RSVD, INPUT, 0x337c), + PINGROUP(SPI1_CS0_N, AUDIO, SPI2, SPI1, INVALID, GMI, RSVD, INPUT, 0x3380), + PINGROUP(SPI1_MISO, AUDIO, INVALID, SPI1, INVALID, RSVD3, RSVD, INPUT, 0x3384), + PINGROUP(SPI2_CS1_N, AUDIO, INVALID, SPI2, INVALID, INVALID, RSVD, INPUT, 0x3388), + PINGROUP(SPI2_CS2_N, AUDIO, INVALID, SPI2, INVALID, INVALID, RSVD, INPUT, 0x338c), + PINGROUP(SDMMC3_CLK, SDMMC3, UARTA, PWM2, SDIO3, INVALID, RSVD, INPUT, 0x3390), + PINGROUP(SDMMC3_CMD, SDMMC3, UARTA, PWM3, SDIO3, INVALID, RSVD, INPUT, 0x3394), + PINGROUP(SDMMC3_DAT0, SDMMC3, RSVD, RSVD1, SDIO3, INVALID, RSVD, INPUT, 0x3398), + PINGROUP(SDMMC3_DAT1, SDMMC3, RSVD, RSVD1, SDIO3, INVALID, RSVD, INPUT, 0x339c), + PINGROUP(SDMMC3_DAT2, SDMMC3, RSVD, PWM1, SDIO3, INVALID, RSVD, INPUT, 0x33a0), + PINGROUP(SDMMC3_DAT3, SDMMC3, RSVD, PWM0, SDIO3, INVALID, RSVD, INPUT, 0x33a4), + PINGROUP(SDMMC3_DAT4, SDMMC3, PWM1, INVALID, SDIO3, INVALID, RSVD, INPUT, 0x33a8), + PINGROUP(SDMMC3_DAT5, SDMMC3, PWM0, INVALID, SDIO3, INVALID, RSVD, INPUT, 0x33ac), + PINGROUP(SDMMC3_DAT6, SDMMC3, SPDIF, INVALID, SDIO3, INVALID, RSVD, INPUT, 0x33b0), + PINGROUP(SDMMC3_DAT7, SDMMC3, SPDIF, INVALID, SDIO3, INVALID, RSVD, INPUT, 0x33b4), + PINGROUP(PEX_L0_PRSNT_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33b8), + PINGROUP(PEX_L0_RST_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33bc), + PINGROUP(PEX_L0_CLKREQ_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33c0), + PINGROUP(PEX_WAKE_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33c4), + PINGROUP(PEX_L1_PRSNT_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33c8), + PINGROUP(PEX_L1_RST_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33cc), + PINGROUP(PEX_L1_CLKREQ_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33d0), + PINGROUP(PEX_L2_PRSNT_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33d4), + PINGROUP(PEX_L2_RST_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33d8), + PINGROUP(PEX_L2_CLKREQ_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33dc), + PINGROUP(HDMI_CEC, SYS, CEC, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x33e0), +}; + +void __devinit tegra30_pinmux_init(const struct tegra_pingroup_desc **pg, + int *pg_max, const struct tegra_drive_pingroup_desc **pgdrive, + int *pgdrive_max) +{ + *pg = tegra_soc_pingroups; + *pg_max = TEGRA_MAX_PINGROUP; + *pgdrive = tegra_soc_drive_pingroups; + *pgdrive_max = TEGRA_MAX_DRIVE_PINGROUP; +} + diff --git a/arch/arm/mach-tegra/pinmux.c b/arch/arm/mach-tegra/pinmux.c index 1d201650d7a..ac35d2b7685 100644 --- a/arch/arm/mach-tegra/pinmux.c +++ b/arch/arm/mach-tegra/pinmux.c @@ -21,6 +21,7 @@ #include <linux/spinlock.h> #include <linux/io.h> #include <linux/platform_device.h> +#include <linux/of_device.h> #include <mach/iomap.h> #include <mach/pinmux.h> @@ -33,8 +34,10 @@ #define SLWR(reg) (((reg) >> 28) & 0x3) #define SLWF(reg) (((reg) >> 30) & 0x3) -static const struct tegra_pingroup_desc *const pingroups = tegra_soc_pingroups; -static const struct tegra_drive_pingroup_desc *const drive_pingroups = tegra_soc_drive_pingroups; +static const struct tegra_pingroup_desc *pingroups; +static const struct tegra_drive_pingroup_desc *drive_pingroups; +static int pingroup_max; +static int drive_max; static char *tegra_mux_names[TEGRA_MAX_MUX] = { [TEGRA_MUX_AHB_CLK] = "AHB_CLK", @@ -97,6 +100,49 @@ static char *tegra_mux_names[TEGRA_MAX_MUX] = { [TEGRA_MUX_VI] = "VI", [TEGRA_MUX_VI_SENSOR_CLK] = "VI_SENSOR_CLK", [TEGRA_MUX_XIO] = "XIO", + [TEGRA_MUX_BLINK] = "BLINK", + [TEGRA_MUX_CEC] = "CEC", + [TEGRA_MUX_CLK12] = "CLK12", + [TEGRA_MUX_DAP] = "DAP", + [TEGRA_MUX_DAPSDMMC2] = "DAPSDMMC2", + [TEGRA_MUX_DDR] = "DDR", + [TEGRA_MUX_DEV3] = "DEV3", + [TEGRA_MUX_DTV] = "DTV", + [TEGRA_MUX_VI_ALT1] = "VI_ALT1", + [TEGRA_MUX_VI_ALT2] = "VI_ALT2", + [TEGRA_MUX_VI_ALT3] = "VI_ALT3", + [TEGRA_MUX_EMC_DLL] = "EMC_DLL", + [TEGRA_MUX_EXTPERIPH1] = "EXTPERIPH1", + [TEGRA_MUX_EXTPERIPH2] = "EXTPERIPH2", + [TEGRA_MUX_EXTPERIPH3] = "EXTPERIPH3", + [TEGRA_MUX_GMI_ALT] = "GMI_ALT", + [TEGRA_MUX_HDA] = "HDA", + [TEGRA_MUX_HSI] = "HSI", + [TEGRA_MUX_I2C4] = "I2C4", + [TEGRA_MUX_I2C5] = "I2C5", + [TEGRA_MUX_I2CPWR] = "I2CPWR", + [TEGRA_MUX_I2S0] = "I2S0", + [TEGRA_MUX_I2S1] = "I2S1", + [TEGRA_MUX_I2S2] = "I2S2", + [TEGRA_MUX_I2S3] = "I2S3", + [TEGRA_MUX_I2S4] = "I2S4", + [TEGRA_MUX_NAND_ALT] = "NAND_ALT", + [TEGRA_MUX_POPSDIO4] = "POPSDIO4", + [TEGRA_MUX_POPSDMMC4] = "POPSDMMC4", + [TEGRA_MUX_PWM0] = "PWM0", + [TEGRA_MUX_PWM1] = "PWM2", + [TEGRA_MUX_PWM2] = "PWM2", + [TEGRA_MUX_PWM3] = "PWM3", + [TEGRA_MUX_SATA] = "SATA", + [TEGRA_MUX_SPI5] = "SPI5", + [TEGRA_MUX_SPI6] = "SPI6", + [TEGRA_MUX_SYSCLK] = "SYSCLK", + [TEGRA_MUX_VGP1] = "VGP1", + [TEGRA_MUX_VGP2] = "VGP2", + [TEGRA_MUX_VGP3] = "VGP3", + [TEGRA_MUX_VGP4] = "VGP4", + [TEGRA_MUX_VGP5] = "VGP5", + [TEGRA_MUX_VGP6] = "VGP6", [TEGRA_MUX_SAFE] = "<safe>", }; @@ -116,9 +162,9 @@ static const char *tegra_slew_names[TEGRA_MAX_SLEW] = { static DEFINE_SPINLOCK(mux_lock); -static const char *pingroup_name(enum tegra_pingroup pg) +static const char *pingroup_name(int pg) { - if (pg < 0 || pg >= TEGRA_MAX_PINGROUP) + if (pg < 0 || pg >= pingroup_max) return "<UNKNOWN>"; return pingroups[pg].name; @@ -189,10 +235,10 @@ static int tegra_pinmux_set_func(const struct tegra_pingroup_config *config) int i; unsigned long reg; unsigned long flags; - enum tegra_pingroup pg = config->pingroup; + int pg = config->pingroup; enum tegra_mux_func func = config->func; - if (pg < 0 || pg >= TEGRA_MAX_PINGROUP) + if (pg < 0 || pg >= pingroup_max) return -ERANGE; if (pingroups[pg].mux_reg < 0) @@ -230,13 +276,12 @@ static int tegra_pinmux_set_func(const struct tegra_pingroup_config *config) return 0; } -int tegra_pinmux_set_tristate(enum tegra_pingroup pg, - enum tegra_tristate tristate) +int tegra_pinmux_set_tristate(int pg, enum tegra_tristate tristate) { unsigned long reg; unsigned long flags; - if (pg < 0 || pg >= TEGRA_MAX_PINGROUP) + if (pg < 0 || pg >= pingroup_max) return -ERANGE; if (pingroups[pg].tri_reg < 0) @@ -255,13 +300,12 @@ int tegra_pinmux_set_tristate(enum tegra_pingroup pg, return 0; } -int tegra_pinmux_set_pullupdown(enum tegra_pingroup pg, - enum tegra_pullupdown pupd) +int tegra_pinmux_set_pullupdown(int pg, enum tegra_pullupdown pupd) { unsigned long reg; unsigned long flags; - if (pg < 0 || pg >= TEGRA_MAX_PINGROUP) + if (pg < 0 || pg >= pingroup_max) return -ERANGE; if (pingroups[pg].pupd_reg < 0) @@ -287,7 +331,7 @@ int tegra_pinmux_set_pullupdown(enum tegra_pingroup pg, static void tegra_pinmux_config_pingroup(const struct tegra_pingroup_config *config) { - enum tegra_pingroup pingroup = config->pingroup; + int pingroup = config->pingroup; enum tegra_mux_func func = config->func; enum tegra_pullupdown pupd = config->pupd; enum tegra_tristate tristate = config->tristate; @@ -323,9 +367,9 @@ void tegra_pinmux_config_table(const struct tegra_pingroup_config *config, int l tegra_pinmux_config_pingroup(&config[i]); } -static const char *drive_pinmux_name(enum tegra_drive_pingroup pg) +static const char *drive_pinmux_name(int pg) { - if (pg < 0 || pg >= TEGRA_MAX_DRIVE_PINGROUP) + if (pg < 0 || pg >= drive_max) return "<UNKNOWN>"; return drive_pingroups[pg].name; @@ -352,12 +396,11 @@ static const char *slew_name(unsigned long val) return tegra_slew_names[val]; } -static int tegra_drive_pinmux_set_hsm(enum tegra_drive_pingroup pg, - enum tegra_hsm hsm) +static int tegra_drive_pinmux_set_hsm(int pg, enum tegra_hsm hsm) { unsigned long flags; u32 reg; - if (pg < 0 || pg >= TEGRA_MAX_DRIVE_PINGROUP) + if (pg < 0 || pg >= drive_max) return -ERANGE; if (hsm != TEGRA_HSM_ENABLE && hsm != TEGRA_HSM_DISABLE) @@ -377,12 +420,11 @@ static int tegra_drive_pinmux_set_hsm(enum tegra_drive_pingroup pg, return 0; } -static int tegra_drive_pinmux_set_schmitt(enum tegra_drive_pingroup pg, - enum tegra_schmitt schmitt) +static int tegra_drive_pinmux_set_schmitt(int pg, enum tegra_schmitt schmitt) { unsigned long flags; u32 reg; - if (pg < 0 || pg >= TEGRA_MAX_DRIVE_PINGROUP) + if (pg < 0 || pg >= drive_max) return -ERANGE; if (schmitt != TEGRA_SCHMITT_ENABLE && schmitt != TEGRA_SCHMITT_DISABLE) @@ -402,12 +444,11 @@ static int tegra_drive_pinmux_set_schmitt(enum tegra_drive_pingroup pg, return 0; } -static int tegra_drive_pinmux_set_drive(enum tegra_drive_pingroup pg, - enum tegra_drive drive) +static int tegra_drive_pinmux_set_drive(int pg, enum tegra_drive drive) { unsigned long flags; u32 reg; - if (pg < 0 || pg >= TEGRA_MAX_DRIVE_PINGROUP) + if (pg < 0 || pg >= drive_max) return -ERANGE; if (drive < 0 || drive >= TEGRA_MAX_DRIVE) @@ -425,12 +466,12 @@ static int tegra_drive_pinmux_set_drive(enum tegra_drive_pingroup pg, return 0; } -static int tegra_drive_pinmux_set_pull_down(enum tegra_drive_pingroup pg, +static int tegra_drive_pinmux_set_pull_down(int pg, enum tegra_pull_strength pull_down) { unsigned long flags; u32 reg; - if (pg < 0 || pg >= TEGRA_MAX_DRIVE_PINGROUP) + if (pg < 0 || pg >= drive_max) return -ERANGE; if (pull_down < 0 || pull_down >= TEGRA_MAX_PULL) @@ -448,12 +489,12 @@ static int tegra_drive_pinmux_set_pull_down(enum tegra_drive_pingroup pg, return 0; } -static int tegra_drive_pinmux_set_pull_up(enum tegra_drive_pingroup pg, +static int tegra_drive_pinmux_set_pull_up(int pg, enum tegra_pull_strength pull_up) { unsigned long flags; u32 reg; - if (pg < 0 || pg >= TEGRA_MAX_DRIVE_PINGROUP) + if (pg < 0 || pg >= drive_max) return -ERANGE; if (pull_up < 0 || pull_up >= TEGRA_MAX_PULL) @@ -471,12 +512,12 @@ static int tegra_drive_pinmux_set_pull_up(enum tegra_drive_pingroup pg, return 0; } -static int tegra_drive_pinmux_set_slew_rising(enum tegra_drive_pingroup pg, +static int tegra_drive_pinmux_set_slew_rising(int pg, enum tegra_slew slew_rising) { unsigned long flags; u32 reg; - if (pg < 0 || pg >= TEGRA_MAX_DRIVE_PINGROUP) + if (pg < 0 || pg >= drive_max) return -ERANGE; if (slew_rising < 0 || slew_rising >= TEGRA_MAX_SLEW) @@ -494,12 +535,12 @@ static int tegra_drive_pinmux_set_slew_rising(enum tegra_drive_pingroup pg, return 0; } -static int tegra_drive_pinmux_set_slew_falling(enum tegra_drive_pingroup pg, +static int tegra_drive_pinmux_set_slew_falling(int pg, enum tegra_slew slew_falling) { unsigned long flags; u32 reg; - if (pg < 0 || pg >= TEGRA_MAX_DRIVE_PINGROUP) + if (pg < 0 || pg >= drive_max) return -ERANGE; if (slew_falling < 0 || slew_falling >= TEGRA_MAX_SLEW) @@ -517,7 +558,7 @@ static int tegra_drive_pinmux_set_slew_falling(enum tegra_drive_pingroup pg, return 0; } -static void tegra_drive_pinmux_config_pingroup(enum tegra_drive_pingroup pingroup, +static void tegra_drive_pinmux_config_pingroup(int pingroup, enum tegra_hsm hsm, enum tegra_schmitt schmitt, enum tegra_drive drive, @@ -596,7 +637,7 @@ void tegra_pinmux_set_safe_pinmux_table(const struct tegra_pingroup_config *conf for (i = 0; i < len; i++) { int err; c = config[i]; - if (c.pingroup < 0 || c.pingroup >= TEGRA_MAX_PINGROUP) { + if (c.pingroup < 0 || c.pingroup >= pingroup_max) { WARN_ON(1); continue; } @@ -617,7 +658,7 @@ void tegra_pinmux_config_pinmux_table(const struct tegra_pingroup_config *config for (i = 0; i < len; i++) { int err; if (config[i].pingroup < 0 || - config[i].pingroup >= TEGRA_MAX_PINGROUP) { + config[i].pingroup >= pingroup_max) { WARN_ON(1); continue; } @@ -635,7 +676,7 @@ void tegra_pinmux_config_tristate_table(const struct tegra_pingroup_config *conf { int i; int err; - enum tegra_pingroup pingroup; + int pingroup; for (i = 0; i < len; i++) { pingroup = config[i].pingroup; @@ -654,7 +695,7 @@ void tegra_pinmux_config_pullupdown_table(const struct tegra_pingroup_config *co { int i; int err; - enum tegra_pingroup pingroup; + int pingroup; for (i = 0; i < len; i++) { pingroup = config[i].pingroup; @@ -668,11 +709,36 @@ void tegra_pinmux_config_pullupdown_table(const struct tegra_pingroup_config *co } } +static struct of_device_id tegra_pinmux_of_match[] __devinitdata = { +#ifdef CONFIG_ARCH_TEGRA_2x_SOC + { .compatible = "nvidia,tegra20-pinmux", tegra20_pinmux_init }, +#endif +#ifdef CONFIG_ARCH_TEGRA_3x_SOC + { .compatible = "nvidia,tegra30-pinmux", tegra30_pinmux_init }, +#endif + { }, +}; + static int __devinit tegra_pinmux_probe(struct platform_device *pdev) { struct resource *res; int i; int config_bad = 0; + const struct of_device_id *match; + + match = of_match_device(tegra_pinmux_of_match, &pdev->dev); + + if (match) + ((pinmux_init)(match->data))(&pingroups, &pingroup_max, + &drive_pingroups, &drive_max); +#ifdef CONFIG_ARCH_TEGRA_2x_SOC + else + /* no device tree available, so we must be on tegra20 */ + tegra20_pinmux_init(&pingroups, &pingroup_max, + &drive_pingroups, &drive_max); +#else + pr_warn("non Tegra20 platform requires pinmux devicetree node\n"); +#endif for (i = 0; ; i++) { res = platform_get_resource(pdev, IORESOURCE_MEM, i); @@ -681,7 +747,7 @@ static int __devinit tegra_pinmux_probe(struct platform_device *pdev) } nbanks = i; - for (i = 0; i < TEGRA_MAX_PINGROUP; i++) { + for (i = 0; i < pingroup_max; i++) { if (pingroups[i].tri_bank >= nbanks) { dev_err(&pdev->dev, "pingroup %d: bad tri_bank\n", i); config_bad = 1; @@ -698,7 +764,7 @@ static int __devinit tegra_pinmux_probe(struct platform_device *pdev) } } - for (i = 0; i < TEGRA_MAX_DRIVE_PINGROUP; i++) { + for (i = 0; i < drive_max; i++) { if (drive_pingroups[i].reg_bank >= nbanks) { dev_err(&pdev->dev, "drive pingroup %d: bad reg_bank\n", i); @@ -741,11 +807,6 @@ static int __devinit tegra_pinmux_probe(struct platform_device *pdev) return 0; } -static struct of_device_id tegra_pinmux_of_match[] __devinitdata = { - { .compatible = "nvidia,tegra20-pinmux", }, - { }, -}; - static struct platform_driver tegra_pinmux_driver = { .driver = { .name = "tegra-pinmux", @@ -779,7 +840,7 @@ static int dbg_pinmux_show(struct seq_file *s, void *unused) int i; int len; - for (i = 0; i < TEGRA_MAX_PINGROUP; i++) { + for (i = 0; i < pingroup_max; i++) { unsigned long reg; unsigned long tri; unsigned long mux; @@ -850,7 +911,7 @@ static int dbg_drive_pinmux_show(struct seq_file *s, void *unused) int i; int len; - for (i = 0; i < TEGRA_MAX_DRIVE_PINGROUP; i++) { + for (i = 0; i < drive_max; i++) { u32 reg; seq_printf(s, "\t{TEGRA_DRIVE_PINGROUP_%s", diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c index 371869d8ea0..ff9e6b6c046 100644 --- a/arch/arm/mach-tegra/tegra2_clocks.c +++ b/arch/arm/mach-tegra/tegra2_clocks.c @@ -174,7 +174,7 @@ static int tegra_periph_clk_enable_refcount[3 * 32]; #define pmc_readl(reg) \ __raw_readl(reg_pmc_base + (reg)) -unsigned long clk_measure_input_freq(void) +static unsigned long clk_measure_input_freq(void) { u32 clock_autodetect; clk_writel(OSC_FREQ_DET_TRIG | 1, OSC_FREQ_DET); @@ -278,18 +278,6 @@ static struct clk_ops tegra_clk_m_ops = { .disable = tegra2_clk_m_disable, }; -void tegra2_periph_reset_assert(struct clk *c) -{ - BUG_ON(!c->ops->reset); - c->ops->reset(c, true); -} - -void tegra2_periph_reset_deassert(struct clk *c) -{ - BUG_ON(!c->ops->reset); - c->ops->reset(c, false); -} - /* super clock functions */ /* "super clocks" on tegra have two-stage muxes and a clock skipping * super divider. We will ignore the clock skipping divider, since we @@ -1132,6 +1120,9 @@ static struct clk_ops tegra_periph_clk_ops = { void tegra2_sdmmc_tap_delay(struct clk *c, int delay) { u32 reg; + unsigned long flags; + + spin_lock_irqsave(&c->spinlock, flags); delay = clamp(delay, 0, 15); reg = clk_readl(c->reg); @@ -1139,6 +1130,8 @@ void tegra2_sdmmc_tap_delay(struct clk *c, int delay) reg |= SDMMC_CLK_INT_FB_SEL; reg |= delay << SDMMC_CLK_INT_FB_DLY_SHIFT; clk_writel(reg, c->reg); + + spin_unlock_irqrestore(&c->spinlock, flags); } /* External memory controller clock ops */ diff --git a/arch/arm/mach-tegra/timer.c b/arch/arm/mach-tegra/timer.c index 732c724008b..1d1acda4f3e 100644 --- a/arch/arm/mach-tegra/timer.c +++ b/arch/arm/mach-tegra/timer.c @@ -165,20 +165,28 @@ static struct irqaction tegra_timer_irq = { static void __init tegra_init_timer(void) { struct clk *clk; - unsigned long rate = clk_measure_input_freq(); + unsigned long rate; int ret; clk = clk_get_sys("timer", NULL); - BUG_ON(IS_ERR(clk)); - clk_enable(clk); + if (IS_ERR(clk)) { + pr_warn("Unable to get timer clock." + " Assuming 12Mhz input clock.\n"); + rate = 12000000; + } else { + clk_enable(clk); + rate = clk_get_rate(clk); + } /* * rtc registers are used by read_persistent_clock, keep the rtc clock * enabled */ clk = clk_get_sys("rtc-tegra", NULL); - BUG_ON(IS_ERR(clk)); - clk_enable(clk); + if (IS_ERR(clk)) + pr_warn("Unable to get rtc-tegra clock\n"); + else + clk_enable(clk); #ifdef CONFIG_HAVE_ARM_TWD twd_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x600); diff --git a/arch/arm/mach-u300/Kconfig b/arch/arm/mach-u300/Kconfig index 1cbcd4fc1e1..54d8f34fdee 100644 --- a/arch/arm/mach-u300/Kconfig +++ b/arch/arm/mach-u300/Kconfig @@ -7,8 +7,8 @@ comment "ST-Ericsson Mobile Platform Products" config MACH_U300 bool "U300" select PINCTRL - select PINMUX_U300 - select GPIO_U300 + select PINCTRL_U300 + select PINCTRL_COH901 comment "ST-Ericsson U300/U330/U335/U365 Feature Selections" diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c index 697930761b3..b4c6926a700 100644 --- a/arch/arm/mach-u300/core.c +++ b/arch/arm/mach-u300/core.c @@ -1605,15 +1605,15 @@ static struct platform_device pinmux_device = { }; /* Pinmux settings */ -static struct pinmux_map u300_pinmux_map[] = { +static struct pinmux_map __initdata u300_pinmux_map[] = { /* anonymous maps for chip power and EMIFs */ - PINMUX_MAP_PRIMARY_SYS_HOG("POWER", "power"), - PINMUX_MAP_PRIMARY_SYS_HOG("EMIF0", "emif0"), - PINMUX_MAP_PRIMARY_SYS_HOG("EMIF1", "emif1"), + PINMUX_MAP_SYS_HOG("POWER", "pinmux-u300", "power"), + PINMUX_MAP_SYS_HOG("EMIF0", "pinmux-u300", "emif0"), + PINMUX_MAP_SYS_HOG("EMIF1", "pinmux-u300", "emif1"), /* per-device maps for MMC/SD, SPI and UART */ - PINMUX_MAP_PRIMARY("MMCSD", "mmc0", "mmci"), - PINMUX_MAP_PRIMARY("SPI", "spi0", "pl022"), - PINMUX_MAP_PRIMARY("UART0", "uart0", "uart0"), + PINMUX_MAP("MMCSD", "pinmux-u300", "mmc0", "mmci"), + PINMUX_MAP("SPI", "pinmux-u300", "spi0", "pl022"), + PINMUX_MAP("UART0", "pinmux-u300", "uart0", "uart0"), }; struct u300_mux_hog { diff --git a/arch/arm/mach-u300/include/mach/gpio-u300.h b/arch/arm/mach-u300/include/mach/gpio-u300.h index 0c2b2021951..bf4c7935aec 100644 --- a/arch/arm/mach-u300/include/mach/gpio-u300.h +++ b/arch/arm/mach-u300/include/mach/gpio-u300.h @@ -9,121 +9,6 @@ #ifndef __MACH_U300_GPIO_U300_H #define __MACH_U300_GPIO_U300_H -/* - * Individual pin assignments for the B26/S26. Notice that the - * actual usage of these pins depends on the PAD MUX settings, that - * is why the same number can potentially appear several times. - * In the reference design each pin is only used for one purpose. - * These were determined by inspecting the B26/S26 schematic: - * 2/1911-ROA 128 1603 - */ -#ifdef CONFIG_MACH_U300_BS2X -#define U300_GPIO_PIN_UART_RX 0 -#define U300_GPIO_PIN_UART_TX 1 -#define U300_GPIO_PIN_GPIO02 2 /* Unrouted */ -#define U300_GPIO_PIN_GPIO03 3 /* Unrouted */ -#define U300_GPIO_PIN_CAM_SLEEP 4 -#define U300_GPIO_PIN_CAM_REG_EN 5 -#define U300_GPIO_PIN_GPIO06 6 /* Unrouted */ -#define U300_GPIO_PIN_GPIO07 7 /* Unrouted */ - -#define U300_GPIO_PIN_GPIO08 8 /* Service point SP2321 */ -#define U300_GPIO_PIN_GPIO09 9 /* Service point SP2322 */ -#define U300_GPIO_PIN_PHFSENSE 10 /* Headphone jack sensing */ -#define U300_GPIO_PIN_MMC_CLKRET 11 /* Clock return from MMC/SD card */ -#define U300_GPIO_PIN_MMC_CD 12 /* MMC Card insertion detection */ -#define U300_GPIO_PIN_FLIPSENSE 13 /* Mechanical flip sensing */ -#define U300_GPIO_PIN_GPIO14 14 /* DSP JTAG Port RTCK */ -#define U300_GPIO_PIN_GPIO15 15 /* Unrouted */ - -#define U300_GPIO_PIN_GPIO16 16 /* Unrouted */ -#define U300_GPIO_PIN_GPIO17 17 /* Unrouted */ -#define U300_GPIO_PIN_GPIO18 18 /* Unrouted */ -#define U300_GPIO_PIN_GPIO19 19 /* Unrouted */ -#define U300_GPIO_PIN_GPIO20 20 /* Unrouted */ -#define U300_GPIO_PIN_GPIO21 21 /* Unrouted */ -#define U300_GPIO_PIN_GPIO22 22 /* Unrouted */ -#define U300_GPIO_PIN_GPIO23 23 /* Unrouted */ -#endif - -/* - * Individual pin assignments for the B330/S330 and B365/S365. - * Notice that the actual usage of these pins depends on the - * PAD MUX settings, that is why the same number can potentially - * appear several times. In the reference design each pin is only - * used for one purpose. These were determined by inspecting the - * S365 schematic. - */ -#if defined(CONFIG_MACH_U300_BS330) || defined(CONFIG_MACH_U300_BS365) || \ - defined(CONFIG_MACH_U300_BS335) -#define U300_GPIO_PIN_UART_RX 0 -#define U300_GPIO_PIN_UART_TX 1 -#define U300_GPIO_PIN_UART_CTS 2 -#define U300_GPIO_PIN_UART_RTS 3 -#define U300_GPIO_PIN_CAM_MAIN_STANDBY 4 /* Camera MAIN standby */ -#define U300_GPIO_PIN_GPIO05 5 /* Unrouted */ -#define U300_GPIO_PIN_MS_CD 6 /* Memory Stick Card insertion */ -#define U300_GPIO_PIN_GPIO07 7 /* Test point TP2430 */ - -#define U300_GPIO_PIN_GPIO08 8 /* Test point TP2437 */ -#define U300_GPIO_PIN_GPIO09 9 /* Test point TP2431 */ -#define U300_GPIO_PIN_GPIO10 10 /* Test point TP2432 */ -#define U300_GPIO_PIN_MMC_CLKRET 11 /* Clock return from MMC/SD card */ -#define U300_GPIO_PIN_MMC_CD 12 /* MMC Card insertion detection */ -#define U300_GPIO_PIN_CAM_SUB_STANDBY 13 /* Camera SUB standby */ -#define U300_GPIO_PIN_GPIO14 14 /* Test point TP2436 */ -#define U300_GPIO_PIN_GPIO15 15 /* Unrouted */ - -#define U300_GPIO_PIN_GPIO16 16 /* Test point TP2438 */ -#define U300_GPIO_PIN_PHFSENSE 17 /* Headphone jack sensing */ -#define U300_GPIO_PIN_GPIO18 18 /* Test point TP2439 */ -#define U300_GPIO_PIN_GPIO19 19 /* Routed somewhere */ -#define U300_GPIO_PIN_GPIO20 20 /* Unrouted */ -#define U300_GPIO_PIN_GPIO21 21 /* Unrouted */ -#define U300_GPIO_PIN_GPIO22 22 /* Unrouted */ -#define U300_GPIO_PIN_GPIO23 23 /* Unrouted */ - -#define U300_GPIO_PIN_GPIO24 24 /* Unrouted */ -#define U300_GPIO_PIN_GPIO25 25 /* Unrouted */ -#define U300_GPIO_PIN_GPIO26 26 /* Unrouted */ -#define U300_GPIO_PIN_GPIO27 27 /* Unrouted */ -#define U300_GPIO_PIN_GPIO28 28 /* Unrouted */ -#define U300_GPIO_PIN_GPIO29 29 /* Unrouted */ -#define U300_GPIO_PIN_GPIO30 30 /* Unrouted */ -#define U300_GPIO_PIN_GPIO31 31 /* Unrouted */ - -#define U300_GPIO_PIN_GPIO32 32 /* Unrouted */ -#define U300_GPIO_PIN_GPIO33 33 /* Unrouted */ -#define U300_GPIO_PIN_GPIO34 34 /* Unrouted */ -#define U300_GPIO_PIN_GPIO35 35 /* Unrouted */ -#define U300_GPIO_PIN_GPIO36 36 /* Unrouted */ -#define U300_GPIO_PIN_GPIO37 37 /* Unrouted */ -#define U300_GPIO_PIN_GPIO38 38 /* Unrouted */ -#define U300_GPIO_PIN_GPIO39 39 /* Unrouted */ - -#ifdef CONFIG_MACH_U300_BS335 - -#define U300_GPIO_PIN_GPIO40 40 /* Unrouted */ -#define U300_GPIO_PIN_GPIO41 41 /* Unrouted */ -#define U300_GPIO_PIN_GPIO42 42 /* Unrouted */ -#define U300_GPIO_PIN_GPIO43 43 /* Unrouted */ -#define U300_GPIO_PIN_GPIO44 44 /* Unrouted */ -#define U300_GPIO_PIN_GPIO45 45 /* Unrouted */ -#define U300_GPIO_PIN_GPIO46 46 /* Unrouted */ -#define U300_GPIO_PIN_GPIO47 47 /* Unrouted */ - -#define U300_GPIO_PIN_GPIO48 48 /* Unrouted */ -#define U300_GPIO_PIN_GPIO49 49 /* Unrouted */ -#define U300_GPIO_PIN_GPIO50 50 /* Unrouted */ -#define U300_GPIO_PIN_GPIO51 51 /* Unrouted */ -#define U300_GPIO_PIN_GPIO52 52 /* Unrouted */ -#define U300_GPIO_PIN_GPIO53 53 /* Unrouted */ -#define U300_GPIO_PIN_GPIO54 54 /* Unrouted */ -#define U300_GPIO_PIN_GPIO55 55 /* Unrouted */ -#endif - -#endif - /** * enum u300_gpio_variant - the type of U300 GPIO employed */ diff --git a/arch/arm/mach-u300/include/mach/irqs.h b/arch/arm/mach-u300/include/mach/irqs.h index db3fbfa1d6e..ee78a26707e 100644 --- a/arch/arm/mach-u300/include/mach/irqs.h +++ b/arch/arm/mach-u300/include/mach/irqs.h @@ -110,7 +110,7 @@ #endif /* Maximum 8*7 GPIO lines */ -#ifdef CONFIG_GPIO_U300 +#ifdef CONFIG_PINCTRL_COH901 #define IRQ_U300_GPIO_BASE (U300_VIC_IRQS_END) #define IRQ_U300_GPIO_END (IRQ_U300_GPIO_BASE + 56) #else diff --git a/arch/arm/mach-u300/include/mach/memory.h b/arch/arm/mach-u300/include/mach/memory.h deleted file mode 100644 index c808f347a08..00000000000 --- a/arch/arm/mach-u300/include/mach/memory.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * - * arch/arm/mach-u300/include/mach/memory.h - * - * - * Copyright (C) 2007-2009 ST-Ericsson AB - * License terms: GNU General Public License (GPL) version 2 - * Memory virtual/physical mapping constants. - * Author: Linus Walleij <linus.walleij@stericsson.com> - * Author: Jonas Aaberg <jonas.aberg@stericsson.com> - */ - -#ifndef __MACH_MEMORY_H -#define __MACH_MEMORY_H - -#define PLAT_PHYS_OFFSET UL(0x48000000) -#define BOOT_PARAMS_OFFSET 0x100 - -#endif diff --git a/arch/arm/mach-u300/mmc.c b/arch/arm/mach-u300/mmc.c index 4d482aacc27..05abd6ad9fa 100644 --- a/arch/arm/mach-u300/mmc.c +++ b/arch/arm/mach-u300/mmc.c @@ -18,8 +18,8 @@ #include <linux/slab.h> #include <mach/coh901318.h> #include <mach/dma_channels.h> -#include <mach/gpio-u300.h> +#include "u300-gpio.h" #include "mmc.h" static struct mmci_platform_data mmc0_plat_data = { diff --git a/arch/arm/mach-u300/u300-gpio.h b/arch/arm/mach-u300/u300-gpio.h new file mode 100644 index 00000000000..847dc25300c --- /dev/null +++ b/arch/arm/mach-u300/u300-gpio.h @@ -0,0 +1,114 @@ +/* + * Individual pin assignments for the B26/S26. Notice that the + * actual usage of these pins depends on the PAD MUX settings, that + * is why the same number can potentially appear several times. + * In the reference design each pin is only used for one purpose. + * These were determined by inspecting the B26/S26 schematic: + * 2/1911-ROA 128 1603 + */ +#ifdef CONFIG_MACH_U300_BS2X +#define U300_GPIO_PIN_UART_RX 0 +#define U300_GPIO_PIN_UART_TX 1 +#define U300_GPIO_PIN_GPIO02 2 /* Unrouted */ +#define U300_GPIO_PIN_GPIO03 3 /* Unrouted */ +#define U300_GPIO_PIN_CAM_SLEEP 4 +#define U300_GPIO_PIN_CAM_REG_EN 5 +#define U300_GPIO_PIN_GPIO06 6 /* Unrouted */ +#define U300_GPIO_PIN_GPIO07 7 /* Unrouted */ + +#define U300_GPIO_PIN_GPIO08 8 /* Service point SP2321 */ +#define U300_GPIO_PIN_GPIO09 9 /* Service point SP2322 */ +#define U300_GPIO_PIN_PHFSENSE 10 /* Headphone jack sensing */ +#define U300_GPIO_PIN_MMC_CLKRET 11 /* Clock return from MMC/SD card */ +#define U300_GPIO_PIN_MMC_CD 12 /* MMC Card insertion detection */ +#define U300_GPIO_PIN_FLIPSENSE 13 /* Mechanical flip sensing */ +#define U300_GPIO_PIN_GPIO14 14 /* DSP JTAG Port RTCK */ +#define U300_GPIO_PIN_GPIO15 15 /* Unrouted */ + +#define U300_GPIO_PIN_GPIO16 16 /* Unrouted */ +#define U300_GPIO_PIN_GPIO17 17 /* Unrouted */ +#define U300_GPIO_PIN_GPIO18 18 /* Unrouted */ +#define U300_GPIO_PIN_GPIO19 19 /* Unrouted */ +#define U300_GPIO_PIN_GPIO20 20 /* Unrouted */ +#define U300_GPIO_PIN_GPIO21 21 /* Unrouted */ +#define U300_GPIO_PIN_GPIO22 22 /* Unrouted */ +#define U300_GPIO_PIN_GPIO23 23 /* Unrouted */ +#endif + +/* + * Individual pin assignments for the B330/S330 and B365/S365. + * Notice that the actual usage of these pins depends on the + * PAD MUX settings, that is why the same number can potentially + * appear several times. In the reference design each pin is only + * used for one purpose. These were determined by inspecting the + * S365 schematic. + */ +#if defined(CONFIG_MACH_U300_BS330) || defined(CONFIG_MACH_U300_BS365) || \ + defined(CONFIG_MACH_U300_BS335) +#define U300_GPIO_PIN_UART_RX 0 +#define U300_GPIO_PIN_UART_TX 1 +#define U300_GPIO_PIN_UART_CTS 2 +#define U300_GPIO_PIN_UART_RTS 3 +#define U300_GPIO_PIN_CAM_MAIN_STANDBY 4 /* Camera MAIN standby */ +#define U300_GPIO_PIN_GPIO05 5 /* Unrouted */ +#define U300_GPIO_PIN_MS_CD 6 /* Memory Stick Card insertion */ +#define U300_GPIO_PIN_GPIO07 7 /* Test point TP2430 */ + +#define U300_GPIO_PIN_GPIO08 8 /* Test point TP2437 */ +#define U300_GPIO_PIN_GPIO09 9 /* Test point TP2431 */ +#define U300_GPIO_PIN_GPIO10 10 /* Test point TP2432 */ +#define U300_GPIO_PIN_MMC_CLKRET 11 /* Clock return from MMC/SD card */ +#define U300_GPIO_PIN_MMC_CD 12 /* MMC Card insertion detection */ +#define U300_GPIO_PIN_CAM_SUB_STANDBY 13 /* Camera SUB standby */ +#define U300_GPIO_PIN_GPIO14 14 /* Test point TP2436 */ +#define U300_GPIO_PIN_GPIO15 15 /* Unrouted */ + +#define U300_GPIO_PIN_GPIO16 16 /* Test point TP2438 */ +#define U300_GPIO_PIN_PHFSENSE 17 /* Headphone jack sensing */ +#define U300_GPIO_PIN_GPIO18 18 /* Test point TP2439 */ +#define U300_GPIO_PIN_GPIO19 19 /* Routed somewhere */ +#define U300_GPIO_PIN_GPIO20 20 /* Unrouted */ +#define U300_GPIO_PIN_GPIO21 21 /* Unrouted */ +#define U300_GPIO_PIN_GPIO22 22 /* Unrouted */ +#define U300_GPIO_PIN_GPIO23 23 /* Unrouted */ + +#define U300_GPIO_PIN_GPIO24 24 /* Unrouted */ +#define U300_GPIO_PIN_GPIO25 25 /* Unrouted */ +#define U300_GPIO_PIN_GPIO26 26 /* Unrouted */ +#define U300_GPIO_PIN_GPIO27 27 /* Unrouted */ +#define U300_GPIO_PIN_GPIO28 28 /* Unrouted */ +#define U300_GPIO_PIN_GPIO29 29 /* Unrouted */ +#define U300_GPIO_PIN_GPIO30 30 /* Unrouted */ +#define U300_GPIO_PIN_GPIO31 31 /* Unrouted */ + +#define U300_GPIO_PIN_GPIO32 32 /* Unrouted */ +#define U300_GPIO_PIN_GPIO33 33 /* Unrouted */ +#define U300_GPIO_PIN_GPIO34 34 /* Unrouted */ +#define U300_GPIO_PIN_GPIO35 35 /* Unrouted */ +#define U300_GPIO_PIN_GPIO36 36 /* Unrouted */ +#define U300_GPIO_PIN_GPIO37 37 /* Unrouted */ +#define U300_GPIO_PIN_GPIO38 38 /* Unrouted */ +#define U300_GPIO_PIN_GPIO39 39 /* Unrouted */ + +#ifdef CONFIG_MACH_U300_BS335 + +#define U300_GPIO_PIN_GPIO40 40 /* Unrouted */ +#define U300_GPIO_PIN_GPIO41 41 /* Unrouted */ +#define U300_GPIO_PIN_GPIO42 42 /* Unrouted */ +#define U300_GPIO_PIN_GPIO43 43 /* Unrouted */ +#define U300_GPIO_PIN_GPIO44 44 /* Unrouted */ +#define U300_GPIO_PIN_GPIO45 45 /* Unrouted */ +#define U300_GPIO_PIN_GPIO46 46 /* Unrouted */ +#define U300_GPIO_PIN_GPIO47 47 /* Unrouted */ + +#define U300_GPIO_PIN_GPIO48 48 /* Unrouted */ +#define U300_GPIO_PIN_GPIO49 49 /* Unrouted */ +#define U300_GPIO_PIN_GPIO50 50 /* Unrouted */ +#define U300_GPIO_PIN_GPIO51 51 /* Unrouted */ +#define U300_GPIO_PIN_GPIO52 52 /* Unrouted */ +#define U300_GPIO_PIN_GPIO53 53 /* Unrouted */ +#define U300_GPIO_PIN_GPIO54 54 /* Unrouted */ +#define U300_GPIO_PIN_GPIO55 55 /* Unrouted */ +#endif + +#endif diff --git a/arch/arm/mach-u300/u300.c b/arch/arm/mach-u300/u300.c index def45bda293..f30c69d91d9 100644 --- a/arch/arm/mach-u300/u300.c +++ b/arch/arm/mach-u300/u300.c @@ -47,7 +47,7 @@ static void __init u300_init_machine(void) MACHINE_START(U300, MACH_U300_STRING) /* Maintainer: Linus Walleij <linus.walleij@stericsson.com> */ - .atag_offset = BOOT_PARAMS_OFFSET, + .atag_offset = 0x100, .map_io = u300_map_io, .init_irq = u300_init_irq, .handle_irq = vic_handle_irq, diff --git a/arch/arm/mach-ux500/board-mop500-sdi.c b/arch/arm/mach-ux500/board-mop500-sdi.c index 6826faeecc6..23be34b3bb6 100644 --- a/arch/arm/mach-ux500/board-mop500-sdi.c +++ b/arch/arm/mach-ux500/board-mop500-sdi.c @@ -22,6 +22,12 @@ #include "ste-dma40-db8500.h" /* + * v2 has a new version of this block that need to be forced, the number found + * in hardware is incorrect + */ +#define U8500_SDI_V2_PERIPHID 0x10480180 + +/* * SDI 0 (MicroSD slot) */ @@ -117,10 +123,7 @@ static void sdi0_configure(void) gpio_direction_output(sdi0_en, 1); /* Add the device, force v2 to subrevision 1 */ - if (cpu_is_u8500v2()) - db8500_add_sdi0(&mop500_sdi0_data, 0x10480180); - else - db8500_add_sdi0(&mop500_sdi0_data, 0); + db8500_add_sdi0(&mop500_sdi0_data, U8500_SDI_V2_PERIPHID); } void mop500_sdi_tc35892_init(void) @@ -132,6 +135,42 @@ void mop500_sdi_tc35892_init(void) } /* + * SDI1 (SDIO WLAN) + */ +#ifdef CONFIG_STE_DMA40 +static struct stedma40_chan_cfg sdi1_dma_cfg_rx = { + .mode = STEDMA40_MODE_LOGICAL, + .dir = STEDMA40_PERIPH_TO_MEM, + .src_dev_type = DB8500_DMA_DEV32_SD_MM1_RX, + .dst_dev_type = STEDMA40_DEV_DST_MEMORY, + .src_info.data_width = STEDMA40_WORD_WIDTH, + .dst_info.data_width = STEDMA40_WORD_WIDTH, +}; + +static struct stedma40_chan_cfg sdi1_dma_cfg_tx = { + .mode = STEDMA40_MODE_LOGICAL, + .dir = STEDMA40_MEM_TO_PERIPH, + .src_dev_type = STEDMA40_DEV_SRC_MEMORY, + .dst_dev_type = DB8500_DMA_DEV32_SD_MM1_TX, + .src_info.data_width = STEDMA40_WORD_WIDTH, + .dst_info.data_width = STEDMA40_WORD_WIDTH, +}; +#endif + +static struct mmci_platform_data mop500_sdi1_data = { + .ocr_mask = MMC_VDD_29_30, + .f_max = 50000000, + .capabilities = MMC_CAP_4_BIT_DATA, + .gpio_cd = -1, + .gpio_wp = -1, +#ifdef CONFIG_STE_DMA40 + .dma_filter = stedma40_filter, + .dma_rx_param = &sdi1_dma_cfg_rx, + .dma_tx_param = &sdi1_dma_cfg_tx, +#endif +}; + +/* * SDI 2 (POP eMMC, not on DB8500ed) */ @@ -158,7 +197,8 @@ static struct stedma40_chan_cfg mop500_sdi2_dma_cfg_tx = { static struct mmci_platform_data mop500_sdi2_data = { .ocr_mask = MMC_VDD_165_195, .f_max = 50000000, - .capabilities = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, + .capabilities = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA | + MMC_CAP_MMC_HIGHSPEED, .gpio_cd = -1, .gpio_wp = -1, #ifdef CONFIG_STE_DMA40 @@ -208,20 +248,10 @@ static struct mmci_platform_data mop500_sdi4_data = { void __init mop500_sdi_init(void) { - u32 periphid = 0; - - /* v2 has a new version of this block that need to be forced */ - if (cpu_is_u8500v2()) - periphid = 0x10480180; - /* PoP:ed eMMC on top of DB8500 v1.0 has problems with high speed */ - if (!cpu_is_u8500v10()) - mop500_sdi2_data.capabilities |= MMC_CAP_MMC_HIGHSPEED; - - db8500_add_sdi2(&mop500_sdi2_data, periphid); - + /* PoP:ed eMMC */ + db8500_add_sdi2(&mop500_sdi2_data, U8500_SDI_V2_PERIPHID); /* On-board eMMC */ - db8500_add_sdi4(&mop500_sdi4_data, periphid); - + db8500_add_sdi4(&mop500_sdi4_data, U8500_SDI_V2_PERIPHID); /* * On boards with the TC35892 GPIO expander, sdi0 will finally * be added when the TC35892 initializes and calls @@ -231,13 +261,9 @@ void __init mop500_sdi_init(void) void __init snowball_sdi_init(void) { - u32 periphid = 0x10480180; - - mop500_sdi2_data.capabilities |= MMC_CAP_MMC_HIGHSPEED; - /* On-board eMMC */ - db8500_add_sdi4(&mop500_sdi4_data, periphid); - + db8500_add_sdi4(&mop500_sdi4_data, U8500_SDI_V2_PERIPHID); + /* External Micro SD slot */ mop500_sdi0_data.gpio_cd = SNOWBALL_SDMMC_CD_GPIO; mop500_sdi0_data.cd_invert = true; sdi0_en = SNOWBALL_SDMMC_EN_GPIO; @@ -247,17 +273,15 @@ void __init snowball_sdi_init(void) void __init hrefv60_sdi_init(void) { - u32 periphid = 0x10480180; - - mop500_sdi2_data.capabilities |= MMC_CAP_MMC_HIGHSPEED; - - db8500_add_sdi2(&mop500_sdi2_data, periphid); - + /* PoP:ed eMMC */ + db8500_add_sdi2(&mop500_sdi2_data, U8500_SDI_V2_PERIPHID); /* On-board eMMC */ - db8500_add_sdi4(&mop500_sdi4_data, periphid); - + db8500_add_sdi4(&mop500_sdi4_data, U8500_SDI_V2_PERIPHID); + /* External Micro SD slot */ mop500_sdi0_data.gpio_cd = HREFV60_SDMMC_CD_GPIO; sdi0_en = HREFV60_SDMMC_EN_GPIO; sdi0_vsel = HREFV60_SDMMC_1V8_3V_GPIO; sdi0_configure(); + /* WLAN SDIO channel */ + db8500_add_sdi1(&mop500_sdi1_data, U8500_SDI_V2_PERIPHID); } diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c index de1f5f8f733..9361a529017 100644 --- a/arch/arm/mach-ux500/board-mop500.c +++ b/arch/arm/mach-ux500/board-mop500.c @@ -673,7 +673,7 @@ static void __init hrefv60_init_machine(void) ARRAY_SIZE(mop500_platform_devs)); mop500_i2c_init(); - mop500_sdi_init(); + hrefv60_sdi_init(); mop500_spi_init(); mop500_uart_init(); diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h index de18a2a23e6..f926d3db620 100644 --- a/arch/arm/mach-ux500/board-mop500.h +++ b/arch/arm/mach-ux500/board-mop500.h @@ -7,40 +7,77 @@ #ifndef __BOARD_MOP500_H #define __BOARD_MOP500_H -/* snowball GPIO for MMC card */ -#define SNOWBALL_SDMMC_EN_GPIO 217 -#define SNOWBALL_SDMMC_1V8_3V_GPIO 228 -#define SNOWBALL_SDMMC_CD_GPIO 218 +/* Snowball specific GPIO assignments, this board has no GPIO expander */ +#define SNOWBALL_ACCEL_INT1_GPIO 163 +#define SNOWBALL_ACCEL_INT2_GPIO 164 +#define SNOWBALL_MAGNET_DRDY_GPIO 165 +#define SNOWBALL_SDMMC_EN_GPIO 217 +#define SNOWBALL_SDMMC_1V8_3V_GPIO 228 +#define SNOWBALL_SDMMC_CD_GPIO 218 /* HREFv60-specific GPIO assignments, this board has no GPIO expander */ -#define HREFV60_TOUCH_RST_GPIO 143 -#define HREFV60_PROX_SENSE_GPIO 217 -#define HREFV60_HAL_SW_GPIO 145 -#define HREFV60_SDMMC_EN_GPIO 169 #define HREFV60_SDMMC_1V8_3V_GPIO 5 -#define HREFV60_SDMMC_CD_GPIO 95 -#define HREFV60_ACCEL_INT1_GPIO 82 -#define HREFV60_ACCEL_INT2_GPIO 83 +#define HREFV60_CAMERA_FLASH_ENABLE 21 #define HREFV60_MAGNET_DRDY_GPIO 32 #define HREFV60_DISP1_RST_GPIO 65 #define HREFV60_DISP2_RST_GPIO 66 +#define HREFV60_ACCEL_INT1_GPIO 82 +#define HREFV60_ACCEL_INT2_GPIO 83 +#define HREFV60_SDMMC_CD_GPIO 95 +#define HREFV60_XSHUTDOWN_SECONDARY_SENSOR 140 +#define HREFV60_TOUCH_RST_GPIO 143 +#define HREFV60_HAL_SW_GPIO 145 +#define HREFV60_SDMMC_EN_GPIO 169 +#define HREFV60_MMIO_XENON_CHARGE 170 +#define HREFV60_PROX_SENSE_GPIO 217 + +/* MOP500 generic GPIOs */ +#define CAMERA_FLASH_INT_PIN 7 +#define CYPRESS_TOUCH_INT_PIN 84 +#define XSHUTDOWN_PRIMARY_SENSOR 141 +#define XSHUTDOWN_SECONDARY_SENSOR 142 +#define CYPRESS_TOUCH_RST_GPIO 143 +#define MOP500_HDMI_RST_GPIO 196 +#define CYPRESS_SLAVE_SELECT_GPIO 216 /* GPIOs on the TC35892 expander */ #define MOP500_EGPIO(x) (NOMADIK_NR_GPIO + (x)) +#define GPIO_MAGNET_DRDY MOP500_EGPIO(1) #define GPIO_SDMMC_CD MOP500_EGPIO(3) +#define GPIO_CAMERA_FLASH_ENABLE MOP500_EGPIO(4) +#define GPIO_MMIO_XENON_CHARGE MOP500_EGPIO(5) #define GPIO_PROX_SENSOR MOP500_EGPIO(7) +#define GPIO_HAL_SENSOR MOP500_EGPIO(8) +#define GPIO_ACCEL_INT1 MOP500_EGPIO(10) +#define GPIO_ACCEL_INT2 MOP500_EGPIO(11) #define GPIO_BU21013_CS MOP500_EGPIO(13) +#define MOP500_DISP2_RST_GPIO MOP500_EGPIO(14) +#define MOP500_DISP1_RST_GPIO MOP500_EGPIO(15) #define GPIO_SDMMC_EN MOP500_EGPIO(17) #define GPIO_SDMMC_1V8_3V_SEL MOP500_EGPIO(18) #define MOP500_EGPIO_END MOP500_EGPIO(24) -/* GPIOs on the AB8500 mixed-signals circuit */ -#define MOP500_AB8500_GPIO(x) (MOP500_EGPIO_END + (x)) +/* + * GPIOs on the AB8500 mixed-signals circuit + * Notice that we subtract 1 from the number passed into the macro, this is + * because the AB8500 GPIO pins are enumbered starting from 1, so the value in + * parens matches the GPIO pin number in the data sheet. + */ +#define MOP500_AB8500_GPIO(x) (MOP500_EGPIO_END + (x) - 1) +/*Snowball AB8500 GPIO */ +#define SNOWBALL_VSMPS2_1V8_GPIO MOP500_AB8500_PIN_GPIO(1) /* SYSCLKREQ2/GPIO1 */ +#define SNOWBALL_PM_GPIO1_GPIO MOP500_AB8500_PIN_GPIO(2) /* SYSCLKREQ3/GPIO2 */ +#define SNOWBALL_WLAN_CLK_REQ_GPIO MOP500_AB8500_PIN_GPIO(3) /* SYSCLKREQ4/GPIO3 */ +#define SNOWBALL_PM_GPIO4_GPIO MOP500_AB8500_PIN_GPIO(4) /* SYSCLKREQ6/GPIO4 */ +#define SNOWBALL_EN_3V6_GPIO MOP500_AB8500_PIN_GPIO(16) /* PWMOUT3/GPIO16 */ +#define SNOWBALL_PME_ETH_GPIO MOP500_AB8500_PIN_GPIO(24) /* SYSCLKREQ7/GPIO24 */ +#define SNOWBALL_EN_3V3_ETH_GPIO MOP500_AB8500_PIN_GPIO(26) /* GPIO26 */ struct i2c_board_info; extern void mop500_sdi_init(void); extern void snowball_sdi_init(void); +extern void hrefv60_sdi_init(void); extern void mop500_sdi_tc35892_init(void); void __init mop500_u8500uib_init(void); void __init mop500_stuib_init(void); diff --git a/arch/arm/mach-ux500/clock.c b/arch/arm/mach-ux500/clock.c index e832664d1bd..73790753700 100644 --- a/arch/arm/mach-ux500/clock.c +++ b/arch/arm/mach-ux500/clock.c @@ -239,23 +239,6 @@ static void clk_prcmu_disable(struct clk *clk) writel(1 << clk->prcmu_cg_bit, cg_clr_reg); } -/* ED doesn't have the combined set/clr registers */ -static void clk_prcmu_ed_enable(struct clk *clk) -{ - void __iomem *addr = __io_address(U8500_PRCMU_BASE) - + clk->prcmu_cg_mgt; - - writel(readl(addr) | PRCM_MGT_ENABLE, addr); -} - -static void clk_prcmu_ed_disable(struct clk *clk) -{ - void __iomem *addr = __io_address(U8500_PRCMU_BASE) - + clk->prcmu_cg_mgt; - - writel(readl(addr) & ~PRCM_MGT_ENABLE, addr); -} - static struct clkops clk_prcmu_ops = { .enable = clk_prcmu_enable, .disable = clk_prcmu_disable, @@ -267,7 +250,6 @@ static unsigned int clkrst_base[] = { [3] = U8500_CLKRST3_BASE, [5] = U8500_CLKRST5_BASE, [6] = U8500_CLKRST6_BASE, - [7] = U8500_CLKRST7_BASE_ED, }; static void clk_prcc_enable(struct clk *clk) @@ -321,7 +303,6 @@ static DEFINE_PRCMU_CLK(per2clk, 0x0, 12, PER2CLK); static DEFINE_PRCMU_CLK(per3clk, 0x0, 13, PER3CLK); static DEFINE_PRCMU_CLK(per5clk, 0x0, 14, PER5CLK); static DEFINE_PRCMU_CLK_RATE(per6clk, 0x0, 15, PER6CLK, 133330000); -static DEFINE_PRCMU_CLK_RATE(per7clk, 0x0, 16, PER7CLK, 100000000); static DEFINE_PRCMU_CLK(lcdclk, 0x0, 17, LCDCLK); static DEFINE_PRCMU_CLK(bmlclk, 0x0, 18, BMLCLK); static DEFINE_PRCMU_CLK(hsitxclk, 0x0, 19, HSITXCLK); @@ -351,44 +332,28 @@ static DEFINE_PRCMU_CLK(uiccclk, 0x4, 1, UICCCLK); /* v1 */ static DEFINE_PRCC_CLK(1, i2c4, 10, 9, &clk_i2cclk); static DEFINE_PRCC_CLK(1, gpio0, 9, -1, NULL); static DEFINE_PRCC_CLK(1, slimbus0, 8, 8, &clk_slimclk); -static DEFINE_PRCC_CLK(1, spi3_ed, 7, 7, NULL); -static DEFINE_PRCC_CLK(1, spi3_v1, 7, -1, NULL); +static DEFINE_PRCC_CLK(1, spi3, 7, -1, NULL); static DEFINE_PRCC_CLK(1, i2c2, 6, 6, &clk_i2cclk); static DEFINE_PRCC_CLK(1, sdi0, 5, 5, &clk_sdmmcclk); -static DEFINE_PRCC_CLK(1, msp1_ed, 4, 4, &clk_msp02clk); -static DEFINE_PRCC_CLK(1, msp1_v1, 4, 4, &clk_msp1clk); +static DEFINE_PRCC_CLK(1, msp1, 4, 4, &clk_msp1clk); static DEFINE_PRCC_CLK(1, msp0, 3, 3, &clk_msp02clk); static DEFINE_PRCC_CLK(1, i2c1, 2, 2, &clk_i2cclk); static DEFINE_PRCC_CLK(1, uart1, 1, 1, &clk_uartclk); static DEFINE_PRCC_CLK(1, uart0, 0, 0, &clk_uartclk); /* Peripheral Cluster #2 */ - -static DEFINE_PRCC_CLK(2, gpio1_ed, 12, -1, NULL); -static DEFINE_PRCC_CLK(2, ssitx_ed, 11, -1, NULL); -static DEFINE_PRCC_CLK(2, ssirx_ed, 10, -1, NULL); -static DEFINE_PRCC_CLK(2, spi0_ed, 9, -1, NULL); -static DEFINE_PRCC_CLK(2, sdi3_ed, 8, 6, &clk_sdmmcclk); -static DEFINE_PRCC_CLK(2, sdi1_ed, 7, 5, &clk_sdmmcclk); -static DEFINE_PRCC_CLK(2, msp2_ed, 6, 4, &clk_msp02clk); -static DEFINE_PRCC_CLK(2, sdi4_ed, 4, 2, &clk_sdmmcclk); -static DEFINE_PRCC_CLK(2, pwl_ed, 3, 1, NULL); -static DEFINE_PRCC_CLK(2, spi1_ed, 2, -1, NULL); -static DEFINE_PRCC_CLK(2, spi2_ed, 1, -1, NULL); -static DEFINE_PRCC_CLK(2, i2c3_ed, 0, 0, &clk_i2cclk); - -static DEFINE_PRCC_CLK(2, gpio1_v1, 11, -1, NULL); -static DEFINE_PRCC_CLK(2, ssitx_v1, 10, 7, NULL); -static DEFINE_PRCC_CLK(2, ssirx_v1, 9, 6, NULL); -static DEFINE_PRCC_CLK(2, spi0_v1, 8, -1, NULL); -static DEFINE_PRCC_CLK(2, sdi3_v1, 7, 5, &clk_sdmmcclk); -static DEFINE_PRCC_CLK(2, sdi1_v1, 6, 4, &clk_sdmmcclk); -static DEFINE_PRCC_CLK(2, msp2_v1, 5, 3, &clk_msp02clk); -static DEFINE_PRCC_CLK(2, sdi4_v1, 4, 2, &clk_sdmmcclk); -static DEFINE_PRCC_CLK(2, pwl_v1, 3, 1, NULL); -static DEFINE_PRCC_CLK(2, spi1_v1, 2, -1, NULL); -static DEFINE_PRCC_CLK(2, spi2_v1, 1, -1, NULL); -static DEFINE_PRCC_CLK(2, i2c3_v1, 0, 0, &clk_i2cclk); +static DEFINE_PRCC_CLK(2, gpio1, 11, -1, NULL); +static DEFINE_PRCC_CLK(2, ssitx, 10, 7, NULL); +static DEFINE_PRCC_CLK(2, ssirx, 9, 6, NULL); +static DEFINE_PRCC_CLK(2, spi0, 8, -1, NULL); +static DEFINE_PRCC_CLK(2, sdi3, 7, 5, &clk_sdmmcclk); +static DEFINE_PRCC_CLK(2, sdi1, 6, 4, &clk_sdmmcclk); +static DEFINE_PRCC_CLK(2, msp2, 5, 3, &clk_msp02clk); +static DEFINE_PRCC_CLK(2, sdi4, 4, 2, &clk_sdmmcclk); +static DEFINE_PRCC_CLK(2, pwl, 3, 1, NULL); +static DEFINE_PRCC_CLK(2, spi1, 2, -1, NULL); +static DEFINE_PRCC_CLK(2, spi2, 1, -1, NULL); +static DEFINE_PRCC_CLK(2, i2c3, 0, 0, &clk_i2cclk); /* Peripheral Cluster #3 */ static DEFINE_PRCC_CLK(3, gpio2, 8, -1, NULL); @@ -397,49 +362,34 @@ static DEFINE_PRCC_CLK(3, uart2, 6, 6, &clk_uartclk); static DEFINE_PRCC_CLK(3, ske, 5, 5, &clk_32khz); static DEFINE_PRCC_CLK(3, sdi2, 4, 4, &clk_sdmmcclk); static DEFINE_PRCC_CLK(3, i2c0, 3, 3, &clk_i2cclk); -static DEFINE_PRCC_CLK(3, ssp1_ed, 2, 2, &clk_i2cclk); -static DEFINE_PRCC_CLK(3, ssp0_ed, 1, 1, &clk_i2cclk); -static DEFINE_PRCC_CLK(3, ssp1_v1, 2, 2, &clk_sspclk); -static DEFINE_PRCC_CLK(3, ssp0_v1, 1, 1, &clk_sspclk); +static DEFINE_PRCC_CLK(3, ssp1, 2, 2, &clk_sspclk); +static DEFINE_PRCC_CLK(3, ssp0, 1, 1, &clk_sspclk); static DEFINE_PRCC_CLK(3, fsmc, 0, -1, NULL); /* Peripheral Cluster #4 is in the always on domain */ /* Peripheral Cluster #5 */ static DEFINE_PRCC_CLK(5, gpio3, 1, -1, NULL); -static DEFINE_PRCC_CLK(5, usb_ed, 0, 0, &clk_i2cclk); -static DEFINE_PRCC_CLK(5, usb_v1, 0, 0, NULL); +static DEFINE_PRCC_CLK(5, usb, 0, 0, NULL); /* Peripheral Cluster #6 */ /* MTU ID in data */ -static DEFINE_PRCC_CLK_CUSTOM(6, mtu1_v1, 8, -1, NULL, clk_mtu_get_rate, 1); -static DEFINE_PRCC_CLK_CUSTOM(6, mtu0_v1, 7, -1, NULL, clk_mtu_get_rate, 0); -static DEFINE_PRCC_CLK(6, cfgreg_v1, 6, 6, NULL); -static DEFINE_PRCC_CLK(6, dmc_ed, 6, 6, NULL); +static DEFINE_PRCC_CLK_CUSTOM(6, mtu1, 8, -1, NULL, clk_mtu_get_rate, 1); +static DEFINE_PRCC_CLK_CUSTOM(6, mtu0, 7, -1, NULL, clk_mtu_get_rate, 0); +static DEFINE_PRCC_CLK(6, cfgreg, 6, 6, NULL); static DEFINE_PRCC_CLK(6, hash1, 5, -1, NULL); -static DEFINE_PRCC_CLK(6, unipro_v1, 4, 1, &clk_uniproclk); -static DEFINE_PRCC_CLK(6, cryp1_ed, 4, -1, NULL); +static DEFINE_PRCC_CLK(6, unipro, 4, 1, &clk_uniproclk); static DEFINE_PRCC_CLK(6, pka, 3, -1, NULL); static DEFINE_PRCC_CLK(6, hash0, 2, -1, NULL); static DEFINE_PRCC_CLK(6, cryp0, 1, -1, NULL); -static DEFINE_PRCC_CLK(6, rng_ed, 0, 0, &clk_i2cclk); -static DEFINE_PRCC_CLK(6, rng_v1, 0, 0, &clk_rngclk); - -/* Peripheral Cluster #7 */ - -static DEFINE_PRCC_CLK(7, tzpc0_ed, 4, -1, NULL); -/* MTU ID in data */ -static DEFINE_PRCC_CLK_CUSTOM(7, mtu1_ed, 3, -1, NULL, clk_mtu_get_rate, 1); -static DEFINE_PRCC_CLK_CUSTOM(7, mtu0_ed, 2, -1, NULL, clk_mtu_get_rate, 0); -static DEFINE_PRCC_CLK(7, wdg_ed, 1, -1, NULL); -static DEFINE_PRCC_CLK(7, cfgreg_ed, 0, -1, NULL); +static DEFINE_PRCC_CLK(6, rng, 0, 0, &clk_rngclk); static struct clk clk_dummy_apb_pclk = { .name = "apb_pclk", }; -static struct clk_lookup u8500_common_clks[] = { +static struct clk_lookup u8500_clks[] = { CLK(dummy_apb_pclk, NULL, "apb_pclk"), /* Peripheral Cluster #1 */ @@ -494,83 +444,41 @@ static struct clk_lookup u8500_common_clks[] = { CLK(dmaclk, "dma40.0", NULL), CLK(b2r2clk, "b2r2", NULL), CLK(tvclk, "tv", NULL), -}; -static struct clk_lookup u8500_ed_clks[] = { - /* Peripheral Cluster #1 */ - CLK(spi3_ed, "spi3", NULL), - CLK(msp1_ed, "msp1", NULL), - - /* Peripheral Cluster #2 */ - CLK(gpio1_ed, "gpio.6", NULL), - CLK(gpio1_ed, "gpio.7", NULL), - CLK(ssitx_ed, "ssitx", NULL), - CLK(ssirx_ed, "ssirx", NULL), - CLK(spi0_ed, "spi0", NULL), - CLK(sdi3_ed, "sdi3", NULL), - CLK(sdi1_ed, "sdi1", NULL), - CLK(msp2_ed, "msp2", NULL), - CLK(sdi4_ed, "sdi4", NULL), - CLK(pwl_ed, "pwl", NULL), - CLK(spi1_ed, "spi1", NULL), - CLK(spi2_ed, "spi2", NULL), - CLK(i2c3_ed, "nmk-i2c.3", NULL), - - /* Peripheral Cluster #3 */ - CLK(ssp1_ed, "ssp1", NULL), - CLK(ssp0_ed, "ssp0", NULL), - - /* Peripheral Cluster #5 */ - CLK(usb_ed, "musb-ux500.0", "usb"), - - /* Peripheral Cluster #6 */ - CLK(dmc_ed, "dmc", NULL), - CLK(cryp1_ed, "cryp1", NULL), - CLK(rng_ed, "rng", NULL), - - /* Peripheral Cluster #7 */ - CLK(tzpc0_ed, "tzpc0", NULL), - CLK(mtu1_ed, "mtu1", NULL), - CLK(mtu0_ed, "mtu0", NULL), - CLK(wdg_ed, "wdg", NULL), - CLK(cfgreg_ed, "cfgreg", NULL), -}; - -static struct clk_lookup u8500_v1_clks[] = { /* Peripheral Cluster #1 */ CLK(i2c4, "nmk-i2c.4", NULL), - CLK(spi3_v1, "spi3", NULL), - CLK(msp1_v1, "msp1", NULL), + CLK(spi3, "spi3", NULL), + CLK(msp1, "msp1", NULL), /* Peripheral Cluster #2 */ - CLK(gpio1_v1, "gpio.6", NULL), - CLK(gpio1_v1, "gpio.7", NULL), - CLK(ssitx_v1, "ssitx", NULL), - CLK(ssirx_v1, "ssirx", NULL), - CLK(spi0_v1, "spi0", NULL), - CLK(sdi3_v1, "sdi3", NULL), - CLK(sdi1_v1, "sdi1", NULL), - CLK(msp2_v1, "msp2", NULL), - CLK(sdi4_v1, "sdi4", NULL), - CLK(pwl_v1, "pwl", NULL), - CLK(spi1_v1, "spi1", NULL), - CLK(spi2_v1, "spi2", NULL), - CLK(i2c3_v1, "nmk-i2c.3", NULL), + CLK(gpio1, "gpio.6", NULL), + CLK(gpio1, "gpio.7", NULL), + CLK(ssitx, "ssitx", NULL), + CLK(ssirx, "ssirx", NULL), + CLK(spi0, "spi0", NULL), + CLK(sdi3, "sdi3", NULL), + CLK(sdi1, "sdi1", NULL), + CLK(msp2, "msp2", NULL), + CLK(sdi4, "sdi4", NULL), + CLK(pwl, "pwl", NULL), + CLK(spi1, "spi1", NULL), + CLK(spi2, "spi2", NULL), + CLK(i2c3, "nmk-i2c.3", NULL), /* Peripheral Cluster #3 */ - CLK(ssp1_v1, "ssp1", NULL), - CLK(ssp0_v1, "ssp0", NULL), + CLK(ssp1, "ssp1", NULL), + CLK(ssp0, "ssp0", NULL), /* Peripheral Cluster #5 */ - CLK(usb_v1, "musb-ux500.0", "usb"), + CLK(usb, "musb-ux500.0", "usb"), /* Peripheral Cluster #6 */ - CLK(mtu1_v1, "mtu1", NULL), - CLK(mtu0_v1, "mtu0", NULL), - CLK(cfgreg_v1, "cfgreg", NULL), + CLK(mtu1, "mtu1", NULL), + CLK(mtu0, "mtu0", NULL), + CLK(cfgreg, "cfgreg", NULL), CLK(hash1, "hash1", NULL), - CLK(unipro_v1, "unipro", NULL), - CLK(rng_v1, "rng", NULL), + CLK(unipro, "unipro", NULL), + CLK(rng, "rng", NULL), /* PRCMU level clock gating */ @@ -743,7 +651,7 @@ err_out: late_initcall(clk_debugfs_init); #endif /* defined(CONFIG_DEBUG_FS) */ -unsigned long clk_smp_twd_rate = 400000000; +unsigned long clk_smp_twd_rate = 500000000; unsigned long clk_smp_twd_get_rate(struct clk *clk) { @@ -769,7 +677,7 @@ static int clk_twd_cpufreq_transition(struct notifier_block *nb, if (state == CPUFREQ_PRECHANGE) { /* Save frequency in simple Hz */ - clk_smp_twd_rate = f->new * 1000; + clk_smp_twd_rate = (f->new * 1000) / 2; } return NOTIFY_OK; @@ -790,11 +698,7 @@ late_initcall(clk_init_smp_twd_cpufreq); int __init clk_init(void) { - if (cpu_is_u8500ed()) { - clk_prcmu_ops.enable = clk_prcmu_ed_enable; - clk_prcmu_ops.disable = clk_prcmu_ed_disable; - clk_per6clk.rate = 100000000; - } else if (cpu_is_u5500()) { + if (cpu_is_u5500()) { /* Clock tree for U5500 not implemented yet */ clk_prcc_ops.enable = clk_prcc_ops.disable = NULL; clk_prcmu_ops.enable = clk_prcmu_ops.disable = NULL; @@ -802,20 +706,11 @@ int __init clk_init(void) clk_sdmmcclk.rate = 99900000; } - clkdev_add_table(u8500_common_clks, ARRAY_SIZE(u8500_common_clks)); - if (cpu_is_u8500ed()) - clkdev_add_table(u8500_ed_clks, ARRAY_SIZE(u8500_ed_clks)); - else - clkdev_add_table(u8500_v1_clks, ARRAY_SIZE(u8500_v1_clks)); - + clkdev_add_table(u8500_clks, ARRAY_SIZE(u8500_clks)); clkdev_add(&clk_smp_twd_lookup); #ifdef CONFIG_DEBUG_FS - clk_debugfs_add_table(u8500_common_clks, ARRAY_SIZE(u8500_common_clks)); - if (cpu_is_u8500ed()) - clk_debugfs_add_table(u8500_ed_clks, ARRAY_SIZE(u8500_ed_clks)); - else - clk_debugfs_add_table(u8500_v1_clks, ARRAY_SIZE(u8500_v1_clks)); + clk_debugfs_add_table(u8500_clks, ARRAY_SIZE(u8500_clks)); #endif return 0; } diff --git a/arch/arm/mach-ux500/cpu-db5500.c b/arch/arm/mach-ux500/cpu-db5500.c index 5323286b265..18aa5c05c69 100644 --- a/arch/arm/mach-ux500/cpu-db5500.c +++ b/arch/arm/mach-ux500/cpu-db5500.c @@ -46,26 +46,6 @@ static struct map_desc u5500_io_desc[] __initdata = { __IO_DEV_DESC(U5500_PRCMU_TCDM_BASE, SZ_4K), }; -static struct resource db5500_pmu_resources[] = { - [0] = { - .start = IRQ_DB5500_PMU0, - .end = IRQ_DB5500_PMU0, - .flags = IORESOURCE_IRQ, - }, - [1] = { - .start = IRQ_DB5500_PMU1, - .end = IRQ_DB5500_PMU1, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device db5500_pmu_device = { - .name = "arm-pmu", - .id = ARM_PMU_DEVICE_CPU, - .num_resources = ARRAY_SIZE(db5500_pmu_resources), - .resource = db5500_pmu_resources, -}; - static struct resource mbox0_resources[] = { { .name = "mbox_peer", @@ -151,7 +131,6 @@ static struct platform_device mbox2_device = { }; static struct platform_device *db5500_platform_devs[] __initdata = { - &db5500_pmu_device, &mbox0_device, &mbox1_device, &mbox2_device, @@ -192,6 +171,25 @@ void __init u5500_map_io(void) _PRCMU_BASE = __io_address(U5500_PRCMU_BASE); } +static void __init db5500_pmu_init(void) +{ + struct resource res[] = { + [0] = { + .start = IRQ_DB5500_PMU0, + .end = IRQ_DB5500_PMU0, + .flags = IORESOURCE_IRQ, + }, + [1] = { + .start = IRQ_DB5500_PMU1, + .end = IRQ_DB5500_PMU1, + .flags = IORESOURCE_IRQ, + }, + }; + + platform_device_register_simple("arm-pmu", ARM_PMU_DEVICE_CPU, + res, ARRAY_SIZE(res)); +} + static int usb_db5500_rx_dma_cfg[] = { DB5500_DMA_DEV4_USB_OTG_IEP_1_9, DB5500_DMA_DEV5_USB_OTG_IEP_2_10, @@ -217,6 +215,7 @@ static int usb_db5500_tx_dma_cfg[] = { void __init u5500_init_devices(void) { db5500_add_gpios(); + db5500_pmu_init(); db5500_dma_init(); db5500_add_rtc(); db5500_add_usb(usb_db5500_rx_dma_cfg, usb_db5500_tx_dma_cfg); diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c index 7f2729c05db..7176ee7491a 100644 --- a/arch/arm/mach-ux500/cpu-db8500.c +++ b/arch/arm/mach-ux500/cpu-db8500.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2008-2009 ST-Ericsson + * Copyright (C) 2008-2009 ST-Ericsson SA * * Author: Srinidhi KASAGAR <srinidhi.kasagar@stericsson.com> * @@ -53,19 +53,6 @@ static struct map_desc u8500_io_desc[] __initdata = { __IO_DEV_DESC(U8500_GPIO1_BASE, SZ_4K), __IO_DEV_DESC(U8500_GPIO2_BASE, SZ_4K), __IO_DEV_DESC(U8500_GPIO3_BASE, SZ_4K), -}; - -static struct map_desc u8500_ed_io_desc[] __initdata = { - __IO_DEV_DESC(U8500_MTU0_BASE_ED, SZ_4K), - __IO_DEV_DESC(U8500_CLKRST7_BASE_ED, SZ_8K), -}; - -static struct map_desc u8500_v1_io_desc[] __initdata = { - __IO_DEV_DESC(U8500_MTU0_BASE, SZ_4K), - __IO_DEV_DESC(U8500_PRCMU_TCDM_BASE_V1, SZ_4K), -}; - -static struct map_desc u8500_v2_io_desc[] __initdata = { __IO_DEV_DESC(U8500_PRCMU_TCDM_BASE, SZ_4K), }; @@ -80,13 +67,6 @@ void __init u8500_map_io(void) iotable_init(u8500_io_desc, ARRAY_SIZE(u8500_io_desc)); - if (cpu_is_u8500ed()) - iotable_init(u8500_ed_io_desc, ARRAY_SIZE(u8500_ed_io_desc)); - else if (cpu_is_u8500v1()) - iotable_init(u8500_v1_io_desc, ARRAY_SIZE(u8500_v1_io_desc)); - else if (cpu_is_u8500v2()) - iotable_init(u8500_v2_io_desc, ARRAY_SIZE(u8500_v2_io_desc)); - _PRCMU_BASE = __io_address(U8500_PRCMU_BASE); } @@ -155,12 +135,9 @@ static resource_size_t __initdata db8500_gpio_base[] = { static void __init db8500_add_gpios(void) { struct nmk_gpio_platform_data pdata = { - /* No custom data yet */ + .supports_sleepmode = true, }; - if (cpu_is_u8500v2()) - pdata.supports_sleepmode = true; - dbx500_add_gpios(ARRAY_AND_SIZE(db8500_gpio_base), IRQ_DB8500_GPIO0, &pdata); } @@ -192,9 +169,6 @@ static int usb_db8500_tx_dma_cfg[] = { */ void __init u8500_init_devices(void) { - if (cpu_is_u8500ed()) - dma40_u8500ed_fixup(); - db8500_add_rtc(); db8500_add_gpios(); db8500_add_usb(usb_db8500_rx_dma_cfg, usb_db8500_tx_dma_cfg); diff --git a/arch/arm/mach-ux500/devices-db8500.c b/arch/arm/mach-ux500/devices-db8500.c index 73b17404b19..a7c6cdc9b11 100644 --- a/arch/arm/mach-ux500/devices-db8500.c +++ b/arch/arm/mach-ux500/devices-db8500.c @@ -166,16 +166,6 @@ struct platform_device u8500_dma40_device = { .resource = dma40_resources }; -void dma40_u8500ed_fixup(void) -{ - dma40_plat_data.memcpy = NULL; - dma40_plat_data.memcpy_len = 0; - dma40_resources[0].start = U8500_DMA_BASE_ED; - dma40_resources[0].end = U8500_DMA_BASE_ED + SZ_4K - 1; - dma40_resources[1].start = U8500_DMA_LCPA_BASE_ED; - dma40_resources[1].end = U8500_DMA_LCPA_BASE_ED + 2 * SZ_1K - 1; -} - struct resource keypad_resources[] = { [0] = { .start = U8500_SKE_BASE, diff --git a/arch/arm/mach-ux500/id.c b/arch/arm/mach-ux500/id.c index d35122ebc67..15a0f63b2e2 100644 --- a/arch/arm/mach-ux500/id.c +++ b/arch/arm/mach-ux500/id.c @@ -65,6 +65,7 @@ static unsigned int partnumber(unsigned int asicid) * DB8500v1 0x411fc091 0x9001FFF4 0x008500A0 * DB8500v1.1 0x411fc091 0x9001FFF4 0x008500A1 * DB8500v2 0x412fc091 0x9001DBF4 0x008500B0 + * DB8520v2.2 0x412fc091 0x9001DBF4 0x008500B2 * DB5500v1 0x412fc091 0x9001FFF4 0x005500A0 */ @@ -80,9 +81,10 @@ void __init ux500_map_io(void) addr = 0x9001FFF4; break; - case 0x412fc091: /* DB8500v2 / DB5500v1 */ + case 0x412fc091: /* DB8520 / DB8500v2 / DB5500v1 */ asicid = ux500_read_asicid(0x9001DBF4); - if (partnumber(asicid) == 0x8500) + if (partnumber(asicid) == 0x8500 || + partnumber(asicid) == 0x8520) /* DB8500v2 */ break; diff --git a/arch/arm/mach-ux500/include/mach/db5500-regs.h b/arch/arm/mach-ux500/include/mach/db5500-regs.h index 994b5fe6f85..8e714bcb099 100644 --- a/arch/arm/mach-ux500/include/mach/db5500-regs.h +++ b/arch/arm/mach-ux500/include/mach/db5500-regs.h @@ -65,8 +65,11 @@ #define U5500_PRCMU_TIMER_4_BASE (U5500_PER4_BASE + 0x07450) #define U5500_MSP1_BASE (U5500_PER4_BASE + 0x9000) #define U5500_GPIO2_BASE (U5500_PER4_BASE + 0xA000) +#define U5500_MTIMER_BASE (U5500_PER4_BASE + 0xC000) #define U5500_CDETECT_BASE (U5500_PER4_BASE + 0xF000) #define U5500_PRCMU_TCDM_BASE (U5500_PER4_BASE + 0x18000) +#define U5500_PRCMU_TCPM_BASE (U5500_PER4_BASE + 0x10000) +#define U5500_TPIU_BASE (U5500_PER4_BASE + 0x50000) #define U5500_SPI0_BASE (U5500_PER5_BASE + 0x0000) #define U5500_SPI1_BASE (U5500_PER5_BASE + 0x1000) @@ -125,6 +128,7 @@ #define U5500_ACCCON_BASE (0xBFFF1000) #define U5500_ACCCON_CPUVEC_RESET_ADDR_OFFSET (0x00000020) #define U5500_ACCCON_ACC_CPU_CTRL_OFFSET (0x000000BC) +#define U5500_INTCON_MBOX1_INT_RESET_ADDR (0xBFFD31A4) #define U5500_ESRAM_BASE 0x40000000 #define U5500_ESRAM_DMA_LCPA_OFFSET 0x10000 diff --git a/arch/arm/mach-ux500/include/mach/db8500-regs.h b/arch/arm/mach-ux500/include/mach/db8500-regs.h index 751b0e6938d..80e10f50282 100644 --- a/arch/arm/mach-ux500/include/mach/db8500-regs.h +++ b/arch/arm/mach-ux500/include/mach/db8500-regs.h @@ -22,7 +22,9 @@ #define U8500_ESRAM_DMA_LCPA_OFFSET 0x10000 #define U8500_DMA_LCPA_BASE (U8500_ESRAM_BANK0 + U8500_ESRAM_DMA_LCPA_OFFSET) -#define U8500_DMA_LCPA_BASE_ED (U8500_ESRAM_BANK4 + 0x4000) + +/* This address fulfills the 256k alignment requirement of the lcla base */ +#define U8500_DMA_LCLA_BASE U8500_ESRAM_BANK4 #define U8500_PER3_BASE 0x80000000 #define U8500_STM_BASE 0x80100000 @@ -40,15 +42,14 @@ #define U8500_ASIC_ID_BASE 0x9001D000 #define U8500_PER6_BASE 0xa03c0000 +#define U8500_PER7_BASE 0xa03d0000 #define U8500_PER5_BASE 0xa03e0000 -#define U8500_PER7_BASE_ED 0xa03d0000 #define U8500_SVA_BASE 0xa0100000 #define U8500_SIA_BASE 0xa0200000 #define U8500_SGA_BASE 0xa0300000 #define U8500_MCDE_BASE 0xa0350000 -#define U8500_DMA_BASE_ED 0xa0362000 #define U8500_DMA_BASE 0x801C0000 /* v1 */ #define U8500_SBAG_BASE 0xa0390000 @@ -66,13 +67,6 @@ #define U8500_GPIO2_BASE (U8500_PER2_BASE + 0xE000) #define U8500_GPIO3_BASE (U8500_PER5_BASE + 0x1E000) -/* per7 base addresses */ -#define U8500_CR_BASE_ED (U8500_PER7_BASE_ED + 0x8000) -#define U8500_MTU0_BASE_ED (U8500_PER7_BASE_ED + 0xa000) -#define U8500_MTU1_BASE_ED (U8500_PER7_BASE_ED + 0xb000) -#define U8500_TZPC0_BASE_ED (U8500_PER7_BASE_ED + 0xc000) -#define U8500_CLKRST7_BASE_ED (U8500_PER7_BASE_ED + 0xf000) - #define U8500_UART0_BASE (U8500_PER1_BASE + 0x0000) #define U8500_UART1_BASE (U8500_PER1_BASE + 0x1000) @@ -102,12 +96,10 @@ #define U8500_SCR_BASE (U8500_PER4_BASE + 0x05000) #define U8500_DMC_BASE (U8500_PER4_BASE + 0x06000) #define U8500_PRCMU_BASE (U8500_PER4_BASE + 0x07000) -#define U8500_PRCMU_TIMER_3_BASE (U8500_PER4_BASE + 0x07338) -#define U8500_PRCMU_TIMER_4_BASE (U8500_PER4_BASE + 0x07450) -#define U8500_PRCMU_TCDM_BASE_V1 (U8500_PER4_BASE + 0x0f000) #define U8500_PRCMU_TCDM_BASE (U8500_PER4_BASE + 0x68000) #define U8500_PRCMU_TCPM_BASE (U8500_PER4_BASE + 0x60000) - +#define U8500_PRCMU_TIMER_3_BASE (U8500_PER4_BASE + 0x07338) +#define U8500_PRCMU_TIMER_4_BASE (U8500_PER4_BASE + 0x07450) /* per3 base addresses */ #define U8500_FSMC_BASE (U8500_PER3_BASE + 0x0000) diff --git a/arch/arm/mach-ux500/include/mach/devices.h b/arch/arm/mach-ux500/include/mach/devices.h index 020b6369a30..5f6cb71fc62 100644 --- a/arch/arm/mach-ux500/include/mach/devices.h +++ b/arch/arm/mach-ux500/include/mach/devices.h @@ -18,6 +18,4 @@ extern struct amba_device ux500_pl031_device; extern struct platform_device u8500_dma40_device; extern struct platform_device ux500_ske_keypad_device; -void dma40_u8500ed_fixup(void); - #endif diff --git a/arch/arm/mach-ux500/include/mach/hardware.h b/arch/arm/mach-ux500/include/mach/hardware.h index 470ac52663d..b6ba26a1367 100644 --- a/arch/arm/mach-ux500/include/mach/hardware.h +++ b/arch/arm/mach-ux500/include/mach/hardware.h @@ -10,20 +10,21 @@ #ifndef __MACH_HARDWARE_H #define __MACH_HARDWARE_H -/* macros to get at IO space when running virtually +/* + * Macros to get at IO space when running virtually * We dont map all the peripherals, let ioremap do * this for us. We map only very basic peripherals here. */ #define U8500_IO_VIRTUAL 0xf0000000 #define U8500_IO_PHYSICAL 0xa0000000 -/* this macro is used in assembly, so no cast */ +/* This macro is used in assembly, so no cast */ #define IO_ADDRESS(x) \ (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + U8500_IO_VIRTUAL) /* typesafe io address */ #define __io_address(n) __io(IO_ADDRESS(n)) -/* used by some plat-nomadik code */ +/* Used by some plat-nomadik code */ #define io_p2v(n) __io_address(n) #include <mach/db8500-regs.h> @@ -36,6 +37,5 @@ extern void __iomem *_PRCMU_BASE; #define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x) -#endif - +#endif /* __ASSEMBLY__ */ #endif /* __MACH_HARDWARE_H */ diff --git a/arch/arm/mach-ux500/include/mach/id.h b/arch/arm/mach-ux500/include/mach/id.h index 02b541a37ee..833d6a6edc9 100644 --- a/arch/arm/mach-ux500/include/mach/id.h +++ b/arch/arm/mach-ux500/include/mach/id.h @@ -47,6 +47,30 @@ static inline bool __attribute_const__ cpu_is_u5500(void) } /* + * 5500 revisions + */ + +static inline bool __attribute_const__ cpu_is_u5500v1(void) +{ + return cpu_is_u5500() && (dbx500_revision() & 0xf0) == 0xA0; +} + +static inline bool __attribute_const__ cpu_is_u5500v2(void) +{ + return (dbx500_id.revision & 0xf0) == 0xB0; +} + +static inline bool __attribute_const__ cpu_is_u5500v20(void) +{ + return cpu_is_u5500() && ((dbx500_revision() & 0xf0) == 0xB0); +} + +static inline bool __attribute_const__ cpu_is_u5500v21(void) +{ + return cpu_is_u5500() && (dbx500_revision() == 0xB1); +} + +/* * 8500 revisions */ diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c index cbcda61162d..02b7b9303f3 100644 --- a/arch/arm/mach-versatile/core.c +++ b/arch/arm/mach-versatile/core.c @@ -22,7 +22,6 @@ #include <linux/device.h> #include <linux/dma-mapping.h> #include <linux/platform_device.h> -#include <linux/sysdev.h> #include <linux/interrupt.h> #include <linux/irqdomain.h> #include <linux/of_address.h> diff --git a/arch/arm/mach-versatile/pci.c b/arch/arm/mach-versatile/pci.c index c898deb3ada..90069bce23b 100644 --- a/arch/arm/mach-versatile/pci.c +++ b/arch/arm/mach-versatile/pci.c @@ -191,7 +191,7 @@ static struct resource pre_mem = { .flags = IORESOURCE_MEM | IORESOURCE_PREFETCH, }; -static int __init pci_versatile_setup_resources(struct resource **resource) +static int __init pci_versatile_setup_resources(struct list_head *resources) { int ret = 0; @@ -215,13 +215,13 @@ static int __init pci_versatile_setup_resources(struct resource **resource) } /* - * bus->resource[0] is the IO resource for this bus - * bus->resource[1] is the mem resource for this bus - * bus->resource[2] is the prefetch mem resource for this bus + * the IO resource for this bus + * the mem resource for this bus + * the prefetch mem resource for this bus */ - resource[0] = &io_mem; - resource[1] = &non_mem; - resource[2] = &pre_mem; + pci_add_resource(resources, &io_mem); + pci_add_resource(resources, &non_mem); + pci_add_resource(resources, &pre_mem); goto out; @@ -250,7 +250,7 @@ int __init pci_versatile_setup(int nr, struct pci_sys_data *sys) if (nr == 0) { sys->mem_offset = 0; - ret = pci_versatile_setup_resources(sys->resource); + ret = pci_versatile_setup_resources(&sys->resources); if (ret < 0) { printk("pci_versatile_setup: resources... oops?\n"); goto out; @@ -306,7 +306,8 @@ int __init pci_versatile_setup(int nr, struct pci_sys_data *sys) struct pci_bus * __init pci_versatile_scan_bus(int nr, struct pci_sys_data *sys) { - return pci_scan_bus(sys->busnr, &pci_versatile_ops, sys); + return pci_scan_root_bus(NULL, sys->busnr, &pci_versatile_ops, sys, + &sys->resources); } void __init pci_versatile_preinit(void) diff --git a/arch/arm/mach-versatile/versatile_ab.c b/arch/arm/mach-versatile/versatile_ab.c index 63b8dd2b9f4..98f65493177 100644 --- a/arch/arm/mach-versatile/versatile_ab.c +++ b/arch/arm/mach-versatile/versatile_ab.c @@ -21,7 +21,6 @@ #include <linux/init.h> #include <linux/device.h> -#include <linux/sysdev.h> #include <linux/amba/bus.h> #include <linux/io.h> diff --git a/arch/arm/mach-versatile/versatile_pb.c b/arch/arm/mach-versatile/versatile_pb.c index 7aab79b665e..9581c197500 100644 --- a/arch/arm/mach-versatile/versatile_pb.c +++ b/arch/arm/mach-versatile/versatile_pb.c @@ -21,7 +21,6 @@ #include <linux/init.h> #include <linux/device.h> -#include <linux/sysdev.h> #include <linux/amba/bus.h> #include <linux/amba/pl061.h> #include <linux/amba/mmci.h> diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c index 6dd10e320ef..b4a28ca0e50 100644 --- a/arch/arm/mach-vexpress/v2m.c +++ b/arch/arm/mach-vexpress/v2m.c @@ -10,7 +10,7 @@ #include <linux/ata_platform.h> #include <linux/smsc911x.h> #include <linux/spinlock.h> -#include <linux/sysdev.h> +#include <linux/device.h> #include <linux/usb/isp1760.h> #include <linux/clkdev.h> #include <linux/mtd/physmap.h> diff --git a/arch/arm/mach-w90x900/irq.c b/arch/arm/mach-w90x900/irq.c index b466e2450ba..d66d43ae8df 100644 --- a/arch/arm/mach-w90x900/irq.c +++ b/arch/arm/mach-w90x900/irq.c @@ -19,7 +19,7 @@ #include <linux/interrupt.h> #include <linux/ioport.h> #include <linux/ptrace.h> -#include <linux/sysdev.h> +#include <linux/device.h> #include <linux/io.h> #include <asm/irq.h> diff --git a/arch/arm/mm/iomap.c b/arch/arm/mm/iomap.c index 430df1a5978..e62956e1203 100644 --- a/arch/arm/mm/iomap.c +++ b/arch/arm/mm/iomap.c @@ -35,27 +35,6 @@ EXPORT_SYMBOL(pcibios_min_mem); unsigned int pci_flags = PCI_REASSIGN_ALL_RSRC; EXPORT_SYMBOL(pci_flags); -void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen) -{ - resource_size_t start = pci_resource_start(dev, bar); - resource_size_t len = pci_resource_len(dev, bar); - unsigned long flags = pci_resource_flags(dev, bar); - - if (!len || !start) - return NULL; - if (maxlen && len > maxlen) - len = maxlen; - if (flags & IORESOURCE_IO) - return ioport_map(start, len); - if (flags & IORESOURCE_MEM) { - if (flags & IORESOURCE_CACHEABLE) - return ioremap(start, len); - return ioremap_nocache(start, len); - } - return NULL; -} -EXPORT_SYMBOL(pci_iomap); - void pci_iounmap(struct pci_dev *dev, void __iomem *addr) { if ((unsigned long)addr >= VMALLOC_START && diff --git a/arch/arm/plat-iop/pci.c b/arch/arm/plat-iop/pci.c index 845549cbbb2..f4d40a27111 100644 --- a/arch/arm/plat-iop/pci.c +++ b/arch/arm/plat-iop/pci.c @@ -215,16 +215,16 @@ int iop3xx_pci_setup(int nr, struct pci_sys_data *sys) sys->mem_offset = IOP3XX_PCI_LOWER_MEM_PA - *IOP3XX_OMWTVR0; sys->io_offset = IOP3XX_PCI_LOWER_IO_PA - *IOP3XX_OIOWTVR; - sys->resource[0] = &res[0]; - sys->resource[1] = &res[1]; - sys->resource[2] = NULL; + pci_add_resource(&sys->resources, &res[0]); + pci_add_resource(&sys->resources, &res[1]); return 1; } struct pci_bus *iop3xx_pci_scan_bus(int nr, struct pci_sys_data *sys) { - return pci_scan_bus(sys->busnr, &iop3xx_ops, sys); + return pci_scan_root_bus(NULL, sys->busnr, &iop3xx_ops, sys, + &sys->resources); } void __init iop3xx_atu_setup(void) diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h index 83cca9bcfc9..1bf0df81bdc 100644 --- a/arch/arm/plat-mxc/include/mach/common.h +++ b/arch/arm/plat-mxc/include/mach/common.h @@ -131,6 +131,12 @@ extern void imx53_evk_common_init(void); extern void imx53_qsb_common_init(void); extern void imx53_smd_common_init(void); extern int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode); -extern void imx6q_pm_init(void); extern void imx6q_clock_map_io(void); + +#ifdef CONFIG_PM +extern void imx6q_pm_init(void); +#else +static inline void imx6q_pm_init(void) {} +#endif + #endif diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx25.h b/arch/arm/plat-mxc/include/mach/iomux-mx25.h index bf64e1e594e..f0726d48df2 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx25.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx25.h @@ -265,16 +265,20 @@ #define MX25_PAD_CSI_D2__CSI_D2 IOMUX_PAD(0x318, 0x120, 0x10, 0, 0, NO_PAD_CTRL) #define MX25_PAD_CSI_D2__UART5_RXD_MUX IOMUX_PAD(0x318, 0x120, 0x11, 0x578, 1, NO_PAD_CTRL) #define MX25_PAD_CSI_D2__GPIO_1_27 IOMUX_PAD(0x318, 0x120, 0x15, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_D2__CSPI3_MOSI IOMUX_PAD(0x318, 0x120, 0x17, 0, 0, NO_PAD_CTRL) #define MX25_PAD_CSI_D3__CSI_D3 IOMUX_PAD(0x31c, 0x124, 0x10, 0, 0, NO_PAD_CTRL) #define MX25_PAD_CSI_D3__GPIO_1_28 IOMUX_PAD(0x31c, 0x124, 0x15, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_D3__CSPI3_MISO IOMUX_PAD(0x31c, 0x124, 0x17, 0x4b4, 1, NO_PAD_CTRL) #define MX25_PAD_CSI_D4__CSI_D4 IOMUX_PAD(0x320, 0x128, 0x10, 0, 0, NO_PAD_CTRL) #define MX25_PAD_CSI_D4__UART5_RTS IOMUX_PAD(0x320, 0x128, 0x11, 0x574, 1, NO_PAD_CTRL) #define MX25_PAD_CSI_D4__GPIO_1_29 IOMUX_PAD(0x320, 0x128, 0x15, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_D4__CSPI3_SCLK IOMUX_PAD(0x320, 0x128, 0x17, 0, 0, NO_PAD_CTRL) #define MX25_PAD_CSI_D5__CSI_D5 IOMUX_PAD(0x324, 0x12c, 0x10, 0, 0, NO_PAD_CTRL) #define MX25_PAD_CSI_D5__GPIO_1_30 IOMUX_PAD(0x324, 0x12c, 0x15, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_D5__CSPI3_RDY IOMUX_PAD(0x324, 0x12c, 0x17, 0, 0, NO_PAD_CTRL) #define MX25_PAD_CSI_D6__CSI_D6 IOMUX_PAD(0x328, 0x130, 0x10, 0, 0, NO_PAD_CTRL) #define MX25_PAD_CSI_D6__GPIO_1_31 IOMUX_PAD(0x328, 0x130, 0x15, 0, 0, NO_PAD_CTRL) diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h index a4d36d601d5..d78298366a9 100644 --- a/arch/arm/plat-mxc/include/mach/mxc.h +++ b/arch/arm/plat-mxc/include/mach/mxc.h @@ -168,7 +168,7 @@ struct cpu_op { u32 cpu_rate; }; -int tzic_enable_wake(int is_idle); +int tzic_enable_wake(void); extern struct cpu_op *(*get_cpu_op)(int *op); #endif diff --git a/arch/arm/plat-mxc/tzic.c b/arch/arm/plat-mxc/tzic.c index a3c164c7ba8..98308ec1f32 100644 --- a/arch/arm/plat-mxc/tzic.c +++ b/arch/arm/plat-mxc/tzic.c @@ -73,7 +73,28 @@ static int tzic_set_irq_fiq(unsigned int irq, unsigned int type) #define tzic_set_irq_fiq NULL #endif -static unsigned int *wakeup_intr[4]; +#ifdef CONFIG_PM +static void tzic_irq_suspend(struct irq_data *d) +{ + struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); + int idx = gc->irq_base >> 5; + + __raw_writel(gc->wake_active, tzic_base + TZIC_WAKEUP0(idx)); +} + +static void tzic_irq_resume(struct irq_data *d) +{ + struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); + int idx = gc->irq_base >> 5; + + __raw_writel(__raw_readl(tzic_base + TZIC_ENSET0(idx)), + tzic_base + TZIC_WAKEUP0(idx)); +} + +#else +#define tzic_irq_suspend NULL +#define tzic_irq_resume NULL +#endif static struct mxc_extra_irq tzic_extra_irq = { #ifdef CONFIG_FIQ @@ -91,12 +112,13 @@ static __init void tzic_init_gc(unsigned int irq_start) handle_level_irq); gc->private = &tzic_extra_irq; gc->wake_enabled = IRQ_MSK(32); - wakeup_intr[idx] = &gc->wake_active; ct = gc->chip_types; ct->chip.irq_mask = irq_gc_mask_disable_reg; ct->chip.irq_unmask = irq_gc_unmask_enable_reg; ct->chip.irq_set_wake = irq_gc_set_wake; + ct->chip.irq_suspend = tzic_irq_suspend; + ct->chip.irq_resume = tzic_irq_resume; ct->regs.disable = TZIC_ENCLEAR0(idx); ct->regs.enable = TZIC_ENSET0(idx); @@ -167,23 +189,19 @@ void __init tzic_init_irq(void __iomem *irqbase) /** * tzic_enable_wake() - enable wakeup interrupt * - * @param is_idle 1 if called in idle loop (ENSET0 register); - * 0 to be used when called from low power entry * @return 0 if successful; non-zero otherwise */ -int tzic_enable_wake(int is_idle) +int tzic_enable_wake(void) { - unsigned int i, v; + unsigned int i; __raw_writel(1, tzic_base + TZIC_DSMINT); if (unlikely(__raw_readl(tzic_base + TZIC_DSMINT) == 0)) return -EAGAIN; - for (i = 0; i < 4; i++) { - v = is_idle ? __raw_readl(tzic_base + TZIC_ENSET0(i)) : - *wakeup_intr[i]; - __raw_writel(v, tzic_base + TZIC_WAKEUP0(i)); - } + for (i = 0; i < 4; i++) + __raw_writel(__raw_readl(tzic_base + TZIC_ENSET0(i)), + tzic_base + TZIC_WAKEUP0(i)); return 0; } diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile index 3df04d944e4..9a584614e7e 100644 --- a/arch/arm/plat-omap/Makefile +++ b/arch/arm/plat-omap/Makefile @@ -19,7 +19,6 @@ obj-$(CONFIG_ARCH_OMAP4) += omap_device.o obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o -obj-$(CONFIG_CPU_FREQ) += cpu-omap.o obj-$(CONFIG_OMAP_DM_TIMER) += dmtimer.o obj-$(CONFIG_OMAP_DEBUG_DEVICES) += debug-devices.o obj-$(CONFIG_OMAP_DEBUG_LEDS) += debug-leds.o diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c index 2ee6341fffd..06383b51e65 100644 --- a/arch/arm/plat-omap/common.c +++ b/arch/arm/plat-omap/common.c @@ -22,6 +22,8 @@ #include <plat/vram.h> #include <plat/dsp.h> +#include <plat/omap-secure.h> + #define NO_LENGTH_CHECK 0xffffffff @@ -66,6 +68,7 @@ void __init omap_reserve(void) omapfb_reserve_sdram_memblock(); omap_vram_reserve_sdram_memblock(); omap_dsp_reserve_sdram_memblock(); + omap_secure_ram_reserve_memblock(); } void __init omap_init_consistent_dma_size(void) diff --git a/arch/arm/plat-omap/cpu-omap.c b/arch/arm/plat-omap/cpu-omap.c deleted file mode 100644 index da4f68dbba1..00000000000 --- a/arch/arm/plat-omap/cpu-omap.c +++ /dev/null @@ -1,171 +0,0 @@ -/* - * linux/arch/arm/plat-omap/cpu-omap.c - * - * CPU frequency scaling for OMAP - * - * Copyright (C) 2005 Nokia Corporation - * Written by Tony Lindgren <tony@atomide.com> - * - * Based on cpu-sa1110.c, Copyright (C) 2001 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include <linux/types.h> -#include <linux/kernel.h> -#include <linux/sched.h> -#include <linux/cpufreq.h> -#include <linux/delay.h> -#include <linux/init.h> -#include <linux/err.h> -#include <linux/clk.h> -#include <linux/io.h> - -#include <mach/hardware.h> -#include <plat/clock.h> -#include <asm/system.h> - -#define VERY_HI_RATE 900000000 - -static struct cpufreq_frequency_table *freq_table; - -#ifdef CONFIG_ARCH_OMAP1 -#define MPU_CLK "mpu" -#else -#define MPU_CLK "virt_prcm_set" -#endif - -static struct clk *mpu_clk; - -/* TODO: Add support for SDRAM timing changes */ - -static int omap_verify_speed(struct cpufreq_policy *policy) -{ - if (freq_table) - return cpufreq_frequency_table_verify(policy, freq_table); - - if (policy->cpu) - return -EINVAL; - - cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, - policy->cpuinfo.max_freq); - - policy->min = clk_round_rate(mpu_clk, policy->min * 1000) / 1000; - policy->max = clk_round_rate(mpu_clk, policy->max * 1000) / 1000; - cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, - policy->cpuinfo.max_freq); - return 0; -} - -static unsigned int omap_getspeed(unsigned int cpu) -{ - unsigned long rate; - - if (cpu) - return 0; - - rate = clk_get_rate(mpu_clk) / 1000; - return rate; -} - -static int omap_target(struct cpufreq_policy *policy, - unsigned int target_freq, - unsigned int relation) -{ - struct cpufreq_freqs freqs; - int ret = 0; - - /* Ensure desired rate is within allowed range. Some govenors - * (ondemand) will just pass target_freq=0 to get the minimum. */ - if (target_freq < policy->min) - target_freq = policy->min; - if (target_freq > policy->max) - target_freq = policy->max; - - freqs.old = omap_getspeed(0); - freqs.new = clk_round_rate(mpu_clk, target_freq * 1000) / 1000; - freqs.cpu = 0; - - if (freqs.old == freqs.new) - return ret; - - cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); -#ifdef CONFIG_CPU_FREQ_DEBUG - printk(KERN_DEBUG "cpufreq-omap: transition: %u --> %u\n", - freqs.old, freqs.new); -#endif - ret = clk_set_rate(mpu_clk, freqs.new * 1000); - cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); - - return ret; -} - -static int __cpuinit omap_cpu_init(struct cpufreq_policy *policy) -{ - int result = 0; - - mpu_clk = clk_get(NULL, MPU_CLK); - if (IS_ERR(mpu_clk)) - return PTR_ERR(mpu_clk); - - if (policy->cpu != 0) - return -EINVAL; - - policy->cur = policy->min = policy->max = omap_getspeed(0); - - clk_init_cpufreq_table(&freq_table); - if (freq_table) { - result = cpufreq_frequency_table_cpuinfo(policy, freq_table); - if (!result) - cpufreq_frequency_table_get_attr(freq_table, - policy->cpu); - } else { - policy->cpuinfo.min_freq = clk_round_rate(mpu_clk, 0) / 1000; - policy->cpuinfo.max_freq = clk_round_rate(mpu_clk, - VERY_HI_RATE) / 1000; - } - - /* FIXME: what's the actual transition time? */ - policy->cpuinfo.transition_latency = 300 * 1000; - - return 0; -} - -static int omap_cpu_exit(struct cpufreq_policy *policy) -{ - clk_exit_cpufreq_table(&freq_table); - clk_put(mpu_clk); - return 0; -} - -static struct freq_attr *omap_cpufreq_attr[] = { - &cpufreq_freq_attr_scaling_available_freqs, - NULL, -}; - -static struct cpufreq_driver omap_driver = { - .flags = CPUFREQ_STICKY, - .verify = omap_verify_speed, - .target = omap_target, - .get = omap_getspeed, - .init = omap_cpu_init, - .exit = omap_cpu_exit, - .name = "omap", - .attr = omap_cpufreq_attr, -}; - -static int __init omap_cpufreq_init(void) -{ - return cpufreq_register_driver(&omap_driver); -} - -arch_initcall(omap_cpufreq_init); - -/* - * if ever we want to remove this, upon cleanup call: - * - * cpufreq_unregister_driver() - * cpufreq_frequency_table_put_attr() - */ - diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c index c22217c2ee5..002fb4d96bb 100644 --- a/arch/arm/plat-omap/dma.c +++ b/arch/arm/plat-omap/dma.c @@ -1034,6 +1034,18 @@ dma_addr_t omap_get_dma_src_pos(int lch) if (IS_DMA_ERRATA(DMA_ERRATA_3_3) && offset == 0) offset = p->dma_read(CSAC, lch); + if (!cpu_is_omap15xx()) { + /* + * CDAC == 0 indicates that the DMA transfer on the channel has + * not been started (no data has been transferred so far). + * Return the programmed source start address in this case. + */ + if (likely(p->dma_read(CDAC, lch))) + offset = p->dma_read(CSAC, lch); + else + offset = p->dma_read(CSSA, lch); + } + if (cpu_class_is_omap1()) offset |= (p->dma_read(CSSA, lch) & 0xFFFF0000); @@ -1062,8 +1074,16 @@ dma_addr_t omap_get_dma_dst_pos(int lch) * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is * read before the DMA controller finished disabling the channel. */ - if (!cpu_is_omap15xx() && offset == 0) + if (!cpu_is_omap15xx() && offset == 0) { offset = p->dma_read(CDAC, lch); + /* + * CDAC == 0 indicates that the DMA transfer on the channel has + * not been started (no data has been transferred so far). + * Return the programmed destination start address in this case. + */ + if (unlikely(!offset)) + offset = p->dma_read(CDSA, lch); + } if (cpu_class_is_omap1()) offset |= (p->dma_read(CDSA, lch) & 0xFFFF0000); diff --git a/arch/arm/plat-omap/include/plat/am33xx.h b/arch/arm/plat-omap/include/plat/am33xx.h new file mode 100644 index 00000000000..06c19bb7bca --- /dev/null +++ b/arch/arm/plat-omap/include/plat/am33xx.h @@ -0,0 +1,25 @@ +/* + * This file contains the address info for various AM33XX modules. + * + * Copyright (C) 2011 Texas Instruments, Inc. - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __ASM_ARCH_AM33XX_H +#define __ASM_ARCH_AM33XX_H + +#define L4_SLOW_AM33XX_BASE 0x48000000 + +#define AM33XX_SCM_BASE 0x44E10000 +#define AM33XX_CTRL_BASE AM33XX_SCM_BASE +#define AM33XX_PRCM_BASE 0x44E00000 + +#endif /* __ASM_ARCH_AM33XX_H */ diff --git a/arch/arm/plat-omap/include/plat/clkdev_omap.h b/arch/arm/plat-omap/include/plat/clkdev_omap.h index 387a9638991..b299b8d201c 100644 --- a/arch/arm/plat-omap/include/plat/clkdev_omap.h +++ b/arch/arm/plat-omap/include/plat/clkdev_omap.h @@ -40,6 +40,7 @@ struct omap_clk { #define CK_443X (1 << 11) #define CK_TI816X (1 << 12) #define CK_446X (1 << 13) +#define CK_1710 (1 << 15) /* 1710 extra for rate selection */ #define CK_34XX (CK_3430ES1 | CK_3430ES2PLUS) diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h index eb73ab40e95..240a7b9fd94 100644 --- a/arch/arm/plat-omap/include/plat/clock.h +++ b/arch/arm/plat-omap/include/plat/clock.h @@ -59,6 +59,8 @@ struct clkops { #define RATE_IN_4430 (1 << 5) #define RATE_IN_TI816X (1 << 6) #define RATE_IN_4460 (1 << 7) +#define RATE_IN_AM33XX (1 << 8) +#define RATE_IN_TI814X (1 << 9) #define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X) #define RATE_IN_34XX (RATE_IN_3430ES1 | RATE_IN_3430ES2PLUS) @@ -84,7 +86,7 @@ struct clkops { struct clksel_rate { u32 val; u8 div; - u8 flags; + u16 flags; }; /** diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h index 408a12f7920..6b51086fce1 100644 --- a/arch/arm/plat-omap/include/plat/cpu.h +++ b/arch/arm/plat-omap/include/plat/cpu.h @@ -69,6 +69,7 @@ unsigned int omap_rev(void); * cpu_is_omap343x(): True for OMAP3430 * cpu_is_omap443x(): True for OMAP4430 * cpu_is_omap446x(): True for OMAP4460 + * cpu_is_omap447x(): True for OMAP4470 */ #define GET_OMAP_CLASS (omap_rev() & 0xff) @@ -78,6 +79,22 @@ static inline int is_omap ##class (void) \ return (GET_OMAP_CLASS == (id)) ? 1 : 0; \ } +#define GET_AM_CLASS ((omap_rev() >> 24) & 0xff) + +#define IS_AM_CLASS(class, id) \ +static inline int is_am ##class (void) \ +{ \ + return (GET_AM_CLASS == (id)) ? 1 : 0; \ +} + +#define GET_TI_CLASS ((omap_rev() >> 24) & 0xff) + +#define IS_TI_CLASS(class, id) \ +static inline int is_ti ##class (void) \ +{ \ + return (GET_TI_CLASS == (id)) ? 1 : 0; \ +} + #define GET_OMAP_SUBCLASS ((omap_rev() >> 20) & 0x0fff) #define IS_OMAP_SUBCLASS(subclass, id) \ @@ -92,12 +109,21 @@ static inline int is_ti ##subclass (void) \ return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0; \ } +#define IS_AM_SUBCLASS(subclass, id) \ +static inline int is_am ##subclass (void) \ +{ \ + return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0; \ +} + IS_OMAP_CLASS(7xx, 0x07) IS_OMAP_CLASS(15xx, 0x15) IS_OMAP_CLASS(16xx, 0x16) IS_OMAP_CLASS(24xx, 0x24) IS_OMAP_CLASS(34xx, 0x34) IS_OMAP_CLASS(44xx, 0x44) +IS_AM_CLASS(33xx, 0x33) + +IS_TI_CLASS(81xx, 0x81) IS_OMAP_SUBCLASS(242x, 0x242) IS_OMAP_SUBCLASS(243x, 0x243) @@ -105,8 +131,11 @@ IS_OMAP_SUBCLASS(343x, 0x343) IS_OMAP_SUBCLASS(363x, 0x363) IS_OMAP_SUBCLASS(443x, 0x443) IS_OMAP_SUBCLASS(446x, 0x446) +IS_OMAP_SUBCLASS(447x, 0x447) IS_TI_SUBCLASS(816x, 0x816) +IS_TI_SUBCLASS(814x, 0x814) +IS_AM_SUBCLASS(335x, 0x335) #define cpu_is_omap7xx() 0 #define cpu_is_omap15xx() 0 @@ -116,10 +145,15 @@ IS_TI_SUBCLASS(816x, 0x816) #define cpu_is_omap243x() 0 #define cpu_is_omap34xx() 0 #define cpu_is_omap343x() 0 +#define cpu_is_ti81xx() 0 #define cpu_is_ti816x() 0 +#define cpu_is_ti814x() 0 +#define cpu_is_am33xx() 0 +#define cpu_is_am335x() 0 #define cpu_is_omap44xx() 0 #define cpu_is_omap443x() 0 #define cpu_is_omap446x() 0 +#define cpu_is_omap447x() 0 #if defined(MULTI_OMAP1) # if defined(CONFIG_ARCH_OMAP730) @@ -322,7 +356,11 @@ IS_OMAP_TYPE(3517, 0x3517) # undef cpu_is_omap3530 # undef cpu_is_omap3505 # undef cpu_is_omap3517 +# undef cpu_is_ti81xx # undef cpu_is_ti816x +# undef cpu_is_ti814x +# undef cpu_is_am33xx +# undef cpu_is_am335x # define cpu_is_omap3430() is_omap3430() # define cpu_is_omap3503() (cpu_is_omap3430() && \ (!omap3_has_iva()) && \ @@ -339,16 +377,22 @@ IS_OMAP_TYPE(3517, 0x3517) !omap3_has_sgx()) # undef cpu_is_omap3630 # define cpu_is_omap3630() is_omap363x() +# define cpu_is_ti81xx() is_ti81xx() # define cpu_is_ti816x() is_ti816x() +# define cpu_is_ti814x() is_ti814x() +# define cpu_is_am33xx() is_am33xx() +# define cpu_is_am335x() is_am335x() #endif # if defined(CONFIG_ARCH_OMAP4) # undef cpu_is_omap44xx # undef cpu_is_omap443x # undef cpu_is_omap446x +# undef cpu_is_omap447x # define cpu_is_omap44xx() is_omap44xx() # define cpu_is_omap443x() is_omap443x() # define cpu_is_omap446x() is_omap446x() +# define cpu_is_omap447x() is_omap447x() # endif /* Macros to detect if we have OMAP1 or OMAP2 */ @@ -386,15 +430,27 @@ IS_OMAP_TYPE(3517, 0x3517) #define TI8168_REV_ES1_0 TI816X_CLASS #define TI8168_REV_ES1_1 (TI816X_CLASS | (0x1 << 8)) +#define TI814X_CLASS 0x81400034 +#define TI8148_REV_ES1_0 TI814X_CLASS +#define TI8148_REV_ES2_0 (TI814X_CLASS | (0x1 << 8)) +#define TI8148_REV_ES2_1 (TI814X_CLASS | (0x2 << 8)) + +#define AM335X_CLASS 0x33500034 +#define AM335X_REV_ES1_0 AM335X_CLASS + #define OMAP443X_CLASS 0x44300044 #define OMAP4430_REV_ES1_0 (OMAP443X_CLASS | (0x10 << 8)) #define OMAP4430_REV_ES2_0 (OMAP443X_CLASS | (0x20 << 8)) #define OMAP4430_REV_ES2_1 (OMAP443X_CLASS | (0x21 << 8)) #define OMAP4430_REV_ES2_2 (OMAP443X_CLASS | (0x22 << 8)) +#define OMAP4430_REV_ES2_3 (OMAP443X_CLASS | (0x23 << 8)) #define OMAP446X_CLASS 0x44600044 #define OMAP4460_REV_ES1_0 (OMAP446X_CLASS | (0x10 << 8)) +#define OMAP447X_CLASS 0x44700044 +#define OMAP4470_REV_ES1_0 (OMAP447X_CLASS | (0x10 << 8)) + void omap2_check_revision(void); /* diff --git a/arch/arm/plat-omap/include/plat/hardware.h b/arch/arm/plat-omap/include/plat/hardware.h index e87efe1499b..e897978371c 100644 --- a/arch/arm/plat-omap/include/plat/hardware.h +++ b/arch/arm/plat-omap/include/plat/hardware.h @@ -286,6 +286,7 @@ #include <plat/omap24xx.h> #include <plat/omap34xx.h> #include <plat/omap44xx.h> -#include <plat/ti816x.h> +#include <plat/ti81xx.h> +#include <plat/am33xx.h> #endif /* __ASM_ARCH_OMAP_HARDWARE_H */ diff --git a/arch/arm/plat-omap/include/plat/io.h b/arch/arm/plat-omap/include/plat/io.h index 1234944a4da..0696bae1818 100644 --- a/arch/arm/plat-omap/include/plat/io.h +++ b/arch/arm/plat-omap/include/plat/io.h @@ -73,6 +73,9 @@ #define OMAP4_L3_IO_OFFSET 0xb4000000 #define OMAP4_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_L3_IO_OFFSET) /* L3 */ +#define AM33XX_L4_WK_IO_OFFSET 0xb5000000 +#define AM33XX_L4_WK_IO_ADDRESS(pa) IOMEM((pa) + AM33XX_L4_WK_IO_OFFSET) + #define OMAP4_L3_PER_IO_OFFSET 0xb1100000 #define OMAP4_L3_PER_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_L3_PER_IO_OFFSET) @@ -154,6 +157,15 @@ #define L4_34XX_SIZE SZ_4M /* 1MB of 128MB used, want 1MB sect */ /* + * ---------------------------------------------------------------------------- + * AM33XX specific IO mapping + * ---------------------------------------------------------------------------- + */ +#define L4_WK_AM33XX_PHYS L4_WK_AM33XX_BASE +#define L4_WK_AM33XX_VIRT (L4_WK_AM33XX_PHYS + AM33XX_L4_WK_IO_OFFSET) +#define L4_WK_AM33XX_SIZE SZ_4M /* 1MB of 128MB used, want 1MB sect */ + +/* * Need to look at the Size 4M for L4. * VPOM3430 was not working for Int controller */ diff --git a/arch/arm/plat-omap/include/plat/iommu.h b/arch/arm/plat-omap/include/plat/iommu.h index a1d79ee1925..88be3e628b3 100644 --- a/arch/arm/plat-omap/include/plat/iommu.h +++ b/arch/arm/plat-omap/include/plat/iommu.h @@ -111,6 +111,32 @@ struct iommu_platform_data { u32 da_end; }; +/** + * struct iommu_arch_data - omap iommu private data + * @name: name of the iommu device + * @iommu_dev: handle of the iommu device + * + * This is an omap iommu private data object, which binds an iommu user + * to its iommu device. This object should be placed at the iommu user's + * dev_archdata so generic IOMMU API can be used without having to + * utilize omap-specific plumbing anymore. + */ +struct omap_iommu_arch_data { + const char *name; + struct omap_iommu *iommu_dev; +}; + +/** + * dev_to_omap_iommu() - retrieves an omap iommu object from a user device + * @dev: iommu client device + */ +static inline struct omap_iommu *dev_to_omap_iommu(struct device *dev) +{ + struct omap_iommu_arch_data *arch_data = dev->archdata.iommu; + + return arch_data->iommu_dev; +} + /* IOMMU errors */ #define OMAP_IOMMU_ERR_TLB_MISS (1 << 0) #define OMAP_IOMMU_ERR_TRANS_FAULT (1 << 1) @@ -163,8 +189,8 @@ extern int omap_iommu_set_isr(const char *name, void *priv), void *isr_priv); -extern void omap_iommu_save_ctx(struct omap_iommu *obj); -extern void omap_iommu_restore_ctx(struct omap_iommu *obj); +extern void omap_iommu_save_ctx(struct device *dev); +extern void omap_iommu_restore_ctx(struct device *dev); extern int omap_install_iommu_arch(const struct iommu_functions *ops); extern void omap_uninstall_iommu_arch(const struct iommu_functions *ops); @@ -176,6 +202,5 @@ extern ssize_t omap_iommu_dump_ctx(struct omap_iommu *obj, char *buf, ssize_t len); extern size_t omap_dump_tlb_entries(struct omap_iommu *obj, char *buf, ssize_t len); -struct device *omap_find_iommu_device(const char *name); #endif /* __MACH_IOMMU_H */ diff --git a/arch/arm/plat-omap/include/plat/iovmm.h b/arch/arm/plat-omap/include/plat/iovmm.h index 6af1a91c0f3..498e57cda6c 100644 --- a/arch/arm/plat-omap/include/plat/iovmm.h +++ b/arch/arm/plat-omap/include/plat/iovmm.h @@ -72,18 +72,18 @@ struct iovm_struct { #define IOVMF_DA_FIXED (1 << (4 + IOVMF_SW_SHIFT)) -extern struct iovm_struct *omap_find_iovm_area(struct omap_iommu *obj, u32 da); +extern struct iovm_struct *omap_find_iovm_area(struct device *dev, u32 da); extern u32 -omap_iommu_vmap(struct iommu_domain *domain, struct omap_iommu *obj, u32 da, +omap_iommu_vmap(struct iommu_domain *domain, struct device *dev, u32 da, const struct sg_table *sgt, u32 flags); extern struct sg_table *omap_iommu_vunmap(struct iommu_domain *domain, - struct omap_iommu *obj, u32 da); + struct device *dev, u32 da); extern u32 -omap_iommu_vmalloc(struct iommu_domain *domain, struct omap_iommu *obj, +omap_iommu_vmalloc(struct iommu_domain *domain, struct device *dev, u32 da, size_t bytes, u32 flags); extern void -omap_iommu_vfree(struct iommu_domain *domain, struct omap_iommu *obj, +omap_iommu_vfree(struct iommu_domain *domain, struct device *dev, const u32 da); -extern void *omap_da_to_va(struct omap_iommu *obj, u32 da); +extern void *omap_da_to_va(struct device *dev, u32 da); #endif /* __IOMMU_MMAP_H */ diff --git a/arch/arm/plat-omap/include/plat/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h index ebda7382c65..2efd6454bce 100644 --- a/arch/arm/plat-omap/include/plat/irqs.h +++ b/arch/arm/plat-omap/include/plat/irqs.h @@ -357,7 +357,7 @@ #define INT_35XX_EMAC_C0_TX_PULSE_IRQ 69 #define INT_35XX_EMAC_C0_MISC_PULSE_IRQ 70 #define INT_35XX_USBOTG_IRQ 71 -#define INT_35XX_UART4 84 +#define INT_35XX_UART4_IRQ 84 #define INT_35XX_CCDC_VD0_IRQ 88 #define INT_35XX_CCDC_VD1_IRQ 92 #define INT_35XX_CCDC_VD2_IRQ 93 diff --git a/arch/arm/plat-omap/include/plat/mmc.h b/arch/arm/plat-omap/include/plat/mmc.h index 94cf70afb23..f75946c3293 100644 --- a/arch/arm/plat-omap/include/plat/mmc.h +++ b/arch/arm/plat-omap/include/plat/mmc.h @@ -96,6 +96,7 @@ struct omap_mmc_platform_data { */ u8 wires; /* Used for the MMC driver on omap1 and 2420 */ u32 caps; /* Used for the MMC driver on 2430 and later */ + u32 pm_caps; /* PM capabilities of the mmc */ /* * nomux means "standard" muxing is wrong on this board, and diff --git a/arch/arm/plat-omap/include/plat/omap-secure.h b/arch/arm/plat-omap/include/plat/omap-secure.h new file mode 100644 index 00000000000..64f9d1c7f1b --- /dev/null +++ b/arch/arm/plat-omap/include/plat/omap-secure.h @@ -0,0 +1,13 @@ +#ifndef __OMAP_SECURE_H__ +#define __OMAP_SECURE_H__ + +#include <linux/types.h> + +#ifdef CONFIG_ARCH_OMAP2PLUS +extern int omap_secure_ram_reserve_memblock(void); +#else +static inline void omap_secure_ram_reserve_memblock(void) +{ } +#endif + +#endif /* __OMAP_SECURE_H__ */ diff --git a/arch/arm/plat-omap/include/plat/omap-serial.h b/arch/arm/plat-omap/include/plat/omap-serial.h index 2682043f5a5..9ff444469f3 100644 --- a/arch/arm/plat-omap/include/plat/omap-serial.h +++ b/arch/arm/plat-omap/include/plat/omap-serial.h @@ -19,6 +19,7 @@ #include <linux/serial_core.h> #include <linux/platform_device.h> +#include <linux/pm_qos.h> #include <plat/mux.h> @@ -33,6 +34,8 @@ #define OMAP_MODE13X_SPEED 230400 +#define OMAP_UART_SCR_TX_EMPTY 0x08 + /* WER = 0x7F * Enable module level wakeup in WER reg */ @@ -51,18 +54,27 @@ #define OMAP_UART_DMA_CH_FREE -1 -#define RX_TIMEOUT (3 * HZ) #define OMAP_MAX_HSUART_PORTS 4 #define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA +#define UART_ERRATA_i202_MDR1_ACCESS BIT(0) +#define UART_ERRATA_i291_DMA_FORCEIDLE BIT(1) + struct omap_uart_port_info { bool dma_enabled; /* To specify DMA Mode */ unsigned int uartclk; /* UART clock rate */ - void __iomem *membase; /* ioremap cookie or NULL */ - resource_size_t mapbase; /* resource base */ - unsigned long irqflags; /* request_irq flags */ upf_t flags; /* UPF_* flags */ + u32 errata; + unsigned int dma_rx_buf_size; + unsigned int dma_rx_timeout; + unsigned int autosuspend_timeout; + unsigned int dma_rx_poll_rate; + + int (*get_context_loss_count)(struct device *); + void (*set_forceidle)(struct platform_device *); + void (*set_noidle)(struct platform_device *); + void (*enable_wakeup)(struct platform_device *, bool); }; struct uart_omap_dma { @@ -86,8 +98,9 @@ struct uart_omap_dma { spinlock_t rx_lock; /* timer to poll activity on rx dma */ struct timer_list rx_timer; - int rx_buf_size; - int rx_timeout; + unsigned int rx_buf_size; + unsigned int rx_poll_rate; + unsigned int rx_timeout; }; struct uart_omap_port { @@ -100,6 +113,10 @@ struct uart_omap_port { unsigned char mcr; unsigned char fcr; unsigned char efr; + unsigned char dll; + unsigned char dlh; + unsigned char mdr1; + unsigned char scr; int use_dma; /* @@ -111,6 +128,14 @@ struct uart_omap_port { unsigned char msr_saved_flags; char name[20]; unsigned long port_activity; + u32 context_loss_cnt; + u32 errata; + u8 wakeups_enabled; + + struct pm_qos_request pm_qos_request; + u32 latency; + u32 calc_latency; + struct work_struct qos_work; }; #endif /* __OMAP_SERIAL_H__ */ diff --git a/arch/arm/plat-omap/include/plat/omap34xx.h b/arch/arm/plat-omap/include/plat/omap34xx.h index b9e85886b9d..0d818acf391 100644 --- a/arch/arm/plat-omap/include/plat/omap34xx.h +++ b/arch/arm/plat-omap/include/plat/omap34xx.h @@ -35,6 +35,8 @@ #define L4_EMU_34XX_BASE 0x54000000 #define L3_34XX_BASE 0x68000000 +#define L4_WK_AM33XX_BASE 0x44C00000 + #define OMAP3430_32KSYNCT_BASE 0x48320000 #define OMAP3430_CM_BASE 0x48004800 #define OMAP3430_PRM_BASE 0x48306800 diff --git a/arch/arm/plat-omap/include/plat/omap44xx.h b/arch/arm/plat-omap/include/plat/omap44xx.h index ea2b8a6306e..c0d478e55c8 100644 --- a/arch/arm/plat-omap/include/plat/omap44xx.h +++ b/arch/arm/plat-omap/include/plat/omap44xx.h @@ -45,6 +45,7 @@ #define OMAP44XX_WKUPGEN_BASE 0x48281000 #define OMAP44XX_MCPDM_BASE 0x40132000 #define OMAP44XX_MCPDM_L3_BASE 0x49032000 +#define OMAP44XX_SAR_RAM_BASE 0x4a326000 #define OMAP44XX_MAILBOX_BASE (L4_44XX_BASE + 0xF4000) #define OMAP44XX_HSUSB_OTG_BASE (L4_44XX_BASE + 0xAB000) diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h index 8b372ede17c..647010109af 100644 --- a/arch/arm/plat-omap/include/plat/omap_hwmod.h +++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h @@ -97,6 +97,7 @@ struct omap_hwmod_mux_info { struct omap_device_pad *pads; int nr_pads_dynamic; struct omap_device_pad **pads_dynamic; + int *irqs; bool enabled; }; @@ -416,10 +417,13 @@ struct omap_hwmod_omap4_prcm { * _HWMOD_NO_MPU_PORT: no path exists for the MPU to write to this module * _HWMOD_WAKEUP_ENABLED: set when the omap_hwmod code has enabled ENAWAKEUP * _HWMOD_SYSCONFIG_LOADED: set when the OCP_SYSCONFIG value has been cached + * _HWMOD_SKIP_ENABLE: set if hwmod enabled during init (HWMOD_INIT_NO_IDLE) - + * causes the first call to _enable() to only update the pinmux */ #define _HWMOD_NO_MPU_PORT (1 << 0) #define _HWMOD_WAKEUP_ENABLED (1 << 1) #define _HWMOD_SYSCONFIG_LOADED (1 << 2) +#define _HWMOD_SKIP_ENABLE (1 << 3) /* * omap_hwmod._state definitions @@ -604,6 +608,8 @@ int omap_hwmod_get_context_loss_count(struct omap_hwmod *oh); int omap_hwmod_no_setup_reset(struct omap_hwmod *oh); +int omap_hwmod_pad_route_irq(struct omap_hwmod *oh, int pad_idx, int irq_idx); + /* * Chip variant-specific hwmod init routines - XXX should be converted * to use initcalls once the initial boot ordering is straightened out diff --git a/arch/arm/plat-omap/include/plat/serial.h b/arch/arm/plat-omap/include/plat/serial.h index 1ab9fd6abe6..198d1e6a4a6 100644 --- a/arch/arm/plat-omap/include/plat/serial.h +++ b/arch/arm/plat-omap/include/plat/serial.h @@ -2,7 +2,7 @@ * arch/arm/plat-omap/include/mach/serial.h * * Copyright (C) 2009 Texas Instruments - * Addded OMAP4 support- Santosh Shilimkar <santosh.shilimkar@ti.com> + * Added OMAP4 support- Santosh Shilimkar <santosh.shilimkar@ti.com> * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of @@ -44,6 +44,7 @@ #define OMAP3_UART2_BASE OMAP2_UART2_BASE #define OMAP3_UART3_BASE 0x49020000 #define OMAP3_UART4_BASE 0x49042000 /* Only on 36xx */ +#define OMAP3_UART4_AM35XX_BASE 0x4809E000 /* Only on AM35xx */ /* OMAP4 serial ports */ #define OMAP4_UART1_BASE OMAP2_UART1_BASE @@ -51,10 +52,10 @@ #define OMAP4_UART3_BASE 0x48020000 #define OMAP4_UART4_BASE 0x4806e000 -/* TI816X serial ports */ -#define TI816X_UART1_BASE 0x48020000 -#define TI816X_UART2_BASE 0x48022000 -#define TI816X_UART3_BASE 0x48024000 +/* TI81XX serial ports */ +#define TI81XX_UART1_BASE 0x48020000 +#define TI81XX_UART2_BASE 0x48022000 +#define TI81XX_UART3_BASE 0x48024000 /* AM3505/3517 UART4 */ #define AM35XX_UART4_BASE 0x4809E000 /* Only on AM3505/3517 */ @@ -89,9 +90,9 @@ #define OMAP4UART2 OMAP2UART2 #define OMAP4UART3 43 #define OMAP4UART4 44 -#define TI816XUART1 81 -#define TI816XUART2 82 -#define TI816XUART3 83 +#define TI81XXUART1 81 +#define TI81XXUART2 82 +#define TI81XXUART3 83 #define ZOOM_UART 95 /* Only on zoom2/3 */ /* This is only used by 8250.c for omap1510 */ @@ -106,15 +107,13 @@ #ifndef __ASSEMBLER__ struct omap_board_data; +struct omap_uart_port_info; extern void omap_serial_init(void); -extern void omap_serial_init_port(struct omap_board_data *bdata); extern int omap_uart_can_sleep(void); -extern void omap_uart_check_wakeup(void); -extern void omap_uart_prepare_suspend(void); -extern void omap_uart_prepare_idle(int num); -extern void omap_uart_resume_idle(int num); -extern void omap_uart_enable_irqs(int enable); +extern void omap_serial_board_init(struct omap_uart_port_info *platform_data); +extern void omap_serial_init_port(struct omap_board_data *bdata, + struct omap_uart_port_info *platform_data); #endif #endif diff --git a/arch/arm/plat-omap/include/plat/sram.h b/arch/arm/plat-omap/include/plat/sram.h index f500fc34d06..75aa1b2bef5 100644 --- a/arch/arm/plat-omap/include/plat/sram.h +++ b/arch/arm/plat-omap/include/plat/sram.h @@ -95,6 +95,10 @@ static inline void omap_push_sram_idle(void) {} */ #define OMAP2_SRAM_PA 0x40200000 #define OMAP3_SRAM_PA 0x40200000 +#ifdef CONFIG_OMAP4_ERRATA_I688 +#define OMAP4_SRAM_PA 0x40304000 +#define OMAP4_SRAM_VA 0xfe404000 +#else #define OMAP4_SRAM_PA 0x40300000 - +#endif #endif diff --git a/arch/arm/plat-omap/include/plat/ti816x.h b/arch/arm/plat-omap/include/plat/ti81xx.h index 50510f5dda1..8f9843f7842 100644 --- a/arch/arm/plat-omap/include/plat/ti816x.h +++ b/arch/arm/plat-omap/include/plat/ti81xx.h @@ -1,5 +1,5 @@ /* - * This file contains the address data for various TI816X modules. + * This file contains the address data for various TI81XX modules. * * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/ * @@ -13,15 +13,15 @@ * GNU General Public License for more details. */ -#ifndef __ASM_ARCH_TI816X_H -#define __ASM_ARCH_TI816X_H +#ifndef __ASM_ARCH_TI81XX_H +#define __ASM_ARCH_TI81XX_H -#define L4_SLOW_TI816X_BASE 0x48000000 +#define L4_SLOW_TI81XX_BASE 0x48000000 -#define TI816X_SCM_BASE 0x48140000 -#define TI816X_CTRL_BASE TI816X_SCM_BASE -#define TI816X_PRCM_BASE 0x48180000 +#define TI81XX_SCM_BASE 0x48140000 +#define TI81XX_CTRL_BASE TI81XX_SCM_BASE +#define TI81XX_PRCM_BASE 0x48180000 -#define TI816X_ARM_INTC_BASE 0x48200000 +#define TI81XX_ARM_INTC_BASE 0x48200000 -#endif /* __ASM_ARCH_TI816X_H */ +#endif /* __ASM_ARCH_TI81XX_H */ diff --git a/arch/arm/plat-omap/include/plat/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h index 2f472e989ec..6ee90495ca4 100644 --- a/arch/arm/plat-omap/include/plat/uncompress.h +++ b/arch/arm/plat-omap/include/plat/uncompress.h @@ -99,9 +99,9 @@ static inline void flush(void) #define DEBUG_LL_ZOOM(mach) \ _DEBUG_LL_ENTRY(mach, ZOOM_UART_BASE, ZOOM_PORT_SHIFT, ZOOM_UART) -#define DEBUG_LL_TI816X(p, mach) \ - _DEBUG_LL_ENTRY(mach, TI816X_UART##p##_BASE, OMAP_PORT_SHIFT, \ - TI816XUART##p) +#define DEBUG_LL_TI81XX(p, mach) \ + _DEBUG_LL_ENTRY(mach, TI81XX_UART##p##_BASE, OMAP_PORT_SHIFT, \ + TI81XXUART##p) static inline void __arch_decomp_setup(unsigned long arch_id) { @@ -177,7 +177,10 @@ static inline void __arch_decomp_setup(unsigned long arch_id) DEBUG_LL_ZOOM(omap_zoom3); /* TI8168 base boards using UART3 */ - DEBUG_LL_TI816X(3, ti8168evm); + DEBUG_LL_TI81XX(3, ti8168evm); + + /* TI8148 base boards using UART1 */ + DEBUG_LL_TI81XX(1, ti8148evm); } while (0); } diff --git a/arch/arm/plat-omap/include/plat/usb.h b/arch/arm/plat-omap/include/plat/usb.h index 17d3c939775..dc864b580da 100644 --- a/arch/arm/plat-omap/include/plat/usb.h +++ b/arch/arm/plat-omap/include/plat/usb.h @@ -100,9 +100,6 @@ extern void usb_musb_init(struct omap_musb_board_data *board_data); extern void usbhs_init(const struct usbhs_omap_board_data *pdata); -extern int omap_usbhs_enable(struct device *dev); -extern void omap_usbhs_disable(struct device *dev); - extern int omap4430_phy_power(struct device *dev, int ID, int on); extern int omap4430_phy_set_clk(struct device *dev, int on); extern int omap4430_phy_init(struct device *dev); @@ -114,6 +111,7 @@ extern void am35x_musb_reset(void); extern void am35x_musb_phy_power(u8 on); extern void am35x_musb_clear_irq(void); extern void am35x_set_mode(u8 musb_mode); +extern void ti81xx_musb_phy_power(u8 on); /* * FIXME correct answer depends on hmc_mode, @@ -273,6 +271,37 @@ static inline void omap2_usbfs_init(struct omap_usb_config *pdata) #define CONF2_OTGPWRDN (1 << 2) #define CONF2_DATPOL (1 << 1) +/* TI81XX specific definitions */ +#define USBCTRL0 0x620 +#define USBSTAT0 0x624 + +/* TI816X PHY controls bits */ +#define TI816X_USBPHY0_NORMAL_MODE (1 << 0) +#define TI816X_USBPHY_REFCLK_OSC (1 << 8) + +/* TI814X PHY controls bits */ +#define USBPHY_CM_PWRDN (1 << 0) +#define USBPHY_OTG_PWRDN (1 << 1) +#define USBPHY_CHGDET_DIS (1 << 2) +#define USBPHY_CHGDET_RSTRT (1 << 3) +#define USBPHY_SRCONDM (1 << 4) +#define USBPHY_SINKONDP (1 << 5) +#define USBPHY_CHGISINK_EN (1 << 6) +#define USBPHY_CHGVSRC_EN (1 << 7) +#define USBPHY_DMPULLUP (1 << 8) +#define USBPHY_DPPULLUP (1 << 9) +#define USBPHY_CDET_EXTCTL (1 << 10) +#define USBPHY_GPIO_MODE (1 << 12) +#define USBPHY_DPOPBUFCTL (1 << 13) +#define USBPHY_DMOPBUFCTL (1 << 14) +#define USBPHY_DPINPUT (1 << 15) +#define USBPHY_DMINPUT (1 << 16) +#define USBPHY_DPGPIO_PD (1 << 17) +#define USBPHY_DMGPIO_PD (1 << 18) +#define USBPHY_OTGVDET_EN (1 << 19) +#define USBPHY_OTGSESSEND_EN (1 << 20) +#define USBPHY_DATA_POLARITY (1 << 23) + #if defined(CONFIG_ARCH_OMAP1) && defined(CONFIG_USB) u32 omap1_usb0_init(unsigned nwires, unsigned is_device); u32 omap1_usb1_init(unsigned nwires); diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c index 8b28664d1c6..4243bdcc87b 100644 --- a/arch/arm/plat-omap/sram.c +++ b/arch/arm/plat-omap/sram.c @@ -40,7 +40,11 @@ #define OMAP1_SRAM_PA 0x20000000 #define OMAP2_SRAM_PUB_PA (OMAP2_SRAM_PA + 0xf800) #define OMAP3_SRAM_PUB_PA (OMAP3_SRAM_PA + 0x8000) +#ifdef CONFIG_OMAP4_ERRATA_I688 +#define OMAP4_SRAM_PUB_PA OMAP4_SRAM_PA +#else #define OMAP4_SRAM_PUB_PA (OMAP4_SRAM_PA + 0x4000) +#endif #if defined(CONFIG_ARCH_OMAP2PLUS) #define SRAM_BOOTLOADER_SZ 0x00 @@ -141,11 +145,9 @@ static void __init omap_detect_sram(void) omap_sram_size = 0x32000; /* 200K */ else if (cpu_is_omap15xx()) omap_sram_size = 0x30000; /* 192K */ - else if (cpu_is_omap1610() || cpu_is_omap1621() || - cpu_is_omap1710()) + else if (cpu_is_omap1610() || cpu_is_omap1611() || + cpu_is_omap1621() || cpu_is_omap1710()) omap_sram_size = 0x4000; /* 16K */ - else if (cpu_is_omap1611()) - omap_sram_size = SZ_256K; else { pr_err("Could not detect SRAM size\n"); omap_sram_size = 0x4000; @@ -163,6 +165,10 @@ static void __init omap_map_sram(void) if (omap_sram_size == 0) return; +#ifdef CONFIG_OMAP4_ERRATA_I688 + omap_sram_start += PAGE_SIZE; + omap_sram_size -= SZ_16K; +#endif if (cpu_is_omap34xx()) { /* * SRAM must be marked as non-cached on OMAP3 since the @@ -224,6 +230,9 @@ static void (*_omap_sram_reprogram_clock)(u32 dpllctl, u32 ckctl); void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl) { BUG_ON(!_omap_sram_reprogram_clock); + /* On 730, bit 13 must always be 1 */ + if (cpu_is_omap7xx()) + ckctl |= 0x2000; _omap_sram_reprogram_clock(dpllctl, ckctl); } diff --git a/arch/arm/plat-orion/Makefile b/arch/arm/plat-orion/Makefile index 95a5fc53b6d..c20ce0f5ce3 100644 --- a/arch/arm/plat-orion/Makefile +++ b/arch/arm/plat-orion/Makefile @@ -2,7 +2,7 @@ # Makefile for the linux kernel. # -obj-y := irq.o pcie.o time.o common.o mpp.o +obj-y := irq.o pcie.o time.o common.o mpp.o addr-map.o obj-m := obj-n := obj- := diff --git a/arch/arm/plat-orion/addr-map.c b/arch/arm/plat-orion/addr-map.c new file mode 100644 index 00000000000..367ca89ac40 --- /dev/null +++ b/arch/arm/plat-orion/addr-map.c @@ -0,0 +1,174 @@ +/* + * arch/arm/plat-orion/addr-map.c + * + * Address map functions for Marvell Orion based SoCs + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/init.h> +#include <linux/mbus.h> +#include <linux/io.h> +#include <plat/addr-map.h> + +struct mbus_dram_target_info orion_mbus_dram_info; + +const struct mbus_dram_target_info *mv_mbus_dram_info(void) +{ + return &orion_mbus_dram_info; +} +EXPORT_SYMBOL_GPL(mv_mbus_dram_info); + +/* + * DDR target is the same on all Orion platforms. + */ +#define TARGET_DDR 0 + +/* + * Helpers to get DDR bank info + */ +#define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3)) +#define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3)) + +/* + * CPU Address Decode Windows registers + */ +#define WIN_CTRL_OFF 0x0000 +#define WIN_BASE_OFF 0x0004 +#define WIN_REMAP_LO_OFF 0x0008 +#define WIN_REMAP_HI_OFF 0x000c + +/* + * Default implementation + */ +static void __init __iomem * +orion_win_cfg_base(const struct orion_addr_map_cfg *cfg, int win) +{ + return (void __iomem *)(cfg->bridge_virt_base + (win << 4)); +} + +/* + * Default implementation + */ +static int __init orion_cpu_win_can_remap(const struct orion_addr_map_cfg *cfg, + const int win) +{ + if (win < cfg->remappable_wins) + return 1; + + return 0; +} + +void __init orion_setup_cpu_win(const struct orion_addr_map_cfg *cfg, + const int win, const u32 base, + const u32 size, const u8 target, + const u8 attr, const int remap) +{ + void __iomem *addr = cfg->win_cfg_base(cfg, win); + u32 ctrl, base_high, remap_addr; + + if (win >= cfg->num_wins) { + printk(KERN_ERR "setup_cpu_win: trying to allocate window " + "%d when only %d allowed\n", win, cfg->num_wins); + } + + base_high = base & 0xffff0000; + ctrl = ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1; + + writel(base_high, addr + WIN_BASE_OFF); + writel(ctrl, addr + WIN_CTRL_OFF); + if (cfg->cpu_win_can_remap(cfg, win)) { + if (remap < 0) + remap_addr = base; + else + remap_addr = remap; + writel(remap_addr & 0xffff0000, addr + WIN_REMAP_LO_OFF); + writel(0, addr + WIN_REMAP_HI_OFF); + } +} + +/* + * Configure a number of windows. + */ +static void __init orion_setup_cpu_wins(const struct orion_addr_map_cfg * cfg, + const struct orion_addr_map_info *info) +{ + while (info->win != -1) { + orion_setup_cpu_win(cfg, info->win, info->base, info->size, + info->target, info->attr, info->remap); + info++; + } +} + +static void __init orion_disable_wins(const struct orion_addr_map_cfg * cfg) +{ + void __iomem *addr; + int i; + + for (i = 0; i < cfg->num_wins; i++) { + addr = cfg->win_cfg_base(cfg, i); + + writel(0, addr + WIN_BASE_OFF); + writel(0, addr + WIN_CTRL_OFF); + if (cfg->cpu_win_can_remap(cfg, i)) { + writel(0, addr + WIN_REMAP_LO_OFF); + writel(0, addr + WIN_REMAP_HI_OFF); + } + } +} + +/* + * Disable, clear and configure windows. + */ +void __init orion_config_wins(struct orion_addr_map_cfg * cfg, + const struct orion_addr_map_info *info) +{ + if (!cfg->cpu_win_can_remap) + cfg->cpu_win_can_remap = orion_cpu_win_can_remap; + + if (!cfg->win_cfg_base) + cfg->win_cfg_base = orion_win_cfg_base; + + orion_disable_wins(cfg); + + if (info) + orion_setup_cpu_wins(cfg, info); +} + +/* + * Setup MBUS dram target info. + */ +void __init orion_setup_cpu_mbus_target(const struct orion_addr_map_cfg *cfg, + const u32 ddr_window_cpu_base) +{ + void __iomem *addr; + int i; + int cs; + + orion_mbus_dram_info.mbus_dram_target_id = TARGET_DDR; + + addr = (void __iomem *)ddr_window_cpu_base; + + for (i = 0, cs = 0; i < 4; i++) { + u32 base = readl(addr + DDR_BASE_CS_OFF(i)); + u32 size = readl(addr + DDR_SIZE_CS_OFF(i)); + + /* + * Chip select enabled? + */ + if (size & 1) { + struct mbus_dram_window *w; + + w = &orion_mbus_dram_info.cs[cs++]; + w->cs_index = i; + w->mbus_attr = 0xf & ~(1 << i); + w->base = base & 0xffff0000; + w->size = (size | 0x0000ffff) + 1; + } + } + orion_mbus_dram_info.num_cs = cs; +} diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c index 9e5451b3c8e..e5a2fde29b1 100644 --- a/arch/arm/plat-orion/common.c +++ b/arch/arm/plat-orion/common.c @@ -13,7 +13,6 @@ #include <linux/platform_device.h> #include <linux/dma-mapping.h> #include <linux/serial_8250.h> -#include <linux/mbus.h> #include <linux/ata_platform.h> #include <linux/mv643xx_eth.h> #include <linux/mv643xx_i2c.h> @@ -203,13 +202,12 @@ void __init orion_rtc_init(unsigned long mapbase, ****************************************************************************/ static __init void ge_complete( struct mv643xx_eth_shared_platform_data *orion_ge_shared_data, - struct mbus_dram_target_info *mbus_dram_info, int tclk, + int tclk, struct resource *orion_ge_resource, unsigned long irq, struct platform_device *orion_ge_shared, struct mv643xx_eth_platform_data *eth_data, struct platform_device *orion_ge) { - orion_ge_shared_data->dram = mbus_dram_info; orion_ge_shared_data->t_clk = tclk; orion_ge_resource->start = irq; orion_ge_resource->end = irq; @@ -259,7 +257,6 @@ static struct platform_device orion_ge00 = { }; void __init orion_ge00_init(struct mv643xx_eth_platform_data *eth_data, - struct mbus_dram_target_info *mbus_dram_info, unsigned long mapbase, unsigned long irq, unsigned long irq_err, @@ -267,7 +264,7 @@ void __init orion_ge00_init(struct mv643xx_eth_platform_data *eth_data, { fill_resources(&orion_ge00_shared, orion_ge00_shared_resources, mapbase + 0x2000, SZ_16K - 1, irq_err); - ge_complete(&orion_ge00_shared_data, mbus_dram_info, tclk, + ge_complete(&orion_ge00_shared_data, tclk, orion_ge00_resources, irq, &orion_ge00_shared, eth_data, &orion_ge00); } @@ -313,7 +310,6 @@ static struct platform_device orion_ge01 = { }; void __init orion_ge01_init(struct mv643xx_eth_platform_data *eth_data, - struct mbus_dram_target_info *mbus_dram_info, unsigned long mapbase, unsigned long irq, unsigned long irq_err, @@ -321,7 +317,7 @@ void __init orion_ge01_init(struct mv643xx_eth_platform_data *eth_data, { fill_resources(&orion_ge01_shared, orion_ge01_shared_resources, mapbase + 0x2000, SZ_16K - 1, irq_err); - ge_complete(&orion_ge01_shared_data, mbus_dram_info, tclk, + ge_complete(&orion_ge01_shared_data, tclk, orion_ge01_resources, irq, &orion_ge01_shared, eth_data, &orion_ge01); } @@ -367,7 +363,6 @@ static struct platform_device orion_ge10 = { }; void __init orion_ge10_init(struct mv643xx_eth_platform_data *eth_data, - struct mbus_dram_target_info *mbus_dram_info, unsigned long mapbase, unsigned long irq, unsigned long irq_err, @@ -375,7 +370,7 @@ void __init orion_ge10_init(struct mv643xx_eth_platform_data *eth_data, { fill_resources(&orion_ge10_shared, orion_ge10_shared_resources, mapbase + 0x2000, SZ_16K - 1, irq_err); - ge_complete(&orion_ge10_shared_data, mbus_dram_info, tclk, + ge_complete(&orion_ge10_shared_data, tclk, orion_ge10_resources, irq, &orion_ge10_shared, eth_data, &orion_ge10); } @@ -421,7 +416,6 @@ static struct platform_device orion_ge11 = { }; void __init orion_ge11_init(struct mv643xx_eth_platform_data *eth_data, - struct mbus_dram_target_info *mbus_dram_info, unsigned long mapbase, unsigned long irq, unsigned long irq_err, @@ -429,7 +423,7 @@ void __init orion_ge11_init(struct mv643xx_eth_platform_data *eth_data, { fill_resources(&orion_ge11_shared, orion_ge11_shared_resources, mapbase + 0x2000, SZ_16K - 1, irq_err); - ge_complete(&orion_ge11_shared_data, mbus_dram_info, tclk, + ge_complete(&orion_ge11_shared_data, tclk, orion_ge11_resources, irq, &orion_ge11_shared, eth_data, &orion_ge11); } @@ -592,8 +586,6 @@ void __init orion_wdt_init(unsigned long tclk) /***************************************************************************** * XOR ****************************************************************************/ -static struct mv_xor_platform_shared_data orion_xor_shared_data; - static u64 orion_xor_dmamask = DMA_BIT_MASK(32); void __init orion_xor_init_channels( @@ -632,9 +624,6 @@ static struct resource orion_xor0_shared_resources[] = { static struct platform_device orion_xor0_shared = { .name = MV_XOR_SHARED_NAME, .id = 0, - .dev = { - .platform_data = &orion_xor_shared_data, - }, .num_resources = ARRAY_SIZE(orion_xor0_shared_resources), .resource = orion_xor0_shared_resources, }; @@ -687,14 +676,11 @@ static struct platform_device orion_xor01_channel = { }, }; -void __init orion_xor0_init(struct mbus_dram_target_info *mbus_dram_info, - unsigned long mapbase_low, +void __init orion_xor0_init(unsigned long mapbase_low, unsigned long mapbase_high, unsigned long irq_0, unsigned long irq_1) { - orion_xor_shared_data.dram = mbus_dram_info; - orion_xor0_shared_resources[0].start = mapbase_low; orion_xor0_shared_resources[0].end = mapbase_low + 0xff; orion_xor0_shared_resources[1].start = mapbase_high; @@ -727,9 +713,6 @@ static struct resource orion_xor1_shared_resources[] = { static struct platform_device orion_xor1_shared = { .name = MV_XOR_SHARED_NAME, .id = 1, - .dev = { - .platform_data = &orion_xor_shared_data, - }, .num_resources = ARRAY_SIZE(orion_xor1_shared_resources), .resource = orion_xor1_shared_resources, }; @@ -828,11 +811,9 @@ static struct platform_device orion_ehci = { }, }; -void __init orion_ehci_init(struct mbus_dram_target_info *mbus_dram_info, - unsigned long mapbase, +void __init orion_ehci_init(unsigned long mapbase, unsigned long irq) { - orion_ehci_data.dram = mbus_dram_info; fill_resources(&orion_ehci, orion_ehci_resources, mapbase, SZ_4K - 1, irq); @@ -854,11 +835,9 @@ static struct platform_device orion_ehci_1 = { }, }; -void __init orion_ehci_1_init(struct mbus_dram_target_info *mbus_dram_info, - unsigned long mapbase, +void __init orion_ehci_1_init(unsigned long mapbase, unsigned long irq) { - orion_ehci_data.dram = mbus_dram_info; fill_resources(&orion_ehci_1, orion_ehci_1_resources, mapbase, SZ_4K - 1, irq); @@ -880,11 +859,9 @@ static struct platform_device orion_ehci_2 = { }, }; -void __init orion_ehci_2_init(struct mbus_dram_target_info *mbus_dram_info, - unsigned long mapbase, +void __init orion_ehci_2_init(unsigned long mapbase, unsigned long irq) { - orion_ehci_data.dram = mbus_dram_info; fill_resources(&orion_ehci_2, orion_ehci_2_resources, mapbase, SZ_4K - 1, irq); @@ -911,11 +888,9 @@ static struct platform_device orion_sata = { }; void __init orion_sata_init(struct mv_sata_platform_data *sata_data, - struct mbus_dram_target_info *mbus_dram_info, unsigned long mapbase, unsigned long irq) { - sata_data->dram = mbus_dram_info; orion_sata.dev.platform_data = sata_data; fill_resources(&orion_sata, orion_sata_resources, mapbase, 0x5000 - 1, irq); diff --git a/arch/arm/plat-orion/include/plat/addr-map.h b/arch/arm/plat-orion/include/plat/addr-map.h new file mode 100644 index 00000000000..fd556f77562 --- /dev/null +++ b/arch/arm/plat-orion/include/plat/addr-map.h @@ -0,0 +1,53 @@ +/* + * arch/arm/plat-orion/include/plat/addr-map.h + * + * Marvell Orion SoC address map handling. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __PLAT_ADDR_MAP_H +#define __PLAT_ADDR_MAP_H + +extern struct mbus_dram_target_info orion_mbus_dram_info; + +struct orion_addr_map_cfg { + const int num_wins; /* Total number of windows */ + const int remappable_wins; + const u32 bridge_virt_base; + + /* If NULL, the default cpu_win_can_remap will be used, using + the value in remappable_wins */ + int (*cpu_win_can_remap) (const struct orion_addr_map_cfg *cfg, + const int win); + /* If NULL, the default win_cfg_base will be used, using the + value in bridge_virt_base */ + void __iomem *(*win_cfg_base) (const struct orion_addr_map_cfg *cfg, + const int win); +}; + +/* + * Information needed to setup one address mapping. + */ +struct orion_addr_map_info { + const int win; + const u32 base; + const u32 size; + const u8 target; + const u8 attr; + const int remap; +}; + +void __init orion_config_wins(struct orion_addr_map_cfg *cfg, + const struct orion_addr_map_info *info); + +void __init orion_setup_cpu_win(const struct orion_addr_map_cfg *cfg, + const int win, const u32 base, + const u32 size, const u8 target, + const u8 attr, const int remap); + +void __init orion_setup_cpu_mbus_target(const struct orion_addr_map_cfg *cfg, + const u32 ddr_window_cpu_base); +#endif diff --git a/arch/arm/plat-orion/include/plat/audio.h b/arch/arm/plat-orion/include/plat/audio.h index 9cf1f781329..885f8abd927 100644 --- a/arch/arm/plat-orion/include/plat/audio.h +++ b/arch/arm/plat-orion/include/plat/audio.h @@ -1,11 +1,8 @@ #ifndef __PLAT_AUDIO_H #define __PLAT_AUDIO_H -#include <linux/mbus.h> - struct kirkwood_asoc_platform_data { u32 tclk; - struct mbus_dram_target_info *dram; int burst; }; #endif diff --git a/arch/arm/plat-orion/include/plat/common.h b/arch/arm/plat-orion/include/plat/common.h index a63c357e2ab..0fe08d77e83 100644 --- a/arch/arm/plat-orion/include/plat/common.h +++ b/arch/arm/plat-orion/include/plat/common.h @@ -37,28 +37,24 @@ void __init orion_rtc_init(unsigned long mapbase, unsigned long irq); void __init orion_ge00_init(struct mv643xx_eth_platform_data *eth_data, - struct mbus_dram_target_info *mbus_dram_info, unsigned long mapbase, unsigned long irq, unsigned long irq_err, int tclk); void __init orion_ge01_init(struct mv643xx_eth_platform_data *eth_data, - struct mbus_dram_target_info *mbus_dram_info, unsigned long mapbase, unsigned long irq, unsigned long irq_err, int tclk); void __init orion_ge10_init(struct mv643xx_eth_platform_data *eth_data, - struct mbus_dram_target_info *mbus_dram_info, unsigned long mapbase, unsigned long irq, unsigned long irq_err, int tclk); void __init orion_ge11_init(struct mv643xx_eth_platform_data *eth_data, - struct mbus_dram_target_info *mbus_dram_info, unsigned long mapbase, unsigned long irq, unsigned long irq_err, @@ -82,8 +78,7 @@ void __init orion_spi_1_init(unsigned long mapbase, void __init orion_wdt_init(unsigned long tclk); -void __init orion_xor0_init(struct mbus_dram_target_info *mbus_dram_info, - unsigned long mapbase_low, +void __init orion_xor0_init(unsigned long mapbase_low, unsigned long mapbase_high, unsigned long irq_0, unsigned long irq_1); @@ -93,20 +88,16 @@ void __init orion_xor1_init(unsigned long mapbase_low, unsigned long irq_0, unsigned long irq_1); -void __init orion_ehci_init(struct mbus_dram_target_info *mbus_dram_info, - unsigned long mapbase, +void __init orion_ehci_init(unsigned long mapbase, unsigned long irq); -void __init orion_ehci_1_init(struct mbus_dram_target_info *mbus_dram_info, - unsigned long mapbase, +void __init orion_ehci_1_init(unsigned long mapbase, unsigned long irq); -void __init orion_ehci_2_init(struct mbus_dram_target_info *mbus_dram_info, - unsigned long mapbase, +void __init orion_ehci_2_init(unsigned long mapbase, unsigned long irq); void __init orion_sata_init(struct mv_sata_platform_data *sata_data, - struct mbus_dram_target_info *mbus_dram_info, unsigned long mapbase, unsigned long irq); diff --git a/arch/arm/plat-orion/include/plat/ehci-orion.h b/arch/arm/plat-orion/include/plat/ehci-orion.h index 4ec668e7746..6fc78e43042 100644 --- a/arch/arm/plat-orion/include/plat/ehci-orion.h +++ b/arch/arm/plat-orion/include/plat/ehci-orion.h @@ -19,7 +19,6 @@ enum orion_ehci_phy_ver { }; struct orion_ehci_data { - struct mbus_dram_target_info *dram; enum orion_ehci_phy_ver phy_version; }; diff --git a/arch/arm/plat-orion/include/plat/mv_xor.h b/arch/arm/plat-orion/include/plat/mv_xor.h index bd5f3bdb4ae..2ba1f7d76ee 100644 --- a/arch/arm/plat-orion/include/plat/mv_xor.h +++ b/arch/arm/plat-orion/include/plat/mv_xor.h @@ -13,12 +13,6 @@ #define MV_XOR_SHARED_NAME "mv_xor_shared" #define MV_XOR_NAME "mv_xor" -struct mbus_dram_target_info; - -struct mv_xor_platform_shared_data { - struct mbus_dram_target_info *dram; -}; - struct mv_xor_platform_data { struct platform_device *shared; int hw_id; diff --git a/arch/arm/plat-orion/include/plat/mvsdio.h b/arch/arm/plat-orion/include/plat/mvsdio.h index 14ca8867600..1190efedcb9 100644 --- a/arch/arm/plat-orion/include/plat/mvsdio.h +++ b/arch/arm/plat-orion/include/plat/mvsdio.h @@ -12,7 +12,6 @@ #include <linux/mbus.h> struct mvsdio_platform_data { - struct mbus_dram_target_info *dram; unsigned int clock; int gpio_card_detect; int gpio_write_protect; diff --git a/arch/arm/plat-orion/include/plat/pcie.h b/arch/arm/plat-orion/include/plat/pcie.h index cc99163e73f..fe5b9e86274 100644 --- a/arch/arm/plat-orion/include/plat/pcie.h +++ b/arch/arm/plat-orion/include/plat/pcie.h @@ -20,8 +20,7 @@ int orion_pcie_x4_mode(void __iomem *base); int orion_pcie_get_local_bus_nr(void __iomem *base); void orion_pcie_set_local_bus_nr(void __iomem *base, int nr); void orion_pcie_reset(void __iomem *base); -void orion_pcie_setup(void __iomem *base, - struct mbus_dram_target_info *dram); +void orion_pcie_setup(void __iomem *base); int orion_pcie_rd_conf(void __iomem *base, struct pci_bus *bus, u32 devfn, int where, int size, u32 *val); int orion_pcie_rd_conf_tlp(void __iomem *base, struct pci_bus *bus, diff --git a/arch/arm/plat-orion/pcie.c b/arch/arm/plat-orion/pcie.c index af2d733c50b..86dbb5bdb17 100644 --- a/arch/arm/plat-orion/pcie.c +++ b/arch/arm/plat-orion/pcie.c @@ -13,6 +13,7 @@ #include <linux/mbus.h> #include <asm/mach/pci.h> #include <plat/pcie.h> +#include <plat/addr-map.h> #include <linux/delay.h> /* @@ -175,8 +176,7 @@ static void __init orion_pcie_setup_wins(void __iomem *base, writel(((size - 1) & 0xffff0000) | 1, base + PCIE_BAR_CTRL_OFF(1)); } -void __init orion_pcie_setup(void __iomem *base, - struct mbus_dram_target_info *dram) +void __init orion_pcie_setup(void __iomem *base) { u16 cmd; u32 mask; @@ -184,7 +184,7 @@ void __init orion_pcie_setup(void __iomem *base, /* * Point PCIe unit MBUS decode windows to DRAM space. */ - orion_pcie_setup_wins(base, dram); + orion_pcie_setup_wins(base, &orion_mbus_dram_info); /* * Master + slave enable. diff --git a/arch/arm/plat-pxa/include/plat/gpio-pxa.h b/arch/arm/plat-pxa/include/plat/gpio-pxa.h deleted file mode 100644 index b6390beff32..00000000000 --- a/arch/arm/plat-pxa/include/plat/gpio-pxa.h +++ /dev/null @@ -1,44 +0,0 @@ -#ifndef __PLAT_PXA_GPIO_H -#define __PLAT_PXA_GPIO_H - -struct irq_data; - -/* - * We handle the GPIOs by banks, each bank covers up to 32 GPIOs with - * one set of registers. The register offsets are organized below: - * - * GPLR GPDR GPSR GPCR GRER GFER GEDR - * BANK 0 - 0x0000 0x000C 0x0018 0x0024 0x0030 0x003C 0x0048 - * BANK 1 - 0x0004 0x0010 0x001C 0x0028 0x0034 0x0040 0x004C - * BANK 2 - 0x0008 0x0014 0x0020 0x002C 0x0038 0x0044 0x0050 - * - * BANK 3 - 0x0100 0x010C 0x0118 0x0124 0x0130 0x013C 0x0148 - * BANK 4 - 0x0104 0x0110 0x011C 0x0128 0x0134 0x0140 0x014C - * BANK 5 - 0x0108 0x0114 0x0120 0x012C 0x0138 0x0144 0x0150 - * - * NOTE: - * BANK 3 is only available on PXA27x and later processors. - * BANK 4 and 5 are only available on PXA935 - */ - -#define GPIO_BANK(n) (GPIO_REGS_VIRT + BANK_OFF(n)) - -#define GPLR_OFFSET 0x00 -#define GPDR_OFFSET 0x0C -#define GPSR_OFFSET 0x18 -#define GPCR_OFFSET 0x24 -#define GRER_OFFSET 0x30 -#define GFER_OFFSET 0x3C -#define GEDR_OFFSET 0x48 - -/* NOTE: some PXAs have fewer on-chip GPIOs (like PXA255, with 85). - * Those cases currently cause holes in the GPIO number space, the - * actual number of the last GPIO is recorded by 'pxa_last_gpio'. - */ -extern int pxa_last_gpio; - -typedef int (*set_wake_t)(struct irq_data *d, unsigned int on); - -extern void pxa_init_gpio(int mux_irq, int start, int end, set_wake_t fn); - -#endif /* __PLAT_PXA_GPIO_H */ diff --git a/arch/arm/plat-pxa/include/plat/gpio.h b/arch/arm/plat-pxa/include/plat/gpio.h deleted file mode 100644 index 258f77210b0..00000000000 --- a/arch/arm/plat-pxa/include/plat/gpio.h +++ /dev/null @@ -1,30 +0,0 @@ -#ifndef __PLAT_GPIO_H -#define __PLAT_GPIO_H - -#define __ARM_GPIOLIB_COMPLEX - -/* The individual machine provides register offsets and NR_BUILTIN_GPIO */ -#include <mach/gpio-pxa.h> - -static inline int gpio_get_value(unsigned gpio) -{ - if (__builtin_constant_p(gpio) && (gpio < NR_BUILTIN_GPIO)) - return GPLR(gpio) & GPIO_bit(gpio); - else - return __gpio_get_value(gpio); -} - -static inline void gpio_set_value(unsigned gpio, int value) -{ - if (__builtin_constant_p(gpio) && (gpio < NR_BUILTIN_GPIO)) { - if (value) - GPSR(gpio) = GPIO_bit(gpio); - else - GPCR(gpio) = GPIO_bit(gpio); - } else - __gpio_set_value(gpio, value); -} - -#define gpio_cansleep __gpio_cansleep - -#endif /* __PLAT_GPIO_H */ diff --git a/arch/arm/plat-s3c24xx/common-smdk.c b/arch/arm/plat-s3c24xx/common-smdk.c index bcc43f34627..084604be6ad 100644 --- a/arch/arm/plat-s3c24xx/common-smdk.c +++ b/arch/arm/plat-s3c24xx/common-smdk.c @@ -19,7 +19,7 @@ #include <linux/timer.h> #include <linux/init.h> #include <linux/gpio.h> -#include <linux/sysdev.h> +#include <linux/device.h> #include <linux/platform_device.h> #include <linux/mtd/mtd.h> diff --git a/arch/arm/plat-s3c24xx/cpu-freq.c b/arch/arm/plat-s3c24xx/cpu-freq.c index b3d3d027899..46807993888 100644 --- a/arch/arm/plat-s3c24xx/cpu-freq.c +++ b/arch/arm/plat-s3c24xx/cpu-freq.c @@ -20,7 +20,7 @@ #include <linux/clk.h> #include <linux/err.h> #include <linux/io.h> -#include <linux/sysdev.h> +#include <linux/device.h> #include <linux/sysfs.h> #include <linux/slab.h> diff --git a/arch/arm/plat-s3c24xx/dma.c b/arch/arm/plat-s3c24xx/dma.c index 53754bcf15a..9fe35348e03 100644 --- a/arch/arm/plat-s3c24xx/dma.c +++ b/arch/arm/plat-s3c24xx/dma.c @@ -1437,11 +1437,10 @@ int __init s3c24xx_dma_init_map(struct s3c24xx_dma_selection *sel) size_t map_sz = sizeof(*nmap) * sel->map_size; int ptr; - nmap = kmalloc(map_sz, GFP_KERNEL); + nmap = kmemdup(sel->map, map_sz, GFP_KERNEL); if (nmap == NULL) return -ENOMEM; - memcpy(nmap, sel->map, map_sz); memcpy(&dma_sel, sel, sizeof(*sel)); dma_sel.map = nmap; diff --git a/arch/arm/plat-s3c24xx/irq.c b/arch/arm/plat-s3c24xx/irq.c index fc8c5f89954..bc42c04091f 100644 --- a/arch/arm/plat-s3c24xx/irq.c +++ b/arch/arm/plat-s3c24xx/irq.c @@ -22,7 +22,7 @@ #include <linux/module.h> #include <linux/interrupt.h> #include <linux/ioport.h> -#include <linux/sysdev.h> +#include <linux/device.h> #include <linux/syscore_ops.h> #include <asm/irq.h> diff --git a/arch/arm/plat-s3c24xx/pm-simtec.c b/arch/arm/plat-s3c24xx/pm-simtec.c index 663b280d65d..68296b1fe7e 100644 --- a/arch/arm/plat-s3c24xx/pm-simtec.c +++ b/arch/arm/plat-s3c24xx/pm-simtec.c @@ -18,7 +18,6 @@ #include <linux/list.h> #include <linux/timer.h> #include <linux/init.h> -#include <linux/sysdev.h> #include <linux/device.h> #include <linux/io.h> diff --git a/arch/arm/plat-s3c24xx/s3c2410-clock.c b/arch/arm/plat-s3c24xx/s3c2410-clock.c index def76aa3825..25dc4d4397b 100644 --- a/arch/arm/plat-s3c24xx/s3c2410-clock.c +++ b/arch/arm/plat-s3c24xx/s3c2410-clock.c @@ -26,7 +26,7 @@ #include <linux/list.h> #include <linux/errno.h> #include <linux/err.h> -#include <linux/sysdev.h> +#include <linux/device.h> #include <linux/clk.h> #include <linux/mutex.h> #include <linux/delay.h> diff --git a/arch/arm/plat-s3c24xx/s3c2412-iotiming.c b/arch/arm/plat-s3c24xx/s3c2412-iotiming.c index 0b46d3895d6..48eee39ab36 100644 --- a/arch/arm/plat-s3c24xx/s3c2412-iotiming.c +++ b/arch/arm/plat-s3c24xx/s3c2412-iotiming.c @@ -17,7 +17,7 @@ #include <linux/ioport.h> #include <linux/cpufreq.h> #include <linux/seq_file.h> -#include <linux/sysdev.h> +#include <linux/device.h> #include <linux/delay.h> #include <linux/clk.h> #include <linux/err.h> diff --git a/arch/arm/plat-s3c24xx/s3c2443-clock.c b/arch/arm/plat-s3c24xx/s3c2443-clock.c index 5a21b15b2a9..95e68190d59 100644 --- a/arch/arm/plat-s3c24xx/s3c2443-clock.c +++ b/arch/arm/plat-s3c24xx/s3c2443-clock.c @@ -297,13 +297,6 @@ static struct clksrc_clk clk_usb_bus_host = { static struct clksrc_clk clksrc_clks[] = { { - /* ART baud-rate clock sourced from esysclk via a divisor */ - .clk = { - .name = "uartclk", - .parent = &clk_esysclk.clk, - }, - .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 8 }, - }, { /* camera interface bus-clock, divided down from esysclk */ .clk = { .name = "camif-upll", /* same as 2440 name */ @@ -323,6 +316,15 @@ static struct clksrc_clk clksrc_clks[] = { }, }; +static struct clksrc_clk clk_esys_uart = { + /* ART baud-rate clock sourced from esysclk via a divisor */ + .clk = { + .name = "uartclk", + .parent = &clk_esysclk.clk, + }, + .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 8 }, +}; + static struct clk clk_i2s_ext = { .name = "i2s-ext", }; @@ -425,12 +427,6 @@ static struct clk init_clocks[] = { .enable = s3c2443_clkcon_enable_h, .ctrlbit = S3C2443_HCLKCON_DMA5, }, { - .name = "hsmmc", - .devname = "s3c-sdhci.1", - .parent = &clk_h, - .enable = s3c2443_clkcon_enable_h, - .ctrlbit = S3C2443_HCLKCON_HSMMC, - }, { .name = "gpio", .parent = &clk_p, .enable = s3c2443_clkcon_enable_p, @@ -512,6 +508,14 @@ static struct clk init_clocks[] = { } }; +static struct clk hsmmc1_clk = { + .name = "hsmmc", + .devname = "s3c-sdhci.1", + .parent = &clk_h, + .enable = s3c2443_clkcon_enable_h, + .ctrlbit = S3C2443_HCLKCON_HSMMC, +}; + static inline unsigned long s3c2443_get_hdiv(unsigned long clkcon0) { clkcon0 &= S3C2443_CLKDIV0_HCLKDIV_MASK; @@ -577,6 +581,7 @@ static struct clk *clks[] __initdata = { &clk_epll, &clk_usb_bus, &clk_armdiv, + &hsmmc1_clk, }; static struct clksrc_clk *clksrcs[] __initdata = { @@ -589,6 +594,13 @@ static struct clksrc_clk *clksrcs[] __initdata = { &clk_arm, }; +static struct clk_lookup s3c2443_clk_lookup[] = { + CLKDEV_INIT(NULL, "clk_uart_baud1", &s3c24xx_uclk), + CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p), + CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_esys_uart.clk), + CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &hsmmc1_clk), +}; + void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll, unsigned int *divs, int nr_divs, int divmask) @@ -618,6 +630,7 @@ void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll, /* See s3c2443/etc notes on disabling clocks at init time */ s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); + clkdev_add_table(s3c2443_clk_lookup, ARRAY_SIZE(s3c2443_clk_lookup)); s3c2443_common_setup_clocks(get_mpll); } diff --git a/arch/arm/plat-s5p/clock.c b/arch/arm/plat-s5p/clock.c index 5f84a3f13ef..963edea7f7e 100644 --- a/arch/arm/plat-s5p/clock.c +++ b/arch/arm/plat-s5p/clock.c @@ -17,7 +17,7 @@ #include <linux/errno.h> #include <linux/err.h> #include <linux/clk.h> -#include <linux/sysdev.h> +#include <linux/device.h> #include <linux/io.h> #include <asm/div64.h> diff --git a/arch/arm/plat-s5p/irq-eint.c b/arch/arm/plat-s5p/irq-eint.c index b5bb774985b..c496b359c37 100644 --- a/arch/arm/plat-s5p/irq-eint.c +++ b/arch/arm/plat-s5p/irq-eint.c @@ -14,7 +14,7 @@ #include <linux/interrupt.h> #include <linux/irq.h> #include <linux/io.h> -#include <linux/sysdev.h> +#include <linux/device.h> #include <linux/gpio.h> #include <asm/hardware/vic.h> diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig index 313eb26cfa6..6a2abe67c8b 100644 --- a/arch/arm/plat-samsung/Kconfig +++ b/arch/arm/plat-samsung/Kconfig @@ -88,12 +88,20 @@ config S5P_GPIO_DRVSTR config SAMSUNG_GPIO_EXTRA int "Number of additional GPIO pins" + default 128 if SAMSUNG_GPIO_EXTRA128 + default 64 if SAMSUNG_GPIO_EXTRA64 default 0 help Use additional GPIO space in addition to the GPIO's the SOC provides. This allows expanding the GPIO space for use with GPIO expanders. +config SAMSUNG_GPIO_EXTRA64 + bool + +config SAMSUNG_GPIO_EXTRA128 + bool + config S3C_GPIO_SPACE int "Space between gpio banks" default 0 @@ -226,11 +234,23 @@ config SAMSUNG_DEV_IDE help Compile in platform device definitions for IDE -config S3C64XX_DEV_SPI +config S3C64XX_DEV_SPI0 + bool + help + Compile in platform device definitions for S3C64XX's type + SPI controller 0 + +config S3C64XX_DEV_SPI1 + bool + help + Compile in platform device definitions for S3C64XX's type + SPI controller 1 + +config S3C64XX_DEV_SPI2 bool help Compile in platform device definitions for S3C64XX's type - SPI controllers. + SPI controller 2 config SAMSUNG_DEV_TS bool diff --git a/arch/arm/plat-samsung/clock-clksrc.c b/arch/arm/plat-samsung/clock-clksrc.c index ae8b8507663..786a4107a15 100644 --- a/arch/arm/plat-samsung/clock-clksrc.c +++ b/arch/arm/plat-samsung/clock-clksrc.c @@ -16,7 +16,7 @@ #include <linux/errno.h> #include <linux/err.h> #include <linux/clk.h> -#include <linux/sysdev.h> +#include <linux/device.h> #include <linux/io.h> #include <plat/clock.h> diff --git a/arch/arm/plat-samsung/clock.c b/arch/arm/plat-samsung/clock.c index 3b4451979d1..10f71179071 100644 --- a/arch/arm/plat-samsung/clock.c +++ b/arch/arm/plat-samsung/clock.c @@ -33,7 +33,7 @@ #include <linux/errno.h> #include <linux/err.h> #include <linux/platform_device.h> -#include <linux/sysdev.h> +#include <linux/device.h> #include <linux/interrupt.h> #include <linux/ioport.h> #include <linux/clk.h> diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c index 4ca8b571f97..32a6e394db2 100644 --- a/arch/arm/plat-samsung/devs.c +++ b/arch/arm/plat-samsung/devs.c @@ -29,6 +29,7 @@ #include <linux/mtd/partitions.h> #include <linux/mmc/host.h> #include <linux/ioport.h> +#include <linux/platform_data/s3c-hsudc.h> #include <asm/irq.h> #include <asm/pmu.h> @@ -61,6 +62,7 @@ #include <plat/regs-iic.h> #include <plat/regs-serial.h> #include <plat/regs-spi.h> +#include <plat/s3c64xx-spi.h> static u64 samsung_device_dma_mask = DMA_BIT_MASK(32); @@ -1461,3 +1463,129 @@ struct platform_device s3c_device_wdt = { .resource = s3c_wdt_resource, }; #endif /* CONFIG_S3C_DEV_WDT */ + +#ifdef CONFIG_S3C64XX_DEV_SPI0 +static struct resource s3c64xx_spi0_resource[] = { + [0] = DEFINE_RES_MEM(S3C_PA_SPI0, SZ_256), + [1] = DEFINE_RES_DMA(DMACH_SPI0_TX), + [2] = DEFINE_RES_DMA(DMACH_SPI0_RX), + [3] = DEFINE_RES_IRQ(IRQ_SPI0), +}; + +struct platform_device s3c64xx_device_spi0 = { + .name = "s3c64xx-spi", + .id = 0, + .num_resources = ARRAY_SIZE(s3c64xx_spi0_resource), + .resource = s3c64xx_spi0_resource, + .dev = { + .dma_mask = &samsung_device_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + +void __init s3c64xx_spi0_set_platdata(struct s3c64xx_spi_info *pd, + int src_clk_nr, int num_cs) +{ + if (!pd) { + pr_err("%s:Need to pass platform data\n", __func__); + return; + } + + /* Reject invalid configuration */ + if (!num_cs || src_clk_nr < 0) { + pr_err("%s: Invalid SPI configuration\n", __func__); + return; + } + + pd->num_cs = num_cs; + pd->src_clk_nr = src_clk_nr; + if (!pd->cfg_gpio) + pd->cfg_gpio = s3c64xx_spi0_cfg_gpio; + + s3c_set_platdata(pd, sizeof(*pd), &s3c64xx_device_spi0); +} +#endif /* CONFIG_S3C64XX_DEV_SPI0 */ + +#ifdef CONFIG_S3C64XX_DEV_SPI1 +static struct resource s3c64xx_spi1_resource[] = { + [0] = DEFINE_RES_MEM(S3C_PA_SPI1, SZ_256), + [1] = DEFINE_RES_DMA(DMACH_SPI1_TX), + [2] = DEFINE_RES_DMA(DMACH_SPI1_RX), + [3] = DEFINE_RES_IRQ(IRQ_SPI1), +}; + +struct platform_device s3c64xx_device_spi1 = { + .name = "s3c64xx-spi", + .id = 1, + .num_resources = ARRAY_SIZE(s3c64xx_spi1_resource), + .resource = s3c64xx_spi1_resource, + .dev = { + .dma_mask = &samsung_device_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + +void __init s3c64xx_spi1_set_platdata(struct s3c64xx_spi_info *pd, + int src_clk_nr, int num_cs) +{ + if (!pd) { + pr_err("%s:Need to pass platform data\n", __func__); + return; + } + + /* Reject invalid configuration */ + if (!num_cs || src_clk_nr < 0) { + pr_err("%s: Invalid SPI configuration\n", __func__); + return; + } + + pd->num_cs = num_cs; + pd->src_clk_nr = src_clk_nr; + if (!pd->cfg_gpio) + pd->cfg_gpio = s3c64xx_spi1_cfg_gpio; + + s3c_set_platdata(pd, sizeof(*pd), &s3c64xx_device_spi1); +} +#endif /* CONFIG_S3C64XX_DEV_SPI1 */ + +#ifdef CONFIG_S3C64XX_DEV_SPI2 +static struct resource s3c64xx_spi2_resource[] = { + [0] = DEFINE_RES_MEM(S3C_PA_SPI2, SZ_256), + [1] = DEFINE_RES_DMA(DMACH_SPI2_TX), + [2] = DEFINE_RES_DMA(DMACH_SPI2_RX), + [3] = DEFINE_RES_IRQ(IRQ_SPI2), +}; + +struct platform_device s3c64xx_device_spi2 = { + .name = "s3c64xx-spi", + .id = 2, + .num_resources = ARRAY_SIZE(s3c64xx_spi2_resource), + .resource = s3c64xx_spi2_resource, + .dev = { + .dma_mask = &samsung_device_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + +void __init s3c64xx_spi2_set_platdata(struct s3c64xx_spi_info *pd, + int src_clk_nr, int num_cs) +{ + if (!pd) { + pr_err("%s:Need to pass platform data\n", __func__); + return; + } + + /* Reject invalid configuration */ + if (!num_cs || src_clk_nr < 0) { + pr_err("%s: Invalid SPI configuration\n", __func__); + return; + } + + pd->num_cs = num_cs; + pd->src_clk_nr = src_clk_nr; + if (!pd->cfg_gpio) + pd->cfg_gpio = s3c64xx_spi2_cfg_gpio; + + s3c_set_platdata(pd, sizeof(*pd), &s3c64xx_device_spi2); +} +#endif /* CONFIG_S3C64XX_DEV_SPI2 */ diff --git a/arch/arm/plat-samsung/dma-ops.c b/arch/arm/plat-samsung/dma-ops.c index 93a994a5dd8..2cded872f22 100644 --- a/arch/arm/plat-samsung/dma-ops.c +++ b/arch/arm/plat-samsung/dma-ops.c @@ -18,23 +18,24 @@ #include <mach/dma.h> -static inline bool pl330_filter(struct dma_chan *chan, void *param) -{ - struct dma_pl330_peri *peri = chan->private; - return peri->peri_id == (unsigned)param; -} - static unsigned samsung_dmadev_request(enum dma_ch dma_ch, struct samsung_dma_info *info) { struct dma_chan *chan; dma_cap_mask_t mask; struct dma_slave_config slave_config; + void *filter_param; dma_cap_zero(mask); dma_cap_set(info->cap, mask); - chan = dma_request_channel(mask, pl330_filter, (void *)dma_ch); + /* + * If a dma channel property of a device node from device tree is + * specified, use that as the fliter parameter. + */ + filter_param = (dma_ch == DMACH_DT_PROP) ? (void *)info->dt_dmach_prop : + (void *)dma_ch; + chan = dma_request_channel(mask, pl330_filter, filter_param); if (info->direction == DMA_FROM_DEVICE) { memset(&slave_config, 0, sizeof(struct dma_slave_config)); diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h index 258d9d8a94f..73cb3cfd068 100644 --- a/arch/arm/plat-samsung/include/plat/cpu.h +++ b/arch/arm/plat-samsung/include/plat/cpu.h @@ -180,19 +180,19 @@ extern struct syscore_ops s3c2412_pm_syscore_ops; extern struct syscore_ops s3c2416_pm_syscore_ops; extern struct syscore_ops s3c244x_pm_syscore_ops; -/* system device classes */ - -extern struct sysdev_class s3c2410_sysclass; -extern struct sysdev_class s3c2410a_sysclass; -extern struct sysdev_class s3c2412_sysclass; -extern struct sysdev_class s3c2416_sysclass; -extern struct sysdev_class s3c2440_sysclass; -extern struct sysdev_class s3c2442_sysclass; -extern struct sysdev_class s3c2443_sysclass; -extern struct sysdev_class s3c6410_sysclass; -extern struct sysdev_class s5p64x0_sysclass; -extern struct sysdev_class s5pv210_sysclass; -extern struct sysdev_class exynos4_sysclass; +/* system device subsystems */ + +extern struct bus_type s3c2410_subsys; +extern struct bus_type s3c2410a_subsys; +extern struct bus_type s3c2412_subsys; +extern struct bus_type s3c2416_subsys; +extern struct bus_type s3c2440_subsys; +extern struct bus_type s3c2442_subsys; +extern struct bus_type s3c2443_subsys; +extern struct bus_type s3c6410_subsys; +extern struct bus_type s5p64x0_subsys; +extern struct bus_type s5pv210_subsys; +extern struct bus_type exynos4_subsys; extern void (*s5pc1xx_idle)(void); diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h index ab633c9c2ae..4214ea0ff8f 100644 --- a/arch/arm/plat-samsung/include/plat/devs.h +++ b/arch/arm/plat-samsung/include/plat/devs.h @@ -39,6 +39,7 @@ extern struct platform_device s3c64xx_device_pcm0; extern struct platform_device s3c64xx_device_pcm1; extern struct platform_device s3c64xx_device_spi0; extern struct platform_device s3c64xx_device_spi1; +extern struct platform_device s3c64xx_device_spi2; extern struct platform_device s3c_device_adc; extern struct platform_device s3c_device_cfcon; @@ -98,8 +99,6 @@ extern struct platform_device s5p6450_device_iis1; extern struct platform_device s5p6450_device_iis2; extern struct platform_device s5p6450_device_pcm0; -extern struct platform_device s5p64x0_device_spi0; -extern struct platform_device s5p64x0_device_spi1; extern struct platform_device s5pc100_device_ac97; extern struct platform_device s5pc100_device_iis0; @@ -108,9 +107,6 @@ extern struct platform_device s5pc100_device_iis2; extern struct platform_device s5pc100_device_pcm0; extern struct platform_device s5pc100_device_pcm1; extern struct platform_device s5pc100_device_spdif; -extern struct platform_device s5pc100_device_spi0; -extern struct platform_device s5pc100_device_spi1; -extern struct platform_device s5pc100_device_spi2; extern struct platform_device s5pv210_device_ac97; extern struct platform_device s5pv210_device_iis0; @@ -120,8 +116,6 @@ extern struct platform_device s5pv210_device_pcm0; extern struct platform_device s5pv210_device_pcm1; extern struct platform_device s5pv210_device_pcm2; extern struct platform_device s5pv210_device_spdif; -extern struct platform_device s5pv210_device_spi0; -extern struct platform_device s5pv210_device_spi1; extern struct platform_device exynos4_device_ac97; extern struct platform_device exynos4_device_ahci; @@ -129,6 +123,7 @@ extern struct platform_device exynos4_device_dwmci; extern struct platform_device exynos4_device_i2s0; extern struct platform_device exynos4_device_i2s1; extern struct platform_device exynos4_device_i2s2; +extern struct platform_device exynos4_device_ohci; extern struct platform_device exynos4_device_pcm0; extern struct platform_device exynos4_device_pcm1; extern struct platform_device exynos4_device_pcm2; diff --git a/arch/arm/plat-samsung/include/plat/dma-ops.h b/arch/arm/plat-samsung/include/plat/dma-ops.h index 4c1a363526c..22eafc310bd 100644 --- a/arch/arm/plat-samsung/include/plat/dma-ops.h +++ b/arch/arm/plat-samsung/include/plat/dma-ops.h @@ -31,6 +31,7 @@ struct samsung_dma_info { enum dma_slave_buswidth width; dma_addr_t fifo; struct s3c2410_dma_client *client; + struct property *dt_dmach_prop; }; struct samsung_dma_ops { diff --git a/arch/arm/plat-samsung/include/plat/dma-pl330.h b/arch/arm/plat-samsung/include/plat/dma-pl330.h index 2e55e595867..c5eaad529de 100644 --- a/arch/arm/plat-samsung/include/plat/dma-pl330.h +++ b/arch/arm/plat-samsung/include/plat/dma-pl330.h @@ -21,7 +21,8 @@ * use these just as IDs. */ enum dma_ch { - DMACH_UART0_RX, + DMACH_DT_PROP = -1, + DMACH_UART0_RX = 0, DMACH_UART0_TX, DMACH_UART1_RX, DMACH_UART1_TX, diff --git a/arch/arm/plat-samsung/include/plat/dma-s3c24xx.h b/arch/arm/plat-samsung/include/plat/dma-s3c24xx.h index 1c1ed548125..d01576318b2 100644 --- a/arch/arm/plat-samsung/include/plat/dma-s3c24xx.h +++ b/arch/arm/plat-samsung/include/plat/dma-s3c24xx.h @@ -12,7 +12,7 @@ #include <plat/dma-core.h> -extern struct sysdev_class dma_sysclass; +extern struct bus_type dma_subsys; extern struct s3c2410_dma_chan s3c2410_chans[S3C_DMA_CHANNELS]; #define DMA_CH_VALID (1<<31) diff --git a/arch/arm/plat-samsung/include/plat/irqs.h b/arch/arm/plat-samsung/include/plat/irqs.h index 08d1a7ef97b..df46b776976 100644 --- a/arch/arm/plat-samsung/include/plat/irqs.h +++ b/arch/arm/plat-samsung/include/plat/irqs.h @@ -44,13 +44,14 @@ #define S5P_IRQ_VIC2(x) (S5P_VIC2_BASE + (x)) #define S5P_IRQ_VIC3(x) (S5P_VIC3_BASE + (x)) -#define S5P_TIMER_IRQ(x) (11 + (x)) +#define S5P_TIMER_IRQ(x) (IRQ_TIMER_BASE + (x)) #define IRQ_TIMER0 S5P_TIMER_IRQ(0) #define IRQ_TIMER1 S5P_TIMER_IRQ(1) #define IRQ_TIMER2 S5P_TIMER_IRQ(2) #define IRQ_TIMER3 S5P_TIMER_IRQ(3) #define IRQ_TIMER4 S5P_TIMER_IRQ(4) +#define IRQ_TIMER_COUNT (5) #define IRQ_EINT(x) ((x) < 16 ? ((x) + S5P_EINT_BASE1) \ : ((x) - 16 + S5P_EINT_BASE2)) diff --git a/arch/arm/plat-samsung/include/plat/keypad.h b/arch/arm/plat-samsung/include/plat/keypad.h index b59a6483cd8..c81ace332a1 100644 --- a/arch/arm/plat-samsung/include/plat/keypad.h +++ b/arch/arm/plat-samsung/include/plat/keypad.h @@ -13,32 +13,7 @@ #ifndef __PLAT_SAMSUNG_KEYPAD_H #define __PLAT_SAMSUNG_KEYPAD_H -#include <linux/input/matrix_keypad.h> - -#define SAMSUNG_MAX_ROWS 8 -#define SAMSUNG_MAX_COLS 8 - -/** - * struct samsung_keypad_platdata - Platform device data for Samsung Keypad. - * @keymap_data: pointer to &matrix_keymap_data. - * @rows: number of keypad row supported. - * @cols: number of keypad col supported. - * @no_autorepeat: disable key autorepeat. - * @wakeup: controls whether the device should be set up as wakeup source. - * @cfg_gpio: configure the GPIO. - * - * Initialisation data specific to either the machine or the platform - * for the device driver to use or call-back when configuring gpio. - */ -struct samsung_keypad_platdata { - const struct matrix_keymap_data *keymap_data; - unsigned int rows; - unsigned int cols; - bool no_autorepeat; - bool wakeup; - - void (*cfg_gpio)(unsigned int rows, unsigned int cols); -}; +#include <linux/input/samsung-keypad.h> /** * samsung_keypad_set_platdata - Set platform data for Samsung Keypad device. diff --git a/arch/arm/plat-samsung/include/plat/pm.h b/arch/arm/plat-samsung/include/plat/pm.h index dcf68709f9c..61fc53740fb 100644 --- a/arch/arm/plat-samsung/include/plat/pm.h +++ b/arch/arm/plat-samsung/include/plat/pm.h @@ -17,11 +17,12 @@ #include <linux/irq.h> -struct sys_device; +struct device; #ifdef CONFIG_PM extern __init int s3c_pm_init(void); +extern __init int s3c64xx_pm_init(void); #else @@ -29,6 +30,11 @@ static inline int s3c_pm_init(void) { return 0; } + +static inline int s3c64xx_pm_init(void) +{ + return 0; +} #endif /* configuration for the IRQ mask over sleep */ diff --git a/arch/arm/plat-samsung/include/plat/regs-serial.h b/arch/arm/plat-samsung/include/plat/regs-serial.h index 72073484702..29c26a81884 100644 --- a/arch/arm/plat-samsung/include/plat/regs-serial.h +++ b/arch/arm/plat-samsung/include/plat/regs-serial.h @@ -71,6 +71,7 @@ #define S3C2410_LCON_IRM (1<<6) #define S3C2440_UCON_CLKMASK (3<<10) +#define S3C2440_UCON_CLKSHIFT (10) #define S3C2440_UCON_PCLK (0<<10) #define S3C2440_UCON_UCLK (1<<10) #define S3C2440_UCON_PCLK2 (2<<10) @@ -78,6 +79,7 @@ #define S3C2443_UCON_EPLL (3<<10) #define S3C6400_UCON_CLKMASK (3<<10) +#define S3C6400_UCON_CLKSHIFT (10) #define S3C6400_UCON_PCLK (0<<10) #define S3C6400_UCON_PCLK2 (2<<10) #define S3C6400_UCON_UCLK0 (1<<10) @@ -90,11 +92,14 @@ #define S3C2440_UCON_DIVSHIFT (12) #define S3C2412_UCON_CLKMASK (3<<10) +#define S3C2412_UCON_CLKSHIFT (10) #define S3C2412_UCON_UCLK (1<<10) #define S3C2412_UCON_USYSCLK (3<<10) #define S3C2412_UCON_PCLK (0<<10) #define S3C2412_UCON_PCLK2 (2<<10) +#define S3C2410_UCON_CLKMASK (1 << 10) +#define S3C2410_UCON_CLKSHIFT (10) #define S3C2410_UCON_UCLK (1<<10) #define S3C2410_UCON_SBREAK (1<<4) @@ -193,6 +198,7 @@ /* Following are specific to S5PV210 */ #define S5PV210_UCON_CLKMASK (1<<10) +#define S5PV210_UCON_CLKSHIFT (10) #define S5PV210_UCON_PCLK (0<<10) #define S5PV210_UCON_UCLK (1<<10) @@ -221,29 +227,24 @@ #define S5PV210_UFSTAT_RXMASK (255<<0) #define S5PV210_UFSTAT_RXSHIFT (0) -#define NO_NEED_CHECK_CLKSRC 1 +#define S3C2410_UCON_CLKSEL0 (1 << 0) +#define S3C2410_UCON_CLKSEL1 (1 << 1) +#define S3C2410_UCON_CLKSEL2 (1 << 2) +#define S3C2410_UCON_CLKSEL3 (1 << 3) -#ifndef __ASSEMBLY__ +/* Default values for s5pv210 UCON and UFCON uart registers */ +#define S5PV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ + S3C2410_UCON_RXILEVEL | \ + S3C2410_UCON_TXIRQMODE | \ + S3C2410_UCON_RXIRQMODE | \ + S3C2410_UCON_RXFIFO_TOI | \ + S3C2443_UCON_RXERR_IRQEN) -/* struct s3c24xx_uart_clksrc - * - * this structure defines a named clock source that can be used for the - * uart, so that the best clock can be selected for the requested baud - * rate. - * - * min_baud and max_baud define the range of baud-rates this clock is - * acceptable for, if they are both zero, it is assumed any baud rate that - * can be generated from this clock will be used. - * - * divisor gives the divisor from the clock to the one seen by the uart -*/ +#define S5PV210_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ + S5PV210_UFCON_TXTRIG4 | \ + S5PV210_UFCON_RXTRIG4) -struct s3c24xx_uart_clksrc { - const char *name; - unsigned int divisor; - unsigned int min_baud; - unsigned int max_baud; -}; +#ifndef __ASSEMBLY__ /* configuration structure for per-machine configurations for the * serial port @@ -257,15 +258,13 @@ struct s3c2410_uartcfg { unsigned char unused; unsigned short flags; upf_t uart_flags; /* default uart flags */ + unsigned int clk_sel; unsigned int has_fracval; unsigned long ucon; /* value of ucon for port */ unsigned long ulcon; /* value of ulcon for port */ unsigned long ufcon; /* value of ufcon for port */ - - struct s3c24xx_uart_clksrc *clocks; - unsigned int clocks_size; }; /* s3c24xx_uart_devs diff --git a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h index 4c16fa3621b..aea68b60ef9 100644 --- a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h +++ b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h @@ -31,7 +31,6 @@ struct s3c64xx_spi_csinfo { /** * struct s3c64xx_spi_info - SPI Controller defining structure * @src_clk_nr: Clock source index for the CLK_CFG[SPI_CLKSEL] field. - * @src_clk_name: Platform name of the corresponding clock. * @clk_from_cmu: If the SPI clock/prescalar control block is present * by the platform's clock-management-unit and not in SPI controller. * @num_cs: Number of CS this controller emulates. @@ -43,7 +42,6 @@ struct s3c64xx_spi_csinfo { */ struct s3c64xx_spi_info { int src_clk_nr; - char *src_clk_name; bool clk_from_cmu; int num_cs; @@ -58,18 +56,28 @@ struct s3c64xx_spi_info { }; /** - * s3c64xx_spi_set_info - SPI Controller configure callback by the board + * s3c64xx_spi_set_platdata - SPI Controller configure callback by the board * initialization code. - * @cntrlr: SPI controller number the configuration is for. + * @pd: SPI platform data to set. * @src_clk_nr: Clock the SPI controller is to use to generate SPI clocks. * @num_cs: Number of elements in the 'cs' array. * * Call this from machine init code for each SPI Controller that * has some chips attached to it. */ -extern void s3c64xx_spi_set_info(int cntrlr, int src_clk_nr, int num_cs); -extern void s5pc100_spi_set_info(int cntrlr, int src_clk_nr, int num_cs); -extern void s5pv210_spi_set_info(int cntrlr, int src_clk_nr, int num_cs); -extern void s5p64x0_spi_set_info(int cntrlr, int src_clk_nr, int num_cs); +extern void s3c64xx_spi0_set_platdata(struct s3c64xx_spi_info *pd, + int src_clk_nr, int num_cs); +extern void s3c64xx_spi1_set_platdata(struct s3c64xx_spi_info *pd, + int src_clk_nr, int num_cs); +extern void s3c64xx_spi2_set_platdata(struct s3c64xx_spi_info *pd, + int src_clk_nr, int num_cs); +/* defined by architecture to configure gpio */ +extern int s3c64xx_spi0_cfg_gpio(struct platform_device *dev); +extern int s3c64xx_spi1_cfg_gpio(struct platform_device *dev); +extern int s3c64xx_spi2_cfg_gpio(struct platform_device *dev); + +extern struct s3c64xx_spi_info s3c64xx_spi0_pdata; +extern struct s3c64xx_spi_info s3c64xx_spi1_pdata; +extern struct s3c64xx_spi_info s3c64xx_spi2_pdata; #endif /* __S3C64XX_PLAT_SPI_H */ diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h index e7b3c752e91..656dc00d30e 100644 --- a/arch/arm/plat-samsung/include/plat/sdhci.h +++ b/arch/arm/plat-samsung/include/plat/sdhci.h @@ -66,8 +66,6 @@ struct s3c_sdhci_platdata { enum cd_types cd_type; enum clk_types clk_type; - char **clocks; /* set of clock sources */ - int ext_cd_gpio; bool ext_cd_gpio_invert; int (*ext_cd_init)(void (*notify_func)(struct platform_device *, @@ -125,16 +123,17 @@ extern void exynos4_setup_sdhci0_cfg_gpio(struct platform_device *, int w); extern void exynos4_setup_sdhci1_cfg_gpio(struct platform_device *, int w); extern void exynos4_setup_sdhci2_cfg_gpio(struct platform_device *, int w); extern void exynos4_setup_sdhci3_cfg_gpio(struct platform_device *, int w); +extern void s5p64x0_setup_sdhci0_cfg_gpio(struct platform_device *, int w); +extern void s5p64x0_setup_sdhci1_cfg_gpio(struct platform_device *, int w); +extern void s5p6440_setup_sdhci2_cfg_gpio(struct platform_device *, int w); +extern void s5p6450_setup_sdhci2_cfg_gpio(struct platform_device *, int w); /* S3C2416 SDHCI setup */ #ifdef CONFIG_S3C2416_SETUP_SDHCI -extern char *s3c2416_hsmmc_clksrcs[4]; - static inline void s3c2416_default_sdhci0(void) { #ifdef CONFIG_S3C_DEV_HSMMC - s3c_hsmmc0_def_platdata.clocks = s3c2416_hsmmc_clksrcs; s3c_hsmmc0_def_platdata.cfg_gpio = s3c2416_setup_sdhci0_cfg_gpio; #endif /* CONFIG_S3C_DEV_HSMMC */ } @@ -142,7 +141,6 @@ static inline void s3c2416_default_sdhci0(void) static inline void s3c2416_default_sdhci1(void) { #ifdef CONFIG_S3C_DEV_HSMMC1 - s3c_hsmmc1_def_platdata.clocks = s3c2416_hsmmc_clksrcs; s3c_hsmmc1_def_platdata.cfg_gpio = s3c2416_setup_sdhci1_cfg_gpio; #endif /* CONFIG_S3C_DEV_HSMMC1 */ } @@ -152,15 +150,13 @@ static inline void s3c2416_default_sdhci0(void) { } static inline void s3c2416_default_sdhci1(void) { } #endif /* CONFIG_S3C2416_SETUP_SDHCI */ + /* S3C64XX SDHCI setup */ #ifdef CONFIG_S3C64XX_SETUP_SDHCI -extern char *s3c64xx_hsmmc_clksrcs[4]; - static inline void s3c6400_default_sdhci0(void) { #ifdef CONFIG_S3C_DEV_HSMMC - s3c_hsmmc0_def_platdata.clocks = s3c64xx_hsmmc_clksrcs; s3c_hsmmc0_def_platdata.cfg_gpio = s3c64xx_setup_sdhci0_cfg_gpio; #endif } @@ -168,7 +164,6 @@ static inline void s3c6400_default_sdhci0(void) static inline void s3c6400_default_sdhci1(void) { #ifdef CONFIG_S3C_DEV_HSMMC1 - s3c_hsmmc1_def_platdata.clocks = s3c64xx_hsmmc_clksrcs; s3c_hsmmc1_def_platdata.cfg_gpio = s3c64xx_setup_sdhci1_cfg_gpio; #endif } @@ -176,7 +171,6 @@ static inline void s3c6400_default_sdhci1(void) static inline void s3c6400_default_sdhci2(void) { #ifdef CONFIG_S3C_DEV_HSMMC2 - s3c_hsmmc2_def_platdata.clocks = s3c64xx_hsmmc_clksrcs; s3c_hsmmc2_def_platdata.cfg_gpio = s3c64xx_setup_sdhci2_cfg_gpio; #endif } @@ -184,7 +178,6 @@ static inline void s3c6400_default_sdhci2(void) static inline void s3c6410_default_sdhci0(void) { #ifdef CONFIG_S3C_DEV_HSMMC - s3c_hsmmc0_def_platdata.clocks = s3c64xx_hsmmc_clksrcs; s3c_hsmmc0_def_platdata.cfg_gpio = s3c64xx_setup_sdhci0_cfg_gpio; #endif } @@ -192,7 +185,6 @@ static inline void s3c6410_default_sdhci0(void) static inline void s3c6410_default_sdhci1(void) { #ifdef CONFIG_S3C_DEV_HSMMC1 - s3c_hsmmc1_def_platdata.clocks = s3c64xx_hsmmc_clksrcs; s3c_hsmmc1_def_platdata.cfg_gpio = s3c64xx_setup_sdhci1_cfg_gpio; #endif } @@ -200,7 +192,6 @@ static inline void s3c6410_default_sdhci1(void) static inline void s3c6410_default_sdhci2(void) { #ifdef CONFIG_S3C_DEV_HSMMC2 - s3c_hsmmc2_def_platdata.clocks = s3c64xx_hsmmc_clksrcs; s3c_hsmmc2_def_platdata.cfg_gpio = s3c64xx_setup_sdhci2_cfg_gpio; #endif } @@ -215,15 +206,51 @@ static inline void s3c6400_default_sdhci2(void) { } #endif /* CONFIG_S3C64XX_SETUP_SDHCI */ +/* S5P64X0 SDHCI setup */ + +#ifdef CONFIG_S5P64X0_SETUP_SDHCI +static inline void s5p64x0_default_sdhci0(void) +{ +#ifdef CONFIG_S3C_DEV_HSMMC + s3c_hsmmc0_def_platdata.cfg_gpio = s5p64x0_setup_sdhci0_cfg_gpio; +#endif +} + +static inline void s5p64x0_default_sdhci1(void) +{ +#ifdef CONFIG_S3C_DEV_HSMMC1 + s3c_hsmmc1_def_platdata.cfg_gpio = s5p64x0_setup_sdhci1_cfg_gpio; +#endif +} + +static inline void s5p6440_default_sdhci2(void) +{ +#ifdef CONFIG_S3C_DEV_HSMMC2 + s3c_hsmmc2_def_platdata.cfg_gpio = s5p6440_setup_sdhci2_cfg_gpio; +#endif +} + +static inline void s5p6450_default_sdhci2(void) +{ +#ifdef CONFIG_S3C_DEV_HSMMC2 + s3c_hsmmc2_def_platdata.cfg_gpio = s5p6450_setup_sdhci2_cfg_gpio; +#endif +} + +#else +static inline void s5p64x0_default_sdhci0(void) { } +static inline void s5p64x0_default_sdhci1(void) { } +static inline void s5p6440_default_sdhci2(void) { } +static inline void s5p6450_default_sdhci2(void) { } + +#endif /* CONFIG_S5P64X0_SETUP_SDHCI */ + /* S5PC100 SDHCI setup */ #ifdef CONFIG_S5PC100_SETUP_SDHCI -extern char *s5pc100_hsmmc_clksrcs[4]; - static inline void s5pc100_default_sdhci0(void) { #ifdef CONFIG_S3C_DEV_HSMMC - s3c_hsmmc0_def_platdata.clocks = s5pc100_hsmmc_clksrcs; s3c_hsmmc0_def_platdata.cfg_gpio = s5pc100_setup_sdhci0_cfg_gpio; #endif } @@ -231,7 +258,6 @@ static inline void s5pc100_default_sdhci0(void) static inline void s5pc100_default_sdhci1(void) { #ifdef CONFIG_S3C_DEV_HSMMC1 - s3c_hsmmc1_def_platdata.clocks = s5pc100_hsmmc_clksrcs; s3c_hsmmc1_def_platdata.cfg_gpio = s5pc100_setup_sdhci1_cfg_gpio; #endif } @@ -239,7 +265,6 @@ static inline void s5pc100_default_sdhci1(void) static inline void s5pc100_default_sdhci2(void) { #ifdef CONFIG_S3C_DEV_HSMMC2 - s3c_hsmmc2_def_platdata.clocks = s5pc100_hsmmc_clksrcs; s3c_hsmmc2_def_platdata.cfg_gpio = s5pc100_setup_sdhci2_cfg_gpio; #endif } @@ -254,12 +279,9 @@ static inline void s5pc100_default_sdhci2(void) { } /* S5PV210 SDHCI setup */ #ifdef CONFIG_S5PV210_SETUP_SDHCI -extern char *s5pv210_hsmmc_clksrcs[4]; - static inline void s5pv210_default_sdhci0(void) { #ifdef CONFIG_S3C_DEV_HSMMC - s3c_hsmmc0_def_platdata.clocks = s5pv210_hsmmc_clksrcs; s3c_hsmmc0_def_platdata.cfg_gpio = s5pv210_setup_sdhci0_cfg_gpio; #endif } @@ -267,7 +289,6 @@ static inline void s5pv210_default_sdhci0(void) static inline void s5pv210_default_sdhci1(void) { #ifdef CONFIG_S3C_DEV_HSMMC1 - s3c_hsmmc1_def_platdata.clocks = s5pv210_hsmmc_clksrcs; s3c_hsmmc1_def_platdata.cfg_gpio = s5pv210_setup_sdhci1_cfg_gpio; #endif } @@ -275,7 +296,6 @@ static inline void s5pv210_default_sdhci1(void) static inline void s5pv210_default_sdhci2(void) { #ifdef CONFIG_S3C_DEV_HSMMC2 - s3c_hsmmc2_def_platdata.clocks = s5pv210_hsmmc_clksrcs; s3c_hsmmc2_def_platdata.cfg_gpio = s5pv210_setup_sdhci2_cfg_gpio; #endif } @@ -283,7 +303,6 @@ static inline void s5pv210_default_sdhci2(void) static inline void s5pv210_default_sdhci3(void) { #ifdef CONFIG_S3C_DEV_HSMMC3 - s3c_hsmmc3_def_platdata.clocks = s5pv210_hsmmc_clksrcs; s3c_hsmmc3_def_platdata.cfg_gpio = s5pv210_setup_sdhci3_cfg_gpio; #endif } @@ -298,12 +317,9 @@ static inline void s5pv210_default_sdhci3(void) { } /* EXYNOS4 SDHCI setup */ #ifdef CONFIG_EXYNOS4_SETUP_SDHCI -extern char *exynos4_hsmmc_clksrcs[4]; - static inline void exynos4_default_sdhci0(void) { #ifdef CONFIG_S3C_DEV_HSMMC - s3c_hsmmc0_def_platdata.clocks = exynos4_hsmmc_clksrcs; s3c_hsmmc0_def_platdata.cfg_gpio = exynos4_setup_sdhci0_cfg_gpio; #endif } @@ -311,7 +327,6 @@ static inline void exynos4_default_sdhci0(void) static inline void exynos4_default_sdhci1(void) { #ifdef CONFIG_S3C_DEV_HSMMC1 - s3c_hsmmc1_def_platdata.clocks = exynos4_hsmmc_clksrcs; s3c_hsmmc1_def_platdata.cfg_gpio = exynos4_setup_sdhci1_cfg_gpio; #endif } @@ -319,7 +334,6 @@ static inline void exynos4_default_sdhci1(void) static inline void exynos4_default_sdhci2(void) { #ifdef CONFIG_S3C_DEV_HSMMC2 - s3c_hsmmc2_def_platdata.clocks = exynos4_hsmmc_clksrcs; s3c_hsmmc2_def_platdata.cfg_gpio = exynos4_setup_sdhci2_cfg_gpio; #endif } @@ -327,7 +341,6 @@ static inline void exynos4_default_sdhci2(void) static inline void exynos4_default_sdhci3(void) { #ifdef CONFIG_S3C_DEV_HSMMC3 - s3c_hsmmc3_def_platdata.clocks = exynos4_hsmmc_clksrcs; s3c_hsmmc3_def_platdata.cfg_gpio = exynos4_setup_sdhci3_cfg_gpio; #endif } diff --git a/arch/arm/plat-samsung/include/plat/udc.h b/arch/arm/plat-samsung/include/plat/udc.h index 8c22d586bef..de8e2288a50 100644 --- a/arch/arm/plat-samsung/include/plat/udc.h +++ b/arch/arm/plat-samsung/include/plat/udc.h @@ -37,20 +37,7 @@ struct s3c2410_udc_mach_info { extern void __init s3c24xx_udc_set_platdata(struct s3c2410_udc_mach_info *); -/** - * s3c24xx_hsudc_platdata - Platform data for USB High-Speed gadget controller. - * @epnum: Number of endpoints to be instantiated by the controller driver. - * @gpio_init: Platform specific USB related GPIO initialization. - * @gpio_uninit: Platform specific USB releted GPIO uninitialzation. - * - * Representation of platform data for the S3C24XX USB 2.0 High Speed gadget - * controllers. - */ -struct s3c24xx_hsudc_platdata { - unsigned int epnum; - void (*gpio_init)(void); - void (*gpio_uninit)(void); -}; +struct s3c24xx_hsudc_platdata; extern void __init s3c24xx_hsudc_set_platdata(struct s3c24xx_hsudc_platdata *pd); diff --git a/arch/arm/plat-samsung/pm-gpio.c b/arch/arm/plat-samsung/pm-gpio.c index 4be016eaa6d..c2ff92c30bd 100644 --- a/arch/arm/plat-samsung/pm-gpio.c +++ b/arch/arm/plat-samsung/pm-gpio.c @@ -14,7 +14,7 @@ */ #include <linux/kernel.h> -#include <linux/sysdev.h> +#include <linux/device.h> #include <linux/init.h> #include <linux/io.h> #include <linux/gpio.h> diff --git a/arch/arm/plat-samsung/wakeup-mask.c b/arch/arm/plat-samsung/wakeup-mask.c index dc814037297..20c3d9117cc 100644 --- a/arch/arm/plat-samsung/wakeup-mask.c +++ b/arch/arm/plat-samsung/wakeup-mask.c @@ -11,7 +11,7 @@ #include <linux/kernel.h> #include <linux/spinlock.h> -#include <linux/sysdev.h> +#include <linux/device.h> #include <linux/types.h> #include <linux/irq.h> #include <linux/io.h> |