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author | Haavard Skinnemoen <hskinnemoen@atmel.com> | 2007-06-18 14:08:18 +0200 |
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committer | Haavard Skinnemoen <hskinnemoen@atmel.com> | 2007-06-23 14:52:52 +0200 |
commit | ab61f7d21ab7f564fce322c498e4a7d6171140db (patch) | |
tree | d7fbdeea3ea85fd65ce20a5132e4264cb866c9c9 /arch/avr32/boards | |
parent | 75154f402ef18e459ff97ddece25656b6c2b329c (diff) |
[AVR32] Fix bug in invalidate_dcache_region()
If (start + size) is not cacheline aligned and (start & mask) > (end &
mask), the last but one cacheline won't be invalidated as it should.
Fix this by rounding `end' down to the nearest cacheline boundary if
it gets adjusted due to misalignment.
Also flush the write buffer unconditionally -- if the dcache wrote
back a line just before we invalidated it, the dirty data may be
sitting in the write buffer waiting to corrupt our buffer later.
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
Diffstat (limited to 'arch/avr32/boards')
0 files changed, 0 insertions, 0 deletions