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authorHaavard Skinnemoen <hskinnemoen@atmel.com>2006-12-04 12:00:03 +0100
committerHaavard Skinnemoen <hskinnemoen@atmel.com>2006-12-08 13:06:23 +0100
commit01cb087e747538d6a831c3ab370a1e1fd4538d5c (patch)
tree7b91d418ee2da150f62d1db09a9b1b26fdc7a6ae /arch/avr32/mach-at32ap
parentda58e92f1f2939587ac85ae3abfec8b1c743400b (diff)
[AVR32] Set flow handler for external interrupts
Make sure that the flow handler for external interrupts is updated whenever they type is changed. Also make sure that the defaults correspond with how the interrupt controller is configured. Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
Diffstat (limited to 'arch/avr32/mach-at32ap')
-rw-r--r--arch/avr32/mach-at32ap/extint.c22
1 files changed, 20 insertions, 2 deletions
diff --git a/arch/avr32/mach-at32ap/extint.c b/arch/avr32/mach-at32ap/extint.c
index 4dff1f98890..b59272e81b9 100644
--- a/arch/avr32/mach-at32ap/extint.c
+++ b/arch/avr32/mach-at32ap/extint.c
@@ -49,12 +49,25 @@ static void eim_unmask_irq(unsigned int irq)
static int eim_set_irq_type(unsigned int irq, unsigned int flow_type)
{
struct at32_sm *sm = get_irq_chip_data(irq);
+ struct irq_desc *desc;
unsigned int i = irq - sm->eim_first_irq;
u32 mode, edge, level;
unsigned long flags;
int ret = 0;
- flow_type &= IRQ_TYPE_SENSE_MASK;
+ if (flow_type == IRQ_TYPE_NONE)
+ flow_type = IRQ_TYPE_LEVEL_LOW;
+
+ desc = &irq_desc[irq];
+ desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
+ desc->status |= flow_type & IRQ_TYPE_SENSE_MASK;
+
+ if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) {
+ desc->status |= IRQ_LEVEL;
+ set_irq_handler(irq, handle_level_irq);
+ } else {
+ set_irq_handler(irq, handle_edge_irq);
+ }
spin_lock_irqsave(&sm->lock, flags);
@@ -148,10 +161,15 @@ static int __init eim_init(void)
pattern = sm_readl(sm, EIM_MODE);
nr_irqs = fls(pattern);
+ /* Trigger on falling edge unless overridden by driver */
+ sm_writel(sm, EIM_MODE, 0UL);
+ sm_writel(sm, EIM_EDGE, 0UL);
+
sm->eim_chip = &eim_chip;
for (i = 0; i < nr_irqs; i++) {
- set_irq_chip(sm->eim_first_irq + i, &eim_chip);
+ set_irq_chip_and_handler(sm->eim_first_irq + i, &eim_chip,
+ handle_edge_irq);
set_irq_chip_data(sm->eim_first_irq + i, sm);
}