diff options
| author | Graf Yang <graf.yang@analog.com> | 2009-05-07 04:09:15 +0000 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2009-06-12 06:11:41 -0400 |
| commit | 5ba766752d14a741aa2d7a3c321917a310b34afb (patch) | |
| tree | a97d8174cded42843de44b08d613c350b28a2729 /arch/blackfin/Kconfig | |
| parent | a261eec0009b6093727fb7a59b12a10c6c981714 (diff) | |
Blackfin: work around anomaly 05000220
When possible, work around anomaly 05000220 (external memory is write
back cached, but L2 is not cached). If not possible, detect the
conditions at build time and reject any qualifying configurations.
Signed-off-by: Graf Yang <graf.yang@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin/Kconfig')
| -rw-r--r-- | arch/blackfin/Kconfig | 24 |
1 files changed, 17 insertions, 7 deletions
diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig index c04e7a4836f..f1a7969b46c 100644 --- a/arch/blackfin/Kconfig +++ b/arch/blackfin/Kconfig @@ -913,7 +913,7 @@ config BFIN_ICACHE_LOCK bool "Enable Instruction Cache Locking" choice - prompt "Policy" + prompt "External memory cache policy" depends on BFIN_DCACHE default BFIN_WB if !SMP default BFIN_WT if SMP @@ -954,12 +954,22 @@ config BFIN_WT endchoice -config BFIN_L2_CACHEABLE - bool "Cache L2 SRAM" - depends on (BFIN_DCACHE || BFIN_ICACHE) && (BF54x || (BF561 && !SMP)) - default n - help - Select to make L2 SRAM cacheable in L1 data and instruction cache. +choice + prompt "L2 SRAM cache policy" + depends on (BF54x || BF561) + default BFIN_L2_WT +config BFIN_L2_WB + bool "Write back" + depends on !SMP + +config BFIN_L2_WT + bool "Write through" + depends on !SMP + +config BFIN_L2_NOT_CACHED + bool "Not cached" + +endchoice config MPU bool "Enable the memory protection unit (EXPERIMENTAL)" |