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author | Robert Richter <robert.richter@amd.com> | 2008-09-24 11:25:31 +0200 |
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committer | Robert Richter <robert.richter@amd.com> | 2008-09-24 11:25:31 +0200 |
commit | f78e80209cf143be49f268c340431ae9fa3abb74 (patch) | |
tree | 820fa64b688099dfdd93d27ba03252738ca5c7e2 /arch/blackfin/include/asm/cache.h | |
parent | 4c168eaf7ea39f25a45a3d8c7eebc3fedb633a1d (diff) | |
parent | 24342c34a022ee90839873d91396045e12ef1090 (diff) |
Merge commit 'v2.6.27-rc5' into tip/oprofile
Conflicts:
arch/x86/oprofile/nmi_int.c
Diffstat (limited to 'arch/blackfin/include/asm/cache.h')
-rw-r--r-- | arch/blackfin/include/asm/cache.h | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/arch/blackfin/include/asm/cache.h b/arch/blackfin/include/asm/cache.h new file mode 100644 index 00000000000..023d72133b5 --- /dev/null +++ b/arch/blackfin/include/asm/cache.h @@ -0,0 +1,29 @@ +/* + * include/asm-blackfin/cache.h + */ +#ifndef __ARCH_BLACKFIN_CACHE_H +#define __ARCH_BLACKFIN_CACHE_H + +/* + * Bytes per L1 cache line + * Blackfin loads 32 bytes for cache + */ +#define L1_CACHE_SHIFT 5 +#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) +#define SMP_CACHE_BYTES L1_CACHE_BYTES + +/* + * Put cacheline_aliged data to L1 data memory + */ +#ifdef CONFIG_CACHELINE_ALIGNED_L1 +#define __cacheline_aligned \ + __attribute__((__aligned__(L1_CACHE_BYTES), \ + __section__(".data_l1.cacheline_aligned"))) +#endif + +/* + * largest L1 which this arch supports + */ +#define L1_CACHE_SHIFT_MAX 5 + +#endif |