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authorSonic Zhang <sonic.zhang@analog.com>2010-09-06 10:16:04 +0000
committerMike Frysinger <vapier@gentoo.org>2010-10-22 03:48:59 -0400
commit99a5b2878b56d24919eb7e646f2d8e02f63a6efc (patch)
tree5db99463ad9f68e383aa54c9d102f91f5b890091 /arch/blackfin/include/asm/cachectl.h
parent73775b892ee70bdc0dbd6aeeebb50894d062f9a1 (diff)
Blackfin: add new cacheflush syscall
Flushing caches sometimes requires anomaly workarounds which require supervisor-only insns. Normally we don't need to flush caches from userspace so this isn't a problem, but when gcc generates trampolines on the stack, we do. So add a new syscall for gcc to use modeled after the mips version. Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin/include/asm/cachectl.h')
-rw-r--r--arch/blackfin/include/asm/cachectl.h20
1 files changed, 20 insertions, 0 deletions
diff --git a/arch/blackfin/include/asm/cachectl.h b/arch/blackfin/include/asm/cachectl.h
new file mode 100644
index 00000000000..03255df6c1e
--- /dev/null
+++ b/arch/blackfin/include/asm/cachectl.h
@@ -0,0 +1,20 @@
+/*
+ * based on the mips/cachectl.h
+ *
+ * Copyright 2010 Analog Devices Inc.
+ * Copyright (C) 1994, 1995, 1996 by Ralf Baechle
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef _ASM_CACHECTL
+#define _ASM_CACHECTL
+
+/*
+ * Options for cacheflush system call
+ */
+#define ICACHE (1<<0) /* flush instruction cache */
+#define DCACHE (1<<1) /* writeback and flush data cache */
+#define BCACHE (ICACHE|DCACHE) /* flush both caches */
+
+#endif /* _ASM_CACHECTL */