diff options
author | Ingo Molnar <mingo@elte.hu> | 2009-06-17 12:52:15 +0200 |
---|---|---|
committer | Ingo Molnar <mingo@elte.hu> | 2009-06-17 12:56:49 +0200 |
commit | eadb8a091b27a840de7450f84ecff5ef13476424 (patch) | |
tree | 58c3782d40def63baa8167f3d31e3048cb4c7660 /arch/blackfin/include/asm/cplb.h | |
parent | 73874005cd8800440be4299bd095387fff4b90ac (diff) | |
parent | 65795efbd380a832ae508b04dba8f8e53f0b84d9 (diff) |
Merge branch 'linus' into tracing/hw-breakpoints
Conflicts:
arch/x86/Kconfig
arch/x86/kernel/traps.c
arch/x86/power/cpu.c
arch/x86/power/cpu_32.c
kernel/Makefile
Semantic conflict:
arch/x86/kernel/hw_breakpoint.c
Merge reason: Resolve the conflicts, move from put_cpu_no_sched() to
put_cpu() in arch/x86/kernel/hw_breakpoint.c.
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/blackfin/include/asm/cplb.h')
-rw-r--r-- | arch/blackfin/include/asm/cplb.h | 35 |
1 files changed, 19 insertions, 16 deletions
diff --git a/arch/blackfin/include/asm/cplb.h b/arch/blackfin/include/asm/cplb.h index ad566ff9ad1..a75a6a9f094 100644 --- a/arch/blackfin/include/asm/cplb.h +++ b/arch/blackfin/include/asm/cplb.h @@ -53,29 +53,32 @@ #define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_COMMON) #endif +#define SDRAM_DNON_CHBL (CPLB_COMMON) +#define SDRAM_EBIU (CPLB_COMMON) +#define SDRAM_OOPS (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY) + #define L1_DMEMORY (CPLB_LOCK | CPLB_COMMON) #ifdef CONFIG_SMP -#define L2_ATTR (INITIAL_T | I_CPLB | D_CPLB) -#define L2_IMEMORY (CPLB_COMMON | CPLB_LOCK) -#define L2_DMEMORY (CPLB_COMMON | CPLB_LOCK) +#define L2_ATTR (INITIAL_T | I_CPLB | D_CPLB) +#define L2_IMEMORY (CPLB_COMMON) +#define L2_DMEMORY (CPLB_LOCK | CPLB_COMMON) #else -#ifdef CONFIG_BFIN_L2_CACHEABLE -#define L2_IMEMORY (SDRAM_IGENERIC) -#define L2_DMEMORY (SDRAM_DGENERIC) -#else -#define L2_IMEMORY (CPLB_COMMON) -#define L2_DMEMORY (CPLB_COMMON) -#endif /* CONFIG_BFIN_L2_CACHEABLE */ - -#define L2_ATTR (INITIAL_T | SWITCH_T | I_CPLB | D_CPLB) +#define L2_ATTR (INITIAL_T | SWITCH_T | I_CPLB | D_CPLB) +#define L2_IMEMORY (SDRAM_IGENERIC) + +# if defined(CONFIG_BFIN_L2_WB) +# define L2_DMEMORY (CPLB_L1_CHBL | CPLB_COMMON) +# elif defined(CONFIG_BFIN_L2_WT) +# define L2_DMEMORY (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_COMMON) +# elif defined(CONFIG_BFIN_L2_NOT_CACHED) +# define L2_DMEMORY (CPLB_COMMON) +# else +# define L2_DMEMORY (0) +# endif #endif /* CONFIG_SMP */ -#define SDRAM_DNON_CHBL (CPLB_COMMON) -#define SDRAM_EBIU (CPLB_COMMON) -#define SDRAM_OOPS (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY) - #define SIZE_1K 0x00000400 /* 1K */ #define SIZE_4K 0x00001000 /* 4K */ #define SIZE_1M 0x00100000 /* 1M */ |