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authorSonic Zhang <sonic.zhang@analog.com>2013-12-04 15:27:47 +0800
committerSteven Miao <realmz6@gmail.com>2014-01-29 15:12:20 +0800
commit1b6012394bec5dc653d495245c5495db08f817f6 (patch)
tree88c290099d8155fd3c4c5828843c29837c815e05 /arch/blackfin/include/asm/def_LPBlackfin.h
parentcccdfcf728e2f322e8986a39bc02bf5aaa8fe8a7 (diff)
blackfin: Support L1 SRAM parity checking feature on bf60x
Move code for the SEC faults from the IRQ hanlders into IRQ actions. refine bfin fault routine handle Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Steven Miao <realmz6@gmail.com>
Diffstat (limited to 'arch/blackfin/include/asm/def_LPBlackfin.h')
-rw-r--r--arch/blackfin/include/asm/def_LPBlackfin.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/blackfin/include/asm/def_LPBlackfin.h b/arch/blackfin/include/asm/def_LPBlackfin.h
index ca67145c6a4..c5c8d8a3a5f 100644
--- a/arch/blackfin/include/asm/def_LPBlackfin.h
+++ b/arch/blackfin/include/asm/def_LPBlackfin.h
@@ -544,6 +544,7 @@ do { \
#define DCBS_P 0x04 /* L1 Data Cache Bank Select */
#define PORT_PREF0_P 0x12 /* DAG0 Port Preference */
#define PORT_PREF1_P 0x13 /* DAG1 Port Preference */
+#define RDCHK 0x9 /* Enable L1 Parity Check */
/* Masks */
#define ENDM 0x00000001 /* (doesn't really exist) Enable