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authorRobin Getz <robin.getz@analog.com>2010-07-09 17:29:26 +0000
committerMike Frysinger <vapier@gentoo.org>2010-10-22 03:48:55 -0400
commitc0ab9387456d7660dead96ce1b5463741f087db1 (patch)
treed14c3893db3f35db1f856c59dbe68781f954b310 /arch/blackfin/include
parent3d7dc8836a0f08cbe6d8d499ddce05809b687f58 (diff)
Blackfin: workaround anomaly 05000481 (corruption with ITEST MMRs)
Nothing actually needs to use these MMRs (as direct cache manipulation is done with the DTEST MMRs), so simply hide the read funcs behind the anomaly define. They're generally unusable anyways when this anomaly is in effect. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin/include')
-rw-r--r--arch/blackfin/include/asm/cdef_LPBlackfin.h9
1 files changed, 6 insertions, 3 deletions
diff --git a/arch/blackfin/include/asm/cdef_LPBlackfin.h b/arch/blackfin/include/asm/cdef_LPBlackfin.h
index 6c39d94b44d..a1f6817687e 100644
--- a/arch/blackfin/include/asm/cdef_LPBlackfin.h
+++ b/arch/blackfin/include/asm/cdef_LPBlackfin.h
@@ -172,16 +172,19 @@
#define bfin_write_ICPLB_DATA14(val) bfin_write32(ICPLB_DATA14,val)
#define bfin_read_ICPLB_DATA15() bfin_read32(ICPLB_DATA15)
#define bfin_write_ICPLB_DATA15(val) bfin_write32(ICPLB_DATA15,val)
-#define bfin_read_ITEST_COMMAND() bfin_read32(ITEST_COMMAND)
#define bfin_write_ITEST_COMMAND(val) bfin_write32(ITEST_COMMAND,val)
#if 0
#define ITEST_INDEX 0xFFE01304 /* Instruction Test Index Register */
#endif
-#define bfin_read_ITEST_DATA0() bfin_read32(ITEST_DATA0)
#define bfin_write_ITEST_DATA0(val) bfin_write32(ITEST_DATA0,val)
-#define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1)
#define bfin_write_ITEST_DATA1(val) bfin_write32(ITEST_DATA1,val)
+#if ANOMALY_05000481
+#define bfin_read_ITEST_COMMAND() bfin_read32(ITEST_COMMAND)
+#define bfin_read_ITEST_DATA0() bfin_read32(ITEST_DATA0)
+#define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1)
+#endif
+
/* Event/Interrupt Registers*/
#define bfin_read_EVT0() bfin_read32(EVT0)