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| author | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2009-06-15 10:36:54 +1000 |
|---|---|---|
| committer | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2009-06-15 10:36:54 +1000 |
| commit | 7dafd239ab522d38979ebe44d79aa68ad7b1a383 (patch) | |
| tree | 04754a0c6495e57c1fe5f417fbfc99272d353c0e /arch/blackfin/kernel/cplb-mpu/cacheinit.c | |
| parent | bc47ab0241c7c86da4f5e5f82fbca7d45387c18d (diff) | |
| parent | 45e3e1935e2857c54783291107d33323b3ef33c8 (diff) | |
Merge commit 'origin/master' into next
Diffstat (limited to 'arch/blackfin/kernel/cplb-mpu/cacheinit.c')
| -rw-r--r-- | arch/blackfin/kernel/cplb-mpu/cacheinit.c | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/arch/blackfin/kernel/cplb-mpu/cacheinit.c b/arch/blackfin/kernel/cplb-mpu/cacheinit.c index c6ff947f9d3..d5a86c3017f 100644 --- a/arch/blackfin/kernel/cplb-mpu/cacheinit.c +++ b/arch/blackfin/kernel/cplb-mpu/cacheinit.c @@ -55,7 +55,14 @@ void __cpuinit bfin_dcache_init(struct cplb_entry *dcplb_tbl) } ctrl = bfin_read_DMEM_CONTROL(); - ctrl |= DMEM_CNTR; + + /* + * Anomaly notes: + * 05000287 - We implement workaround #2 - Change the DMEM_CONTROL + * register, so that the port preferences for DAG0 and DAG1 are set + * to port B + */ + ctrl |= DMEM_CNTR | PORT_PREF0 | (ANOMALY_05000287 ? PORT_PREF1 : 0); bfin_write_DMEM_CONTROL(ctrl); SSYNC(); } |