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authorYi Li <yi.li@analog.com>2009-08-07 01:20:58 +0000
committerMike Frysinger <vapier@gentoo.org>2009-09-16 22:10:19 -0400
commiteb7bd9c461bbfbb195cb1e1346453222a4352df4 (patch)
tree9c92f6ce5160b655213bbcff8175878771594121 /arch/blackfin/mach-bf561
parent8312440e05ea74feabc648ad8f36c823af4ddd8e (diff)
Blackfin: cleanup sync handling when enabling/disabling cplbs
The handling of updating the [DI]MEM_CONTROL MMRs does not follow proper sync procedures as laid out in the Blackfin programming manual. So rather than audit/fix every call location, create helper functions that do the right things in order to safely update these MMRs. Then convert all call sites to use these new helper functions. While we're fixing the code, drop the workaround for anomaly 05000125 as that anomaly applies to old versions of silicon that we do not support. Signed-off-by: Yi Li <yi.li@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin/mach-bf561')
-rw-r--r--arch/blackfin/mach-bf561/secondary.S20
1 files changed, 4 insertions, 16 deletions
diff --git a/arch/blackfin/mach-bf561/secondary.S b/arch/blackfin/mach-bf561/secondary.S
index 097550f7b55..f72a6af20c4 100644
--- a/arch/blackfin/mach-bf561/secondary.S
+++ b/arch/blackfin/mach-bf561/secondary.S
@@ -85,16 +85,10 @@ ENTRY(_coreb_trampoline_start)
R0 = ~ENICPLB;
R0 = R0 & R1;
- /* Anomaly 05000125 */
-#ifdef ANOMALY_05000125
- CLI R2;
- SSYNC;
-#endif
+ /* Disabling of CPLBs should be proceeded by a CSYNC */
+ CSYNC;
[p0] = R0;
SSYNC;
-#ifdef ANOMALY_05000125
- STI R2;
-#endif
/* Turn off the dcache */
p0.l = LO(DMEM_CONTROL);
@@ -103,16 +97,10 @@ ENTRY(_coreb_trampoline_start)
R0 = ~ENDCPLB;
R0 = R0 & R1;
- /* Anomaly 05000125 */
-#ifdef ANOMALY_05000125
- CLI R2;
- SSYNC;
-#endif
+ /* Disabling of CPLBs should be proceeded by a CSYNC */
+ CSYNC;
[p0] = R0;
SSYNC;
-#ifdef ANOMALY_05000125
- STI R2;
-#endif
/* in case of double faults, save a few things */
p0.l = _init_retx_coreb;