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author | Sonic Zhang <sonic.zhang@analog.com> | 2013-12-04 15:27:47 +0800 |
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committer | Steven Miao <realmz6@gmail.com> | 2014-01-29 15:12:20 +0800 |
commit | 1b6012394bec5dc653d495245c5495db08f817f6 (patch) | |
tree | 88c290099d8155fd3c4c5828843c29837c815e05 /arch/blackfin/mach-bf609 | |
parent | cccdfcf728e2f322e8986a39bc02bf5aaa8fe8a7 (diff) |
blackfin: Support L1 SRAM parity checking feature on bf60x
Move code for the SEC faults from the IRQ hanlders into IRQ actions.
refine bfin fault routine handle
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Steven Miao <realmz6@gmail.com>
Diffstat (limited to 'arch/blackfin/mach-bf609')
-rw-r--r-- | arch/blackfin/mach-bf609/Kconfig | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/blackfin/mach-bf609/Kconfig b/arch/blackfin/mach-bf609/Kconfig index b0fca44110b..6584190faeb 100644 --- a/arch/blackfin/mach-bf609/Kconfig +++ b/arch/blackfin/mach-bf609/Kconfig @@ -17,6 +17,12 @@ config SEC_IRQ_PRIORITY_LEVELS Divide the total number of interrupt priority levels into sub-levels. There is 2 ^ (SEC_IRQ_PRIORITY_LEVELS + 1) different levels. +config L1_PARITY_CHECK + bool "Enable L1 parity check" + default n + help + Enable the L1 parity check in L1 sram. A fault event is raised + when L1 parity error is found. comment "System Cross Bar Priority Assignment" |