diff options
| author | Mike Frysinger <michael.frysinger@analog.com> | 2007-06-11 15:31:30 +0800 |
|---|---|---|
| committer | Bryan Wu <bryan.wu@analog.com> | 2007-06-11 15:31:30 +0800 |
| commit | 51be24c351bc9ee4937121100adb098eeb1effdd (patch) | |
| tree | b766c400cab7c51bfc7672cfbc3402bc83be5fb3 /arch/blackfin/mach-common/cache.S | |
| parent | 52a078120c33b06a9abb721357adaafc3b55b7c1 (diff) | |
Blackfin arch: add proper ENDPROC()
add proper ENDPROC() to close out assembly functions
so size/type is set properly in the final ELF image
Signed-off-by: Mike Frysinger <michael.frysinger@analog.com>
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Diffstat (limited to 'arch/blackfin/mach-common/cache.S')
| -rw-r--r-- | arch/blackfin/mach-common/cache.S | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/blackfin/mach-common/cache.S b/arch/blackfin/mach-common/cache.S index bb9446ef66e..8bd2af1935b 100644 --- a/arch/blackfin/mach-common/cache.S +++ b/arch/blackfin/mach-common/cache.S @@ -70,6 +70,7 @@ ENTRY(_cache_invalidate) .Lno_dcache_b: R7 = [SP++]; RTS; +ENDPROC(_cache_invalidate) /* Invalidate the Entire Instruction cache by * disabling IMC bit @@ -106,6 +107,8 @@ ENTRY(_invalidate_entire_icache) ( R7:5) = [SP++]; RTS; +ENDPROC(_invalidate_entire_icache) +ENDPROC(_icache_invalidate) /* * blackfin_cache_flush_range(start, end) @@ -129,6 +132,7 @@ ENTRY(_blackfin_icache_flush_range) IFLUSH [P0]; SSYNC; RTS; +ENDPROC(_blackfin_icache_flush_range) /* * blackfin_icache_dcache_flush_range(start, end) @@ -155,6 +159,7 @@ ENTRY(_blackfin_icache_dcache_flush_range) FLUSH [P0]; SSYNC; RTS; +ENDPROC(_blackfin_icache_dcache_flush_range) /* Throw away all D-cached data in specified region without any obligation to * write them back. However, we must clean the D-cached entries around the @@ -183,6 +188,7 @@ ENTRY(_blackfin_dcache_invalidate_range) FLUSHINV[P0]; SSYNC; RTS; +ENDPROC(_blackfin_dcache_invalidate_range) /* Invalidate the Entire Data cache by * clearing DMC[1:0] bits @@ -221,6 +227,8 @@ ENTRY(_dcache_invalidate) ( R7:6) = [SP++]; RTS; +ENDPROC(_dcache_invalidate) +ENDPROC(_invalidate_entire_dcache) ENTRY(_blackfin_dcache_flush_range) R2 = -L1_CACHE_BYTES; @@ -241,6 +249,7 @@ ENTRY(_blackfin_dcache_flush_range) FLUSH[P0]; SSYNC; RTS; +ENDPROC(_blackfin_dcache_flush_range) ENTRY(_blackfin_dflush_page) P1 = 1 << (PAGE_SHIFT - L1_CACHE_SHIFT); @@ -251,3 +260,4 @@ ENTRY(_blackfin_dflush_page) .Lfl1: FLUSH [P0++]; SSYNC; RTS; +ENDPROC(_blackfin_dflush_page) |