summaryrefslogtreecommitdiffstats
path: root/arch/blackfin/mach-common/cache.S
diff options
context:
space:
mode:
authorLinus Torvalds <torvalds@linux-foundation.org>2010-08-09 21:01:11 -0700
committerLinus Torvalds <torvalds@linux-foundation.org>2010-08-09 21:01:11 -0700
commit0fc2f137226eff4c9dd90864dda5c237474c3ec5 (patch)
tree50ec67f1f9d144a3ceb5ccff45a37bc5005f6c3d /arch/blackfin/mach-common/cache.S
parentdcded10f6dce10411b16134ce9cc87bfdf75c13f (diff)
parentaab2393e2ec52c74b419af7c26a12e21584e483b (diff)
Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/vapier/blackfin
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/vapier/blackfin: (32 commits) Blackfin: gpio: add a debounce stub Blackfin: update defconfigs Blackfin: remove CONFIG_MEM_GENERIC_BOARD Blackfin: dpmc: punt unnecessary RTC_ISTAT clearing Blackfin: unify rotary encoder bitmasks Blackfin: unify SDH/RSI bitmasks Blackfin: BF54x: tweak DMAC MMR naming to match other ports Blackfin: TWI: clean up the MMR names Blackfin: add EVT_OVERRIDE/IPRIO core MMR helpers Blackfin: add support for dynamic ftrace Blackfin: add support for LZO compressed kernels Blackfin: portmux: fix peripheral map overflow when requesting pins Blackfin: document SPI CS limitations with CPHA=0 Blackfin: remove useless and outdated documentation Blackfin: BF51x/BF52x: support GPIO Hysteresis/Schmitt Trigger options Blackfin: gpio/portmux: clean up whitespace corruption Blackfin: make sure mmiowb inserts a write barrier with SSYNC Blackfin: fix DMA/cache bug when resuming from suspend to RAM Blackfin: BF51x: fix handling of PH8 (the "internal" SPI0SEL4 pin) Blackfin: add a GPIO_DEFAULT_BOOT_SPI_CS ...
Diffstat (limited to 'arch/blackfin/mach-common/cache.S')
-rw-r--r--arch/blackfin/mach-common/cache.S15
1 files changed, 4 insertions, 11 deletions
diff --git a/arch/blackfin/mach-common/cache.S b/arch/blackfin/mach-common/cache.S
index ea540318a22..790c767ca95 100644
--- a/arch/blackfin/mach-common/cache.S
+++ b/arch/blackfin/mach-common/cache.S
@@ -11,7 +11,11 @@
#include <asm/cache.h>
#include <asm/page.h>
+#ifdef CONFIG_CACHE_FLUSH_L1
+.section .l1.text
+#else
.text
+#endif
/* 05000443 - IFLUSH cannot be last instruction in hardware loop */
#if ANOMALY_05000443
@@ -64,17 +68,6 @@
/* Invalidate all instruction cache lines assocoiated with this memory area */
ENTRY(_blackfin_icache_flush_range)
-/*
- * Walkaround to avoid loading wrong instruction after invalidating icache
- * and following sequence is met.
- *
- * 1) One instruction address is cached in the instruction cache.
- * 2) This instruction in SDRAM is changed.
- * 3) IFLASH[P0] is executed only once in blackfin_icache_flush_range().
- * 4) This instruction is executed again, but the old one is loaded.
- */
- P0 = R0;
- IFLUSH[P0];
do_flush IFLUSH
ENDPROC(_blackfin_icache_flush_range)