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authorArnd Bergmann <arnd@arndb.de>2009-06-26 08:14:36 +0200
committerJesper Nilsson <jesper.nilsson@axis.com>2009-08-31 18:38:11 +0200
commitd8fb91e8344ff11381fc47d43e0b234065be4bd0 (patch)
tree36b72b3b6fff5f53d53cc14587dbc96f73d29ae5 /arch/cris/include/asm
parentadda766193ea1cf3137484a9521972d080d0b7af (diff)
CRIS: add pgprot_noncached
On CRIS, the high address bit controls caching, which means that we can add a pgprot_noncached() macro that sets this bit in the address. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Jesper Nilsson <jesper.nilsson@axis.com>
Diffstat (limited to 'arch/cris/include/asm')
-rw-r--r--arch/cris/include/asm/pgtable.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/cris/include/asm/pgtable.h b/arch/cris/include/asm/pgtable.h
index 50aa974aa83..1fcce00f01f 100644
--- a/arch/cris/include/asm/pgtable.h
+++ b/arch/cris/include/asm/pgtable.h
@@ -197,6 +197,8 @@ static inline pte_t __mk_pte(void * page, pgprot_t pgprot)
static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
{ pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot); return pte; }
+#define pgprot_noncached(prot) __pgprot((pgprot_val(prot) | _PAGE_NO_CACHE))
+
/* pte_val refers to a page in the 0x4xxxxxxx physical DRAM interval
* __pte_page(pte_val) refers to the "virtual" DRAM interval