summaryrefslogtreecommitdiffstats
path: root/arch/frv/mm/cache-page.c
diff options
context:
space:
mode:
authorJohn Fastabend <john.r.fastabend@intel.com>2011-11-12 01:12:22 +0000
committerJeff Kirsher <jeffrey.t.kirsher@intel.com>2011-12-05 00:12:53 -0800
commit43497cc21889725a0fa0dcea1ce72ec567796f3a (patch)
treef9d02cf34021d2bbea95590ac13b9080a5359f9b /arch/frv/mm/cache-page.c
parent4909fe979c4863bb748cd35e2cec9aab1e140a10 (diff)
ixgbe: DCB: IEEE transitions may fail to reprogram hardware.
Transitioning through an IEEE DCBX version from a CEE DCBX and back (CEE->IEEE->CEE) may leave IEEE attributes programmed in the hardware. DCB uses a bit field in the set routines to determine which attributes PG, PFC, APP need to be reprogrammed. This is needed because user flow allows queueing a series of changes and then reprogramming the hardware with the entire set in one operation. When transitioning from IEEE DCBX mode back into CEE DCBX mode the PG and PFC bits need to be set so the possibly different CEE attributes get programmed into the device. This patch fixes broken logic that was evaluating to 0 and never setting any bits. Further this removes some checks for num_tc in set routines. This logic only worked when the number of traffic classes and user priorities were equal. This is no longer the case for X540 devices. Besides we can trust user input in this case if the device is incorrectly configured the DCB bandwidths will be incorrectly mapped but no OOPs, BUG, or hardware failure will occur. Signed-off-by: John Fastabend <john.r.fastabend@intel.com> Tested-by: Ross Brattain <ross.b.brattain@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Diffstat (limited to 'arch/frv/mm/cache-page.c')
0 files changed, 0 insertions, 0 deletions