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| author | Jisheng Zhang <jszhang@marvell.com> | 2014-06-12 17:38:40 +0800 |
|---|---|---|
| committer | Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> | 2014-06-16 13:09:04 +0200 |
| commit | 44991eb4bfd63b043b50e880d347a7946d6a9736 (patch) | |
| tree | 8fcacf5483a5efe8b605521867cdbc72fc1c3ede /arch/hexagon | |
| parent | 7171511eaec5bf23fb06078f59784a3a0626b38f (diff) | |
ARM: dts: berlin2q: set L2CC tag and data latency to 2 cycles
For all BG2Q SoCs, 2 cycles is the best/correct value.
Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Diffstat (limited to 'arch/hexagon')
0 files changed, 0 insertions, 0 deletions