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authorAndi Kleen <ak@suse.de>2006-01-27 02:03:50 +0100
committerGreg Kroah-Hartman <gregkh@suse.de>2006-01-31 18:00:13 -0800
commit3103039cc2a8dc6ababc29afac5c3cadbfa69af9 (patch)
treef89e6a1ca25281fbf78f6438c0463d06251ae3a3 /arch/i386/pci
parent877be3f0304de16a77f11b2b47f1291b800d5479 (diff)
[PATCH] PCI: handle bogus MCFG entries
Handle more bogus MCFG entries Some Asus P4 boards seem to have broken MCFG tables with only a single entry for busses 0-0. Special case these and assume they mean all busses can be accessed. Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'arch/i386/pci')
-rw-r--r--arch/i386/pci/mmconfig.c15
1 files changed, 13 insertions, 2 deletions
diff --git a/arch/i386/pci/mmconfig.c b/arch/i386/pci/mmconfig.c
index 4bb4d4b0f73..0ee8a983708 100644
--- a/arch/i386/pci/mmconfig.c
+++ b/arch/i386/pci/mmconfig.c
@@ -36,8 +36,7 @@ static u32 get_base_addr(unsigned int seg, int bus, unsigned devfn)
while (1) {
++cfg_num;
if (cfg_num >= pci_mmcfg_config_num) {
- /* Not found - fallback to type 1 */
- return 0;
+ break;
}
cfg = &pci_mmcfg_config[cfg_num];
if (cfg->pci_segment_group_number != seg)
@@ -46,6 +45,18 @@ static u32 get_base_addr(unsigned int seg, int bus, unsigned devfn)
(cfg->end_bus_number >= bus))
return cfg->base_address;
}
+
+ /* Handle more broken MCFG tables on Asus etc.
+ They only contain a single entry for bus 0-0. Assume
+ this applies to all busses. */
+ cfg = &pci_mmcfg_config[0];
+ if (pci_mmcfg_config_num == 1 &&
+ cfg->pci_segment_group_number == 0 &&
+ (cfg->start_bus_number | cfg->end_bus_number) == 0)
+ return cfg->base_address;
+
+ /* Fall back to type 0 */
+ return 0;
}
static inline void pci_exp_set_dev_base(unsigned int base, int bus, int devfn)