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authorKisoo Yu <ksoo.yu@samsung.com>2012-04-24 14:54:15 -0700
committerKukjin Kim <kgene.kim@samsung.com>2012-05-16 07:03:41 +0900
commit57b317f912b3f4b05c834818c73d7c8ea22642f7 (patch)
tree9963b419762b3bbe9a30544c9543edb199df5cde /arch/ia64/Kconfig
parentf10590c9836c9fc595d1dafff965b280029d4f16 (diff)
ARM: EXYNOS: Add pre-divider and fout mux clocks for bpll and mpll
The fout clock of BPLL and MPLL have a selectable source on EXYNOS5250. The clock options are a fixed divided by 2 clock and the output of the PLL itself. Add support for these new clock instances. Signed-off-by: Kisoo Yu <ksoo.yu@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> [kgene.kim@samsung.com: moved common pll stuff into s5p-clock.c] Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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