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| author | David Woodhouse <David.Woodhouse@intel.com> | 2008-08-12 11:28:00 +0100 |
|---|---|---|
| committer | David Woodhouse <David.Woodhouse@intel.com> | 2008-08-12 11:28:00 +0100 |
| commit | 742c52533b05d8ae83c794bd6811100675b85ce5 (patch) | |
| tree | de89a81d88c19504d1dc4f023a4b480c9022b3b5 /arch/ia64/include/asm/cache.h | |
| parent | 36cd4fb5d277f34fe9e4db0deac2d4efd7dff735 (diff) | |
| parent | 10fec20ef5eec1c91913baec1225400f0d02df40 (diff) | |
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
Conflicts:
include/asm-arm/arch-omap/onenand.h
Diffstat (limited to 'arch/ia64/include/asm/cache.h')
| -rw-r--r-- | arch/ia64/include/asm/cache.h | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/arch/ia64/include/asm/cache.h b/arch/ia64/include/asm/cache.h new file mode 100644 index 00000000000..e7482bd628f --- /dev/null +++ b/arch/ia64/include/asm/cache.h @@ -0,0 +1,29 @@ +#ifndef _ASM_IA64_CACHE_H +#define _ASM_IA64_CACHE_H + + +/* + * Copyright (C) 1998-2000 Hewlett-Packard Co + * David Mosberger-Tang <davidm@hpl.hp.com> + */ + +/* Bytes per L1 (data) cache line. */ +#define L1_CACHE_SHIFT CONFIG_IA64_L1_CACHE_SHIFT +#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) + +#ifdef CONFIG_SMP +# define SMP_CACHE_SHIFT L1_CACHE_SHIFT +# define SMP_CACHE_BYTES L1_CACHE_BYTES +#else + /* + * The "aligned" directive can only _increase_ alignment, so this is + * safe and provides an easy way to avoid wasting space on a + * uni-processor: + */ +# define SMP_CACHE_SHIFT 3 +# define SMP_CACHE_BYTES (1 << 3) +#endif + +#define __read_mostly __attribute__((__section__(".data.read_mostly"))) + +#endif /* _ASM_IA64_CACHE_H */ |